diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index a8672d6..76e440e3 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <amu.h>
 #include <arch.h>
 #include <arch_helpers.h>
 #include <assert.h>
@@ -132,6 +133,9 @@
 static void enable_extensions_nonsecure(int el2_unused)
 {
 #if IMAGE_BL32
+#if ENABLE_AMU
+	amu_enable(el2_unused);
+#endif
 #endif
 }
 
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
new file mode 100644
index 0000000..d450bd6
--- /dev/null
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <amu.h>
+#include <arch.h>
+#include <arch_helpers.h>
+
+void amu_enable(int el2_unused)
+{
+	uint64_t features;
+
+	features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
+	if ((features & ID_PFR0_AMU_MASK) == 1) {
+		if (el2_unused) {
+			uint64_t v;
+
+			/*
+			 * Non-secure access from EL0 or EL1 to the Activity Monitor
+			 * registers do not trap to EL2.
+			 */
+			v = read_hcptr();
+			v &= ~TAM_BIT;
+			write_hcptr(v);
+		}
+
+		/* Enable group 0 counters */
+		write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
+	}
+}