diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 0f069cb..4c10e7b 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -133,8 +133,10 @@
 	 * Tell BL31 where the non-trusted software image
 	 * is located and the entry state information
 	 */
+# if ARM_LINUX_KERNEL_AS_BL33
 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 	bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+#endif
 
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 }
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 4e3397f..84124bd 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -29,6 +29,13 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index 5789261..d954406 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -41,6 +41,13 @@
 #define CAD_QSPIDATA_OFST					0x10900000
 #define CAD_QSPI_OFFSET						0x108d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE					U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE					U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE				0x1c000000
 #define SOCFPGA_F2SDRAMMGR_REG_BASE				0x18001000
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index 23c93ea..7679f59 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -22,16 +22,21 @@
 #include <drivers/partition/partition.h>
 #include <lib/mmio.h>
 #include <tools_share/firmware_image_package.h>
-
 #include "drivers/sdmmc/sdmmc.h"
 #include "socfpga_private.h"
 #include "socfpga_ros.h"
 
 
 #define PLAT_FIP_BASE		(0)
+# if ARM_LINUX_KERNEL_AS_BL33
 #define PLAT_FIP_MAX_SIZE	(0x8000000)
 #define PLAT_MMC_DATA_BASE	(0x10000000)
 #define PLAT_MMC_DATA_SIZE	(0x100000)
+# else
+#define PLAT_FIP_MAX_SIZE	(0x1000000)
+#define PLAT_MMC_DATA_BASE	(0xffe3c000)
+#define PLAT_MMC_DATA_SIZE	(0x2000)
+# endif
 
 static const io_dev_connector_t *fip_dev_con;
 static const io_dev_connector_t *boot_dev_con;
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 1b662ad..c5e66c7 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -29,6 +29,13 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		U(0xf7000000)
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index d4c7dab..cd4c163 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -28,6 +28,13 @@
 #define CAD_QSPIDATA_OFST			0xff900000
 #define CAD_QSPI_OFFSET				0xff8d2000
 
+/* SDMMC Setting */
+# if ARM_LINUX_KERNEL_AS_BL33
+#define SOCFPGA_MMC_BLOCK_SIZE			U(32768)
+# else
+#define SOCFPGA_MMC_BLOCK_SIZE			U(8192)
+# endif
+
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		0xf7000000
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)