diff --git a/docs/components/romlib-design.rst b/docs/components/romlib-design.rst
index e0a028e..d34b3cc 100644
--- a/docs/components/romlib-design.rst
+++ b/docs/components/romlib-design.rst
@@ -115,21 +115,27 @@
 ~~~~~~~~~~~~~
 
 Using library at ROM will modify the memory layout of the BL images:
+
 - The ROM library needs a page aligned RAM section to hold the RW data. This
-   section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros.
-   On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM.
-   This will have for effect to shift down all the BL images by 1 page.
+  section is defined by the ROMLIB_RW_BASE and ROMLIB_RW_END macros.
+  On Arm platforms a section of 1 page (0x1000) is allocated at the top of SRAM.
+  This will have for effect to shift down all the BL images by 1 page.
+
 - Depending on the functions moved to the ROM library, the size of the BL images
-   will be reduced.
-   For example: moving MbedTLS function into the ROM library reduces BL1 and
-   BL2, but not BL31.
+  will be reduced.
+  For example: moving MbedTLS function into the ROM library reduces BL1 and
+  BL2, but not BL31.
+
 - This change in BL images size can be taken into consideration to optimize the
-   memory layout when defining the BLx_BASE macros.
+  memory layout when defining the BLx_BASE macros.
 
 Build library at ROM
 ~~~~~~~~~~~~~~~~~~~~~
 
-The environment variable ``CROSS_COMPILE`` must be set as per the user guide.
+The environment variable ``CROSS_COMPILE`` must be set appropriately. Refer to
+:ref:`Performing an Initial Build` for more information about setting this
+variable.
+
 In the below example the usage of ROMLIB together with mbed TLS is demonstrated
 to showcase the benefits of library at ROM - it's not mandatory.
 
diff --git a/docs/design/alt-boot-flows.rst b/docs/design/alt-boot-flows.rst
new file mode 100644
index 0000000..b44c061
--- /dev/null
+++ b/docs/design/alt-boot-flows.rst
@@ -0,0 +1,84 @@
+Alternative Boot Flows
+======================
+
+EL3 payloads alternative boot flow
+----------------------------------
+
+On a pre-production system, the ability to execute arbitrary, bare-metal code at
+the highest exception level is required. It allows full, direct access to the
+hardware, for example to run silicon soak tests.
+
+Although it is possible to implement some baremetal secure firmware from
+scratch, this is a complex task on some platforms, depending on the level of
+configuration required to put the system in the expected state.
+
+Rather than booting a baremetal application, a possible compromise is to boot
+``EL3 payloads`` through TF-A instead. This is implemented as an alternative
+boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
+other BL images and passing control to BL31. It reduces the complexity of
+developing EL3 baremetal code by:
+
+-  putting the system into a known architectural state;
+-  taking care of platform secure world initialization;
+-  loading the SCP_BL2 image if required by the platform.
+
+When booting an EL3 payload on Arm standard platforms, the configuration of the
+TrustZone controller is simplified such that only region 0 is enabled and is
+configured to permit secure access only. This gives full access to the whole
+DRAM to the EL3 payload.
+
+The system is left in the same state as when entering BL31 in the default boot
+flow. In particular:
+
+-  Running in EL3;
+-  Current state is AArch64;
+-  Little-endian data access;
+-  All exceptions disabled;
+-  MMU disabled;
+-  Caches disabled.
+
+.. _alt_boot_flows_el3_payload:
+
+Booting an EL3 payload
+~~~~~~~~~~~~~~~~~~~~~~
+
+The EL3 payload image is a standalone image and is not part of the FIP. It is
+not loaded by TF-A. Therefore, there are 2 possible scenarios:
+
+-  The EL3 payload may reside in non-volatile memory (NVM) and execute in
+   place. In this case, booting it is just a matter of specifying the right
+   address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
+
+-  The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
+   run-time.
+
+To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
+used. The infinite loop that it introduces in BL1 stops execution at the right
+moment for a debugger to take control of the target and load the payload (for
+example, over JTAG).
+
+It is expected that this loading method will work in most cases, as a debugger
+connection is usually available in a pre-production system. The user is free to
+use any other platform-specific mechanism to load the EL3 payload, though.
+
+
+Preloaded BL33 alternative boot flow
+------------------------------------
+
+Some platforms have the ability to preload BL33 into memory instead of relying
+on TF-A to load it. This may simplify packaging of the normal world code and
+improve performance in a development environment. When secure world cold boot
+is complete, TF-A simply jumps to a BL33 base address provided at build time.
+
+For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
+used when compiling TF-A. For example, the following command will create a FIP
+without a BL33 and prepare to jump to a BL33 image loaded at address
+0x80000000:
+
+.. code:: shell
+
+    make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 4958fc0..cae94b5 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -597,7 +597,7 @@
 is not necessary for AArch32 SPs.
 
 Details on BL32 initialization and the SPD's role are described in the
-"Secure-EL1 Payloads and Dispatchers" section below.
+:ref:`firmware_design_sel1_spd` section below.
 
 BL33 (Non-trusted Firmware) execution
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -868,7 +868,7 @@
 
    TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
    (TSPD). Details of SPD design and TSP/TSPD operation are described in the
-   "Secure-EL1 Payloads and Dispatchers" section below.
+   :ref:`firmware_design_sel1_spd` section below.
 
 #. CPU implementation service
 
@@ -978,8 +978,8 @@
 framework finally sets up the execution stack for the handler, and invokes the
 services ``handle()`` function.
 
-On return from the handler the result registers are populated in X0-X3 before
-restoring the stack and CPU state and returning from the original SMC.
+On return from the handler the result registers are populated in X0-X7 as needed
+before restoring the stack and CPU state and returning from the original SMC.
 
 Exception Handling Framework
 ----------------------------
@@ -1875,10 +1875,7 @@
                |   MHU    |
     0x04000000 +----------+
 
-Library at ROM
----------------
-
-Please refer to the :ref:`Library at ROM` document.
+.. _firmware_design_fip:
 
 Firmware Image Package (FIP)
 ----------------------------
@@ -2543,7 +2540,7 @@
 targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
 and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
 
-See also the *Summary of build options* in :ref:`User Guide`.
+.. seealso:: :ref:`Build Options`
 
 For details on the Architecture Extension and available features, please refer
 to the respective Architecture Extension Supplement.
diff --git a/docs/design/index.rst b/docs/design/index.rst
index a51a4eb..e3b8f74 100644
--- a/docs/design/index.rst
+++ b/docs/design/index.rst
@@ -6,6 +6,7 @@
    :caption: Contents
    :numbered:
 
+   alt-boot-flows
    auth-framework
    cpu-specific-build-macros
    firmware-design
@@ -13,3 +14,8 @@
    psci-pd-tree
    reset-design
    trusted-board-boot
+   trusted-board-boot-build
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/design/reset-design.rst b/docs/design/reset-design.rst
index a92ceeb..7b10c95 100644
--- a/docs/design/reset-design.rst
+++ b/docs/design/reset-design.rst
@@ -115,8 +115,8 @@
 It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in
 which case the ``bl31.bin`` image must be loaded to its run address in Trusted
 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
-address. See the :ref:`User Guide` for details of running the FVP models in this
-way.
+address. See the :ref:`Arm Fixed Virtual Platforms (FVP)` for details of running
+the FVP models in this way.
 
 Although technically it would be possible to program the reset base address with
 the right support in the SCP firmware, this is currently not implemented so the
diff --git a/docs/design/trusted-board-boot-build.rst b/docs/design/trusted-board-boot-build.rst
new file mode 100644
index 0000000..2025243
--- /dev/null
+++ b/docs/design/trusted-board-boot-build.rst
@@ -0,0 +1,114 @@
+Building FIP images with support for Trusted Board Boot
+=======================================================
+
+Trusted Board Boot primarily consists of the following two features:
+
+-  Image Authentication, described in :ref:`Trusted Board Boot`, and
+-  Firmware Update, described in :ref:`Firmware Update (FWU)`
+
+The following steps should be followed to build FIP and (optionally) FWU_FIP
+images with support for these features:
+
+#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
+   modules by checking out a recent version of the `mbed TLS Repository`_. It
+   is important to use a version that is compatible with TF-A and fixes any
+   known security vulnerabilities. See `mbed TLS Security Center`_ for more
+   information. See the :ref:`Prerequisites` document for the appropriate
+   version of mbed TLS to use.
+
+   The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
+   source files the modules depend upon.
+   ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
+   options required to build the mbed TLS sources.
+
+   Note that the mbed TLS library is licensed under the Apache version 2.0
+   license. Using mbed TLS source code will affect the licensing of TF-A
+   binaries that are built using this library.
+
+#. To build the FIP image, ensure the following command line variables are set
+   while invoking ``make`` to build TF-A:
+
+   -  ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
+   -  ``TRUSTED_BOARD_BOOT=1``
+   -  ``GENERATE_COT=1``
+
+   In the case of Arm platforms, the location of the ROTPK hash must also be
+   specified at build time. Two locations are currently supported (see
+   ``ARM_ROTPK_LOCATION`` build option):
+
+   -  ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
+      root-key storage registers present in the platform. On Juno, this
+      registers are read-only. On FVP Base and Cortex models, the registers
+      are read-only, but the value can be specified using the command line
+      option ``bp.trusted_key_storage.public_key`` when launching the model.
+      On both Juno and FVP models, the default value corresponds to an
+      ECDSA-SECP256R1 public key hash, whose private part is not currently
+      available.
+
+   -  ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
+      in the Arm platform port. The private/public RSA key pair may be
+      found in ``plat/arm/board/common/rotpk``.
+
+   -  ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
+      in the Arm platform port. The private/public ECDSA key pair may be
+      found in ``plat/arm/board/common/rotpk``.
+
+   Example of command line using RSA development keys:
+
+   .. code:: shell
+
+       MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
+       make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1        \
+       ARM_ROTPK_LOCATION=devel_rsa                                    \
+       ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem        \
+       BL33=<path-to>/<bl33_image>                                     \
+       all fip
+
+   The result of this build will be the bl1.bin and the fip.bin binaries. This
+   FIP will include the certificates corresponding to the Chain of Trust
+   described in the TBBR-client document. These certificates can also be found
+   in the output build directory.
+
+#. The optional FWU_FIP contains any additional images to be loaded from
+   Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To build the
+   FWU_FIP, any FWU images required by the platform must be specified on the
+   command line. On Arm development platforms like Juno, these are:
+
+   -  NS_BL2U. The AP non-secure Firmware Updater image.
+   -  SCP_BL2U. The SCP Firmware Update Configuration image.
+
+   Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
+   targets using RSA development:
+
+   ::
+
+       MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
+       make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1              \
+       ARM_ROTPK_LOCATION=devel_rsa                                    \
+       ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem        \
+       BL33=<path-to>/<bl33_image>                                     \
+       SCP_BL2=<path-to>/<scp_bl2_image>                               \
+       SCP_BL2U=<path-to>/<scp_bl2u_image>                             \
+       NS_BL2U=<path-to>/<ns_bl2u_image>                               \
+       all fip fwu_fip
+
+   .. note::
+      The BL2U image will be built by default and added to the FWU_FIP.
+      The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
+      to the command line above.
+
+   .. note::
+      Building and installing the non-secure and SCP FWU images (NS_BL1U,
+      NS_BL2U and SCP_BL2U) is outside the scope of this document.
+
+   The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
+   Both the FIP and FWU_FIP will include the certificates corresponding to the
+   Chain of Trust described in the TBBR-client document. These certificates
+   can also be found in the output build directory.
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
+
+.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
+.. _mbed TLS Security Center: https://tls.mbed.org/security
diff --git a/docs/design/trusted-board-boot.rst b/docs/design/trusted-board-boot.rst
index f3b1c36..49e8adb 100644
--- a/docs/design/trusted-board-boot.rst
+++ b/docs/design/trusted-board-boot.rst
@@ -187,8 +187,8 @@
 
 The Trusted Board Boot implementation spans both generic and platform-specific
 BL1 and BL2 code, and in tool code on the host build machine. The feature is
-enabled through use of specific build flags as described in the
-:ref:`User Guide`.
+enabled through use of specific build flags as described in
+:ref:`Build Options`.
 
 On the host machine, a tool generates the certificates, which are included in
 the FIP along with the boot loader images. These certificates are loaded in
@@ -222,9 +222,12 @@
 The certificates are also stored individually in the in the output build
 directory.
 
-The tool resides in the ``tools/cert_create`` directory. It uses OpenSSL SSL
-library version 1.0.1 or later to generate the X.509 certificates. Instructions
-for building and using the tool can be found in the :ref:`User Guide`.
+The tool resides in the ``tools/cert_create`` directory. It uses the OpenSSL SSL
+library version to generate the X.509 certificates. The specific version of the
+library that is required is given in the :ref:`Prerequisites` document.
+
+Instructions for building and using the tool can be found at
+:ref:`tools_build_cert_create`.
 
 --------------
 
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
new file mode 100644
index 0000000..fded1e0
--- /dev/null
+++ b/docs/getting_started/build-options.rst
@@ -0,0 +1,623 @@
+Build Options
+=============
+
+The TF-A build system supports the following build options. Unless mentioned
+otherwise, these options are expected to be specified at the build command
+line and are not to be modified in any component makefiles. Note that the
+build system doesn't track dependency for build options. Therefore, if any of
+the build options are changed from a previous build, a clean build must be
+performed.
+
+.. _build_options_common:
+
+Common build options
+--------------------
+
+-  ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
+   compiler should use. Valid values are T32 and A32. It defaults to T32 due to
+   code having a smaller resulting size.
+
+-  ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
+   as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
+   directory containing the SP source, relative to the ``bl32/``; the directory
+   is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
+
+-  ``ARCH`` : Choose the target build architecture for TF-A. It can take either
+   ``aarch64`` or ``aarch32`` as values. By default, it is defined to
+   ``aarch64``.
+
+-  ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
+   compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
+   *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
+   :ref:`Firmware Design`.
+
+-  ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
+   compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
+   *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
+
+-  ``BL2``: This is an optional build option which specifies the path to BL2
+   image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
+   built.
+
+-  ``BL2U``: This is an optional build option which specifies the path to
+   BL2U image. In this case, the BL2U in TF-A will not be built.
+
+-  ``BL2_AT_EL3``: This is an optional build option that enables the use of
+   BL2 at EL3 execution level.
+
+-  ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
+   (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
+   the RW sections in RAM, while leaving the RO sections in place. This option
+   enable this use-case. For now, this option is only supported when BL2_AT_EL3
+   is set to '1'.
+
+-  ``BL31``: This is an optional build option which specifies the path to
+   BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
+   be built.
+
+-  ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
+   file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
+   this file name will be used to save the key.
+
+-  ``BL32``: This is an optional build option which specifies the path to
+   BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
+   be built.
+
+-  ``BL32_EXTRA1``: This is an optional build option which specifies the path to
+   Trusted OS Extra1 image for the  ``fip`` target.
+
+-  ``BL32_EXTRA2``: This is an optional build option which specifies the path to
+   Trusted OS Extra2 image for the ``fip`` target.
+
+-  ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
+   file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
+   this file name will be used to save the key.
+
+-  ``BL33``: Path to BL33 image in the host file system. This is mandatory for
+   ``fip`` target in case TF-A BL2 is used.
+
+-  ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
+   file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
+   this file name will be used to save the key.
+
+-  ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
+   and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
+   If enabled, it is needed to use a compiler that supports the option
+   ``-mbranch-protection``. Selects the branch protection features to use:
+-  0: Default value turns off all types of branch protection
+-  1: Enables all types of branch protection features
+-  2: Return address signing to its standard level
+-  3: Extend the signing to include leaf functions
+
+   The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
+   and resulting PAuth/BTI features.
+
+   +-------+--------------+-------+-----+
+   | Value |  GCC option  | PAuth | BTI |
+   +=======+==============+=======+=====+
+   |   0   |     none     |   N   |  N  |
+   +-------+--------------+-------+-----+
+   |   1   |   standard   |   Y   |  Y  |
+   +-------+--------------+-------+-----+
+   |   2   |   pac-ret    |   Y   |  N  |
+   +-------+--------------+-------+-----+
+   |   3   | pac-ret+leaf |   Y   |  N  |
+   +-------+--------------+-------+-----+
+
+   This option defaults to 0 and this is an experimental feature.
+   Note that Pointer Authentication is enabled for Non-secure world
+   irrespective of the value of this option if the CPU supports it.
+
+-  ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
+   compilation of each build. It must be set to a C string (including quotes
+   where applicable). Defaults to a string that contains the time and date of
+   the compilation.
+
+-  ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
+   build to be uniquely identified. Defaults to the current git commit id.
+
+-  ``CFLAGS``: Extra user options appended on the compiler's command line in
+   addition to the options set by the build system.
+
+-  ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
+   release several CPUs out of reset. It can take either 0 (several CPUs may be
+   brought up) or 1 (only one CPU will ever be brought up during cold reset).
+   Default is 0. If the platform always brings up a single CPU, there is no
+   need to distinguish between primary and secondary CPUs and the boot path can
+   be optimised. The ``plat_is_my_cpu_primary()`` and
+   ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
+   to be implemented in this case.
+
+-  ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
+   register state when an unexpected exception occurs during execution of
+   BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
+   this is only enabled for a debug build of the firmware.
+
+-  ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
+   certificate generation tool to create new keys in case no valid keys are
+   present or specified. Allowed options are '0' or '1'. Default is '1'.
+
+-  ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
+   the AArch32 system registers to be included when saving and restoring the
+   CPU context. The option must be set to 0 for AArch64-only platforms (that
+   is on hardware that does not implement AArch32, or at least not at EL1 and
+   higher ELs). Default value is 1.
+
+-  ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
+   registers to be included when saving and restoring the CPU context. Default
+   is 0.
+
+-  ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
+   Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
+   registers to be included when saving and restoring the CPU context as
+   part of world switch. Default value is 0 and this is an experimental feature.
+   Note that Pointer Authentication is enabled for Non-secure world irrespective
+   of the value of this flag if the CPU supports it.
+
+-  ``DEBUG``: Chooses between a debug and release build. It can take either 0
+   (release) or 1 (debug) as values. 0 is the default.
+
+-  ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
+   of the binary image. If set to 1, then only the ELF image is built.
+   0 is the default.
+
+-  ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
+   Board Boot authentication at runtime. This option is meant to be enabled only
+   for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
+   flag has to be enabled. 0 is the default.
+
+-  ``E``: Boolean option to make warnings into errors. Default is 1.
+
+-  ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
+   the normal boot flow. It must specify the entry point address of the EL3
+   payload. Please refer to the "Booting an EL3 payload" section for more
+   details.
+
+-  ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
+   This is an optional architectural feature available on v8.4 onwards. Some
+   v8.2 implementations also implement an AMU and this option can be used to
+   enable this feature on those systems as well. Default is 0.
+
+-  ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
+   are compiled out. For debug builds, this option defaults to 1, and calls to
+   ``assert()`` are left in place. For release builds, this option defaults to 0
+   and calls to ``assert()`` function are compiled out. This option can be set
+   independently of ``DEBUG``. It can also be used to hide any auxiliary code
+   that is only required for the assertion and does not fit in the assertion
+   itself.
+
+-  ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
+   dumps or not. It is supported in both AArch64 and AArch32. However, in
+   AArch32 the format of the frame records are not defined in the AAPCS and they
+   are defined by the implementation. This implementation of backtrace only
+   supports the format used by GCC when T32 interworking is disabled. For this
+   reason enabling this option in AArch32 will force the compiler to only
+   generate A32 code. This option is enabled by default only in AArch64 debug
+   builds, but this behaviour can be overridden in each platform's Makefile or
+   in the build command line.
+
+-  ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
+   feature. MPAM is an optional Armv8.4 extension that enables various memory
+   system components and resources to define partitions; software running at
+   various ELs can assign themselves to desired partition to control their
+   performance aspects.
+
+   When this option is set to ``1``, EL3 allows lower ELs to access their own
+   MPAM registers without trapping into EL3. This option doesn't make use of
+   partitioning in EL3, however. Platform initialisation code should configure
+   and use partitions in EL3 as required. This option defaults to ``0``.
+
+-  ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
+   support within generic code in TF-A. This option is currently only supported
+   in BL31. Default is 0.
+
+-  ``ENABLE_PMF``: Boolean option to enable support for optional Performance
+   Measurement Framework(PMF). Default is 0.
+
+-  ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
+   functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
+   In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
+   be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
+   software.
+
+-  ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
+   instrumentation which injects timestamp collection points into TF-A to
+   allow runtime performance to be measured. Currently, only PSCI is
+   instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
+   as well. Default is 0.
+
+-  ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
+   extensions. This is an optional architectural feature for AArch64.
+   The default is 1 but is automatically disabled when the target architecture
+   is AArch32.
+
+-  ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
+   Refer to :ref:`Secure Partition Manager` for more details about
+   this feature. Default is 0.
+
+-  ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
+   (SVE) for the Non-secure world only. SVE is an optional architectural feature
+   for AArch64. Note that when SVE is enabled for the Non-secure world, access
+   to SIMD and floating-point functionality from the Secure world is disabled.
+   This is to avoid corruption of the Non-secure world data in the Z-registers
+   which are aliased by the SIMD and FP registers. The build option is not
+   compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
+   assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
+   1. The default is 1 but is automatically disabled when the target
+   architecture is AArch32.
+
+-  ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
+   checks in GCC. Allowed values are "all", "strong", "default" and "none". The
+   default value is set to "none". "strong" is the recommended stack protection
+   level if this feature is desired. "none" disables the stack protection. For
+   all values other than "none", the ``plat_get_stack_protector_canary()``
+   platform hook needs to be implemented. The value is passed as the last
+   component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
+
+-  ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
+   deprecated platform APIs, helper functions or drivers within Trusted
+   Firmware as error. It can take the value 1 (flag the use of deprecated
+   APIs as error) or 0. The default is 0.
+
+-  ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
+   targeted at EL3. When set ``0`` (default), no exceptions are expected or
+   handled at EL3, and a panic will result. This is supported only for AArch64
+   builds.
+
+-  ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
+   injection from lower ELs, and this build option enables lower ELs to use
+   Error Records accessed via System Registers to inject faults. This is
+   applicable only to AArch64 builds.
+
+   This feature is intended for testing purposes only, and is advisable to keep
+   disabled for production images.
+
+-  ``FIP_NAME``: This is an optional build option which specifies the FIP
+   filename for the ``fip`` target. Default is ``fip.bin``.
+
+-  ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
+   FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
+
+-  ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
+   tool to create certificates as per the Chain of Trust described in
+   :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
+   include the certificates in the FIP and FWU_FIP. Default value is '0'.
+
+   Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
+   for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
+   the corresponding certificates, and to include those certificates in the
+   FIP and FWU_FIP.
+
+   Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
+   images will not include support for Trusted Board Boot. The FIP will still
+   include the corresponding certificates. This FIP can be used to verify the
+   Chain of Trust on the host machine through other mechanisms.
+
+   Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
+   images will include support for Trusted Board Boot, but the FIP and FWU_FIP
+   will not include the corresponding certificates, causing a boot failure.
+
+-  ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
+   inherent support for specific EL3 type interrupts. Setting this build option
+   to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
+   by `platform abstraction layer`__ and `Interrupt Management Framework`__.
+   This allows GICv2 platforms to enable features requiring EL3 interrupt type.
+   This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
+   the Secure Payload interrupts needs to be synchronously handed over to Secure
+   EL1 for handling. The default value of this option is ``0``, which means the
+   Group 0 interrupts are assumed to be handled by Secure EL1.
+
+   .. __: `platform-interrupt-controller-API.rst`
+   .. __: `interrupt-framework-design.rst`
+
+-  ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
+   Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
+   ``0`` (default), these exceptions will be trapped in the current exception
+   level (or in EL1 if the current exception level is EL0).
+
+-  ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
+   software operations are required for CPUs to enter and exit coherency.
+   However, newer systems exist where CPUs' entry to and exit from coherency
+   is managed in hardware. Such systems require software to only initiate these
+   operations, and the rest is managed in hardware, minimizing active software
+   management. In such systems, this boolean option enables TF-A to carry out
+   build and run-time optimizations during boot and power management operations.
+   This option defaults to 0 and if it is enabled, then it implies
+   ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
+
+   If this flag is disabled while the platform which TF-A is compiled for
+   includes cores that manage coherency in hardware, then a compilation error is
+   generated. This is based on the fact that a system cannot have, at the same
+   time, cores that manage coherency in hardware and cores that don't. In other
+   words, a platform cannot have, at the same time, cores that require
+   ``HW_ASSISTED_COHERENCY=1`` and cores that require
+   ``HW_ASSISTED_COHERENCY=0``.
+
+   Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
+   translation library (xlat tables v2) must be used; version 1 of translation
+   library is not supported.
+
+-  ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
+   runtime software in AArch32 mode, which is required to run AArch32 on Juno.
+   By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
+   AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
+   images.
+
+-  ``KEY_ALG``: This build flag enables the user to select the algorithm to be
+   used for generating the PKCS keys and subsequent signing of the certificate.
+   It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
+   ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
+   compliant and is retained only for compatibility. The default value of this
+   flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
+
+-  ``HASH_ALG``: This build flag enables the user to select the secure hash
+   algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
+   The default value of this flag is ``sha256``.
+
+-  ``LDFLAGS``: Extra user options appended to the linkers' command line in
+   addition to the one set by the build system.
+
+-  ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
+   output compiled into the build. This should be one of the following:
+
+   ::
+
+       0  (LOG_LEVEL_NONE)
+       10 (LOG_LEVEL_ERROR)
+       20 (LOG_LEVEL_NOTICE)
+       30 (LOG_LEVEL_WARNING)
+       40 (LOG_LEVEL_INFO)
+       50 (LOG_LEVEL_VERBOSE)
+
+   All log output up to and including the selected log level is compiled into
+   the build. The default value is 40 in debug builds and 20 in release builds.
+
+-  ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
+   specifies the file that contains the Non-Trusted World private key in PEM
+   format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
+
+-  ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
+   optional. It is only needed if the platform makefile specifies that it
+   is required in order to build the ``fwu_fip`` target.
+
+-  ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
+   contents upon world switch. It can take either 0 (don't save and restore) or
+   1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
+   wants the timer registers to be saved and restored.
+
+-  ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
+   for the BL image. It can be either 0 (include) or 1 (remove). The default
+   value is 0.
+
+-  ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
+   the underlying hardware is not a full PL011 UART but a minimally compliant
+   generic UART, which is a subset of the PL011. The driver will not access
+   any register that is not part of the SBSA generic UART specification.
+   Default value is 0 (a full PL011 compliant UART is present).
+
+-  ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
+   must be subdirectory of any depth under ``plat/``, and must contain a
+   platform makefile named ``platform.mk``. For example, to build TF-A for the
+   Arm Juno board, select PLAT=juno.
+
+-  ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
+   instead of the normal boot flow. When defined, it must specify the entry
+   point address for the preloaded BL33 image. This option is incompatible with
+   ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
+   over ``PRELOADED_BL33_BASE``.
+
+-  ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
+   vector address can be programmed or is fixed on the platform. It can take
+   either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
+   programmable reset address, it is expected that a CPU will start executing
+   code directly at the right address, both on a cold and warm reset. In this
+   case, there is no need to identify the entrypoint on boot and the boot path
+   can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
+   does not need to be implemented in this case.
+
+-  ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
+   possible for the PSCI power-state parameter: original and extended State-ID
+   formats. This flag if set to 1, configures the generic PSCI layer to use the
+   extended format. The default value of this flag is 0, which means by default
+   the original power-state format is used by the PSCI implementation. This flag
+   should be specified by the platform makefile and it governs the return value
+   of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
+   enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
+   set to 1 as well.
+
+-  ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
+   are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
+   or later CPUs.
+
+   When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
+   set to ``1``.
+
+   This option is disabled by default.
+
+-  ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
+   of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
+   entrypoint) or 1 (CPU reset to BL31 entrypoint).
+   The default value is 0.
+
+-  ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
+   in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
+   instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
+   entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
+
+-  ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
+   file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
+   file name will be used to save the key.
+
+-  ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
+   certificate generation tool to save the keys used to establish the Chain of
+   Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
+
+-  ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
+   If a SCP_BL2 image is present then this option must be passed for the ``fip``
+   target.
+
+-  ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
+   file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
+   this file name will be used to save the key.
+
+-  ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
+   optional. It is only needed if the platform makefile specifies that it
+   is required in order to build the ``fwu_fip`` target.
+
+-  ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
+   Delegated Exception Interface to BL31 image. This defaults to ``0``.
+
+   When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
+   set to ``1``.
+
+-  ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
+   isolated on separate memory pages. This is a trade-off between security and
+   memory usage. See "Isolating code and read-only data on separate memory
+   pages" section in :ref:`Firmware Design`. This flag is disabled by default and
+   affects all BL images.
+
+-  ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
+   This build option is only valid if ``ARCH=aarch64``. The value should be
+   the path to the directory containing the SPD source, relative to
+   ``services/spd/``; the directory is expected to contain a makefile called
+   ``<spd-value>.mk``.
+
+-  ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
+   take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
+   execution in BL1 just before handing over to BL31. At this point, all
+   firmware images have been loaded in memory, and the MMU and caches are
+   turned off. Refer to the "Debugging options" section for more details.
+
+-  ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
+   secure interrupts (caught through the FIQ line). Platforms can enable
+   this directive if they need to handle such interruption. When enabled,
+   the FIQ are handled in monitor mode and non secure world is not allowed
+   to mask these events. Platforms that enable FIQ handling in SP_MIN shall
+   implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
+
+-  ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
+   Boot feature. When set to '1', BL1 and BL2 images include support to load
+   and verify the certificates and images in a FIP, and BL1 includes support
+   for the Firmware Update. The default value is '0'. Generation and inclusion
+   of certificates in the FIP and FWU_FIP depends upon the value of the
+   ``GENERATE_COT`` option.
+
+   .. warning::
+      This option depends on ``CREATE_KEYS`` to be enabled. If the keys
+      already exist in disk, they will be overwritten without further notice.
+
+-  ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
+   specifies the file that contains the Trusted World private key in PEM
+   format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
+
+-  ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
+   synchronous, (see "Initializing a BL32 Image" section in
+   :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
+   synchronous method) or 1 (BL32 is initialized using asynchronous method).
+   Default is 0.
+
+-  ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
+   routing model which routes non-secure interrupts asynchronously from TSP
+   to EL3 causing immediate preemption of TSP. The EL3 is responsible
+   for saving and restoring the TSP context in this routing model. The
+   default routing model (when the value is 0) is to route non-secure
+   interrupts to TSP allowing it to save its context and hand over
+   synchronously to EL3 via an SMC.
+
+   .. note::
+      When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
+      must also be set to ``1``.
+
+-  ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
+   linker. When the ``LINKER`` build variable points to the armlink linker,
+   this flag is enabled automatically. To enable support for armlink, platforms
+   will have to provide a scatter file for the BL image. Currently, Tegra
+   platforms use the armlink support to compile BL3-1 images.
+
+-  ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
+   memory region in the BL memory map or not (see "Use of Coherent memory in
+   TF-A" section in :ref:`Firmware Design`). It can take the value 1
+   (Coherent memory region is included) or 0 (Coherent memory region is
+   excluded). Default is 1.
+
+-  ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
+   This feature creates a library of functions to be placed in ROM and thus
+   reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
+   is 0.
+
+-  ``V``: Verbose build. If assigned anything other than 0, the build commands
+   are printed. Default is 0.
+
+-  ``VERSION_STRING``: String used in the log output for each TF-A image.
+   Defaults to a string formed by concatenating the version number, build type
+   and build string.
+
+-  ``W``: Warning level. Some compiler warning options of interest have been
+   regrouped and put in the root Makefile. This flag can take the values 0 to 3,
+   each level enabling more warning options. Default is 0.
+
+-  ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
+   the CPU after warm boot. This is applicable for platforms which do not
+   require interconnect programming to enable cache coherency (eg: single
+   cluster platforms). If this option is enabled, then warm boot path
+   enables D-caches immediately after enabling MMU. This option defaults to 0.
+
+Debugging options
+-----------------
+
+To compile a debug version and make the build more verbose use
+
+.. code:: shell
+
+    make PLAT=<platform> DEBUG=1 V=1 all
+
+AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
+example DS-5) might not support this and may need an older version of DWARF
+symbols to be emitted by GCC. This can be achieved by using the
+``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
+version to 2 is recommended for DS-5 versions older than 5.16.
+
+When debugging logic problems it might also be useful to disable all compiler
+optimizations by using ``-O0``.
+
+.. warning::
+   Using ``-O0`` could cause output images to be larger and base addresses
+   might need to be recalculated (see the **Memory layout on Arm development
+   platforms** section in the :ref:`Firmware Design`).
+
+Extra debug options can be passed to the build system by setting ``CFLAGS`` or
+``LDFLAGS``:
+
+.. code:: shell
+
+    CFLAGS='-O0 -gdwarf-2'                                     \
+    make PLAT=<platform> DEBUG=1 V=1 all
+
+Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
+ignored as the linker is called directly.
+
+It is also possible to introduce an infinite loop to help in debugging the
+post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
+``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
+section. In this case, the developer may take control of the target using a
+debugger when indicated by the console output. When using DS-5, the following
+commands can be used:
+
+::
+
+    # Stop target execution
+    interrupt
+
+    #
+    # Prepare your debugging environment, e.g. set breakpoints
+    #
+
+    # Jump over the debug loop
+    set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
+
+    # Resume execution
+    continue
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index fa07642..c5625e9 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -22,6 +22,9 @@
 - Python 3 (3.5 or later)
 - PlantUML (1.2017.15 or later)
 
+Optionally, the `Dia`_ application can be installed if you need to edit
+existing ``.dia`` diagram files, or create new ones.
+
 You must also install the Python modules that are specified in the
 ``requirements.txt`` file in the root of the ``docs`` directory. These modules
 can be installed using ``pip3`` (the Python Package Installer). Passing this
@@ -33,7 +36,7 @@
 
 .. code:: shell
 
-    sudo apt install python3 python3-pip plantuml
+    sudo apt install python3 python3-pip plantuml [dia]
     pip3 install [--user] -r requirements.txt
 
 .. note::
@@ -75,3 +78,4 @@
 
 .. _Sphinx: http://www.sphinx-doc.org/en/master/
 .. _pip homepage: https://pip.pypa.io/en/stable/
+.. _Dia: https://wiki.gnome.org/Apps/Dia
diff --git a/docs/getting_started/index.rst b/docs/getting_started/index.rst
index 07e3753..817beaf 100644
--- a/docs/getting_started/index.rst
+++ b/docs/getting_started/index.rst
@@ -6,9 +6,16 @@
    :caption: Contents
    :numbered:
 
-   user-guide
+   prerequisites
    docs-build
+   tools-build
+   initial-build
+   build-options
    image-terminology
    porting-guide
    psci-lib-integration-guide
    rt-svc-writers-guide
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/getting_started/initial-build.rst b/docs/getting_started/initial-build.rst
new file mode 100644
index 0000000..41cd4d1
--- /dev/null
+++ b/docs/getting_started/initial-build.rst
@@ -0,0 +1,117 @@
+Performing an Initial Build
+===========================
+
+-  Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
+   to the Linaro cross compiler.
+
+   For AArch64:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+
+   For AArch32:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
+
+   It is possible to build TF-A using Clang or Arm Compiler 6. To do so
+   ``CC`` needs to point to the clang or armclang binary, which will
+   also select the clang or armclang assembler. Be aware that the
+   GNU linker is used by default.  In case of being needed the linker
+   can be overridden using the ``LD`` variable. Clang linker version 6 is
+   known to work with TF-A.
+
+   In both cases ``CROSS_COMPILE`` should be set as described above.
+
+   Arm Compiler 6 will be selected when the base name of the path assigned
+   to ``CC`` matches the string 'armclang'.
+
+   For AArch64 using Arm Compiler 6:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+       make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
+
+   Clang will be selected when the base name of the path assigned to ``CC``
+   contains the string 'clang'. This is to allow both clang and clang-X.Y
+   to work.
+
+   For AArch64 using clang:
+
+   .. code:: shell
+
+       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+       make CC=<path-to-clang>/bin/clang PLAT=<platform> all
+
+-  Change to the root directory of the TF-A source tree and build.
+
+   For AArch64:
+
+   .. code:: shell
+
+       make PLAT=<platform> all
+
+   For AArch32:
+
+   .. code:: shell
+
+       make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
+
+   Notes:
+
+   -  If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
+      :ref:`Build Options` document for more information on available build
+      options.
+
+   -  (AArch32 only) Currently only ``PLAT=fvp`` is supported.
+
+   -  (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
+      corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
+      provided by TF-A to demonstrate how PSCI Library can be integrated with
+      an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
+      include other runtime services, for example Trusted OS services. A guide
+      to integrate PSCI library with AArch32 EL3 Runtime Software can be found
+      at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
+
+   -  (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
+      image, is not compiled in by default. Refer to the
+      :ref:`Test Secure Payload (TSP) and Dispatcher (TSPD)` document for
+      details on building the TSP.
+
+   -  By default this produces a release version of the build. To produce a
+      debug version instead, refer to the "Debugging options" section below.
+
+   -  The build process creates products in a ``build`` directory tree, building
+      the objects and binaries for each boot loader stage in separate
+      sub-directories. The following boot loader binary files are created
+      from the corresponding ELF files:
+
+      -  ``build/<platform>/<build-type>/bl1.bin``
+      -  ``build/<platform>/<build-type>/bl2.bin``
+      -  ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
+      -  ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
+
+      where ``<platform>`` is the name of the chosen platform and ``<build-type>``
+      is either ``debug`` or ``release``. The actual number of images might differ
+      depending on the platform.
+
+-  Build products for a specific build variant can be removed using:
+
+   .. code:: shell
+
+       make DEBUG=<D> PLAT=<platform> clean
+
+   ... where ``<D>`` is ``0`` or ``1``, as specified when building.
+
+   The build tree can be removed completely using:
+
+   .. code:: shell
+
+       make realclean
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index 9cca75e9..17fd546 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -23,8 +23,6 @@
 discusses these in detail. The subsequent sections discuss the remaining
 modifications for each BL stage in detail.
 
-This document should be read in conjunction with the TF-A :ref:`User Guide`.
-
 Please refer to the :ref:`Platform Compatibility Policy` for the policy
 regarding compatibility and deprecation of these porting interfaces.
 
@@ -2387,8 +2385,8 @@
 `Arm Generic Interrupt Controller version 2.0 (GICv2)`_
 and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
 FVP can be configured to use either GICv2 or GICv3 depending on the build flag
-``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in
-:ref:`User Guide` for more details).
+``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
+details).
 
 See also: `Interrupt Controller Abstraction APIs`__.
 
@@ -2796,10 +2794,10 @@
 
 It is mandatory to implement at least one storage driver. For the Arm
 development platforms the Firmware Image Package (FIP) driver is provided as
-the default means to load data from storage (see the "Firmware Image Package"
-section in the :ref:`User Guide`). The storage layer is described in the header file
-``include/drivers/io/io_storage.h``. The implementation of the common library
-is in ``drivers/io/io_storage.c`` and the driver files are located in
+the default means to load data from storage (see :ref:`firmware_design_fip`).
+The storage layer is described in the header file
+``include/drivers/io/io_storage.h``. The implementation of the common library is
+in ``drivers/io/io_storage.c`` and the driver files are located in
 ``drivers/io/``.
 
 .. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
new file mode 100644
index 0000000..27ad0ed
--- /dev/null
+++ b/docs/getting_started/prerequisites.rst
@@ -0,0 +1,136 @@
+Prerequisites
+=============
+
+This document describes the software requirements for building |TF-A| for
+AArch32 and AArch64 target platforms.
+
+It may possible to build |TF-A| with combinations of software packages that are
+different from those listed below, however only the software described in this
+document can be officially supported.
+
+Build Host
+----------
+
+|TF-A| can be built using either a Linux or a Windows machine as the build host.
+
+A relatively recent Linux distribution is recommended for building |TF-A|. We
+have performed tests using Ubuntu 16.04 LTS (64-bit) but other distributions
+should also work fine as a base, provided that the necessary tools and libraries
+can be installed.
+
+.. _prerequisites_toolchain:
+
+Toolchain
+---------
+
+|TF-A| can be built with any of the following *cross-compiler* toolchains that
+target the Armv7-A or Armv8-A architectures:
+
+- GCC >= 8.3-2019.03 (from the `Arm Developer website`_)
+- Clang >= 4.0
+- Arm Compiler >= 6.0
+
+In addition, a native compiler is required to build the supporting tools.
+
+.. note::
+   The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
+   Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
+
+.. note::
+   For instructions on how to select the cross compiler refer to
+   :ref:`Performing an Initial Build`.
+
+.. _prerequisites_software_and_libraries:
+
+Software and Libraries
+----------------------
+
+The following tools are required to obtain and build |TF-A|:
+
+- An appropriate toolchain (see :ref:`prerequisites_toolchain`)
+- GNU Make
+- Git
+
+The following libraries must be available to build one or more components or
+supporting tools:
+
+- OpenSSL >= 1.0.1
+
+   Required to build the cert_create tool.
+
+The following libraries are required for Trusted Board Boot support:
+
+- mbed TLS == 2.16.2 (tag: ``mbedtls-2.16.2``)
+
+These tools are optional:
+
+- Device Tree Compiler (DTC) >= 1.4.6
+
+   Needed if you want to rebuild the provided Flattened Device Tree (FDT)
+   source files (``.dts`` files). DTC is available for Linux through the package
+   repositories of most distributions.
+
+- Arm `Development Studio 5 (DS-5)`_
+
+   The standard software package used for debugging software on Arm development
+   platforms and |FVP| models.
+
+Package Installation (Linux)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+If you are using the recommended Ubuntu distribution then you can install the
+required packages with the following command:
+
+.. code:: shell
+
+    sudo apt install build-essential git libssl-dev
+
+The optional packages can be installed using:
+
+.. code:: shell
+
+    sudo apt install device-tree-compiler
+
+Supporting Files
+----------------
+
+TF-A has been tested with pre-built binaries and file systems from `Linaro
+Release 19.06`_. Alternatively, you can build the binaries from source using
+instructions in :ref:`Performing an Initial Build`.
+
+.. _prerequisites_get_source:
+
+Getting the TF-A Source
+-----------------------
+
+Source code for |TF-A| is maintained in a Git repository hosted on
+TrustedFirmware.org. To clone this repository from the server, run the following
+in your shell:
+
+.. code:: shell
+
+    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a" && (cd "trusted-firmware-a" && mkdir -p .git/hooks && curl -Lo `git rev-parse --git-dir`/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg; chmod +x `git rev-parse --git-dir`/hooks/commit-msg)
+
+This will clone the Git repository also install a *commit hook* that
+automatically inserts appropriate *Change-Id:* lines at the end of your
+commit messages. These change IDs are required when committing changes that you
+intend to push for review via our Gerrit system.
+
+You can read more about Git hooks in the *githooks* page of the Git documentation,
+available at: https://git-scm.com/docs/githooks
+
+Alternatively, you can clone without the commit hook using:
+
+.. code:: shell
+
+    git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
+
+.. _Arm Developer website: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
+.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
+.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
+.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
+.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst
index 6a06025..5375b65 100644
--- a/docs/getting_started/rt-svc-writers-guide.rst
+++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -244,17 +244,35 @@
 
    TF-A expects owning entities to follow this recommendation.
 
-#. Returning the result to the caller. The `SMCCC`_ allows for up to 256 bits
-   of return value in SMC64 using X0-X3 and 128 bits in SMC32 using W0-W3. The
-   framework provides a family of macros to set the multi-register return
-   value and complete the handler:
+#. Returning the result to the caller. Based on `SMCCC`_ spec, results are
+   returned in W0-W7(X0-X7) registers for SMC32(SMC64) calls from AArch64
+   state. Results are returned in R0-R7 registers for SMC32 calls from AArch32
+   state. The framework provides a family of macros to set the multi-register
+   return value and complete the handler:
 
    .. code:: c
 
+       AArch64 state:
+
        SMC_RET1(handle, x0);
        SMC_RET2(handle, x0, x1);
        SMC_RET3(handle, x0, x1, x2);
        SMC_RET4(handle, x0, x1, x2, x3);
+       SMC_RET5(handle, x0, x1, x2, x3, x4);
+       SMC_RET6(handle, x0, x1, x2, x3, x4, x5);
+       SMC_RET7(handle, x0, x1, x2, x3, x4, x5, x6);
+       SMC_RET8(handle, x0, x1, x2, x3, x4, x5, x6, x7);
+
+       AArch32 state:
+
+       SMC_RET1(handle, r0);
+       SMC_RET2(handle, r0, r1);
+       SMC_RET3(handle, r0, r1, r2);
+       SMC_RET4(handle, r0, r1, r2, r3);
+       SMC_RET5(handle, r0, r1, r2, r3, r4);
+       SMC_RET6(handle, r0, r1, r2, r3, r4, r5);
+       SMC_RET7(handle, r0, r1, r2, r3, r4, r5, r6);
+       SMC_RET8(handle, r0, r1, r2, r3, r4, r5, r6, r7);
 
 The ``cookie`` parameter to the handler is reserved for future use and can be
 ignored. The ``handle`` is returned by the SMC handler - completion of the
diff --git a/docs/getting_started/tools-build.rst b/docs/getting_started/tools-build.rst
new file mode 100644
index 0000000..bb707cb
--- /dev/null
+++ b/docs/getting_started/tools-build.rst
@@ -0,0 +1,140 @@
+Building Supporting Tools
+=========================
+
+Building and using the FIP tool
+-------------------------------
+
+Firmware Image Package (FIP) is a packaging format used by TF-A to package
+firmware images in a single binary. The number and type of images that should
+be packed in a FIP is platform specific and may include TF-A images and other
+firmware images required by the platform. For example, most platforms require
+a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
+U-Boot).
+
+The TF-A build system provides the make target ``fip`` to create a FIP file
+for the specified platform using the FIP creation tool included in the TF-A
+project. Examples below show how to build a FIP file for FVP, packaging TF-A
+and BL33 images.
+
+For AArch64:
+
+.. code:: shell
+
+    make PLAT=fvp BL33=<path-to>/bl33.bin fip
+
+For AArch32:
+
+.. code:: shell
+
+    make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
+
+The resulting FIP may be found in:
+
+::
+
+    build/fvp/<build-type>/fip.bin
+
+For advanced operations on FIP files, it is also possible to independently build
+the tool and create or modify FIPs using this tool. To do this, follow these
+steps:
+
+It is recommended to remove old artifacts before building the tool:
+
+.. code:: shell
+
+    make -C tools/fiptool clean
+
+Build the tool:
+
+.. code:: shell
+
+    make [DEBUG=1] [V=1] fiptool
+
+The tool binary can be located in:
+
+::
+
+    ./tools/fiptool/fiptool
+
+Invoking the tool with ``help`` will print a help message with all available
+options.
+
+Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
+
+.. code:: shell
+
+    ./tools/fiptool/fiptool create \
+        --tb-fw build/<platform>/<build-type>/bl2.bin \
+        --soc-fw build/<platform>/<build-type>/bl31.bin \
+        fip.bin
+
+Example 2: view the contents of an existing Firmware package:
+
+.. code:: shell
+
+    ./tools/fiptool/fiptool info <path-to>/fip.bin
+
+Example 3: update the entries of an existing Firmware package:
+
+.. code:: shell
+
+    # Change the BL2 from Debug to Release version
+    ./tools/fiptool/fiptool update \
+        --tb-fw build/<platform>/release/bl2.bin \
+        build/<platform>/debug/fip.bin
+
+Example 4: unpack all entries from an existing Firmware package:
+
+.. code:: shell
+
+    # Images will be unpacked to the working directory
+    ./tools/fiptool/fiptool unpack <path-to>/fip.bin
+
+Example 5: remove an entry from an existing Firmware package:
+
+.. code:: shell
+
+    ./tools/fiptool/fiptool remove \
+        --tb-fw build/<platform>/debug/fip.bin
+
+Note that if the destination FIP file exists, the create, update and
+remove operations will automatically overwrite it.
+
+The unpack operation will fail if the images already exist at the
+destination. In that case, use -f or --force to continue.
+
+More information about FIP can be found in the :ref:`Firmware Design` document.
+
+.. _tools_build_cert_create:
+
+Building the Certificate Generation Tool
+----------------------------------------
+
+The ``cert_create`` tool is built as part of the TF-A build process when the
+``fip`` make target is specified and TBB is enabled (as described in the
+previous section), but it can also be built separately with the following
+command:
+
+.. code:: shell
+
+    make PLAT=<platform> [DEBUG=1] [V=1] certtool
+
+For platforms that require their own IDs in certificate files, the generic
+'cert_create' tool can be built with the following command. Note that the target
+platform must define its IDs within a ``platform_oid.h`` header file for the
+build to succeed.
+
+.. code:: shell
+
+    make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
+
+``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
+verbose. The following command should be used to obtain help about the tool:
+
+.. code:: shell
+
+    ./tools/cert_create/cert_create -h
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/getting_started/user-guide.rst b/docs/getting_started/user-guide.rst
deleted file mode 100644
index 9876531..0000000
--- a/docs/getting_started/user-guide.rst
+++ /dev/null
@@ -1,2214 +0,0 @@
-User Guide
-==========
-
-This document describes how to build Trusted Firmware-A (TF-A) and run it with a
-tested set of other software components using defined configurations on the Juno
-Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
-possible to use other software components, configurations and platforms but that
-is outside the scope of this document.
-
-This document assumes that the reader has previous experience running a fully
-bootable Linux software stack on Juno or FVP using the prebuilt binaries and
-filesystems provided by Linaro. Further information may be found in the
-`Linaro instructions`_. It also assumes that the user understands the role of
-the different software components required to boot a Linux system:
-
--  Specific firmware images required by the platform (e.g. SCP firmware on Juno)
--  Normal world bootloader (e.g. UEFI or U-Boot)
--  Device tree
--  Linux kernel image
--  Root filesystem
-
-This document also assumes that the user is familiar with the `FVP models`_ and
-the different command line options available to launch the model.
-
-This document should be used in conjunction with the :ref:`Firmware Design`.
-
-Host machine requirements
--------------------------
-
-The minimum recommended machine specification for building the software and
-running the FVP models is a dual-core processor running at 2GHz with 12GB of
-RAM. For best performance, use a machine with a quad-core processor running at
-2.6GHz with 16GB of RAM.
-
-The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
-building the software were installed from that distribution unless otherwise
-specified.
-
-The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
-Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
-
-Tools
------
-
-Install the required packages to build TF-A with the following command:
-
-.. code:: shell
-
-    sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
-
-Download and install the AArch32 (arm-eabi) or AArch64 little-endian
-(aarch64-linux-gnu) GCC 8.3-2019.03 cross compiler from `Arm Developer page`_.
-
-Optionally, TF-A can be built using clang version 4.0 or newer or Arm
-Compiler 6. See instructions below on how to switch the default compiler.
-
-In addition, the following optional packages and tools may be needed:
-
--  ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
-   Tree (FDT) source files (``.dts`` files) provided with this software. The
-   version of dtc must be 1.4.6 or above.
-
--  For debugging, Arm `Development Studio 5 (DS-5)`_.
-
--  To create and modify the diagram files included in the documentation, `Dia`_.
-   This tool can be found in most Linux distributions. Inkscape is needed to
-   generate the actual \*.png files.
-
-TF-A has been tested with pre-built binaries and file systems from
-`Linaro Release 19.06`_. Alternatively, you can build the binaries from
-source using instructions provided at the `Arm Platforms User guide`_.
-
-Getting the TF-A source code
-----------------------------
-
-Clone the repository from the Gerrit server. The project details may be found
-on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
-commit-msg hook`" clone method, which will setup the git commit hook that
-automatically generates and inserts appropriate `Change-Id:` lines in your
-commit messages.
-
-Checking source code style
-~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
-source, for submission to the project, the source must be in compliance with
-this style guide.
-
-Additional, project-specific guidelines are defined in the
-:ref:`Coding Style & Guidelines` document.
-
-To assist with coding style compliance, the project Makefile contains two
-targets which both utilise the `checkpatch.pl` script that ships with the Linux
-source tree. The project also defines certain *checkpatch* options in the
-``.checkpatch.conf`` file in the top-level directory.
-
-.. note::
-   Checkpatch errors will gate upstream merging of pull requests.
-   Checkpatch warnings will not gate merging but should be reviewed and fixed if
-   possible.
-
-To check the entire source tree, you must first download copies of
-``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
-in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
-environment variable to point to ``checkpatch.pl`` (with the other 2 files in
-the same directory) and build the `checkcodebase` target:
-
-.. code:: shell
-
-    make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
-
-To just check the style on the files that differ between your local branch and
-the remote master, use:
-
-.. code:: shell
-
-    make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
-
-If you wish to check your patch against something other than the remote master,
-set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
-is set to ``origin/master``.
-
-Building TF-A
--------------
-
--  Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
-   to the cross compiler.
-
-   For AArch64:
-
-   .. code:: shell
-
-       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
-
-   For AArch32:
-
-   .. code:: shell
-
-       export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
-
-   It is possible to build TF-A using Clang or Arm Compiler 6. To do so
-   ``CC`` needs to point to the clang or armclang binary, which will
-   also select the clang or armclang assembler. Be aware that the
-   GNU linker is used by default.  In case of being needed the linker
-   can be overridden using the ``LD`` variable. Clang linker version 6 is
-   known to work with TF-A.
-
-   In both cases ``CROSS_COMPILE`` should be set as described above.
-
-   Arm Compiler 6 will be selected when the base name of the path assigned
-   to ``CC`` matches the string 'armclang'.
-
-   For AArch64 using Arm Compiler 6:
-
-   .. code:: shell
-
-       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
-       make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
-
-   Clang will be selected when the base name of the path assigned to ``CC``
-   contains the string 'clang'. This is to allow both clang and clang-X.Y
-   to work.
-
-   For AArch64 using clang:
-
-   .. code:: shell
-
-       export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
-       make CC=<path-to-clang>/bin/clang PLAT=<platform> all
-
--  Change to the root directory of the TF-A source tree and build.
-
-   For AArch64:
-
-   .. code:: shell
-
-       make PLAT=<platform> all
-
-   For AArch32:
-
-   .. code:: shell
-
-       make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
-
-   Notes:
-
-   -  If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
-      `Summary of build options`_ for more information on available build
-      options.
-
-   -  (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
-      corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
-      provided by TF-A to demonstrate how PSCI Library can be integrated with
-      an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
-      include other runtime services, for example Trusted OS services. A guide
-      to integrate PSCI library with AArch32 EL3 Runtime Software can be found
-      at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
-
-   -  (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
-      image, is not compiled in by default. Refer to the
-      `Building the Test Secure Payload`_ section below.
-
-   -  By default this produces a release version of the build. To produce a
-      debug version instead, refer to the "Debugging options" section below.
-
-   -  The build process creates products in a ``build`` directory tree, building
-      the objects and binaries for each boot loader stage in separate
-      sub-directories. The following boot loader binary files are created
-      from the corresponding ELF files:
-
-      -  ``build/<platform>/<build-type>/bl1.bin``
-      -  ``build/<platform>/<build-type>/bl2.bin``
-      -  ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
-      -  ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
-
-      where ``<platform>`` is the name of the chosen platform and ``<build-type>``
-      is either ``debug`` or ``release``. The actual number of images might differ
-      depending on the platform.
-
--  Build products for a specific build variant can be removed using:
-
-   .. code:: shell
-
-       make DEBUG=<D> PLAT=<platform> clean
-
-   ... where ``<D>`` is ``0`` or ``1``, as specified when building.
-
-   The build tree can be removed completely using:
-
-   .. code:: shell
-
-       make realclean
-
-Summary of build options
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-The TF-A build system supports the following build options. Unless mentioned
-otherwise, these options are expected to be specified at the build command
-line and are not to be modified in any component makefiles. Note that the
-build system doesn't track dependency for build options. Therefore, if any of
-the build options are changed from a previous build, a clean build must be
-performed.
-
-Common build options
-^^^^^^^^^^^^^^^^^^^^
-
--  ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
-   compiler should use. Valid values are T32 and A32. It defaults to T32 due to
-   code having a smaller resulting size.
-
--  ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
-   as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
-   directory containing the SP source, relative to the ``bl32/``; the directory
-   is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
-
--  ``ARCH`` : Choose the target build architecture for TF-A. It can take either
-   ``aarch64`` or ``aarch32`` as values. By default, it is defined to
-   ``aarch64``.
-
--  ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
-   compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
-   *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
-   :ref:`Firmware Design`.
-
--  ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
-   compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
-   *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
-
--  ``BL2``: This is an optional build option which specifies the path to BL2
-   image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
-   built.
-
--  ``BL2U``: This is an optional build option which specifies the path to
-   BL2U image. In this case, the BL2U in TF-A will not be built.
-
--  ``BL2_AT_EL3``: This is an optional build option that enables the use of
-   BL2 at EL3 execution level.
-
--  ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
-   (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
-   the RW sections in RAM, while leaving the RO sections in place. This option
-   enable this use-case. For now, this option is only supported when BL2_AT_EL3
-   is set to '1'.
-
--  ``BL2_INV_DCACHE``: This is an optional build option which control dcache
-   invalidation upon BL2 entry. Some platform cannot handle cache operations
-   during entry as the coherency unit is not yet initialized. This may cause
-   crashing. Leaving this option to '1' (default) will allow the operation.
-   This option is only relevant when BL2_AT_EL3 is set to '1'.
-
--  ``BL31``: This is an optional build option which specifies the path to
-   BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
-   be built.
-
--  ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
-   file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
-   this file name will be used to save the key.
-
--  ``BL32``: This is an optional build option which specifies the path to
-   BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
-   be built.
-
--  ``BL32_EXTRA1``: This is an optional build option which specifies the path to
-   Trusted OS Extra1 image for the  ``fip`` target.
-
--  ``BL32_EXTRA2``: This is an optional build option which specifies the path to
-   Trusted OS Extra2 image for the ``fip`` target.
-
--  ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
-   file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
-   this file name will be used to save the key.
-
--  ``BL33``: Path to BL33 image in the host file system. This is mandatory for
-   ``fip`` target in case TF-A BL2 is used.
-
--  ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
-   file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
-   this file name will be used to save the key.
-
--  ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
-   and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
-   If enabled, it is needed to use a compiler (e.g GCC 9.1 and later versions) that
-   supports the option ``-mbranch-protection``.
-   Selects the branch protection features to use:
--  0: Default value turns off all types of branch protection
--  1: Enables all types of branch protection features
--  2: Return address signing to its standard level
--  3: Extend the signing to include leaf functions
-
-   The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
-   and resulting PAuth/BTI features.
-
-   +-------+--------------+-------+-----+
-   | Value |  GCC option  | PAuth | BTI |
-   +=======+==============+=======+=====+
-   |   0   |     none     |   N   |  N  |
-   +-------+--------------+-------+-----+
-   |   1   |   standard   |   Y   |  Y  |
-   +-------+--------------+-------+-----+
-   |   2   |   pac-ret    |   Y   |  N  |
-   +-------+--------------+-------+-----+
-   |   3   | pac-ret+leaf |   Y   |  N  |
-   +-------+--------------+-------+-----+
-
-   This option defaults to 0 and this is an experimental feature.
-   Note that Pointer Authentication is enabled for Non-secure world
-   irrespective of the value of this option if the CPU supports it.
-
--  ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
-   compilation of each build. It must be set to a C string (including quotes
-   where applicable). Defaults to a string that contains the time and date of
-   the compilation.
-
--  ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
-   build to be uniquely identified. Defaults to the current git commit id.
-
--  ``CFLAGS``: Extra user options appended on the compiler's command line in
-   addition to the options set by the build system.
-
--  ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
-   release several CPUs out of reset. It can take either 0 (several CPUs may be
-   brought up) or 1 (only one CPU will ever be brought up during cold reset).
-   Default is 0. If the platform always brings up a single CPU, there is no
-   need to distinguish between primary and secondary CPUs and the boot path can
-   be optimised. The ``plat_is_my_cpu_primary()`` and
-   ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
-   to be implemented in this case.
-
--  ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
-   register state when an unexpected exception occurs during execution of
-   BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
-   this is only enabled for a debug build of the firmware.
-
--  ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
-   certificate generation tool to create new keys in case no valid keys are
-   present or specified. Allowed options are '0' or '1'. Default is '1'.
-
--  ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
-   the AArch32 system registers to be included when saving and restoring the
-   CPU context. The option must be set to 0 for AArch64-only platforms (that
-   is on hardware that does not implement AArch32, or at least not at EL1 and
-   higher ELs). Default value is 1.
-
--  ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
-   registers to be included when saving and restoring the CPU context. Default
-   is 0.
-
--  ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
-   ARMv8.5 Memory Tagging Extension. A value of 0 will disable
-   saving/reloading and restrict the use of MTE to the normal world if the
-   CPU has support, while a value of 1 enables the saving/reloading, allowing
-   the use of MTE in both the secure and non-secure worlds. Default is 0
-   (disabled) and this feature is experimental.
-
--  ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
-   Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
-   registers to be included when saving and restoring the CPU context as
-   part of world switch. Default value is 0 and this is an experimental feature.
-   Note that Pointer Authentication is enabled for Non-secure world irrespective
-   of the value of this flag if the CPU supports it.
-
--  ``DEBUG``: Chooses between a debug and release build. It can take either 0
-   (release) or 1 (debug) as values. 0 is the default.
-
--  ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
-   of the binary image. If set to 1, then only the ELF image is built.
-   0 is the default.
-
--  ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
-   Board Boot authentication at runtime. This option is meant to be enabled only
-   for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
-   flag has to be enabled. 0 is the default.
-
--  ``E``: Boolean option to make warnings into errors. Default is 1.
-
--  ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
-   the normal boot flow. It must specify the entry point address of the EL3
-   payload. Please refer to the "Booting an EL3 payload" section for more
-   details.
-
--  ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
-   This is an optional architectural feature available on v8.4 onwards. Some
-   v8.2 implementations also implement an AMU and this option can be used to
-   enable this feature on those systems as well. Default is 0.
-
--  ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
-   are compiled out. For debug builds, this option defaults to 1, and calls to
-   ``assert()`` are left in place. For release builds, this option defaults to 0
-   and calls to ``assert()`` function are compiled out. This option can be set
-   independently of ``DEBUG``. It can also be used to hide any auxiliary code
-   that is only required for the assertion and does not fit in the assertion
-   itself.
-
--  ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
-   dumps or not. It is supported in both AArch64 and AArch32. However, in
-   AArch32 the format of the frame records are not defined in the AAPCS and they
-   are defined by the implementation. This implementation of backtrace only
-   supports the format used by GCC when T32 interworking is disabled. For this
-   reason enabling this option in AArch32 will force the compiler to only
-   generate A32 code. This option is enabled by default only in AArch64 debug
-   builds, but this behaviour can be overridden in each platform's Makefile or
-   in the build command line.
-
--  ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
-   feature. MPAM is an optional Armv8.4 extension that enables various memory
-   system components and resources to define partitions; software running at
-   various ELs can assign themselves to desired partition to control their
-   performance aspects.
-
-   When this option is set to ``1``, EL3 allows lower ELs to access their own
-   MPAM registers without trapping into EL3. This option doesn't make use of
-   partitioning in EL3, however. Platform initialisation code should configure
-   and use partitions in EL3 as required. This option defaults to ``0``.
-
--  ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
-   support within generic code in TF-A. This option is currently only supported
-   in BL31. Default is 0.
-
--  ``ENABLE_PMF``: Boolean option to enable support for optional Performance
-   Measurement Framework(PMF). Default is 0.
-
--  ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
-   functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
-   In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
-   be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
-   software.
-
--  ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
-   instrumentation which injects timestamp collection points into TF-A to
-   allow runtime performance to be measured. Currently, only PSCI is
-   instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
-   as well. Default is 0.
-
--  ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
-   extensions. This is an optional architectural feature for AArch64.
-   The default is 1 but is automatically disabled when the target architecture
-   is AArch32.
-
--  ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
-   Refer to :ref:`Secure Partition Manager` for more details about
-   this feature. Default is 0.
-
--  ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
-   (SVE) for the Non-secure world only. SVE is an optional architectural feature
-   for AArch64. Note that when SVE is enabled for the Non-secure world, access
-   to SIMD and floating-point functionality from the Secure world is disabled.
-   This is to avoid corruption of the Non-secure world data in the Z-registers
-   which are aliased by the SIMD and FP registers. The build option is not
-   compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
-   assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
-   1. The default is 1 but is automatically disabled when the target
-   architecture is AArch32.
-
--  ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
-   checks in GCC. Allowed values are "all", "strong", "default" and "none". The
-   default value is set to "none". "strong" is the recommended stack protection
-   level if this feature is desired. "none" disables the stack protection. For
-   all values other than "none", the ``plat_get_stack_protector_canary()``
-   platform hook needs to be implemented. The value is passed as the last
-   component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
-
--  ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
-   deprecated platform APIs, helper functions or drivers within Trusted
-   Firmware as error. It can take the value 1 (flag the use of deprecated
-   APIs as error) or 0. The default is 0.
-
--  ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
-   targeted at EL3. When set ``0`` (default), no exceptions are expected or
-   handled at EL3, and a panic will result. This is supported only for AArch64
-   builds.
-
--  ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
-   injection from lower ELs, and this build option enables lower ELs to use
-   Error Records accessed via System Registers to inject faults. This is
-   applicable only to AArch64 builds.
-
-   This feature is intended for testing purposes only, and is advisable to keep
-   disabled for production images.
-
--  ``FIP_NAME``: This is an optional build option which specifies the FIP
-   filename for the ``fip`` target. Default is ``fip.bin``.
-
--  ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
-   FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
-
--  ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
-   tool to create certificates as per the Chain of Trust described in
-   :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
-   include the certificates in the FIP and FWU_FIP. Default value is '0'.
-
-   Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
-   for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
-   the corresponding certificates, and to include those certificates in the
-   FIP and FWU_FIP.
-
-   Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
-   images will not include support for Trusted Board Boot. The FIP will still
-   include the corresponding certificates. This FIP can be used to verify the
-   Chain of Trust on the host machine through other mechanisms.
-
-   Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
-   images will include support for Trusted Board Boot, but the FIP and FWU_FIP
-   will not include the corresponding certificates, causing a boot failure.
-
--  ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
-   inherent support for specific EL3 type interrupts. Setting this build option
-   to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
-   by `platform abstraction layer`__ and `Interrupt Management Framework`__.
-   This allows GICv2 platforms to enable features requiring EL3 interrupt type.
-   This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
-   the Secure Payload interrupts needs to be synchronously handed over to Secure
-   EL1 for handling. The default value of this option is ``0``, which means the
-   Group 0 interrupts are assumed to be handled by Secure EL1.
-
-   .. __: `platform-interrupt-controller-API.rst`
-   .. __: `interrupt-framework-design.rst`
-
--  ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
-   Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
-   ``0`` (default), these exceptions will be trapped in the current exception
-   level (or in EL1 if the current exception level is EL0).
-
--  ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
-   software operations are required for CPUs to enter and exit coherency.
-   However, newer systems exist where CPUs' entry to and exit from coherency
-   is managed in hardware. Such systems require software to only initiate these
-   operations, and the rest is managed in hardware, minimizing active software
-   management. In such systems, this boolean option enables TF-A to carry out
-   build and run-time optimizations during boot and power management operations.
-   This option defaults to 0 and if it is enabled, then it implies
-   ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
-
-   If this flag is disabled while the platform which TF-A is compiled for
-   includes cores that manage coherency in hardware, then a compilation error is
-   generated. This is based on the fact that a system cannot have, at the same
-   time, cores that manage coherency in hardware and cores that don't. In other
-   words, a platform cannot have, at the same time, cores that require
-   ``HW_ASSISTED_COHERENCY=1`` and cores that require
-   ``HW_ASSISTED_COHERENCY=0``.
-
-   Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
-   translation library (xlat tables v2) must be used; version 1 of translation
-   library is not supported.
-
--  ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
-   runtime software in AArch32 mode, which is required to run AArch32 on Juno.
-   By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
-   AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
-   images.
-
--  ``KEY_ALG``: This build flag enables the user to select the algorithm to be
-   used for generating the PKCS keys and subsequent signing of the certificate.
-   It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag
-   is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
-
--  ``KEY_SIZE``: This build flag enables the user to select the key size for
-   the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
-   depend on the chosen algorithm.
-
-   +-----------+------------------------------------+
-   |  KEY_ALG  |        Possible key sizes          |
-   +===========+====================================+
-   |    rsa    |  1024, 2048 (default), 3072, 4096  |
-   +-----------+------------------------------------+
-   |   ecdsa   |            unavailable             |
-   +-----------+------------------------------------+
-
--  ``HASH_ALG``: This build flag enables the user to select the secure hash
-   algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
-   The default value of this flag is ``sha256``.
-
--  ``LDFLAGS``: Extra user options appended to the linkers' command line in
-   addition to the one set by the build system.
-
--  ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
-   output compiled into the build. This should be one of the following:
-
-   ::
-
-       0  (LOG_LEVEL_NONE)
-       10 (LOG_LEVEL_ERROR)
-       20 (LOG_LEVEL_NOTICE)
-       30 (LOG_LEVEL_WARNING)
-       40 (LOG_LEVEL_INFO)
-       50 (LOG_LEVEL_VERBOSE)
-
-   All log output up to and including the selected log level is compiled into
-   the build. The default value is 40 in debug builds and 20 in release builds.
-
--  ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
-   specifies the file that contains the Non-Trusted World private key in PEM
-   format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
-
--  ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
-   optional. It is only needed if the platform makefile specifies that it
-   is required in order to build the ``fwu_fip`` target.
-
--  ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
-   contents upon world switch. It can take either 0 (don't save and restore) or
-   1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
-   wants the timer registers to be saved and restored.
-
--  ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
-   for the BL image. It can be either 0 (include) or 1 (remove). The default
-   value is 0.
-
--  ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
-   the underlying hardware is not a full PL011 UART but a minimally compliant
-   generic UART, which is a subset of the PL011. The driver will not access
-   any register that is not part of the SBSA generic UART specification.
-   Default value is 0 (a full PL011 compliant UART is present).
-
--  ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
-   must be subdirectory of any depth under ``plat/``, and must contain a
-   platform makefile named ``platform.mk``. For example, to build TF-A for the
-   Arm Juno board, select PLAT=juno.
-
--  ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
-   instead of the normal boot flow. When defined, it must specify the entry
-   point address for the preloaded BL33 image. This option is incompatible with
-   ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
-   over ``PRELOADED_BL33_BASE``.
-
--  ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
-   vector address can be programmed or is fixed on the platform. It can take
-   either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
-   programmable reset address, it is expected that a CPU will start executing
-   code directly at the right address, both on a cold and warm reset. In this
-   case, there is no need to identify the entrypoint on boot and the boot path
-   can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
-   does not need to be implemented in this case.
-
--  ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
-   possible for the PSCI power-state parameter: original and extended State-ID
-   formats. This flag if set to 1, configures the generic PSCI layer to use the
-   extended format. The default value of this flag is 0, which means by default
-   the original power-state format is used by the PSCI implementation. This flag
-   should be specified by the platform makefile and it governs the return value
-   of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
-   enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
-   set to 1 as well.
-
--  ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
-   are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
-   or later CPUs.
-
-   When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
-   set to ``1``.
-
-   This option is disabled by default.
-
--  ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
-   of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
-   entrypoint) or 1 (CPU reset to BL31 entrypoint).
-   The default value is 0.
-
--  ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
-   in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
-   instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
-   entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
-
--  ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
-   file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
-   file name will be used to save the key.
-
--  ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It
-   can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap',
-   gcc and clang will insert calls to ``__builtin_trap`` on detected
-   undefined behaviour, which defaults to a ``brk`` instruction. When using
-   'on', undefined behaviour is translated to a call to special handlers which
-   prints the exact location of the problem and its cause and then panics.
-
-    .. note::
-        Because of the space penalty of the Undefined Behaviour sanitizer,
-        this option will increase the size of the binary. Depending on the
-        memory constraints of the target platform, it may not be possible to
-        enable the sanitizer for all images (BL1 and BL2 are especially
-        likely to be memory constrained). We recommend that the
-        sanitizer is enabled only in debug builds.
-
--  ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
-   certificate generation tool to save the keys used to establish the Chain of
-   Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
-
--  ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
-   If a SCP_BL2 image is present then this option must be passed for the ``fip``
-   target.
-
--  ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
-   file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
-   this file name will be used to save the key.
-
--  ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
-   optional. It is only needed if the platform makefile specifies that it
-   is required in order to build the ``fwu_fip`` target.
-
--  ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
-   Delegated Exception Interface to BL31 image. This defaults to ``0``.
-
-   When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
-   set to ``1``.
-
--  ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
-   isolated on separate memory pages. This is a trade-off between security and
-   memory usage. See "Isolating code and read-only data on separate memory
-   pages" section in :ref:`Firmware Design`. This flag is disabled by default
-   and affects all BL images.
-
--  ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
-   This build option is only valid if ``ARCH=aarch64``. The value should be
-   the path to the directory containing the SPD source, relative to
-   ``services/spd/``; the directory is expected to contain a makefile called
-   ``<spd-value>.mk``.
-
--  ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
-   take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
-   execution in BL1 just before handing over to BL31. At this point, all
-   firmware images have been loaded in memory, and the MMU and caches are
-   turned off. Refer to the "Debugging options" section for more details.
-
--  ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
-   secure interrupts (caught through the FIQ line). Platforms can enable
-   this directive if they need to handle such interruption. When enabled,
-   the FIQ are handled in monitor mode and non secure world is not allowed
-   to mask these events. Platforms that enable FIQ handling in SP_MIN shall
-   implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
-
--  ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
-   Boot feature. When set to '1', BL1 and BL2 images include support to load
-   and verify the certificates and images in a FIP, and BL1 includes support
-   for the Firmware Update. The default value is '0'. Generation and inclusion
-   of certificates in the FIP and FWU_FIP depends upon the value of the
-   ``GENERATE_COT`` option.
-
-   .. warning::
-      This option depends on ``CREATE_KEYS`` to be enabled. If the keys
-      already exist in disk, they will be overwritten without further notice.
-
--  ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
-   specifies the file that contains the Trusted World private key in PEM
-   format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
-
--  ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
-   synchronous, (see "Initializing a BL32 Image" section in
-   :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
-   synchronous method) or 1 (BL32 is initialized using asynchronous method).
-   Default is 0.
-
--  ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
-   routing model which routes non-secure interrupts asynchronously from TSP
-   to EL3 causing immediate preemption of TSP. The EL3 is responsible
-   for saving and restoring the TSP context in this routing model. The
-   default routing model (when the value is 0) is to route non-secure
-   interrupts to TSP allowing it to save its context and hand over
-   synchronously to EL3 via an SMC.
-
-   .. note::
-      When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
-      must also be set to ``1``.
-
--  ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
-   linker. When the ``LINKER`` build variable points to the armlink linker,
-   this flag is enabled automatically. To enable support for armlink, platforms
-   will have to provide a scatter file for the BL image. Currently, Tegra
-   platforms use the armlink support to compile BL3-1 images.
-
--  ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
-   memory region in the BL memory map or not (see "Use of Coherent memory in
-   TF-A" section in :ref:`Firmware Design`). It can take the value 1
-   (Coherent memory region is included) or 0 (Coherent memory region is
-   excluded). Default is 1.
-
--  ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
-   This feature creates a library of functions to be placed in ROM and thus
-   reduces SRAM usage. Refer to :ref:`Library at ROM` for further details.
-   Default is 0.
-
--  ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock
-    implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
-    Notice this option is experimental and only available to AArch64 builds.
-
--  ``V``: Verbose build. If assigned anything other than 0, the build commands
-   are printed. Default is 0.
-
--  ``VERSION_STRING``: String used in the log output for each TF-A image.
-   Defaults to a string formed by concatenating the version number, build type
-   and build string.
-
--  ``W``: Warning level. Some compiler warning options of interest have been
-   regrouped and put in the root Makefile. This flag can take the values 0 to 3,
-   each level enabling more warning options. Default is 0.
-
--  ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
-   the CPU after warm boot. This is applicable for platforms which do not
-   require interconnect programming to enable cache coherency (eg: single
-   cluster platforms). If this option is enabled, then warm boot path
-   enables D-caches immediately after enabling MMU. This option defaults to 0.
-
-Arm development platform specific build options
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
--  ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
-   DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
-   BL31 in TZC secured DRAM. If TSP is present, then setting this option also
-   sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
-   flag.
-
--  ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
-   frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
-   frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
-   match the frame used by the Non-Secure image (normally the Linux kernel).
-   Default is true (access to the frame is allowed).
-
--  ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
-   By default, Arm platforms use a watchdog to trigger a system reset in case
-   an error is encountered during the boot process (for example, when an image
-   could not be loaded or authenticated). The watchdog is enabled in the early
-   platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
-   Trusted Watchdog may be disabled at build time for testing or development
-   purposes.
-
--  ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
-   have specific values at boot. This boolean option allows the Trusted Firmware
-   to have a Linux kernel image as BL33 by preparing the registers to these
-   values before jumping to BL33. This option defaults to 0 (disabled). For
-   AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
-   using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
-   to the location of a device tree blob (DTB) already loaded in memory. The
-   Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
-   option.
-
--  ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
-   cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
-   is set, the functions which deal with MPIDR assume that the ``MT`` bit in
-   MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
-   this flag is 0. Note that this option is not used on FVP platforms.
-
--  ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
-   for the construction of composite state-ID in the power-state parameter.
-   The existing PSCI clients currently do not support this encoding of
-   State-ID yet. Hence this flag is used to configure whether to use the
-   recommended State-ID encoding or not. The default value of this flag is 0,
-   in which case the platform is configured to expect NULL in the State-ID
-   field of power-state parameter.
-
--  ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
-   location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
-   for Arm platforms. Depending on the selected option, the proper private key
-   must be specified using the ``ROT_KEY`` option when building the Trusted
-   Firmware. This private key will be used by the certificate generation tool
-   to sign the BL2 and Trusted Key certificates. Available options for
-   ``ARM_ROTPK_LOCATION`` are:
-
-   -  ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
-      registers. The private key corresponding to this ROTPK hash is not
-      currently available.
-   -  ``devel_rsa`` : return a development public key hash embedded in the BL1
-      and BL2 binaries. This hash has been obtained from the RSA public key
-      ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
-      this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
-      creating the certificates.
-   -  ``devel_ecdsa`` : return a development public key hash embedded in the BL1
-      and BL2 binaries. This hash has been obtained from the ECDSA public key
-      ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
-      this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
-      when creating the certificates.
-
--  ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
-
-   -  ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
-   -  ``tdram`` : Trusted DRAM (if available)
-   -  ``dram`` : Secure region in DRAM (default option when TBB is enabled,
-      configured by the TrustZone controller)
-
--  ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
-   of the translation tables library instead of version 2. It is set to 0 by
-   default, which selects version 2.
-
--  ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
-   TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
-   platforms. If this option is specified, then the path to the CryptoCell
-   SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
-
-For a better understanding of these options, the Arm development platform memory
-map is explained in the :ref:`Firmware Design`.
-
-Arm CSS platform specific build options
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
--  ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
-   incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
-   compatible change to the MTL protocol, used for AP/SCP communication.
-   TF-A no longer supports earlier SCP versions. If this option is set to 1
-   then TF-A will detect if an earlier version is in use. Default is 1.
-
--  ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
-   SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
-   during boot. Default is 1.
-
--  ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
-   instead of SCPI/BOM driver for communicating with the SCP during power
-   management operations and for SCP RAM Firmware transfer. If this option
-   is set to 1, then SCMI/SDS drivers will be used. Default is 0.
-
-Arm FVP platform specific build options
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
--  ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
-   build the topology tree within TF-A. By default TF-A is configured for dual
-   cluster topology and this option can be used to override the default value.
-
--  ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
-   default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
-   explained in the options below:
-
-   -  ``FVP_CCI`` : The CCI driver is selected. This is the default
-      if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
-   -  ``FVP_CCN`` : The CCN driver is selected. This is the default
-      if ``FVP_CLUSTER_COUNT`` > 2.
-
--  ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
-   a single cluster.  This option defaults to 4.
-
--  ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
-   in the system. This option defaults to 1. Note that the build option
-   ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
-
--  ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
-
-   -  ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
-   -  ``FVP_GICV2`` : The GICv2 only driver is selected
-   -  ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
-
--  ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
-   for functions that wait for an arbitrary time length (udelay and mdelay).
-   The default value is 0.
-
--  ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
-   to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
-   details on HW_CONFIG. By default, this is initialized to a sensible DTS
-   file in ``fdts/`` folder depending on other build options. But some cases,
-   like shifted affinity format for MPIDR, cannot be detected at build time
-   and this option is needed to specify the appropriate DTS file.
-
--  ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
-   FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
-   similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
-   HW_CONFIG blob instead of the DTS file. This option is useful to override
-   the default HW_CONFIG selected by the build system.
-
-ARM JUNO platform specific build options
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
--  ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
-   Media Protection (TZ-MP1). Default value of this flag is 0.
-
-Debugging options
-~~~~~~~~~~~~~~~~~
-
-To compile a debug version and make the build more verbose use
-
-.. code:: shell
-
-    make PLAT=<platform> DEBUG=1 V=1 all
-
-AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
-example DS-5) might not support this and may need an older version of DWARF
-symbols to be emitted by GCC. This can be achieved by using the
-``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
-version to 2 is recommended for DS-5 versions older than 5.16.
-
-When debugging logic problems it might also be useful to disable all compiler
-optimizations by using ``-O0``.
-
-.. warning::
-   Using ``-O0`` could cause output images to be larger and base addresses
-   might need to be recalculated (see the **Memory layout on Arm development
-   platforms** section in the :ref:`Firmware Design`).
-
-Extra debug options can be passed to the build system by setting ``CFLAGS`` or
-``LDFLAGS``:
-
-.. code:: shell
-
-    CFLAGS='-O0 -gdwarf-2'                                     \
-    make PLAT=<platform> DEBUG=1 V=1 all
-
-Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
-ignored as the linker is called directly.
-
-It is also possible to introduce an infinite loop to help in debugging the
-post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
-``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
-section. In this case, the developer may take control of the target using a
-debugger when indicated by the console output. When using DS-5, the following
-commands can be used:
-
-::
-
-    # Stop target execution
-    interrupt
-
-    #
-    # Prepare your debugging environment, e.g. set breakpoints
-    #
-
-    # Jump over the debug loop
-    set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
-
-    # Resume execution
-    continue
-
-Building the Test Secure Payload
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The TSP is coupled with a companion runtime service in the BL31 firmware,
-called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
-must be recompiled as well. For more information on SPs and SPDs, see the
-:ref:`Secure-EL1 Payloads and Dispatchers <firmware_design_sel1_spd>` section
-in the :ref:`Firmware Design` document.
-
-First clean the TF-A build directory to get rid of any previous BL31 binary.
-Then to build the TSP image use:
-
-.. code:: shell
-
-    make PLAT=<platform> SPD=tspd all
-
-An additional boot loader binary file is created in the ``build`` directory:
-
-::
-
-    build/<platform>/<build-type>/bl32.bin
-
-
-Building and using the FIP tool
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Firmware Image Package (FIP) is a packaging format used by TF-A to package
-firmware images in a single binary. The number and type of images that should
-be packed in a FIP is platform specific and may include TF-A images and other
-firmware images required by the platform. For example, most platforms require
-a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
-U-Boot).
-
-The TF-A build system provides the make target ``fip`` to create a FIP file
-for the specified platform using the FIP creation tool included in the TF-A
-project. Examples below show how to build a FIP file for FVP, packaging TF-A
-and BL33 images.
-
-For AArch64:
-
-.. code:: shell
-
-    make PLAT=fvp BL33=<path-to>/bl33.bin fip
-
-For AArch32:
-
-.. code:: shell
-
-    make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
-
-The resulting FIP may be found in:
-
-::
-
-    build/fvp/<build-type>/fip.bin
-
-For advanced operations on FIP files, it is also possible to independently build
-the tool and create or modify FIPs using this tool. To do this, follow these
-steps:
-
-It is recommended to remove old artifacts before building the tool:
-
-.. code:: shell
-
-    make -C tools/fiptool clean
-
-Build the tool:
-
-.. code:: shell
-
-    make [DEBUG=1] [V=1] fiptool
-
-The tool binary can be located in:
-
-::
-
-    ./tools/fiptool/fiptool
-
-Invoking the tool with ``help`` will print a help message with all available
-options.
-
-Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
-
-.. code:: shell
-
-    ./tools/fiptool/fiptool create \
-        --tb-fw build/<platform>/<build-type>/bl2.bin \
-        --soc-fw build/<platform>/<build-type>/bl31.bin \
-        fip.bin
-
-Example 2: view the contents of an existing Firmware package:
-
-.. code:: shell
-
-    ./tools/fiptool/fiptool info <path-to>/fip.bin
-
-Example 3: update the entries of an existing Firmware package:
-
-.. code:: shell
-
-    # Change the BL2 from Debug to Release version
-    ./tools/fiptool/fiptool update \
-        --tb-fw build/<platform>/release/bl2.bin \
-        build/<platform>/debug/fip.bin
-
-Example 4: unpack all entries from an existing Firmware package:
-
-.. code:: shell
-
-    # Images will be unpacked to the working directory
-    ./tools/fiptool/fiptool unpack <path-to>/fip.bin
-
-Example 5: remove an entry from an existing Firmware package:
-
-.. code:: shell
-
-    ./tools/fiptool/fiptool remove \
-        --tb-fw build/<platform>/debug/fip.bin
-
-Note that if the destination FIP file exists, the create, update and
-remove operations will automatically overwrite it.
-
-The unpack operation will fail if the images already exist at the
-destination. In that case, use -f or --force to continue.
-
-More information about FIP can be found in the :ref:`Firmware Design` document.
-
-Building FIP images with support for Trusted Board Boot
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Trusted Board Boot primarily consists of the following two features:
-
--  Image Authentication, described in :ref:`Trusted Board Boot`, and
--  Firmware Update, described in :ref:`Firmware Update (FWU)`
-
-The following steps should be followed to build FIP and (optionally) FWU_FIP
-images with support for these features:
-
-#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
-   modules by checking out a recent version of the `mbed TLS Repository`_. It
-   is important to use a version that is compatible with TF-A and fixes any
-   known security vulnerabilities. See `mbed TLS Security Center`_ for more
-   information. The latest version of TF-A is tested with tag
-   ``mbedtls-2.16.2``.
-
-   The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
-   source files the modules depend upon.
-   ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
-   options required to build the mbed TLS sources.
-
-   Note that the mbed TLS library is licensed under the Apache version 2.0
-   license. Using mbed TLS source code will affect the licensing of TF-A
-   binaries that are built using this library.
-
-#. To build the FIP image, ensure the following command line variables are set
-   while invoking ``make`` to build TF-A:
-
-   -  ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
-   -  ``TRUSTED_BOARD_BOOT=1``
-   -  ``GENERATE_COT=1``
-
-   In the case of Arm platforms, the location of the ROTPK hash must also be
-   specified at build time. Two locations are currently supported (see
-   ``ARM_ROTPK_LOCATION`` build option):
-
-   -  ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
-      root-key storage registers present in the platform. On Juno, this
-      registers are read-only. On FVP Base and Cortex models, the registers
-      are read-only, but the value can be specified using the command line
-      option ``bp.trusted_key_storage.public_key`` when launching the model.
-      On both Juno and FVP models, the default value corresponds to an
-      ECDSA-SECP256R1 public key hash, whose private part is not currently
-      available.
-
-   -  ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
-      in the Arm platform port. The private/public RSA key pair may be
-      found in ``plat/arm/board/common/rotpk``.
-
-   -  ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
-      in the Arm platform port. The private/public ECDSA key pair may be
-      found in ``plat/arm/board/common/rotpk``.
-
-   Example of command line using RSA development keys:
-
-   .. code:: shell
-
-       MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
-       make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1        \
-       ARM_ROTPK_LOCATION=devel_rsa                                    \
-       ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem        \
-       BL33=<path-to>/<bl33_image>                                     \
-       all fip
-
-   The result of this build will be the bl1.bin and the fip.bin binaries. This
-   FIP will include the certificates corresponding to the Chain of Trust
-   described in the TBBR-client document. These certificates can also be found
-   in the output build directory.
-
-#. The optional FWU_FIP contains any additional images to be loaded from
-   Non-Volatile storage during the :ref:`Firmware Update (FWU)` process. To
-   build the FWU_FIP, any FWU images required by the platform must be specified
-   on the command line. On Arm development platforms like Juno, these are:
-
-   -  NS_BL2U. The AP non-secure Firmware Updater image.
-   -  SCP_BL2U. The SCP Firmware Update Configuration image.
-
-   Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
-   targets using RSA development:
-
-   ::
-
-       MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
-       make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1              \
-       ARM_ROTPK_LOCATION=devel_rsa                                    \
-       ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem        \
-       BL33=<path-to>/<bl33_image>                                     \
-       SCP_BL2=<path-to>/<scp_bl2_image>                               \
-       SCP_BL2U=<path-to>/<scp_bl2u_image>                             \
-       NS_BL2U=<path-to>/<ns_bl2u_image>                               \
-       all fip fwu_fip
-
-   .. note::
-      The BL2U image will be built by default and added to the FWU_FIP.
-      The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
-      to the command line above.
-
-   .. note::
-      Building and installing the non-secure and SCP FWU images (NS_BL1U,
-      NS_BL2U and SCP_BL2U) is outside the scope of this document.
-
-   The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
-   Both the FIP and FWU_FIP will include the certificates corresponding to the
-   Chain of Trust described in the TBBR-client document. These certificates
-   can also be found in the output build directory.
-
-Building the Certificate Generation Tool
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The ``cert_create`` tool is built as part of the TF-A build process when the
-``fip`` make target is specified and TBB is enabled (as described in the
-previous section), but it can also be built separately with the following
-command:
-
-.. code:: shell
-
-    make PLAT=<platform> [DEBUG=1] [V=1] certtool
-
-For platforms that require their own IDs in certificate files, the generic
-'cert_create' tool can be built with the following command. Note that the target
-platform must define its IDs within a ``platform_oid.h`` header file for the
-build to succeed.
-
-.. code:: shell
-
-    make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
-
-``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
-verbose. The following command should be used to obtain help about the tool:
-
-.. code:: shell
-
-    ./tools/cert_create/cert_create -h
-
-Building a FIP for Juno and FVP
--------------------------------
-
-This section provides Juno and FVP specific instructions to build Trusted
-Firmware, obtain the additional required firmware, and pack it all together in
-a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
-
-.. note::
-   Pre-built binaries for AArch32 are available from Linaro Release 16.12
-   onwards. Before that release, pre-built binaries are only available for
-   AArch64.
-
-.. warning::
-   Follow the full instructions for one platform before switching to a
-   different one. Mixing instructions for different platforms may result in
-   corrupted binaries.
-
-.. warning::
-   The uboot image downloaded by the Linaro workspace script does not always
-   match the uboot image packaged as BL33 in the corresponding fip file. It is
-   recommended to use the version that is packaged in the fip file using the
-   instructions below.
-
-.. note::
-   For the FVP, the kernel FDT is packaged in FIP during build and loaded
-   by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
-   section for more info on selecting the right FDT to use.
-
-#. Clean the working directory
-
-   .. code:: shell
-
-       make realclean
-
-#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
-
-   Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
-   package included in the Linaro release:
-
-   .. code:: shell
-
-       # Build the fiptool
-       make [DEBUG=1] [V=1] fiptool
-
-       # Unpack firmware images from Linaro FIP
-       ./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
-
-   The unpack operation will result in a set of binary images extracted to the
-   current working directory. The SCP_BL2 image corresponds to
-   ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
-
-   .. note::
-      The fiptool will complain if the images to be unpacked already
-      exist in the current directory. If that is the case, either delete those
-      files or use the ``--force`` option to overwrite.
-
-   .. note::
-      For AArch32, the instructions below assume that nt-fw.bin is a
-      normal world boot loader that supports AArch32.
-
-#. Build TF-A images and create a new FIP for FVP
-
-   .. code:: shell
-
-       # AArch64
-       make PLAT=fvp BL33=nt-fw.bin all fip
-
-       # AArch32
-       make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
-
-#. Build TF-A images and create a new FIP for Juno
-
-   For AArch64:
-
-   Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
-   as a build parameter.
-
-   .. code:: shell
-
-       make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
-
-   For AArch32:
-
-   Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
-   therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
-   separately for AArch32.
-
-   -  Before building BL32, the environment variable ``CROSS_COMPILE`` must point
-      to the AArch32 cross compiler.
-
-      .. code:: shell
-
-          export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
-
-   -  Build BL32 in AArch32.
-
-      .. code:: shell
-
-          make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
-          RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
-
-   -  Save ``bl32.bin`` to a temporary location and clean the build products.
-
-      ::
-
-          cp <path-to-build>/bl32.bin <path-to-temporary>
-          make realclean
-
-   -  Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
-      must point to the AArch64 cross compiler.
-
-      .. code:: shell
-
-          export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
-
-   -  The following parameters should be used to build BL1 and BL2 in AArch64
-      and point to the BL32 file.
-
-      .. code:: shell
-
-          make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
-          BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
-          BL32=<path-to-temporary>/bl32.bin all fip
-
-The resulting BL1 and FIP images may be found in:
-
-::
-
-    # Juno
-    ./build/juno/release/bl1.bin
-    ./build/juno/release/fip.bin
-
-    # FVP
-    ./build/fvp/release/bl1.bin
-    ./build/fvp/release/fip.bin
-
-
-Booting Firmware Update images
--------------------------------------
-
-When Firmware Update (FWU) is enabled there are at least 2 new images
-that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
-FWU FIP.
-
-Juno
-~~~~
-
-The new images must be programmed in flash memory by adding
-an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
-on the Juno SD card (where ``x`` depends on the revision of the Juno board).
-Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
-programming" for more information. User should ensure these do not
-overlap with any other entries in the file.
-
-::
-
-	NOR10UPDATE: AUTO                       ;Image Update:NONE/AUTO/FORCE
-	NOR10ADDRESS: 0x00400000                ;Image Flash Address [ns_bl2u_base_address]
-	NOR10FILE: \SOFTWARE\fwu_fip.bin        ;Image File Name
-	NOR10LOAD: 00000000                     ;Image Load Address
-	NOR10ENTRY: 00000000                    ;Image Entry Point
-
-	NOR11UPDATE: AUTO                       ;Image Update:NONE/AUTO/FORCE
-	NOR11ADDRESS: 0x03EB8000                ;Image Flash Address [ns_bl1u_base_address]
-	NOR11FILE: \SOFTWARE\ns_bl1u.bin        ;Image File Name
-	NOR11LOAD: 00000000                     ;Image Load Address
-
-The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
-In the same way, the address ns_bl2u_base_address is the value of
-NS_BL2U_BASE - 0x8000000.
-
-FVP
-~~~
-
-The additional fip images must be loaded with:
-
-::
-
-    --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000	[ns_bl1u_base_address]
-    --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000	[ns_bl2u_base_address]
-
-The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
-In the same way, the address ns_bl2u_base_address is the value of
-NS_BL2U_BASE.
-
-
-EL3 payloads alternative boot flow
-----------------------------------
-
-On a pre-production system, the ability to execute arbitrary, bare-metal code at
-the highest exception level is required. It allows full, direct access to the
-hardware, for example to run silicon soak tests.
-
-Although it is possible to implement some baremetal secure firmware from
-scratch, this is a complex task on some platforms, depending on the level of
-configuration required to put the system in the expected state.
-
-Rather than booting a baremetal application, a possible compromise is to boot
-``EL3 payloads`` through TF-A instead. This is implemented as an alternative
-boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
-other BL images and passing control to BL31. It reduces the complexity of
-developing EL3 baremetal code by:
-
--  putting the system into a known architectural state;
--  taking care of platform secure world initialization;
--  loading the SCP_BL2 image if required by the platform.
-
-When booting an EL3 payload on Arm standard platforms, the configuration of the
-TrustZone controller is simplified such that only region 0 is enabled and is
-configured to permit secure access only. This gives full access to the whole
-DRAM to the EL3 payload.
-
-The system is left in the same state as when entering BL31 in the default boot
-flow. In particular:
-
--  Running in EL3;
--  Current state is AArch64;
--  Little-endian data access;
--  All exceptions disabled;
--  MMU disabled;
--  Caches disabled.
-
-Booting an EL3 payload
-~~~~~~~~~~~~~~~~~~~~~~
-
-The EL3 payload image is a standalone image and is not part of the FIP. It is
-not loaded by TF-A. Therefore, there are 2 possible scenarios:
-
--  The EL3 payload may reside in non-volatile memory (NVM) and execute in
-   place. In this case, booting it is just a matter of specifying the right
-   address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
-
--  The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
-   run-time.
-
-To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
-used. The infinite loop that it introduces in BL1 stops execution at the right
-moment for a debugger to take control of the target and load the payload (for
-example, over JTAG).
-
-It is expected that this loading method will work in most cases, as a debugger
-connection is usually available in a pre-production system. The user is free to
-use any other platform-specific mechanism to load the EL3 payload, though.
-
-Booting an EL3 payload on FVP
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
-the secondary CPUs holding pen to work properly. Unfortunately, its reset value
-is undefined on the FVP platform and the FVP platform code doesn't clear it.
-Therefore, one must modify the way the model is normally invoked in order to
-clear the mailbox at start-up.
-
-One way to do that is to create an 8-byte file containing all zero bytes using
-the following command:
-
-.. code:: shell
-
-    dd if=/dev/zero of=mailbox.dat bs=1 count=8
-
-and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
-using the following model parameters:
-
-::
-
-    --data cluster0.cpu0=mailbox.dat@0x04000000   [Base FVPs]
-    --data=mailbox.dat@0x04000000                 [Foundation FVP]
-
-To provide the model with the EL3 payload image, the following methods may be
-used:
-
-#. If the EL3 payload is able to execute in place, it may be programmed into
-   flash memory. On Base Cortex and AEM FVPs, the following model parameter
-   loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
-   used for the FIP):
-
-   ::
-
-       -C bp.flashloader1.fname="<path-to>/<el3-payload>"
-
-   On Foundation FVP, there is no flash loader component and the EL3 payload
-   may be programmed anywhere in flash using method 3 below.
-
-#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
-   command may be used to load the EL3 payload ELF image over JTAG:
-
-   ::
-
-       load <path-to>/el3-payload.elf
-
-#. The EL3 payload may be pre-loaded in volatile memory using the following
-   model parameters:
-
-   ::
-
-       --data cluster0.cpu0="<path-to>/el3-payload>"@address   [Base FVPs]
-       --data="<path-to>/<el3-payload>"@address                [Foundation FVP]
-
-   The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
-   used when building TF-A.
-
-Booting an EL3 payload on Juno
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-If the EL3 payload is able to execute in place, it may be programmed in flash
-memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
-on the Juno SD card (where ``x`` depends on the revision of the Juno board).
-Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
-programming" for more information.
-
-Alternatively, the same DS-5 command mentioned in the FVP section above can
-be used to load the EL3 payload's ELF file over JTAG on Juno.
-
-Preloaded BL33 alternative boot flow
-------------------------------------
-
-Some platforms have the ability to preload BL33 into memory instead of relying
-on TF-A to load it. This may simplify packaging of the normal world code and
-improve performance in a development environment. When secure world cold boot
-is complete, TF-A simply jumps to a BL33 base address provided at build time.
-
-For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
-used when compiling TF-A. For example, the following command will create a FIP
-without a BL33 and prepare to jump to a BL33 image loaded at address
-0x80000000:
-
-.. code:: shell
-
-    make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
-
-Boot of a preloaded kernel image on Base FVP
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following example uses a simplified boot flow by directly jumping from the
-TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
-useful if both the kernel and the device tree blob (DTB) are already present in
-memory (like in FVP).
-
-For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
-address ``0x82000000``, the firmware can be built like this:
-
-.. code:: shell
-
-    CROSS_COMPILE=aarch64-linux-gnu-  \
-    make PLAT=fvp DEBUG=1             \
-    RESET_TO_BL31=1                   \
-    ARM_LINUX_KERNEL_AS_BL33=1        \
-    PRELOADED_BL33_BASE=0x80080000    \
-    ARM_PRELOADED_DTB_BASE=0x82000000 \
-    all fip
-
-Now, it is needed to modify the DTB so that the kernel knows the address of the
-ramdisk. The following script generates a patched DTB from the provided one,
-assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
-script assumes that the user is using a ramdisk image prepared for U-Boot, like
-the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
-offset in ``INITRD_START`` has to be removed.
-
-.. code:: bash
-
-    #!/bin/bash
-
-    # Path to the input DTB
-    KERNEL_DTB=<path-to>/<fdt>
-    # Path to the output DTB
-    PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
-    # Base address of the ramdisk
-    INITRD_BASE=0x84000000
-    # Path to the ramdisk
-    INITRD=<path-to>/<ramdisk.img>
-
-    # Skip uboot header (64 bytes)
-    INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
-    INITRD_SIZE=$(stat -Lc %s ${INITRD})
-    INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
-
-    CHOSEN_NODE=$(echo                                        \
-    "/ {                                                      \
-            chosen {                                          \
-                    linux,initrd-start = <${INITRD_START}>;   \
-                    linux,initrd-end = <${INITRD_END}>;       \
-            };                                                \
-    };")
-
-    echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} |  \
-            dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
-
-And the FVP binary can be run with the following command:
-
-.. code:: shell
-
-    <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
-    -C pctl.startup=0.0.0.0                                     \
-    -C bp.secure_memory=1                                       \
-    -C cluster0.NUM_CORES=4                                     \
-    -C cluster1.NUM_CORES=4                                     \
-    -C cache_state_modelled=1                                   \
-    -C cluster0.cpu0.RVBAR=0x04020000                           \
-    -C cluster0.cpu1.RVBAR=0x04020000                           \
-    -C cluster0.cpu2.RVBAR=0x04020000                           \
-    -C cluster0.cpu3.RVBAR=0x04020000                           \
-    -C cluster1.cpu0.RVBAR=0x04020000                           \
-    -C cluster1.cpu1.RVBAR=0x04020000                           \
-    -C cluster1.cpu2.RVBAR=0x04020000                           \
-    -C cluster1.cpu3.RVBAR=0x04020000                           \
-    --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000        \
-    --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000   \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-    --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
-
-Boot of a preloaded kernel image on Juno
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The Trusted Firmware must be compiled in a similar way as for FVP explained
-above. The process to load binaries to memory is the one explained in
-`Booting an EL3 payload on Juno`_.
-
-.. _user_guide_run_fvp:
-
-Running the software on FVP
----------------------------
-
-The latest version of the AArch64 build of TF-A has been tested on the following
-Arm FVPs without shifted affinities, and that do not support threaded CPU cores
-(64-bit host machine only).
-
-.. note::
-   The FVP models used are Version 11.6 Build 45, unless otherwise stated.
-
--  ``FVP_Base_AEMv8A-AEMv8A``
--  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
--  ``FVP_Base_RevC-2xAEMv8A``
--  ``FVP_Base_Cortex-A32x4``
--  ``FVP_Base_Cortex-A35x4``
--  ``FVP_Base_Cortex-A53x4``
--  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
--  ``FVP_Base_Cortex-A55x4``
--  ``FVP_Base_Cortex-A57x1-A53x1``
--  ``FVP_Base_Cortex-A57x2-A53x4``
--  ``FVP_Base_Cortex-A57x4-A53x4``
--  ``FVP_Base_Cortex-A57x4``
--  ``FVP_Base_Cortex-A72x4-A53x4``
--  ``FVP_Base_Cortex-A72x4``
--  ``FVP_Base_Cortex-A73x4-A53x4``
--  ``FVP_Base_Cortex-A73x4``
--  ``FVP_Base_Cortex-A75x4``
--  ``FVP_Base_Cortex-A76x4``
--  ``FVP_Base_Cortex-A76AEx4``
--  ``FVP_Base_Cortex-A76AEx8``
--  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
--  ``FVP_Base_Neoverse-N1x4``
--  ``FVP_Base_Zeusx4``
--  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
--  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
--  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
--  ``FVP_RD_N1Edge``
--  ``Foundation_Platform``
-
-The latest version of the AArch32 build of TF-A has been tested on the following
-Arm FVPs without shifted affinities, and that do not support threaded CPU cores
-(64-bit host machine only).
-
--  ``FVP_Base_AEMv8A-AEMv8A``
--  ``FVP_Base_Cortex-A32x4``
-
-.. note::
-   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
-   is not compatible with legacy GIC configurations. Therefore this FVP does not
-   support these legacy GIC configurations.
-
-.. note::
-   The build numbers quoted above are those reported by launching the FVP
-   with the ``--version`` parameter.
-
-.. note::
-   Linaro provides a ramdisk image in prebuilt FVP configurations and full
-   file systems that can be downloaded separately. To run an FVP with a virtio
-   file system image an additional FVP configuration option
-   ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
-   used.
-
-.. note::
-   The software will not work on Version 1.0 of the Foundation FVP.
-   The commands below would report an ``unhandled argument`` error in this case.
-
-.. note::
-   FVPs can be launched with ``--cadi-server`` option such that a
-   CADI-compliant debugger (for example, Arm DS-5) can connect to and control
-   its execution.
-
-.. warning::
-   Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
-   the internal synchronisation timings changed compared to older versions of
-   the models. The models can be launched with ``-Q 100`` option if they are
-   required to match the run time characteristics of the older versions.
-
-The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
-downloaded for free from `Arm's website`_.
-
-The Cortex-A models listed above are also available to download from
-`Arm's website`_.
-
-Please refer to the FVP documentation for a detailed description of the model
-parameter options. A brief description of the important ones that affect TF-A
-and normal world software behavior is provided below.
-
-Obtaining the Flattened Device Trees
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Depending on the FVP configuration and Linux configuration used, different
-FDT files are required. FDT source files for the Foundation and Base FVPs can
-be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
-a subset of the Base FVP components. For example, the Foundation FVP lacks
-CLCD and MMC support, and has only one CPU cluster.
-
-.. note::
-   It is not recommended to use the FDTs built along the kernel because not
-   all FDTs are available from there.
-
-The dynamic configuration capability is enabled in the firmware for FVPs.
-This means that the firmware can authenticate and load the FDT if present in
-FIP. A default FDT is packaged into FIP during the build based on
-the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
-or ``FVP_HW_CONFIG_DTS`` build options (refer to the
-`Arm FVP platform specific build options`_ section for detail on the options).
-
--  ``fvp-base-gicv2-psci.dts``
-
-   For use with models such as the Cortex-A57-A53 Base FVPs without shifted
-   affinities and with Base memory map configuration.
-
--  ``fvp-base-gicv2-psci-aarch32.dts``
-
-   For use with models such as the Cortex-A32 Base FVPs without shifted
-   affinities and running Linux in AArch32 state with Base memory map
-   configuration.
-
--  ``fvp-base-gicv3-psci.dts``
-
-   For use with models such as the Cortex-A57-A53 Base FVPs without shifted
-   affinities and with Base memory map configuration and Linux GICv3 support.
-
--  ``fvp-base-gicv3-psci-1t.dts``
-
-   For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
-   single threaded CPUs, Base memory map configuration and Linux GICv3 support.
-
--  ``fvp-base-gicv3-psci-dynamiq.dts``
-
-   For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
-   single cluster, single threaded CPUs, Base memory map configuration and Linux
-   GICv3 support.
-
--  ``fvp-base-gicv3-psci-aarch32.dts``
-
-   For use with models such as the Cortex-A32 Base FVPs without shifted
-   affinities and running Linux in AArch32 state with Base memory map
-   configuration and Linux GICv3 support.
-
--  ``fvp-foundation-gicv2-psci.dts``
-
-   For use with Foundation FVP with Base memory map configuration.
-
--  ``fvp-foundation-gicv3-psci.dts``
-
-   (Default) For use with Foundation FVP with Base memory map configuration
-   and Linux GICv3 support.
-
-Running on the Foundation FVP with reset to BL1 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``Foundation_Platform`` parameters should be used to boot Linux with
-4 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/Foundation_Platform                   \
-    --cores=4                                       \
-    --arm-v8.0                                      \
-    --secure-memory                                 \
-    --visualization                                 \
-    --gicv3                                         \
-    --data="<path-to>/<bl1-binary>"@0x0             \
-    --data="<path-to>/<FIP-binary>"@0x08000000      \
-    --data="<path-to>/<kernel-binary>"@0x80080000   \
-    --data="<path-to>/<ramdisk-binary>"@0x84000000
-
-Notes:
-
--  BL1 is loaded at the start of the Trusted ROM.
--  The Firmware Image Package is loaded at the start of NOR FLASH0.
--  The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
-   is specified via the ``hw_config_addr`` property in ``TB_FW_CONFIG`` for FVP.
--  The default use-case for the Foundation FVP is to use the ``--gicv3`` option
-   and enable the GICv3 device in the model. Note that without this option,
-   the Foundation FVP defaults to legacy (Versatile Express) memory map which
-   is not supported by TF-A.
--  In order for TF-A to run correctly on the Foundation FVP, the architecture
-   versions must match. The Foundation FVP defaults to the highest v8.x
-   version it supports but the default build for TF-A is for v8.0. To avoid
-   issues either start the Foundation FVP to use v8.0 architecture using the
-   ``--arm-v8.0`` option, or build TF-A with an appropriate value for
-   ``ARM_ARCH_MINOR``.
-
-Running on the AEMv8 Base FVP with reset to BL1 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_RevC-2xAEMv8A                            \
-    -C pctl.startup=0.0.0.0                                     \
-    -C bp.secure_memory=1                                       \
-    -C bp.tzc_400.diagnostics=1                                 \
-    -C cluster0.NUM_CORES=4                                     \
-    -C cluster1.NUM_CORES=4                                     \
-    -C cache_state_modelled=1                                   \
-    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
-    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-.. note::
-   The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
-   a specific DTS for all the CPUs to be loaded.
-
-Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
-    -C pctl.startup=0.0.0.0                                     \
-    -C bp.secure_memory=1                                       \
-    -C bp.tzc_400.diagnostics=1                                 \
-    -C cluster0.NUM_CORES=4                                     \
-    -C cluster1.NUM_CORES=4                                     \
-    -C cache_state_modelled=1                                   \
-    -C cluster0.cpu0.CONFIG64=0                                 \
-    -C cluster0.cpu1.CONFIG64=0                                 \
-    -C cluster0.cpu2.CONFIG64=0                                 \
-    -C cluster0.cpu3.CONFIG64=0                                 \
-    -C cluster1.cpu0.CONFIG64=0                                 \
-    -C cluster1.cpu1.CONFIG64=0                                 \
-    -C cluster1.cpu2.CONFIG64=0                                 \
-    -C cluster1.cpu3.CONFIG64=0                                 \
-    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
-    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
-boot Linux with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_Cortex-A57x4-A53x4                       \
-    -C pctl.startup=0.0.0.0                                     \
-    -C bp.secure_memory=1                                       \
-    -C bp.tzc_400.diagnostics=1                                 \
-    -C cache_state_modelled=1                                   \
-    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
-    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
-boot Linux with 4 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_Cortex-A32x4                             \
-    -C pctl.startup=0.0.0.0                                     \
-    -C bp.secure_memory=1                                       \
-    -C bp.tzc_400.diagnostics=1                                 \
-    -C cache_state_modelled=1                                   \
-    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
-    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the AEMv8 Base FVP with reset to BL31 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_RevC-2xAEMv8A                             \
-    -C pctl.startup=0.0.0.0                                      \
-    -C bp.secure_memory=1                                        \
-    -C bp.tzc_400.diagnostics=1                                  \
-    -C cluster0.NUM_CORES=4                                      \
-    -C cluster1.NUM_CORES=4                                      \
-    -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.RVBAR=0x04010000                            \
-    -C cluster0.cpu1.RVBAR=0x04010000                            \
-    -C cluster0.cpu2.RVBAR=0x04010000                            \
-    -C cluster0.cpu3.RVBAR=0x04010000                            \
-    -C cluster1.cpu0.RVBAR=0x04010000                            \
-    -C cluster1.cpu1.RVBAR=0x04010000                            \
-    -C cluster1.cpu2.RVBAR=0x04010000                            \
-    -C cluster1.cpu3.RVBAR=0x04010000                            \
-    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000    \
-    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000    \
-    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
-    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Notes:
-
--  If Position Independent Executable (PIE) support is enabled for BL31
-   in this config, it can be loaded at any valid address for execution.
-
--  Since a FIP is not loaded when using BL31 as reset entrypoint, the
-   ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
-   parameter is needed to load the individual bootloader images in memory.
-   BL32 image is only needed if BL31 has been built to expect a Secure-EL1
-   Payload. For the same reason, the FDT needs to be compiled from the DT source
-   and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
-   parameter.
-
--  The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
-   specific DTS for all the CPUs to be loaded.
-
--  The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
-   X and Y are the cluster and CPU numbers respectively, is used to set the
-   reset vector for each core.
-
--  Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
-   changing the value of
-   ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
-   ``BL32_BASE``.
-
-Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
-with 8 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_AEMv8A-AEMv8A                             \
-    -C pctl.startup=0.0.0.0                                      \
-    -C bp.secure_memory=1                                        \
-    -C bp.tzc_400.diagnostics=1                                  \
-    -C cluster0.NUM_CORES=4                                      \
-    -C cluster1.NUM_CORES=4                                      \
-    -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.CONFIG64=0                                  \
-    -C cluster0.cpu1.CONFIG64=0                                  \
-    -C cluster0.cpu2.CONFIG64=0                                  \
-    -C cluster0.cpu3.CONFIG64=0                                  \
-    -C cluster1.cpu0.CONFIG64=0                                  \
-    -C cluster1.cpu1.CONFIG64=0                                  \
-    -C cluster1.cpu2.CONFIG64=0                                  \
-    -C cluster1.cpu3.CONFIG64=0                                  \
-    -C cluster0.cpu0.RVBAR=0x04002000                            \
-    -C cluster0.cpu1.RVBAR=0x04002000                            \
-    -C cluster0.cpu2.RVBAR=0x04002000                            \
-    -C cluster0.cpu3.RVBAR=0x04002000                            \
-    -C cluster1.cpu0.RVBAR=0x04002000                            \
-    -C cluster1.cpu1.RVBAR=0x04002000                            \
-    -C cluster1.cpu2.RVBAR=0x04002000                            \
-    -C cluster1.cpu3.RVBAR=0x04002000                            \
-    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000    \
-    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
-    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-.. note::
-   The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
-   It should match the address programmed into the RVBAR register as well.
-
-Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
-boot Linux with 8 CPUs using the AArch64 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_Cortex-A57x4-A53x4                        \
-    -C pctl.startup=0.0.0.0                                      \
-    -C bp.secure_memory=1                                        \
-    -C bp.tzc_400.diagnostics=1                                  \
-    -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.RVBARADDR=0x04010000                        \
-    -C cluster0.cpu1.RVBARADDR=0x04010000                        \
-    -C cluster0.cpu2.RVBARADDR=0x04010000                        \
-    -C cluster0.cpu3.RVBARADDR=0x04010000                        \
-    -C cluster1.cpu0.RVBARADDR=0x04010000                        \
-    -C cluster1.cpu1.RVBARADDR=0x04010000                        \
-    -C cluster1.cpu2.RVBARADDR=0x04010000                        \
-    -C cluster1.cpu3.RVBARADDR=0x04010000                        \
-    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000    \
-    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000    \
-    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
-    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
-boot Linux with 4 CPUs using the AArch32 build of TF-A.
-
-.. code:: shell
-
-    <path-to>/FVP_Base_Cortex-A32x4                             \
-    -C pctl.startup=0.0.0.0                                     \
-    -C bp.secure_memory=1                                       \
-    -C bp.tzc_400.diagnostics=1                                 \
-    -C cache_state_modelled=1                                   \
-    -C cluster0.cpu0.RVBARADDR=0x04002000                       \
-    -C cluster0.cpu1.RVBARADDR=0x04002000                       \
-    -C cluster0.cpu2.RVBARADDR=0x04002000                       \
-    -C cluster0.cpu3.RVBARADDR=0x04002000                       \
-    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000   \
-    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000   \
-    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000           \
-    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-
-Running the software on Juno
-----------------------------
-
-This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
-
-To execute the software stack on Juno, installing the latest Arm Platforms
-software deliverables is recommended. Please install the deliverables by
-following the `Instructions for using Linaro's deliverables on Juno`_.
-
-Preparing TF-A images
-~~~~~~~~~~~~~~~~~~~~~
-
-After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
-``SOFTWARE/`` directory of the Juno SD card.
-
-Other Juno software information
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
-software information. Please also refer to the `Juno Getting Started Guide`_ to
-get more detailed information about the Juno Arm development platform and how to
-configure it.
-
-Testing SYSTEM SUSPEND on Juno
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
-to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
-on Juno, at the linux shell prompt, issue the following command:
-
-.. code:: shell
-
-    echo +10 > /sys/class/rtc/rtc0/wakealarm
-    echo -n mem > /sys/power/state
-
-The Juno board should suspend to RAM and then wakeup after 10 seconds due to
-wakeup interrupt from RTC.
-
---------------
-
-*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
-
-.. _Arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
-.. _Linaro Release: http://releases.linaro.org/members/arm/platforms
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
-.. _Linaro instructions: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about
-.. _Arm Platforms User guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/user-guide.rst
-.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
-.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
-.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
-.. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
-.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
-.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
-.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
-.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
-.. _mbed TLS Security Center: https://tls.mbed.org/security
-.. _Arm's website: `FVP models`_
-.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
-.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
diff --git a/docs/perf/index.rst b/docs/perf/index.rst
index 50833b8..0f49b48 100644
--- a/docs/perf/index.rst
+++ b/docs/perf/index.rst
@@ -7,3 +7,8 @@
    :numbered:
 
    psci-performance-juno
+   tsp
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/perf/tsp.rst b/docs/perf/tsp.rst
new file mode 100644
index 0000000..f8b0048
--- /dev/null
+++ b/docs/perf/tsp.rst
@@ -0,0 +1,27 @@
+Test Secure Payload (TSP) and Dispatcher (TSPD)
+===============================================
+
+Building the Test Secure Payload
+--------------------------------
+
+The TSP is coupled with a companion runtime service in the BL31 firmware,
+called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
+must be recompiled as well. For more information on SPs and SPDs, see the
+:ref:`firmware_design_sel1_spd` section in the :ref:`Firmware Design`.
+
+First clean the TF-A build directory to get rid of any previous BL31 binary.
+Then to build the TSP image use:
+
+.. code:: shell
+
+    make PLAT=<platform> SPD=tspd all
+
+An additional boot loader binary file is created in the ``build`` directory:
+
+::
+
+    build/<platform>/<build-type>/bl32.bin
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
new file mode 100644
index 0000000..d24ad23
--- /dev/null
+++ b/docs/plat/arm/arm-build-options.rst
@@ -0,0 +1,114 @@
+Arm Development Platform Build Options
+======================================
+
+Arm Platform Build Options
+--------------------------
+
+-  ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
+   DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
+   BL31 in TZC secured DRAM. If TSP is present, then setting this option also
+   sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
+   flag.
+
+-  ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
+   frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
+   frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which
+   should match the frame used by the Non-Secure image (normally the Linux
+   kernel). Default is true (access to the frame is allowed).
+
+-  ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
+   By default, Arm platforms use a watchdog to trigger a system reset in case
+   an error is encountered during the boot process (for example, when an image
+   could not be loaded or authenticated). The watchdog is enabled in the early
+   platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
+   Trusted Watchdog may be disabled at build time for testing or development
+   purposes.
+
+-  ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
+   have specific values at boot. This boolean option allows the Trusted Firmware
+   to have a Linux kernel image as BL33 by preparing the registers to these
+   values before jumping to BL33. This option defaults to 0 (disabled). For
+   AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
+   using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
+   to the location of a device tree blob (DTB) already loaded in memory. The
+   Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
+   option.
+
+-  ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
+   cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
+   is set, the functions which deal with MPIDR assume that the ``MT`` bit in
+   MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
+   this flag is 0. Note that this option is not used on FVP platforms.
+
+-  ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
+   for the construction of composite state-ID in the power-state parameter.
+   The existing PSCI clients currently do not support this encoding of
+   State-ID yet. Hence this flag is used to configure whether to use the
+   recommended State-ID encoding or not. The default value of this flag is 0,
+   in which case the platform is configured to expect NULL in the State-ID
+   field of power-state parameter.
+
+-  ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
+   location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
+   for Arm platforms. Depending on the selected option, the proper private key
+   must be specified using the ``ROT_KEY`` option when building the Trusted
+   Firmware. This private key will be used by the certificate generation tool
+   to sign the BL2 and Trusted Key certificates. Available options for
+   ``ARM_ROTPK_LOCATION`` are:
+
+   -  ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
+      registers. The private key corresponding to this ROTPK hash is not
+      currently available.
+   -  ``devel_rsa`` : return a development public key hash embedded in the BL1
+      and BL2 binaries. This hash has been obtained from the RSA public key
+      ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
+      this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY``
+      when creating the certificates.
+   -  ``devel_ecdsa`` : return a development public key hash embedded in the BL1
+      and BL2 binaries. This hash has been obtained from the ECDSA public key
+      ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To
+      use this option, ``arm_rotprivk_ecdsa.pem`` must be specified as
+      ``ROT_KEY`` when creating the certificates.
+
+-  ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
+
+   -  ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
+   -  ``tdram`` : Trusted DRAM (if available)
+   -  ``dram`` : Secure region in DRAM (default option when TBB is enabled,
+      configured by the TrustZone controller)
+
+-  ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
+   of the translation tables library instead of version 2. It is set to 0 by
+   default, which selects version 2.
+
+-  ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
+   TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
+   platforms. If this option is specified, then the path to the CryptoCell
+   SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
+
+For a better understanding of these options, the Arm development platform memory
+map is explained in the :ref:`Firmware Design`.
+
+.. _build_options_arm_css_platform:
+
+Arm CSS Platform-Specific Build Options
+---------------------------------------
+
+-  ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
+   incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
+   compatible change to the MTL protocol, used for AP/SCP communication.
+   TF-A no longer supports earlier SCP versions. If this option is set to 1
+   then TF-A will detect if an earlier version is in use. Default is 1.
+
+-  ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
+   SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
+   during boot. Default is 1.
+
+-  ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
+   instead of SCPI/BOM driver for communicating with the SCP during power
+   management operations and for SCP RAM Firmware transfer. If this option
+   is set to 1, then SCMI/SDS drivers will be used. Default is 0.
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/plat/fvp_ve.rst b/docs/plat/arm/fvp-ve/index.rst
similarity index 96%
rename from docs/plat/fvp_ve.rst
rename to docs/plat/arm/fvp-ve/index.rst
index 6abf9e5..8ac0741 100644
--- a/docs/plat/fvp_ve.rst
+++ b/docs/plat/arm/fvp-ve/index.rst
@@ -78,3 +78,7 @@
           -C motherboard.flashloader1.fname=<path_to_fip.bin> \
           --data cluster.cpu0=<path_to_zImage>@0x80080000  \
           --data cluster.cpu0=<path_to_ramdisk>@0x84000000
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
new file mode 100644
index 0000000..b6396b9
--- /dev/null
+++ b/docs/plat/arm/fvp/index.rst
@@ -0,0 +1,637 @@
+Arm Fixed Virtual Platforms (FVP)
+=================================
+
+Fixed Virtual Platform (FVP) Support
+------------------------------------
+
+This section lists the supported Arm |FVP| platforms. Please refer to the FVP
+documentation for a detailed description of the model parameter options.
+
+The latest version of the AArch64 build of TF-A has been tested on the following
+Arm FVPs without shifted affinities, and that do not support threaded CPU cores
+(64-bit host machine only).
+
+.. note::
+   The FVP models used are Version 11.6 Build 45, unless otherwise stated.
+
+-  ``FVP_Base_AEMv8A-AEMv8A``
+-  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
+-  ``FVP_Base_RevC-2xAEMv8A``
+-  ``FVP_Base_Cortex-A32x4``
+-  ``FVP_Base_Cortex-A35x4``
+-  ``FVP_Base_Cortex-A53x4``
+-  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
+-  ``FVP_Base_Cortex-A55x4``
+-  ``FVP_Base_Cortex-A57x1-A53x1``
+-  ``FVP_Base_Cortex-A57x2-A53x4``
+-  ``FVP_Base_Cortex-A57x4-A53x4``
+-  ``FVP_Base_Cortex-A57x4``
+-  ``FVP_Base_Cortex-A72x4-A53x4``
+-  ``FVP_Base_Cortex-A72x4``
+-  ``FVP_Base_Cortex-A73x4-A53x4``
+-  ``FVP_Base_Cortex-A73x4``
+-  ``FVP_Base_Cortex-A75x4``
+-  ``FVP_Base_Cortex-A76x4``
+-  ``FVP_Base_Cortex-A76AEx4``
+-  ``FVP_Base_Cortex-A76AEx8``
+-  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
+-  ``FVP_Base_Neoverse-N1x4``
+-  ``FVP_Base_Zeusx4``
+-  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
+-  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
+-  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
+-  ``FVP_RD_N1Edge``
+-  ``Foundation_Platform``
+
+The latest version of the AArch32 build of TF-A has been tested on the
+following Arm FVPs without shifted affinities, and that do not support threaded
+CPU cores (64-bit host machine only).
+
+-  ``FVP_Base_AEMv8A-AEMv8A``
+-  ``FVP_Base_Cortex-A32x4``
+
+.. note::
+   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
+   is not compatible with legacy GIC configurations. Therefore this FVP does not
+   support these legacy GIC configurations.
+
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
+FVP website`_. The Cortex-A models listed above are also available to download
+from `Arm's website`_.
+
+.. note::
+   The build numbers quoted above are those reported by launching the FVP
+   with the ``--version`` parameter.
+
+.. note::
+   Linaro provides a ramdisk image in prebuilt FVP configurations and full
+   file systems that can be downloaded separately. To run an FVP with a virtio
+   file system image an additional FVP configuration option
+   ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
+   used.
+
+.. note::
+   The software will not work on Version 1.0 of the Foundation FVP.
+   The commands below would report an ``unhandled argument`` error in this case.
+
+.. note::
+   FVPs can be launched with ``--cadi-server`` option such that a
+   CADI-compliant debugger (for example, Arm DS-5) can connect to and control
+   its execution.
+
+.. warning::
+   Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
+   the internal synchronisation timings changed compared to older versions of
+   the models. The models can be launched with ``-Q 100`` option if they are
+   required to match the run time characteristics of the older versions.
+
+All the above platforms have been tested with `Linaro Release 19.06`_.
+
+.. _build_options_arm_fvp_platform:
+
+Arm FVP Platform Specific Build Options
+---------------------------------------
+
+-  ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
+   build the topology tree within TF-A. By default TF-A is configured for dual
+   cluster topology and this option can be used to override the default value.
+
+-  ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
+   default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
+   explained in the options below:
+
+   -  ``FVP_CCI`` : The CCI driver is selected. This is the default
+      if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
+   -  ``FVP_CCN`` : The CCN driver is selected. This is the default
+      if ``FVP_CLUSTER_COUNT`` > 2.
+
+-  ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
+   a single cluster.  This option defaults to 4.
+
+-  ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
+   in the system. This option defaults to 1. Note that the build option
+   ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
+
+-  ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
+
+   -  ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
+   -  ``FVP_GICV2`` : The GICv2 only driver is selected
+   -  ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
+
+-  ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
+   for functions that wait for an arbitrary time length (udelay and mdelay).
+   The default value is 0.
+
+-  ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
+   to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
+   details on HW_CONFIG. By default, this is initialized to a sensible DTS
+   file in ``fdts/`` folder depending on other build options. But some cases,
+   like shifted affinity format for MPIDR, cannot be detected at build time
+   and this option is needed to specify the appropriate DTS file.
+
+-  ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
+   FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
+   similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
+   HW_CONFIG blob instead of the DTS file. This option is useful to override
+   the default HW_CONFIG selected by the build system.
+
+Booting Firmware Update images
+------------------------------
+
+When Firmware Update (FWU) is enabled there are at least 2 new images
+that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
+FWU FIP.
+
+The additional fip images must be loaded with:
+
+::
+
+    --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000	[ns_bl1u_base_address]
+    --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000	[ns_bl2u_base_address]
+
+The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
+In the same way, the address ns_bl2u_base_address is the value of
+NS_BL2U_BASE.
+
+Booting an EL3 payload
+----------------------
+
+The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
+the secondary CPUs holding pen to work properly. Unfortunately, its reset value
+is undefined on the FVP platform and the FVP platform code doesn't clear it.
+Therefore, one must modify the way the model is normally invoked in order to
+clear the mailbox at start-up.
+
+One way to do that is to create an 8-byte file containing all zero bytes using
+the following command:
+
+.. code:: shell
+
+    dd if=/dev/zero of=mailbox.dat bs=1 count=8
+
+and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
+using the following model parameters:
+
+::
+
+    --data cluster0.cpu0=mailbox.dat@0x04000000   [Base FVPs]
+    --data=mailbox.dat@0x04000000                 [Foundation FVP]
+
+To provide the model with the EL3 payload image, the following methods may be
+used:
+
+#. If the EL3 payload is able to execute in place, it may be programmed into
+   flash memory. On Base Cortex and AEM FVPs, the following model parameter
+   loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
+   used for the FIP):
+
+   ::
+
+       -C bp.flashloader1.fname="<path-to>/<el3-payload>"
+
+   On Foundation FVP, there is no flash loader component and the EL3 payload
+   may be programmed anywhere in flash using method 3 below.
+
+#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
+   command may be used to load the EL3 payload ELF image over JTAG:
+
+   ::
+
+       load <path-to>/el3-payload.elf
+
+#. The EL3 payload may be pre-loaded in volatile memory using the following
+   model parameters:
+
+   ::
+
+       --data cluster0.cpu0="<path-to>/el3-payload>"@address   [Base FVPs]
+       --data="<path-to>/<el3-payload>"@address                [Foundation FVP]
+
+   The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
+   used when building TF-A.
+
+Booting a preloaded kernel image (Base FVP)
+-------------------------------------------
+
+The following example uses a simplified boot flow by directly jumping from the
+TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
+useful if both the kernel and the device tree blob (DTB) are already present in
+memory (like in FVP).
+
+For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
+address ``0x82000000``, the firmware can be built like this:
+
+.. code:: shell
+
+    CROSS_COMPILE=aarch64-linux-gnu-  \
+    make PLAT=fvp DEBUG=1             \
+    RESET_TO_BL31=1                   \
+    ARM_LINUX_KERNEL_AS_BL33=1        \
+    PRELOADED_BL33_BASE=0x80080000    \
+    ARM_PRELOADED_DTB_BASE=0x82000000 \
+    all fip
+
+Now, it is needed to modify the DTB so that the kernel knows the address of the
+ramdisk. The following script generates a patched DTB from the provided one,
+assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
+script assumes that the user is using a ramdisk image prepared for U-Boot, like
+the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
+offset in ``INITRD_START`` has to be removed.
+
+.. code:: bash
+
+    #!/bin/bash
+
+    # Path to the input DTB
+    KERNEL_DTB=<path-to>/<fdt>
+    # Path to the output DTB
+    PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
+    # Base address of the ramdisk
+    INITRD_BASE=0x84000000
+    # Path to the ramdisk
+    INITRD=<path-to>/<ramdisk.img>
+
+    # Skip uboot header (64 bytes)
+    INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
+    INITRD_SIZE=$(stat -Lc %s ${INITRD})
+    INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
+
+    CHOSEN_NODE=$(echo                                        \
+    "/ {                                                      \
+            chosen {                                          \
+                    linux,initrd-start = <${INITRD_START}>;   \
+                    linux,initrd-end = <${INITRD_END}>;       \
+            };                                                \
+    };")
+
+    echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} |  \
+            dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
+
+And the FVP binary can be run with the following command:
+
+.. code:: shell
+
+    <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
+    -C pctl.startup=0.0.0.0                                     \
+    -C bp.secure_memory=1                                       \
+    -C cluster0.NUM_CORES=4                                     \
+    -C cluster1.NUM_CORES=4                                     \
+    -C cache_state_modelled=1                                   \
+    -C cluster0.cpu0.RVBAR=0x04020000                           \
+    -C cluster0.cpu1.RVBAR=0x04020000                           \
+    -C cluster0.cpu2.RVBAR=0x04020000                           \
+    -C cluster0.cpu3.RVBAR=0x04020000                           \
+    -C cluster1.cpu0.RVBAR=0x04020000                           \
+    -C cluster1.cpu1.RVBAR=0x04020000                           \
+    -C cluster1.cpu2.RVBAR=0x04020000                           \
+    -C cluster1.cpu3.RVBAR=0x04020000                           \
+    --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000        \
+    --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000   \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+    --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
+
+Obtaining the Flattened Device Trees
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Depending on the FVP configuration and Linux configuration used, different
+FDT files are required. FDT source files for the Foundation and Base FVPs can
+be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
+a subset of the Base FVP components. For example, the Foundation FVP lacks
+CLCD and MMC support, and has only one CPU cluster.
+
+.. note::
+   It is not recommended to use the FDTs built along the kernel because not
+   all FDTs are available from there.
+
+The dynamic configuration capability is enabled in the firmware for FVPs.
+This means that the firmware can authenticate and load the FDT if present in
+FIP. A default FDT is packaged into FIP during the build based on
+the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
+or ``FVP_HW_CONFIG_DTS`` build options (refer to
+:ref:`build_options_arm_fvp_platform` for details on the options).
+
+-  ``fvp-base-gicv2-psci.dts``
+
+   For use with models such as the Cortex-A57-A53 Base FVPs without shifted
+   affinities and with Base memory map configuration.
+
+-  ``fvp-base-gicv2-psci-aarch32.dts``
+
+   For use with models such as the Cortex-A32 Base FVPs without shifted
+   affinities and running Linux in AArch32 state with Base memory map
+   configuration.
+
+-  ``fvp-base-gicv3-psci.dts``
+
+   For use with models such as the Cortex-A57-A53 Base FVPs without shifted
+   affinities and with Base memory map configuration and Linux GICv3 support.
+
+-  ``fvp-base-gicv3-psci-1t.dts``
+
+   For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
+   single threaded CPUs, Base memory map configuration and Linux GICv3 support.
+
+-  ``fvp-base-gicv3-psci-dynamiq.dts``
+
+   For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
+   single cluster, single threaded CPUs, Base memory map configuration and Linux
+   GICv3 support.
+
+-  ``fvp-base-gicv3-psci-aarch32.dts``
+
+   For use with models such as the Cortex-A32 Base FVPs without shifted
+   affinities and running Linux in AArch32 state with Base memory map
+   configuration and Linux GICv3 support.
+
+-  ``fvp-foundation-gicv2-psci.dts``
+
+   For use with Foundation FVP with Base memory map configuration.
+
+-  ``fvp-foundation-gicv3-psci.dts``
+
+   (Default) For use with Foundation FVP with Base memory map configuration
+   and Linux GICv3 support.
+
+
+Running on the Foundation FVP with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``Foundation_Platform`` parameters should be used to boot Linux with
+4 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/Foundation_Platform                   \
+    --cores=4                                       \
+    --arm-v8.0                                      \
+    --secure-memory                                 \
+    --visualization                                 \
+    --gicv3                                         \
+    --data="<path-to>/<bl1-binary>"@0x0             \
+    --data="<path-to>/<FIP-binary>"@0x08000000      \
+    --data="<path-to>/<kernel-binary>"@0x80080000   \
+    --data="<path-to>/<ramdisk-binary>"@0x84000000
+
+Notes:
+
+-  BL1 is loaded at the start of the Trusted ROM.
+-  The Firmware Image Package is loaded at the start of NOR FLASH0.
+-  The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
+   is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
+-  The default use-case for the Foundation FVP is to use the ``--gicv3`` option
+   and enable the GICv3 device in the model. Note that without this option,
+   the Foundation FVP defaults to legacy (Versatile Express) memory map which
+   is not supported by TF-A.
+-  In order for TF-A to run correctly on the Foundation FVP, the architecture
+   versions must match. The Foundation FVP defaults to the highest v8.x
+   version it supports but the default build for TF-A is for v8.0. To avoid
+   issues either start the Foundation FVP to use v8.0 architecture using the
+   ``--arm-v8.0`` option, or build TF-A with an appropriate value for
+   ``ARM_ARCH_MINOR``.
+
+Running on the AEMv8 Base FVP with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_RevC-2xAEMv8A                            \
+    -C pctl.startup=0.0.0.0                                     \
+    -C bp.secure_memory=1                                       \
+    -C bp.tzc_400.diagnostics=1                                 \
+    -C cluster0.NUM_CORES=4                                     \
+    -C cluster1.NUM_CORES=4                                     \
+    -C cache_state_modelled=1                                   \
+    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
+    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+.. note::
+   The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
+   a specific DTS for all the CPUs to be loaded.
+
+Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_AEMv8A-AEMv8A                            \
+    -C pctl.startup=0.0.0.0                                     \
+    -C bp.secure_memory=1                                       \
+    -C bp.tzc_400.diagnostics=1                                 \
+    -C cluster0.NUM_CORES=4                                     \
+    -C cluster1.NUM_CORES=4                                     \
+    -C cache_state_modelled=1                                   \
+    -C cluster0.cpu0.CONFIG64=0                                 \
+    -C cluster0.cpu1.CONFIG64=0                                 \
+    -C cluster0.cpu2.CONFIG64=0                                 \
+    -C cluster0.cpu3.CONFIG64=0                                 \
+    -C cluster1.cpu0.CONFIG64=0                                 \
+    -C cluster1.cpu1.CONFIG64=0                                 \
+    -C cluster1.cpu2.CONFIG64=0                                 \
+    -C cluster1.cpu3.CONFIG64=0                                 \
+    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
+    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
+boot Linux with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_Cortex-A57x4-A53x4                       \
+    -C pctl.startup=0.0.0.0                                     \
+    -C bp.secure_memory=1                                       \
+    -C bp.tzc_400.diagnostics=1                                 \
+    -C cache_state_modelled=1                                   \
+    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
+    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
+boot Linux with 4 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_Cortex-A32x4                             \
+    -C pctl.startup=0.0.0.0                                     \
+    -C bp.secure_memory=1                                       \
+    -C bp.tzc_400.diagnostics=1                                 \
+    -C cache_state_modelled=1                                   \
+    -C bp.secureflashloader.fname="<path-to>/<bl1-binary>"      \
+    -C bp.flashloader0.fname="<path-to>/<FIP-binary>"           \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+
+Running on the AEMv8 Base FVP with reset to BL31 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_RevC-2xAEMv8A                             \
+    -C pctl.startup=0.0.0.0                                      \
+    -C bp.secure_memory=1                                        \
+    -C bp.tzc_400.diagnostics=1                                  \
+    -C cluster0.NUM_CORES=4                                      \
+    -C cluster1.NUM_CORES=4                                      \
+    -C cache_state_modelled=1                                    \
+    -C cluster0.cpu0.RVBAR=0x04010000                            \
+    -C cluster0.cpu1.RVBAR=0x04010000                            \
+    -C cluster0.cpu2.RVBAR=0x04010000                            \
+    -C cluster0.cpu3.RVBAR=0x04010000                            \
+    -C cluster1.cpu0.RVBAR=0x04010000                            \
+    -C cluster1.cpu1.RVBAR=0x04010000                            \
+    -C cluster1.cpu2.RVBAR=0x04010000                            \
+    -C cluster1.cpu3.RVBAR=0x04010000                            \
+    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000    \
+    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000    \
+    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
+    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+Notes:
+
+-  If Position Independent Executable (PIE) support is enabled for BL31
+   in this config, it can be loaded at any valid address for execution.
+
+-  Since a FIP is not loaded when using BL31 as reset entrypoint, the
+   ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
+   parameter is needed to load the individual bootloader images in memory.
+   BL32 image is only needed if BL31 has been built to expect a Secure-EL1
+   Payload. For the same reason, the FDT needs to be compiled from the DT source
+   and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
+   parameter.
+
+-  The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
+   specific DTS for all the CPUs to be loaded.
+
+-  The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
+   X and Y are the cluster and CPU numbers respectively, is used to set the
+   reset vector for each core.
+
+-  Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
+   changing the value of
+   ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
+   ``BL32_BASE``.
+
+
+Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
+with 8 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_AEMv8A-AEMv8A                             \
+    -C pctl.startup=0.0.0.0                                      \
+    -C bp.secure_memory=1                                        \
+    -C bp.tzc_400.diagnostics=1                                  \
+    -C cluster0.NUM_CORES=4                                      \
+    -C cluster1.NUM_CORES=4                                      \
+    -C cache_state_modelled=1                                    \
+    -C cluster0.cpu0.CONFIG64=0                                  \
+    -C cluster0.cpu1.CONFIG64=0                                  \
+    -C cluster0.cpu2.CONFIG64=0                                  \
+    -C cluster0.cpu3.CONFIG64=0                                  \
+    -C cluster1.cpu0.CONFIG64=0                                  \
+    -C cluster1.cpu1.CONFIG64=0                                  \
+    -C cluster1.cpu2.CONFIG64=0                                  \
+    -C cluster1.cpu3.CONFIG64=0                                  \
+    -C cluster0.cpu0.RVBAR=0x04002000                            \
+    -C cluster0.cpu1.RVBAR=0x04002000                            \
+    -C cluster0.cpu2.RVBAR=0x04002000                            \
+    -C cluster0.cpu3.RVBAR=0x04002000                            \
+    -C cluster1.cpu0.RVBAR=0x04002000                            \
+    -C cluster1.cpu1.RVBAR=0x04002000                            \
+    -C cluster1.cpu2.RVBAR=0x04002000                            \
+    -C cluster1.cpu3.RVBAR=0x04002000                            \
+    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000    \
+    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
+    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+.. note::
+   The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
+   It should match the address programmed into the RVBAR register as well.
+
+Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
+boot Linux with 8 CPUs using the AArch64 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_Cortex-A57x4-A53x4                        \
+    -C pctl.startup=0.0.0.0                                      \
+    -C bp.secure_memory=1                                        \
+    -C bp.tzc_400.diagnostics=1                                  \
+    -C cache_state_modelled=1                                    \
+    -C cluster0.cpu0.RVBARADDR=0x04010000                        \
+    -C cluster0.cpu1.RVBARADDR=0x04010000                        \
+    -C cluster0.cpu2.RVBARADDR=0x04010000                        \
+    -C cluster0.cpu3.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu0.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu1.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu2.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu3.RVBARADDR=0x04010000                        \
+    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000    \
+    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000    \
+    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
+    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
+boot Linux with 4 CPUs using the AArch32 build of TF-A.
+
+.. code:: shell
+
+    <path-to>/FVP_Base_Cortex-A32x4                             \
+    -C pctl.startup=0.0.0.0                                     \
+    -C bp.secure_memory=1                                       \
+    -C bp.tzc_400.diagnostics=1                                 \
+    -C cache_state_modelled=1                                   \
+    -C cluster0.cpu0.RVBARADDR=0x04002000                       \
+    -C cluster0.cpu1.RVBARADDR=0x04002000                       \
+    -C cluster0.cpu2.RVBARADDR=0x04002000                       \
+    -C cluster0.cpu3.RVBARADDR=0x04002000                       \
+    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000   \
+    --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000   \
+    --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000           \
+    --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
+    --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
+
+.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+.. _Arm's website: `FVP models`_
+.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
new file mode 100644
index 0000000..e26f75e
--- /dev/null
+++ b/docs/plat/arm/index.rst
@@ -0,0 +1,19 @@
+Arm Development Platforms
+=========================
+
+.. toctree::
+   :maxdepth: 1
+   :caption: Contents
+
+   juno/index
+   fvp/index
+   fvp-ve/index
+   arm-build-options
+
+This chapter holds documentation related to Arm's development platforms,
+including both software models (FVPs) and hardware development boards
+such as Juno.
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
new file mode 100644
index 0000000..6429ede
--- /dev/null
+++ b/docs/plat/arm/juno/index.rst
@@ -0,0 +1,246 @@
+Arm Juno Development Platform
+=============================
+
+Platform-specific build options
+-------------------------------
+
+-  ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
+   Media Protection (TZ-MP1). Default value of this flag is 0.
+
+Running software on Juno
+------------------------
+
+This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
+
+To execute the software stack on Juno, the version of the Juno board recovery
+image indicated in the `Linaro Release Notes`_ must be installed. If you have an
+earlier version installed or are unsure which version is installed, please
+re-install the recovery image by following the
+`Instructions for using Linaro's deliverables on Juno`_.
+
+Preparing TF-A images
+---------------------
+
+After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
+``SOFTWARE/`` directory of the Juno SD card.
+
+Creating a Firmware Image Package (FIP)
+---------------------------------------
+
+This section provides Juno and FVP specific instructions to build Trusted
+Firmware, obtain the additional required firmware, and pack it all together in
+a single FIP binary. It assumes that a Linaro release has been installed.
+
+.. note::
+   Pre-built binaries for AArch32 are available from Linaro Release 16.12
+   onwards. Before that release, pre-built binaries are only available for
+   AArch64.
+
+.. warning::
+   Follow the full instructions for one platform before switching to a
+   different one. Mixing instructions for different platforms may result in
+   corrupted binaries.
+
+.. warning::
+   The uboot image downloaded by the Linaro workspace script does not always
+   match the uboot image packaged as BL33 in the corresponding fip file. It is
+   recommended to use the version that is packaged in the fip file using the
+   instructions below.
+
+.. note::
+   For the FVP, the kernel FDT is packaged in FIP during build and loaded
+   by the firmware at runtime.
+
+#. Clean the working directory
+
+   .. code:: shell
+
+       make realclean
+
+#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
+
+   Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
+   package included in the Linaro release:
+
+   .. code:: shell
+
+       # Build the fiptool
+       make [DEBUG=1] [V=1] fiptool
+
+       # Unpack firmware images from Linaro FIP
+       ./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
+
+   The unpack operation will result in a set of binary images extracted to the
+   current working directory. The SCP_BL2 image corresponds to
+   ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
+
+   .. note::
+      The fiptool will complain if the images to be unpacked already
+      exist in the current directory. If that is the case, either delete those
+      files or use the ``--force`` option to overwrite.
+
+   .. note::
+      For AArch32, the instructions below assume that nt-fw.bin is a
+      normal world boot loader that supports AArch32.
+
+#. Build TF-A images and create a new FIP for FVP
+
+   .. code:: shell
+
+       # AArch64
+       make PLAT=fvp BL33=nt-fw.bin all fip
+
+       # AArch32
+       make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
+
+#. Build TF-A images and create a new FIP for Juno
+
+   For AArch64:
+
+   Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
+   as a build parameter.
+
+   .. code:: shell
+
+       make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
+
+   For AArch32:
+
+   Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
+   therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
+   separately for AArch32.
+
+   -  Before building BL32, the environment variable ``CROSS_COMPILE`` must point
+      to the AArch32 Linaro cross compiler.
+
+      .. code:: shell
+
+          export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
+
+   -  Build BL32 in AArch32.
+
+      .. code:: shell
+
+          make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
+          RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
+
+   -  Save ``bl32.bin`` to a temporary location and clean the build products.
+
+      ::
+
+          cp <path-to-build>/bl32.bin <path-to-temporary>
+          make realclean
+
+   -  Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
+      must point to the AArch64 Linaro cross compiler.
+
+      .. code:: shell
+
+          export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
+
+   -  The following parameters should be used to build BL1 and BL2 in AArch64
+      and point to the BL32 file.
+
+      .. code:: shell
+
+          make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
+          BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
+          BL32=<path-to-temporary>/bl32.bin all fip
+
+The resulting BL1 and FIP images may be found in:
+
+::
+
+    # Juno
+    ./build/juno/release/bl1.bin
+    ./build/juno/release/fip.bin
+
+    # FVP
+    ./build/fvp/release/bl1.bin
+    ./build/fvp/release/fip.bin
+
+
+Booting Firmware Update images
+------------------------------
+
+The new images must be programmed in flash memory by adding
+an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
+on the Juno SD card (where ``x`` depends on the revision of the Juno board).
+Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
+programming" for more information. User should ensure these do not
+overlap with any other entries in the file.
+
+::
+
+        NOR10UPDATE: AUTO                       ;Image Update:NONE/AUTO/FORCE
+        NOR10ADDRESS: 0x00400000                ;Image Flash Address [ns_bl2u_base_address]
+        NOR10FILE: \SOFTWARE\fwu_fip.bin        ;Image File Name
+        NOR10LOAD: 00000000                     ;Image Load Address
+        NOR10ENTRY: 00000000                    ;Image Entry Point
+
+        NOR11UPDATE: AUTO                       ;Image Update:NONE/AUTO/FORCE
+        NOR11ADDRESS: 0x03EB8000                ;Image Flash Address [ns_bl1u_base_address]
+        NOR11FILE: \SOFTWARE\ns_bl1u.bin        ;Image File Name
+        NOR11LOAD: 00000000                     ;Image Load Address
+
+The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
+In the same way, the address ns_bl2u_base_address is the value of
+NS_BL2U_BASE - 0x8000000.
+
+.. _plat_juno_booting_el3_payload:
+
+Booting an EL3 payload
+----------------------
+
+If the EL3 payload is able to execute in place, it may be programmed in flash
+memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
+on the Juno SD card (where ``x`` depends on the revision of the Juno board).
+Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
+programming" for more information.
+
+Alternatively, the same DS-5 command mentioned in the FVP section above can
+be used to load the EL3 payload's ELF file over JTAG on Juno.
+
+For more information on EL3 payloads in general, see
+:ref:`alt_boot_flows_el3_payload`.
+
+Booting a preloaded kernel image
+--------------------------------
+
+The Trusted Firmware must be compiled in a similar way as for FVP explained
+above. The process to load binaries to memory is the one explained in
+`plat_juno_booting_el3_payload`_.
+
+Testing System Suspend
+----------------------
+
+The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
+to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
+on Juno, at the linux shell prompt, issue the following command:
+
+.. code:: shell
+
+    echo +10 > /sys/class/rtc/rtc0/wakealarm
+    echo -n mem > /sys/power/state
+
+The Juno board should suspend to RAM and then wakeup after 10 seconds due to
+wakeup interrupt from RTC.
+
+Additional Resources
+--------------------
+
+Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
+software information. Please also refer to the `Juno Getting Started Guide`_ to
+get more detailed information about the Juno Arm development platform and how to
+configure it.
+
+--------------
+
+*Copyright (c) 2019, Arm Limited. All rights reserved.*
+
+.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
+.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
+.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
+.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
+.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
+.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 5495280..63d29a9 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -8,10 +8,10 @@
    :hidden:
 
    allwinner
+   arm/index
    meson-gxbb
    meson-gxl
    meson-g12a
-   fvp_ve
    hikey
    hikey960
    intel-agilex
@@ -38,81 +38,19 @@
    xilinx-zynqmp
 
 This section provides a list of supported upstream *platform ports* and the
-documentation associated with them. The list of suported Arm |FVP| platforms is
-outlined in the following section.
+documentation associated with them.
 
 .. note::
    In addition to the platforms ports listed within the table of contents, there
    are several additional platforms that are supported upstream but which do not
    currently have associated documentation:
 
-   - Arm Juno Software Development Platform. Various |AArch32| and |AArch64|
-     builds of this release have been tested on r0, r1 and r2 variants of the
-     `Juno Arm Development Platform`_.
    - Arm Neoverse N1 System Development Platform (N1SDP)
    - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
    - Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
    - Arm SGI-575 and SGM-775
    - MediaTek MT6795 and MT8173 SoCs
 
-Fixed Virtual Platform (FVP) Support
-------------------------------------
-
-The latest version of the AArch64 build of TF-A has been tested on the
-following Arm FVPs without shifted affinities, and that do not support threaded
-CPU cores (64-bit host machine only).
-
-.. note::
-   The FVP models used are Version 11.6 Build 45, unless otherwise stated.
-
--  ``FVP_Base_AEMv8A-AEMv8A``
--  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
--  ``FVP_Base_RevC-2xAEMv8A``
--  ``FVP_Base_Cortex-A32x4``
--  ``FVP_Base_Cortex-A35x4``
--  ``FVP_Base_Cortex-A53x4``
--  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
--  ``FVP_Base_Cortex-A55x4``
--  ``FVP_Base_Cortex-A57x1-A53x1``
--  ``FVP_Base_Cortex-A57x2-A53x4``
--  ``FVP_Base_Cortex-A57x4-A53x4``
--  ``FVP_Base_Cortex-A57x4``
--  ``FVP_Base_Cortex-A72x4-A53x4``
--  ``FVP_Base_Cortex-A72x4``
--  ``FVP_Base_Cortex-A73x4-A53x4``
--  ``FVP_Base_Cortex-A73x4``
--  ``FVP_Base_Cortex-A75x4``
--  ``FVP_Base_Cortex-A76x4``
--  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
--  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
--  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
--  ``FVP_Base_Zeusx4``
--  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
--  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
--  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
--  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
--  ``FVP_RD_N1Edge`` (Version 11.3 build 42)
--  ``Foundation_Platform``
-
-The latest version of the AArch32 build of TF-A has been tested on the
-following Arm FVPs without shifted affinities, and that do not support threaded
-CPU cores (64-bit host machine only).
-
--  ``FVP_Base_AEMv8A-AEMv8A``
--  ``FVP_Base_Cortex-A32x4``
-
-.. note::
-   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
-
-The *Foundation* and *Base* FVPs can be downloaded free of charge. See the
-`Arm FVP website`_.
-
-All the above platforms have been tested with `Linaro Release 19.06`_.
-
 --------------
 
 *Copyright (c) 2019, Arm Limited. All rights reserved.*
-
-.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
-.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
diff --git a/docs/plat/marvell/build.rst b/docs/plat/marvell/build.rst
index c8923e4..c10bcff 100644
--- a/docs/plat/marvell/build.rst
+++ b/docs/plat/marvell/build.rst
@@ -194,8 +194,8 @@
     can interrupt UART recovery process). This MACRO definition is set in
     ``plat/marvell/a8k/common/include/platform_def.h`` file.
 
-For more information about build options, please refer to section
-'Summary of build options' in the :ref:`User Guide`.
+For more information about build options, please refer to the
+:ref:`Build Options` document.
 
 
 Build output
@@ -251,4 +251,3 @@
     (use the "mv_ddr-armada-atf-mainline" branch):
 
     https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
-
diff --git a/docs/plat/socionext-uniphier.rst b/docs/plat/socionext-uniphier.rst
index 964dd1d..9288193 100644
--- a/docs/plat/socionext-uniphier.rst
+++ b/docs/plat/socionext-uniphier.rst
@@ -80,7 +80,8 @@
 - Trusted Board Boot
 
   `mbed TLS`_ is needed as the cryptographic and image parser modules.
-  Refer to the :ref:`User Guide` for the appropriate version of mbed TLS.
+  Refer to the :ref:`Prerequisites` document for the appropriate version of
+  mbed TLS.
 
   To enable TBB, add the following options to the build command::
 
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index fdb702f..f569fcb 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -13,8 +13,8 @@
       raise a separate `issue`_ for this and ensure that the changes that
       include Third Party IP are made on a separate topic branch.
 
--  Clone `Trusted Firmware-A`_ on your own machine as suggested in the
-   :ref:`User Guide`.
+-  Clone `Trusted Firmware-A`_ on your own machine as described in
+   :ref:`prerequisites_get_source`.
 -  Create a local topic branch based on the `Trusted Firmware-A`_ ``master``
    branch.
 
@@ -26,8 +26,7 @@
 -  Follow the :ref:`Coding Style & Guidelines`.
 
    -  Use the checkpatch.pl script provided with the Linux source tree. A
-      Makefile target is provided for convenience (see the "Checking source code
-      style" section in the :ref:`User Guide`).
+      Makefile target is provided for convenience.
 
 -  Keep the commits on topic. If you need to fix another bug or make another
    enhancement, please create a separate `issue`_ and address it on a separate
@@ -38,8 +37,9 @@
    an `issue`_, include a reference.
 -  Where appropriate, please update the documentation.
 
-   -  Consider whether the :ref:`User Guide`, :ref:`Porting Guide`,
-      :ref:`Firmware Design` or other in-source documentation needs updating.
+   -  Consider whether the :ref:`Porting Guide`,
+      :ref:`Firmware Design` document or other in-source documentation needs
+      updating.
    -  Ensure that each changed file has the correct copyright and license
       information. Files that entirely consist of contributions to this
       project should have a copyright notice and BSD-3-Clause SPDX license
@@ -63,9 +63,9 @@
       include the documentation changes within the single commit.
 
 -  Please test your changes. As a minimum, ensure that Linux boots on the
-   Foundation FVP. See :ref:`user_guide_run_fvp` for more information. For
-   more extensive testing, consider running the `TF-A Tests`_ against your
-   patches.
+   Foundation FVP. See :ref:`Arm Fixed Virtual Platforms (FVP)` for more
+   information. For more extensive testing, consider running the `TF-A Tests`_
+   against your patches.
 
 Submitting Changes
 ------------------
@@ -82,7 +82,8 @@
 
 -  Ensure that each commit also has a unique ``Change-Id:`` line. If you have
    cloned the repository with the "`Clone with commit-msg hook`" clone method
-   (as advised on the :ref:`User Guide`), this should already be the case.
+   (following the :ref:`Prerequisites` document), this should already be the
+   case.
 
    More details may be found in the `Gerrit Change-Ids documentation`_.
 
diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst
index 646b7a1..4967871 100644
--- a/docs/process/security-hardening.rst
+++ b/docs/process/security-hardening.rst
@@ -9,7 +9,7 @@
 -------------
 
 Several build options can be used to check for security issues. Refer to the
-:ref:`User Guide` for detailed information on the specific build options.
+:ref:`Build Options` for detailed information on these.
 
 - The ``BRANCH_PROTECTION`` build flag can be used to enable Pointer
   Authentication and Branch Target Identification.
diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c
index c62c3f5..ca7c43b 100644
--- a/drivers/arm/gic/v3/gic600_multichip.c
+++ b/drivers/arm/gic/v3/gic600_multichip.c
@@ -9,13 +9,13 @@
  */
 
 #include <assert.h>
+
 #include <common/debug.h>
-
-#include <drivers/arm/gicv3.h>
 #include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/gicv3.h>
 
-#include "gic600_multichip_private.h"
 #include "../common/gic_common_private.h"
+#include "gic600_multichip_private.h"
 
 #warning "GIC-600 Multichip driver is currently experimental and the API may change in future."
 
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
new file mode 100644
index 0000000..f35eaf4
--- /dev/null
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/include/ "fvp-base-gicv3-psci-common.dtsi"
+
+&CPU0 {
+	reg = <0x0 0x0>;
+};
+
+&CPU1 {
+	reg = <0x0 0x1>;
+};
+
+&CPU2 {
+	reg = <0x0 0x100>;
+};
+
+&CPU3 {
+	reg = <0x0 0x101>;
+};
+
+&CPU4 {
+	reg = <0x0 0x200>;
+};
+
+&CPU5 {
+	reg = <0x0 0x201>;
+};
+
+&CPU6 {
+	reg = <0x0 0x300>;
+};
+
+&CPU7 {
+	reg = <0x0 0x301>;
+};
diff --git a/include/arch/aarch32/smccc_helpers.h b/include/arch/aarch32/smccc_helpers.h
index b2ee3cf..2ce7874 100644
--- a/include/arch/aarch32/smccc_helpers.h
+++ b/include/arch/aarch32/smccc_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -130,6 +130,22 @@
 	((smc_ctx_t *)(_h))->r3 = (_r3);	\
 	SMC_RET3(_h, (_r0), (_r1), (_r2));	\
 }
+#define SMC_RET5(_h, _r0, _r1, _r2, _r3, _r4) {	\
+	((smc_ctx_t *)(_h))->r4 = (_r4);	\
+	SMC_RET4(_h, (_r0), (_r1), (_r2), (_r3));	\
+}
+#define SMC_RET6(_h, _r0, _r1, _r2, _r3, _r4, _r5) {	\
+	((smc_ctx_t *)(_h))->r5 = (_r5);	\
+	SMC_RET5(_h, (_r0), (_r1), (_r2), (_r3), (_r4));	\
+}
+#define SMC_RET7(_h, _r0, _r1, _r2, _r3, _r4, _r5, _r6) {	\
+	((smc_ctx_t *)(_h))->r6 = (_r6);	\
+	SMC_RET6(_h, (_r0), (_r1), (_r2), (_r3), (_r4), (_r5));	\
+}
+#define SMC_RET8(_h, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) {	\
+	((smc_ctx_t *)(_h))->r7 = (_r7);	\
+	SMC_RET7(_h, (_r0), (_r1), (_r2), (_r3), (_r4), (_r5), (_r6));	\
+}
 
 /*
  * Helper macro to retrieve the SMC parameters from smc_ctx_t.
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 76e6023..dd3c578 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -20,7 +20,7 @@
 						SMCCC_VERSION_MINOR_SHIFT))
 
 #define SMCCC_MAJOR_VERSION U(1)
-#define SMCCC_MINOR_VERSION U(1)
+#define SMCCC_MINOR_VERSION U(2)
 
 /*******************************************************************************
  * Bit definitions inside the function id as per the SMC calling convention
@@ -83,6 +83,12 @@
 #define SMC_UNK				-1
 #define SMC_PREEMPTED			-2	/* Not defined by the SMCCC */
 
+/* Return codes for Arm Architecture Service SMC calls */
+#define SMC_ARCH_CALL_SUCCESS		0
+#define SMC_ARCH_CALL_NOT_SUPPORTED	-1
+#define SMC_ARCH_CALL_NOT_REQUIRED	-2
+#define SMC_ARCH_CALL_INVAL_PARAM	-3
+
 /* Various flags passed to SMC handlers */
 #define SMC_FROM_SECURE		(U(0) << 0)
 #define SMC_FROM_NON_SECURE	(U(1) << 0)
diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c
index 9823fb3..24e79b4 100644
--- a/plat/arm/board/fvp/fvp_topology.c
+++ b/plat/arm/board/fvp/fvp_topology.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -36,7 +36,8 @@
 	fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT;
 
 	for (i = 0; i < FVP_CLUSTER_COUNT; i++)
-		fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER;
+		fvp_power_domain_tree_desc[i + 2] =
+			FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU;
 
 
 	return fvp_power_domain_tree_desc;
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
index 4f158ee..b150b89 100644
--- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
+++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -6,11 +6,11 @@
 
 #include <platform_def.h>
 
+#include <common/debug.h>
 #include <drivers/arm/css/css_mhu_doorbell.h>
 #include <drivers/arm/css/scmi.h>
 #include <drivers/arm/css/sds.h>
 #include <drivers/arm/gic600_multichip.h>
-#include <common/debug.h>
 #include <lib/mmio.h>
 #include <lib/utils.h>
 #include <plat/arm/common/plat_arm.h>
diff --git a/plat/mediatek/mt8183/drivers/spm/spm.c b/plat/mediatek/mt8183/drivers/spm/spm.c
index dcafd55..547af57 100644
--- a/plat/mediatek/mt8183/drivers/spm/spm.c
+++ b/plat/mediatek/mt8183/drivers/spm/spm.c
@@ -12,6 +12,21 @@
 
 DEFINE_BAKERY_LOCK(spm_lock);
 
+/* CLK_SCP_CFG_0 */
+#define SPM_CK_OFF_CONTROL	(0x3FF)
+
+/* CLK_SCP_CFG_1 */
+#define SPM_AXI_26M_SEL		(0x1)
+
+/* AP_PLL_CON3 */
+#define SPM_PLL_CONTROL		(0x7FAAAAF)
+
+/* AP_PLL_CON4 */
+#define SPM_PLL_OUT_OFF_CONTROL	(0xFA0A)
+
+/* AP_PLL_CON6 */
+#define PLL_DLY			(0x20000)
+
 const char *wakeup_src_str[32] = {
 	[0] = "R12_PCM_TIMER",
 	[1] = "R12_SSPM_WDT_EVENT_B",
@@ -324,5 +339,14 @@
 	spm_lock_init();
 	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
 
+	/* switch ck_off/axi_26m control to SPM */
+	mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_OFF_CONTROL);
+	mmio_setbits_32(CLK_SCP_CFG_1, SPM_AXI_26M_SEL);
+
+	/* switch PLL/CLKSQ control to SPM */
+	mmio_clrbits_32(AP_PLL_CON3, SPM_PLL_CONTROL);
+	mmio_clrbits_32(AP_PLL_CON4, SPM_PLL_OUT_OFF_CONTROL);
+	mmio_clrbits_32(AP_PLL_CON6, PLL_DLY);
+
 	NOTICE("%s() end\n", __func__);
 }
diff --git a/plat/mediatek/mt8183/include/mt_gic_v3.h b/plat/mediatek/mt8183/include/mt_gic_v3.h
index 9d78ddb..b6fc29b 100644
--- a/plat/mediatek/mt8183/include/mt_gic_v3.h
+++ b/plat/mediatek/mt8183/include/mt_gic_v3.h
@@ -15,15 +15,19 @@
 #define GIC500_ACTIVE_CPU_SHIFT 16
 #define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT)
 
+#define NR_INT_POL_CTL 20
+
 void mt_gic_driver_init(void);
 void mt_gic_init(void);
 void mt_gic_set_pending(uint32_t irq);
 uint32_t mt_gic_get_pending(uint32_t irq);
 void mt_gic_cpuif_enable(void);
 void mt_gic_cpuif_disable(void);
-void mt_gic_pcpu_init(void);
-void mt_gic_irq_save(void);
-void mt_gic_irq_restore(void);
+void mt_gic_rdistif_init(void);
+void mt_gic_distif_save(void);
+void mt_gic_distif_restore(void);
+void mt_gic_rdistif_save(void);
+void mt_gic_rdistif_restore(void);
 void mt_gic_sync_dcm_enable(void);
 void mt_gic_sync_dcm_disable(void);
 
diff --git a/plat/mediatek/mt8183/include/platform_def.h b/plat/mediatek/mt8183/include/platform_def.h
index 0a1e038..ad81a33 100644
--- a/plat/mediatek/mt8183/include/platform_def.h
+++ b/plat/mediatek/mt8183/include/platform_def.h
@@ -39,7 +39,14 @@
 
 #define INFRACFG_AO_BASE   (IO_PHYS + 0x1000)
 
+#define TOPCKGEN_BASE      (IO_PHYS + 0x0)
+#define CLK_SCP_CFG_0      (TOPCKGEN_BASE + 0x200)
+#define CLK_SCP_CFG_1      (TOPCKGEN_BASE + 0x204)
+
 #define APMIXEDSYS         (IO_PHYS + 0xC000)
+#define AP_PLL_CON3        (APMIXEDSYS + 0xC)
+#define AP_PLL_CON4        (APMIXEDSYS + 0x10)
+#define AP_PLL_CON6        (APMIXEDSYS + 0x18)
 #define ARMPLL_LL_CON0     (APMIXEDSYS + 0x200)
 #define ARMPLL_L_CON0      (APMIXEDSYS + 0x210)
 #define ARMPLL_L_PWR_CON0  (APMIXEDSYS + 0x21c)
diff --git a/plat/mediatek/mt8183/plat_mt_gic.c b/plat/mediatek/mt8183/plat_mt_gic.c
index ccb72be..35792b2 100644
--- a/plat/mediatek/mt8183/plat_mt_gic.c
+++ b/plat/mediatek/mt8183/plat_mt_gic.c
@@ -11,18 +11,17 @@
 #include <bl31/interrupt_mgmt.h>
 #include <mt_gic_v3.h>
 #include <mtk_plat_common.h>
+#include "../drivers/arm/gic/v3/gicv3_private.h"
 #include "plat_private.h"
 #include <plat/common/platform.h>
 #include <platform_def.h>
 #include <stdint.h>
 #include <stdio.h>
 
-#define NR_INT_POL_CTL         20
-
 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
 
 /* we save and restore the GICv3 context on system suspend */
-gicv3_redist_ctx_t rdist_ctx;
 gicv3_dist_ctx_t dist_ctx;
 
 static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
@@ -38,6 +37,16 @@
 	.mpidr_to_core_pos = mt_mpidr_to_core_pos,
 };
 
+struct gic_chip_data {
+	unsigned int saved_group;
+	unsigned int saved_enable;
+	unsigned int saved_conf0;
+	unsigned int saved_conf1;
+	unsigned int saved_grpmod;
+};
+
+static struct gic_chip_data gic_data;
+
 void clear_sec_pol_ctl_en(void)
 {
 	unsigned int i;
@@ -54,15 +63,6 @@
 	gicv3_driver_init(&mt_gicv3_data);
 }
 
-void mt_gic_init(void)
-{
-	gicv3_distif_init();
-	gicv3_rdistif_init(plat_my_core_pos());
-	gicv3_cpuif_enable(plat_my_core_pos());
-
-	clear_sec_pol_ctl_en();
-}
-
 void mt_gic_set_pending(uint32_t irq)
 {
 	gicv3_set_interrupt_pending(irq, plat_my_core_pos());
@@ -78,35 +78,83 @@
 	gicv3_cpuif_disable(plat_my_core_pos());
 }
 
-void mt_gic_pcpu_init(void)
+void mt_gic_rdistif_init(void)
 {
-	gicv3_rdistif_init(plat_my_core_pos());
+	unsigned int proc_num;
+	unsigned int index;
+	uintptr_t gicr_base;
+
+	proc_num = plat_my_core_pos();
+	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+	/* set all SGI/PPI as non-secure GROUP1 by default */
+	mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
+	mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
+
+	/* setup the default PPI/SGI priorities */
+	for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
+		gicr_write_ipriorityr(gicr_base, index,
+				GICD_IPRIORITYR_DEF_VAL);
 }
 
-void mt_gic_irq_save(void)
+void mt_gic_distif_save(void)
 {
-	gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
 	gicv3_distif_save(&dist_ctx);
 }
 
-void mt_gic_irq_restore(void)
+void mt_gic_distif_restore(void)
 {
 	gicv3_distif_init_restore(&dist_ctx);
-	gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
+}
+
+void mt_gic_rdistif_save(void)
+{
+	unsigned int proc_num;
+	uintptr_t gicr_base;
+
+	proc_num = plat_my_core_pos();
+	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+	gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
+	gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
+	gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
+	gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
+	gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
+
+	rdist_has_saved[proc_num] = 1;
+}
+
+void mt_gic_rdistif_restore(void)
+{
+	unsigned int proc_num;
+	uintptr_t gicr_base;
+
+	proc_num = plat_my_core_pos();
+	if (rdist_has_saved[proc_num] == 1) {
+		gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+		mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
+		mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable);
+		mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
+		mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
+		mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod);
+	}
 }
 
 void mt_gic_sync_dcm_enable(void)
 {
-	unsigned int val = mmio_read_32(GIC_SYNC_DCM);
-
-	val &= ~GIC_SYNC_DCM_MASK;
-	mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON);
+	mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON);
 }
 
 void mt_gic_sync_dcm_disable(void)
 {
-	unsigned int val = mmio_read_32(GIC_SYNC_DCM);
+	mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF);
+}
 
-	val &= ~GIC_SYNC_DCM_MASK;
-	mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF);
+void mt_gic_init(void)
+{
+	gicv3_distif_init();
+	gicv3_cpuif_enable(plat_my_core_pos());
+	mt_gic_rdistif_init();
+
+	clear_sec_pol_ctl_en();
 }
diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c
index 555b389..2358ec6 100644
--- a/plat/mediatek/mt8183/plat_pm.c
+++ b/plat/mediatek/mt8183/plat_pm.c
@@ -152,6 +152,21 @@
 	return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx)));
 }
 
+static void plat_cpu_pwrdwn_common(void)
+{
+	/* Prevent interrupts from spuriously waking up this cpu */
+	mt_gic_rdistif_save();
+	mt_gic_cpuif_disable();
+}
+
+static void plat_cpu_pwron_common(void)
+{
+	/* Enable the gic cpu interface */
+	mt_gic_cpuif_enable();
+	mt_gic_rdistif_init();
+	mt_gic_rdistif_restore();
+}
+
 static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster)
 {
 	if (cluster > 0)
@@ -289,13 +304,19 @@
 {
 	int cpu = MPIDR_AFFLVL0_VAL(mpidr);
 	int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+	int clst_pwr = spm_get_cluster_powerstate(cluster);
+	unsigned int i;
 
 	mcdi_ctrl_before_hotplug_on(cluster, cpu);
 	hotplug_ctrl_cluster_on(cluster, cpu);
 
-	/* init cpu reset arch as AARCH64 */
-	mcucfg_init_archstate(cluster, cpu, 1);
-	mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+	if (clst_pwr == 0) {
+		/* init cpu reset arch as AARCH64 of cluster */
+		for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+			mcucfg_init_archstate(cluster, i, 1);
+			mcucfg_set_bootaddr(cluster, i, secure_entrypoint);
+		}
+	}
 
 	hotplug_ctrl_cpu_on(cluster, cpu);
 
@@ -312,7 +333,7 @@
 	bool cluster_off = (HP_CLUSTER_OFF && afflvl1 &&
 					clst_single_on(cluster, cpu));
 
-	mt_gic_cpuif_disable();
+	plat_cpu_pwrdwn_common();
 
 	if (cluster_off)
 		plat_cluster_pwrdwn_common(mpidr, cluster);
@@ -332,8 +353,7 @@
 	if (afflvl1)
 		plat_cluster_pwron_common(mpidr, cluster);
 
-	mt_gic_pcpu_init();
-	mt_gic_cpuif_enable();
+	plat_cpu_pwron_common();
 
 	hotplug_ctrl_cpu_on_finish(cluster, cpu);
 }
@@ -348,12 +368,8 @@
 	bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF);
 	bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu);
 
-	/* init cpu reset arch as AARCH64 */
-	mcucfg_init_archstate(cluster, cpu, 1);
-	mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+	plat_cpu_pwrdwn_common();
 
-	mt_gic_cpuif_disable();
-	mt_gic_irq_save();
 	plat_dcm_mcsi_a_backup();
 
 	if (cluster_off || afflvl2)
@@ -376,6 +392,8 @@
 		if (MCDI_SSPM)
 			while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l))
 				;
+
+		mt_gic_distif_save();
 	} else {
 		mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off);
 	}
@@ -394,7 +412,9 @@
 		uint32_t l = sizeof(spm_d) / sizeof(uint32_t);
 
 		mt_gic_init();
-		mt_gic_irq_restore();
+		mt_gic_distif_restore();
+		mt_gic_rdistif_restore();
+
 		mmio_write_32(EMI_WFIFO, 0xf);
 
 		if (MCDI_SSPM)
@@ -407,6 +427,8 @@
 				;
 
 		mcdi_ctrl_resume();
+	} else {
+		plat_cpu_pwron_common();
 	}
 
 	plat_cluster_pwron_common(mpidr, cluster);
@@ -541,15 +563,23 @@
 	.system_off			= plat_mtk_system_off,
 	.system_reset			= plat_mtk_system_reset,
 	.validate_power_state		= plat_mtk_validate_power_state,
-	.get_sys_suspend_power_state	= plat_mtk_get_sys_suspend_power_state,
+	.get_sys_suspend_power_state	= plat_mtk_get_sys_suspend_power_state
 };
 
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const plat_psci_ops_t **psci_ops)
 {
+	unsigned int i;
+
 	*psci_ops = &plat_plat_pm_ops;
 	secure_entrypoint = sec_entrypoint;
 
+	/* Init cpu reset arch as AARCH64 of cluster 0 */
+	for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+		mcucfg_init_archstate(0, i, 1);
+		mcucfg_set_bootaddr(0, i, secure_entrypoint);
+	}
+
 	if (!check_mcdi_ctl_stat()) {
 		HP_SSPM_CTRL = false;
 		MCDI_SSPM = false;
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index f89e77a..a665276 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -129,10 +129,8 @@
 	struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
 	plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
 	image_info_t bl32_img_info = { {0} };
-	uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base;
-	uint32_t console_clock;
+	uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
 	int32_t ret;
-	static console_16550_t console;
 
 	/*
 	 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
@@ -182,31 +180,9 @@
 	}
 
 	/*
-	 * Reference clock used by the FPGAs is a lot slower.
+	 * Enable console for the platform
 	 */
-	if (tegra_platform_is_fpga()) {
-		console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
-	} else {
-		console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
-	}
-
-	/*
-	 * Get the base address of the UART controller to be used for the
-	 * console
-	 */
-	console_base = plat_get_console_from_id(plat_params->uart_id);
-
-	if (console_base != 0U) {
-		/*
-		 * Configure the UART port to be used as the console
-		 */
-		(void)console_16550_register(console_base,
-					     console_clock,
-					     TEGRA_CONSOLE_BAUDRATE,
-					     &console);
-		console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
-			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
-	}
+	plat_enable_console(plat_params->uart_id);
 
 	/*
 	 * The previous bootloader passes the base address of the shared memory
diff --git a/plat/nvidia/tegra/include/drivers/spe.h b/plat/nvidia/tegra/include/drivers/spe.h
new file mode 100644
index 0000000..0d6d69d
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/spe.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SPE_H
+#define SPE_H
+
+#include <stdint.h>
+
+#include <drivers/console.h>
+
+typedef struct {
+	console_t console;
+	uintptr_t base;
+} console_spe_t;
+
+/*
+ * Initialize a new spe console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ */
+int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
+			   console_spe_t *console);
+
+#endif /* SPE_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra194_private.h b/plat/nvidia/tegra/include/t194/tegra194_private.h
new file mode 100644
index 0000000..e519cdc
--- /dev/null
+++ b/plat/nvidia/tegra/include/t194/tegra194_private.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEGRA194_PRIVATE_H__
+#define __TEGRA194_PRIVATE_H__
+
+void tegra194_cpu_reset_handler(void);
+uint64_t tegra194_get_cpu_reset_handler_base(void);
+uint64_t tegra194_get_cpu_reset_handler_size(void);
+uint64_t tegra194_get_smmu_ctx_offset(void);
+void tegra194_set_system_suspend_entry(void);
+
+#endif /* __TEGRA194_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 79d776f..1a9ba0a 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -14,9 +14,9 @@
  * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
  * parameter.
  ******************************************************************************/
-#define PSTATE_ID_CORE_IDLE		6
-#define PSTATE_ID_CORE_POWERDN		7
-#define PSTATE_ID_SOC_POWERDN		2
+#define PSTATE_ID_CORE_IDLE		U(6)
+#define PSTATE_ID_CORE_POWERDN		U(7)
+#define PSTATE_ID_SOC_POWERDN		U(2)
 
 /*******************************************************************************
  * Platform power states (used by PSCI framework)
@@ -24,215 +24,211 @@
  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
  ******************************************************************************/
-#define PLAT_MAX_RET_STATE		1
-#define PLAT_MAX_OFF_STATE		8
-
-/*******************************************************************************
- * Implementation defined ACTLR_EL3 bit definitions
- ******************************************************************************/
-#define ACTLR_EL3_L2ACTLR_BIT		(1 << 6)
-#define ACTLR_EL3_L2ECTLR_BIT		(1 << 5)
-#define ACTLR_EL3_L2CTLR_BIT		(1 << 4)
-#define ACTLR_EL3_CPUECTLR_BIT		(1 << 1)
-#define ACTLR_EL3_CPUACTLR_BIT		(1 << 0)
-#define ACTLR_EL3_ENABLE_ALL_ACCESS	(ACTLR_EL3_L2ACTLR_BIT | \
-					 ACTLR_EL3_L2ECTLR_BIT | \
-					 ACTLR_EL3_L2CTLR_BIT | \
-					 ACTLR_EL3_CPUECTLR_BIT | \
-					 ACTLR_EL3_CPUACTLR_BIT)
+#define PLAT_MAX_RET_STATE		U(1)
+#define PLAT_MAX_OFF_STATE		U(8)
 
 /*******************************************************************************
  * Secure IRQ definitions
  ******************************************************************************/
-#define TEGRA186_MAX_SEC_IRQS		5
-#define TEGRA186_BPMP_WDT_IRQ		46
-#define TEGRA186_SPE_WDT_IRQ		47
-#define TEGRA186_SCE_WDT_IRQ		48
-#define TEGRA186_TOP_WDT_IRQ		49
-#define TEGRA186_AON_WDT_IRQ		50
+#define TEGRA194_MAX_SEC_IRQS		U(2)
+#define TEGRA194_TOP_WDT_IRQ		U(49)
+#define TEGRA194_AON_WDT_IRQ		U(50)
 
-#define TEGRA186_SEC_IRQ_TARGET_MASK	0xFF /* 8 Carmel */
+#define TEGRA194_SEC_IRQ_TARGET_MASK	U(0xFF) /* 8 Carmel */
 
 /*******************************************************************************
  * Tegra Miscellanous register constants
  ******************************************************************************/
-#define TEGRA_MISC_BASE			0x00100000
-#define  HARDWARE_REVISION_OFFSET	0x4
+#define TEGRA_MISC_BASE			U(0x00100000)
 
-#define  MISCREG_PFCFG			0x200C
-
-/*******************************************************************************
- * Tegra TSA Controller constants
- ******************************************************************************/
-#define TEGRA_TSA_BASE			0x02000000
-
-#define TSA_CONFIG_STATIC0_CSW_SESWR		0x1010
-#define  TSA_CONFIG_STATIC0_CSW_SESWR_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_ETRW		0xD034
-#define  TSA_CONFIG_STATIC0_CSW_ETRW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB		0x3020
-#define  TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_AXISW		0x8008
-#define  TSA_CONFIG_STATIC0_CSW_AXISW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_HDAW		0xD008
-#define  TSA_CONFIG_STATIC0_CSW_HDAW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_AONDMAW		0xE018
-#define  TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_SCEDMAW		0x9008
-#define  TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW		0x9028
-#define  TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_APEDMAW		0xB008
-#define  TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_UFSHCW		0x6008
-#define  TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_AFIW		0xF008
-#define  TSA_CONFIG_STATIC0_CSW_AFIW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_SATAW		0x4008
-#define  TSA_CONFIG_STATIC0_CSW_SATAW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_EQOSW		0x3038
-#define  TSA_CONFIG_STATIC0_CSW_EQOSW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW	0x6018
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET	0x1100
-#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW	0x6028
-#define  TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
-
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK	(0x3 << 11)
-#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU	(0 << 11)
+#define HARDWARE_REVISION_OFFSET	U(0x4)
+#define MISCREG_EMU_REVID		U(0x3160)
+#define  BOARD_MASK_BITS		U(0xFF)
+#define  BOARD_SHIFT_BITS		U(24)
+#define MISCREG_PFCFG			U(0x200C)
 
 /*******************************************************************************
  * Tegra Memory Controller constants
  ******************************************************************************/
-#define TEGRA_MC_STREAMID_BASE		0x02C00000
-#define TEGRA_MC_BASE			0x02C10000
+#define TEGRA_MC_STREAMID_BASE		U(0x02C00000)
+#define TEGRA_MC_BASE			U(0x02C10000)
 
 /* General Security Carveout register macros */
-#define MC_GSC_CONFIG_REGS_SIZE		0x40
-#define MC_GSC_LOCK_CFG_SETTINGS_BIT	(1 << 1)
-#define MC_GSC_ENABLE_TZ_LOCK_BIT	(1 << 0)
-#define MC_GSC_SIZE_RANGE_4KB_SHIFT	27
-#define MC_GSC_BASE_LO_SHIFT		12
-#define MC_GSC_BASE_LO_MASK		0xFFFFF
-#define MC_GSC_BASE_HI_SHIFT		0
-#define MC_GSC_BASE_HI_MASK		3
+#define MC_GSC_CONFIG_REGS_SIZE		U(0x40)
+#define MC_GSC_LOCK_CFG_SETTINGS_BIT	(U(1) << 1)
+#define MC_GSC_ENABLE_TZ_LOCK_BIT	(U(1) << 0)
+#define MC_GSC_SIZE_RANGE_4KB_SHIFT	U(27)
+#define MC_GSC_BASE_LO_SHIFT		U(12)
+#define MC_GSC_BASE_LO_MASK		U(0xFFFFF)
+#define MC_GSC_BASE_HI_SHIFT		U(0)
+#define MC_GSC_BASE_HI_MASK		U(3)
+#define MC_GSC_ENABLE_CPU_SECURE_BIT    (U(1) << 31)
 
 /* TZDRAM carveout configuration registers */
-#define MC_SECURITY_CFG0_0		0x70
-#define MC_SECURITY_CFG1_0		0x74
-#define MC_SECURITY_CFG3_0		0x9BC
+#define MC_SECURITY_CFG0_0		U(0x70)
+#define MC_SECURITY_CFG1_0		U(0x74)
+#define MC_SECURITY_CFG3_0		U(0x9BC)
+
+#define MC_SECURITY_BOM_MASK		(U(0xFFF) << 20)
+#define MC_SECURITY_SIZE_MB_MASK	(U(0x1FFF) << 0)
+#define MC_SECURITY_BOM_HI_MASK		(U(0x3) << 0)
+
+#define MC_SECURITY_CFG_REG_CTRL_0	U(0x154)
+#define  SECURITY_CFG_WRITE_ACCESS_BIT	(U(0x1) << 0)
+#define  SECURITY_CFG_WRITE_ACCESS_ENABLE	U(0x0)
+#define  SECURITY_CFG_WRITE_ACCESS_DISABLE	U(0x1)
 
 /* Video Memory carveout configuration registers */
-#define MC_VIDEO_PROTECT_BASE_HI	0x978
-#define MC_VIDEO_PROTECT_BASE_LO	0x648
-#define MC_VIDEO_PROTECT_SIZE_MB	0x64c
+#define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
+#define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
+#define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
 
 /*
  * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
  * non-overlapping Video memory region
  */
-#define MC_VIDEO_PROTECT_CLEAR_CFG	0x25A0
-#define MC_VIDEO_PROTECT_CLEAR_BASE_LO	0x25A4
-#define MC_VIDEO_PROTECT_CLEAR_BASE_HI	0x25A8
-#define MC_VIDEO_PROTECT_CLEAR_SIZE	0x25AC
-#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0	0x25B0
+#define MC_VIDEO_PROTECT_CLEAR_CFG	U(0x25A0)
+#define MC_VIDEO_PROTECT_CLEAR_BASE_LO	U(0x25A4)
+#define MC_VIDEO_PROTECT_CLEAR_BASE_HI	U(0x25A8)
+#define MC_VIDEO_PROTECT_CLEAR_SIZE	U(0x25AC)
+#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0	U(0x25B0)
 
 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
-#define MC_TZRAM_CARVEOUT_CFG		0x2190
-#define MC_TZRAM_BASE_LO		0x2194
-#define MC_TZRAM_BASE_HI		0x2198
-#define MC_TZRAM_SIZE			0x219C
-#define MC_TZRAM_CLIENT_ACCESS_CFG0	0x21A0
+#define MC_TZRAM_CARVEOUT_CFG		U(0x2190)
+#define MC_TZRAM_BASE_LO		U(0x2194)
+#define MC_TZRAM_BASE_HI		U(0x2198)
+#define MC_TZRAM_SIZE			U(0x219C)
+#define MC_TZRAM_CLIENT_ACCESS0_CFG0	U(0x21A0)
+#define MC_TZRAM_CLIENT_ACCESS1_CFG0	U(0x21A4)
+#define  TZRAM_ALLOW_MPCORER		(U(1) << 7)
+#define  TZRAM_ALLOW_MPCOREW		(U(1) << 25)
 
 /* Memory Controller Reset Control registers */
-#define  MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB	(1 << 27)
-#define  MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB	(1 << 28)
-#define  MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB	(1 << 29)
-#define  MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB	(1 << 30)
-#define  MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB	(1 << 31)
+#define  MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB	(U(1) << 28)
+#define  MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB	(U(1) << 29)
+#define  MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB	(U(1) << 30)
+#define  MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB	(U(1) << 31)
 
 /*******************************************************************************
  * Tegra UART Controller constants
  ******************************************************************************/
-#define TEGRA_UARTA_BASE		0x03100000
-#define TEGRA_UARTB_BASE		0x03110000
-#define TEGRA_UARTC_BASE		0x0C280000
-#define TEGRA_UARTD_BASE		0x03130000
-#define TEGRA_UARTE_BASE		0x03140000
-#define TEGRA_UARTF_BASE		0x03150000
-#define TEGRA_UARTG_BASE		0x0C290000
+#define TEGRA_UARTA_BASE		U(0x03100000)
+#define TEGRA_UARTB_BASE		U(0x03110000)
+#define TEGRA_UARTC_BASE		U(0x0C280000)
+#define TEGRA_UARTD_BASE		U(0x03130000)
+#define TEGRA_UARTE_BASE		U(0x03140000)
+#define TEGRA_UARTF_BASE		U(0x03150000)
+#define TEGRA_UARTG_BASE		U(0x0C290000)
 
 /*******************************************************************************
  * Tegra Fuse Controller related constants
  ******************************************************************************/
-#define TEGRA_FUSE_BASE			0x03820000
-#define  OPT_SUBREVISION		0x248
-#define  SUBREVISION_MASK		0xF
+#define TEGRA_FUSE_BASE			U(0x03820000)
+#define  OPT_SUBREVISION		U(0x248)
+#define  SUBREVISION_MASK		U(0xF)
 
 /*******************************************************************************
  * GICv2 & interrupt handling related constants
  ******************************************************************************/
-#define TEGRA_GICD_BASE			0x03881000
-#define TEGRA_GICC_BASE			0x03882000
+#define TEGRA_GICD_BASE			U(0x03881000)
+#define TEGRA_GICC_BASE			U(0x03882000)
 
 /*******************************************************************************
  * Security Engine related constants
  ******************************************************************************/
-#define TEGRA_SE0_BASE			0x03AC0000
-#define  SE_MUTEX_WATCHDOG_NS_LIMIT	0x6C
-#define TEGRA_PKA1_BASE			0x03AD0000
-#define  PKA_MUTEX_WATCHDOG_NS_LIMIT	0x8144
-#define TEGRA_RNG1_BASE			0x03AE0000
-#define  RNG_MUTEX_WATCHDOG_NS_LIMIT	0xFE0
+#define TEGRA_SE0_BASE			U(0x03AC0000)
+#define  SE0_MUTEX_WATCHDOG_NS_LIMIT	U(0x6C)
+#define  SE0_AES0_ENTROPY_SRC_AGE_CTRL	U(0x2FC)
+#define TEGRA_PKA1_BASE			U(0x03AD0000)
+#define  SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
+#define  PKA1_MUTEX_WATCHDOG_NS_LIMIT	SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
+#define TEGRA_RNG1_BASE			U(0x03AE0000)
+#define  RNG1_MUTEX_WATCHDOG_NS_LIMIT	U(0xFE0)
+
+/*******************************************************************************
+ * Tegra hardware synchronization primitives for the SPE engine
+ ******************************************************************************/
+#define TEGRA_AON_HSP_SM_6_7_BASE	U(0x0c190000)
+#define TEGRA_CONSOLE_SPE_BASE		(TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000))
 
 /*******************************************************************************
  * Tegra micro-seconds timer constants
  ******************************************************************************/
-#define TEGRA_TMRUS_BASE		0x0C2E0000
-#define TEGRA_TMRUS_SIZE		0x10000
+#define TEGRA_TMRUS_BASE		U(0x0C2E0000)
+#define TEGRA_TMRUS_SIZE		U(0x10000)
 
 /*******************************************************************************
  * Tegra Power Mgmt Controller constants
  ******************************************************************************/
-#define TEGRA_PMC_BASE			0x0C360000
+#define TEGRA_PMC_BASE			U(0x0C360000)
 
 /*******************************************************************************
  * Tegra scratch registers constants
  ******************************************************************************/
-#define TEGRA_SCRATCH_BASE		0x0C390000
-#define  SECURE_SCRATCH_RSV1_LO		0x06C
-#define  SECURE_SCRATCH_RSV1_HI		0x070
-#define  SECURE_SCRATCH_RSV6		0x094
-#define  SECURE_SCRATCH_RSV11_LO	0x0BC
-#define  SECURE_SCRATCH_RSV11_HI	0x0C0
-#define  SECURE_SCRATCH_RSV53_LO	0x20C
-#define  SECURE_SCRATCH_RSV53_HI	0x210
-#define  SECURE_SCRATCH_RSV54_HI	0x218
-#define  SECURE_SCRATCH_RSV55_LO	0x21C
-#define  SECURE_SCRATCH_RSV55_HI	0x220
+#define TEGRA_SCRATCH_BASE		U(0x0C390000)
+#define  SECURE_SCRATCH_RSV44_LO	U(0x1C4)
+#define  SECURE_SCRATCH_RSV44_HI	U(0x1C8)
+#define  SECURE_SCRATCH_RSV97		U(0x36C)
+#define  SECURE_SCRATCH_RSV99_LO	U(0x37C)
+#define  SECURE_SCRATCH_RSV99_HI	U(0x380)
+#define  SECURE_SCRATCH_RSV109_LO	U(0x3CC)
+#define  SECURE_SCRATCH_RSV109_HI	U(0x3D0)
+
+#define SCRATCH_BL31_PARAMS_ADDR	SECURE_SCRATCH_RSV44_LO
+#define SCRATCH_BL31_PLAT_PARAMS_ADDR	SECURE_SCRATCH_RSV44_HI
+#define SCRATCH_SECURE_BOOTP_FCFG	SECURE_SCRATCH_RSV97
+#define SCRATCH_SMMU_TABLE_ADDR_LO	SECURE_SCRATCH_RSV99_LO
+#define SCRATCH_SMMU_TABLE_ADDR_HI	SECURE_SCRATCH_RSV99_HI
+#define SCRATCH_RESET_VECTOR_LO		SECURE_SCRATCH_RSV109_LO
+#define SCRATCH_RESET_VECTOR_HI		SECURE_SCRATCH_RSV109_HI
 
 /*******************************************************************************
  * Tegra Memory Mapped Control Register Access Bus constants
  ******************************************************************************/
-#define TEGRA_MMCRAB_BASE		0x0E000000
+#define TEGRA_MMCRAB_BASE		U(0x0E000000)
 
 /*******************************************************************************
  * Tegra SMMU Controller constants
  ******************************************************************************/
-#define TEGRA_SMMU0_BASE		0x12000000
-#define TEGRA_SMMU1_BASE		0x11000000
-#define TEGRA_SMMU2_BASE		0x10000000
+#define TEGRA_SMMU0_BASE		U(0x12000000)
+#define TEGRA_SMMU1_BASE		U(0x11000000)
+#define TEGRA_SMMU2_BASE		U(0x10000000)
 
 /*******************************************************************************
  * Tegra TZRAM constants
  ******************************************************************************/
-#define TEGRA_TZRAM_BASE		0x40000000
-#define TEGRA_TZRAM_SIZE		0x40000
+#define TEGRA_TZRAM_BASE		U(0x40000000)
+#define TEGRA_TZRAM_SIZE		U(0x40000)
 
 /*******************************************************************************
  * Tegra Clock and Reset Controller constants
  ******************************************************************************/
-#define TEGRA_CAR_RESET_BASE		0x200000000
-#define TEGRA_GPU_RESET_REG_OFFSET	0x18UL
-#define  GPU_RESET_BIT			(1UL << 0)
+#define TEGRA_CAR_RESET_BASE		U(0x20000000)
+#define TEGRA_GPU_RESET_REG_OFFSET	U(0x18)
+#define TEGRA_GPU_RESET_GPU_SET_OFFSET  U(0x1C)
+#define  GPU_RESET_BIT			(U(1) << 0)
+#define  GPU_SET_BIT			(U(1) << 0)
+
+/*******************************************************************************
+ * XUSB PADCTL
+ ******************************************************************************/
+#define TEGRA_XUSB_PADCTL_BASE			U(0x3520000)
+#define TEGRA_XUSB_PADCTL_SIZE			U(0x10000)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0	U(0x136c)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0	U(0x1370)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1	U(0x1374)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2	U(0x1378)
+#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3	U(0x137c)
+#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0	U(0x139c)
+
+/*******************************************************************************
+ * XUSB STREAMIDs
+ ******************************************************************************/
+#define TEGRA_SID_XUSB_HOST			U(0x1b)
+#define TEGRA_SID_XUSB_DEV			U(0x1c)
+#define TEGRA_SID_XUSB_VF0			U(0x5d)
+#define TEGRA_SID_XUSB_VF1			U(0x5e)
+#define TEGRA_SID_XUSB_VF2			U(0x5f)
+#define TEGRA_SID_XUSB_VF3			U(0x60)
 
 #endif /* __TEGRA_DEF_H__ */
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index fab0eaf..cd2f773 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -76,7 +76,7 @@
 
 /* Declarations for plat_setup.c */
 const mmap_region_t *plat_get_mmio_map(void);
-uint32_t plat_get_console_from_id(int32_t id);
+void plat_enable_console(int32_t id);
 void plat_gic_setup(void);
 struct tegra_bl31_params *plat_get_bl31_params(void);
 plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 570acd9..df62678 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -6,9 +6,11 @@
 
 #include <arch_helpers.h>
 #include <common/bl_common.h>
+#include <drivers/console.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 #include <tegra_def.h>
+#include <tegra_platform.h>
 #include <tegra_private.h>
 
 /* sets of MMIO ranges setup */
@@ -85,14 +87,30 @@
 };
 
 /*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
  ******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
 {
-	if (id > TEGRA132_MAX_UART_PORTS)
-		return 0;
+	static console_16550_t uart_console;
+	uint32_t console_clock;
 
-	return tegra132_uart_addresses[id];
+	if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
+		/*
+		 * Reference clock used by the FPGAs is a lot slower.
+		 */
+		if (tegra_platform_is_fpga()) {
+			console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+		} else {
+			console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+		}
+
+		(void)console_16550_register(tegra132_uart_addresses[id],
+					     console_clock,
+					     TEGRA_CONSOLE_BAUDRATE,
+					     &uart_console);
+		console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+	}
 }
 
 /*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index ef0ba4e..1018caa 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -141,19 +141,30 @@
 };
 
 /*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
  ******************************************************************************/
-uint32_t plat_get_console_from_id(int32_t id)
+void plat_enable_console(int32_t id)
 {
-	uint32_t ret;
+	static console_16550_t uart_console;
+	uint32_t console_clock;
 
-	if (id > TEGRA186_MAX_UART_PORTS) {
-		ret = 0;
-	} else {
-		ret = tegra186_uart_addresses[id];
+	if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
+		/*
+		 * Reference clock used by the FPGAs is a lot slower.
+		 */
+		if (tegra_platform_is_fpga()) {
+			console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+		} else {
+			console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+		}
+
+		(void)console_16550_register(tegra186_uart_addresses[id],
+					     console_clock,
+					     TEGRA_CONSOLE_BAUDRATE,
+					     &uart_console);
+		console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
 	}
-
-	return ret;
 }
 
 /*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index cc32ec4..3994b2d 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -7,44 +7,40 @@
 #ifndef __MCE_PRIVATE_H__
 #define __MCE_PRIVATE_H__
 
-#include <mmio.h>
 #include <tegra_def.h>
 
 /*******************************************************************************
  * Macros to prepare CSTATE info request
  ******************************************************************************/
 /* Description of the parameters for UPDATE_CSTATE_INFO request */
-#define CLUSTER_CSTATE_MASK				0x7UL
-#define CLUSTER_CSTATE_SHIFT			0X0UL
-#define CLUSTER_CSTATE_UPDATE_BIT		(1UL << 7)
-#define CCPLEX_CSTATE_MASK				0x3UL
-#define CCPLEX_CSTATE_SHIFT				8UL
-#define CCPLEX_CSTATE_UPDATE_BIT		(1UL << 15)
-#define SYSTEM_CSTATE_MASK				0xFUL
-#define SYSTEM_CSTATE_SHIFT				16UL
-#define SYSTEM_CSTATE_UPDATE_BIT		(1UL << 23)
-#define CSTATE_WAKE_MASK_UPDATE_BIT		(1UL << 31)
-#define CSTATE_WAKE_MASK_SHIFT			32UL
-#define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFFUL
-
-/*******************************************************************************
- * Auto-CC3 control macros
- ******************************************************************************/
-#define MCE_AUTO_CC3_FREQ_MASK			0xFFUL
-#define MCE_AUTO_CC3_FREQ_SHIFT			0UL
-#define MCE_AUTO_CC3_ENABLE_BIT			(1UL << 31)
+#define CLUSTER_CSTATE_MASK			0x7U
+#define CLUSTER_CSTATE_SHIFT			0X0U
+#define CLUSTER_CSTATE_UPDATE_BIT		(1U << 7)
+#define CCPLEX_CSTATE_MASK			0x7U
+#define CCPLEX_CSTATE_SHIFT			8U
+#define CCPLEX_CSTATE_UPDATE_BIT		(1U << 15)
+#define SYSTEM_CSTATE_MASK			0xFU
+#define SYSTEM_CSTATE_SHIFT			16U
+#define SYSTEM_CSTATE_UPDATE_BIT		(1U << 23)
+#define CSTATE_WAKE_MASK_UPDATE_BIT		(1U << 31)
+#define CSTATE_WAKE_MASK_SHIFT			32U
+#define CSTATE_WAKE_MASK_CLEAR			0xFFFFFFFFU
 
 /*******************************************************************************
  * Core ID mask (bits 3:0 in the online request)
  ******************************************************************************/
-#define MCE_CORE_ID_MASK				0xFUL
+#define MCE_CORE_ID_MASK			0xFU
 
 /*******************************************************************************
- * Cache control macros
+ * C-state statistics macros
  ******************************************************************************/
-#define CACHE_CLEAN_SET					(1UL << 0)
-#define CACHE_CLEAN_INVAL_SET			(1UL << 1)
-#define CACHE_CLEAN_INVAL_TR_SET		(1UL << 2)
+#define MCE_STAT_ID_SHIFT			16U
+
+/*******************************************************************************
+ * Security config macros
+ ******************************************************************************/
+#define STRICT_CHECKING_ENABLED_SET		(1UL << 0)
+#define STRICT_CHECKING_LOCKED_SET		(1UL << 1)
 
 /* declarations for NVG handler functions */
 uint64_t nvg_get_version(void);
@@ -55,20 +51,25 @@
 void nvg_set_wake_time(uint32_t wake_time);
 void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
 		uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
-int32_t nvg_update_crossover_time(uint32_t type, uint32_t time);
 int32_t nvg_set_cstate_stat_query_value(uint64_t data);
 uint64_t nvg_get_cstate_stat_query_value(void);
 int32_t nvg_is_sc7_allowed(void);
 int32_t nvg_online_core(uint32_t core);
-int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable);
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_flush_cache(void);
 int32_t nvg_roc_clean_cache(void);
+int32_t nvg_roc_flush_cache(void);
 int32_t nvg_roc_clean_cache_trbits(void);
 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
-
 void nvg_set_request_data(uint64_t req, uint64_t data);
 void nvg_set_request(uint64_t req);
 uint64_t nvg_get_result(void);
+uint64_t nvg_cache_clean(void);
+uint64_t nvg_cache_clean_inval(void);
+uint64_t nvg_cache_inval_all(void);
+int32_t nvg_roc_clean_cache_trbits(void);
+void nvg_enable_strict_checking_mode(void);
+
+/* MCE helper functions */
+void mce_enable_strict_checking(void);
 
 #endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h b/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h
deleted file mode 100644
index 8eaae67..0000000
--- a/plat/nvidia/tegra/soc/t194/drivers/include/memctrl_plat_config.h
+++ /dev/null
@@ -1,586 +0,0 @@
-/*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __MEMCTRL_PLAT_CONFIG_H
-#define __MEMCTRL_PLAT_CONFIG_H
-
-#include <memctrl_v2.h>
-
-/*******************************************************************************
- * StreamID to indicate no SMMU translations (requests to be steered on the
- * SMMU bypass path)
- ******************************************************************************/
-#define MC_STREAM_ID_MAX			0x7F
-
-/*******************************************************************************
- * Stream ID Override Config registers
- ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_CFG_PTCR		0x000
-#define MC_STREAMID_OVERRIDE_CFG_HDAR		0x0A8
-#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR	0x0B0
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD	0x0E0
-#define MC_STREAMID_OVERRIDE_CFG_SATAR		0x0F8
-#define MC_STREAMID_OVERRIDE_CFG_MPCORER	0x138
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR	0x158
-#define MC_STREAMID_OVERRIDE_CFG_HDAW		0x1A8
-#define MC_STREAMID_OVERRIDE_CFG_MPCOREW	0x1C8
-#define MC_STREAMID_OVERRIDE_CFG_SATAW		0x1E8
-#define MC_STREAMID_OVERRIDE_CFG_ISPRA		0x220
-#define MC_STREAMID_OVERRIDE_CFG_ISPFALR	0x228
-#define MC_STREAMID_OVERRIDE_CFG_ISPWA		0x230
-#define MC_STREAMID_OVERRIDE_CFG_ISPWB		0x238
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR	0x250
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW	0x258
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR	0x260
-#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW	0x268
-#define MC_STREAMID_OVERRIDE_CFG_TSECSRD	0x2A0
-#define MC_STREAMID_OVERRIDE_CFG_TSECSWR	0x2A8
-#define MC_STREAMID_OVERRIDE_CFG_GPUSRD		0x2C0	/*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_GPUSWR		0x2C8	/*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA	0x300
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCR		0x310
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB	0x318
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA	0x320
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCW		0x330
-#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB	0x338
-#define MC_STREAMID_OVERRIDE_CFG_VICSRD		0x360
-#define MC_STREAMID_OVERRIDE_CFG_VICSWR		0x368
-#define MC_STREAMID_OVERRIDE_CFG_VIW		0x390
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD	0x3C0
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR	0x3C8
-#define MC_STREAMID_OVERRIDE_CFG_APER		0x3D0
-#define MC_STREAMID_OVERRIDE_CFG_APEW		0x3D8
-#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD	0x3F0
-#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR	0x3F8
-#define MC_STREAMID_OVERRIDE_CFG_SESRD		0x400
-#define MC_STREAMID_OVERRIDE_CFG_SESWR		0x408
-#define MC_STREAMID_OVERRIDE_CFG_AXIAPR		0x410
-#define MC_STREAMID_OVERRIDE_CFG_AXIAPW		0x418
-#define MC_STREAMID_OVERRIDE_CFG_ETRR		0x420
-#define MC_STREAMID_OVERRIDE_CFG_ETRW		0x428
-#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB	0x430
-#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB	0x438
-#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2	0x440	/*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2	0x448	/*TODO: remove it after HW team confirmation */
-#define MC_STREAMID_OVERRIDE_CFG_AXISR		0x460
-#define MC_STREAMID_OVERRIDE_CFG_AXISW		0x468
-#define MC_STREAMID_OVERRIDE_CFG_EQOSR		0x470
-#define MC_STREAMID_OVERRIDE_CFG_EQOSW		0x478
-#define MC_STREAMID_OVERRIDE_CFG_UFSHCR		0x480
-#define MC_STREAMID_OVERRIDE_CFG_UFSHCW		0x488
-#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR	0x490
-#define MC_STREAMID_OVERRIDE_CFG_BPMPR		0x498
-#define MC_STREAMID_OVERRIDE_CFG_BPMPW		0x4A0
-#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR	0x4A8
-#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW	0x4B0
-#define MC_STREAMID_OVERRIDE_CFG_AONR		0x4B8
-#define MC_STREAMID_OVERRIDE_CFG_AONW		0x4C0
-#define MC_STREAMID_OVERRIDE_CFG_AONDMAR	0x4C8
-#define MC_STREAMID_OVERRIDE_CFG_AONDMAW	0x4D0
-#define MC_STREAMID_OVERRIDE_CFG_SCER		0x4D8
-#define MC_STREAMID_OVERRIDE_CFG_SCEW		0x4E0
-#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR	0x4E8
-#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW	0x4F0
-#define MC_STREAMID_OVERRIDE_CFG_APEDMAR	0x4F8
-#define MC_STREAMID_OVERRIDE_CFG_APEDMAW	0x500
-#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1	0x508
-#define MC_STREAMID_OVERRIDE_CFG_VICSRD1	0x510
-#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1	0x518
-#define MC_STREAMID_OVERRIDE_CFG_MIU0R		0x530
-#define MC_STREAMID_OVERRIDE_CFG_MIU0W		0x538
-#define MC_STREAMID_OVERRIDE_CFG_MIU1R		0x540
-#define MC_STREAMID_OVERRIDE_CFG_MIU1W		0x548
-#define MC_STREAMID_OVERRIDE_CFG_MIU2R		0x570
-#define MC_STREAMID_OVERRIDE_CFG_MIU2W		0x578
-#define MC_STREAMID_OVERRIDE_CFG_MIU3R		0x580
-#define MC_STREAMID_OVERRIDE_CFG_MIU3W		0x588
-#define MC_STREAMID_OVERRIDE_CFG_VIFALR		0x5E0
-#define MC_STREAMID_OVERRIDE_CFG_VIFALW		0x5E8
-#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA	0x5F0
-#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB	0x5F8
-#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA	0x600
-#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB	0x608
-#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA	0x610
-#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB	0x618
-#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA	0x620
-#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB	0x628
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA	0x630
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB	0x638
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC	0x640
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA	0x648
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB	0x650
-#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC	0x658
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA	0x660
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB	0x668
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC	0x670
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA	0x678
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB	0x680
-#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC	0x688
-#define MC_STREAMID_OVERRIDE_CFG_RCER		0x690
-#define MC_STREAMID_OVERRIDE_CFG_RCEW		0x698
-#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR	0x6A0
-#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW	0x6A8
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD	0x6B0
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR	0x6B8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0R		0x6C0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0W		0x6C8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE1R		0x6D0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE1W		0x6D8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR	0x6E0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW	0x6E8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE3R		0x6F0
-#define MC_STREAMID_OVERRIDE_CFG_PCIE3W		0x6F8
-#define MC_STREAMID_OVERRIDE_CFG_PCIE4R		0x700
-#define MC_STREAMID_OVERRIDE_CFG_PCIE4W		0x708
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5R		0x710
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5W		0x718
-#define MC_STREAMID_OVERRIDE_CFG_ISPFALW	0x720
-#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1	0x748
-#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1	0x750
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1	0x758
-#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1	0x760
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1	0x768
-#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1	0x770
-#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1	0x778
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1	0x780
-#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1	0x788
-#define MC_STREAMID_OVERRIDE_CFG_ISPRA1		0x790
-#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1	0x798
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD	0x7C8
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1	0x7D0
-#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR	0x7D8
-
-/*******************************************************************************
- * Macro to calculate Security cfg register addr from StreamID Override register
- ******************************************************************************/
-#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
-
-/*******************************************************************************
- * Memory Controller transaction override config registers
- ******************************************************************************/
-#define MC_TXN_OVERRIDE_CONFIG_HDAR		0x10a8
-#define MC_TXN_OVERRIDE_CONFIG_BPMPW		0x14a0
-#define MC_TXN_OVERRIDE_CONFIG_PTCR		0x1000
-#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR	0x1490
-#define MC_TXN_OVERRIDE_CONFIG_EQOSW		0x1478
-#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR		0x13f8
-#define MC_TXN_OVERRIDE_CONFIG_ISPRA		0x1220
-#define MC_TXN_OVERRIDE_CONFIG_VICSRD		0x1360
-#define MC_TXN_OVERRIDE_CONFIG_MPCOREW		0x11c8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSRD		0x12c0
-#define MC_TXN_OVERRIDE_CONFIG_AXISR		0x1460
-#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW		0x14f0
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCW		0x1330
-#define MC_TXN_OVERRIDE_CONFIG_EQOSR		0x1470
-#define MC_TXN_OVERRIDE_CONFIG_APEDMAR		0x14f8
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD		0x10e0
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB		0x1318
-#define MC_TXN_OVERRIDE_CONFIG_VICSRD1		0x1510
-#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR		0x14a8
-#define MC_TXN_OVERRIDE_CONFIG_VIW		0x1390
-#define MC_TXN_OVERRIDE_CONFIG_AXISW		0x1468
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR	0x1260
-#define MC_TXN_OVERRIDE_CONFIG_UFSHCR		0x1480
-#define MC_TXN_OVERRIDE_CONFIG_TSECSWR		0x12a8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSWR		0x12c8
-#define MC_TXN_OVERRIDE_CONFIG_SATAR		0x10f8
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW	0x1258
-#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB		0x1438
-#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2		0x1440
-#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR		0x14e8
-#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2		0x1448
-#define MC_TXN_OVERRIDE_CONFIG_AONDMAW		0x14d0
-#define MC_TXN_OVERRIDE_CONFIG_APEDMAW		0x1500
-#define MC_TXN_OVERRIDE_CONFIG_AONW		0x14c0
-#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR	0x10b0
-#define MC_TXN_OVERRIDE_CONFIG_ETRR		0x1420
-#define MC_TXN_OVERRIDE_CONFIG_SESWR		0x1408
-#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD		0x13f0
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD		0x13c0
-#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB		0x1430
-#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW		0x14b0
-#define MC_TXN_OVERRIDE_CONFIG_APER		0x13d0
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1	0x1518
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR	0x1250
-#define MC_TXN_OVERRIDE_CONFIG_ISPWA		0x1230
-#define MC_TXN_OVERRIDE_CONFIG_SESRD		0x1400
-#define MC_TXN_OVERRIDE_CONFIG_SCER		0x14d8
-#define MC_TXN_OVERRIDE_CONFIG_AONR		0x14b8
-#define MC_TXN_OVERRIDE_CONFIG_MPCORER		0x1138
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA		0x1320
-#define MC_TXN_OVERRIDE_CONFIG_HDAW		0x11a8
-#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR		0x13c8
-#define MC_TXN_OVERRIDE_CONFIG_UFSHCW		0x1488
-#define MC_TXN_OVERRIDE_CONFIG_AONDMAR		0x14c8
-#define MC_TXN_OVERRIDE_CONFIG_SATAW		0x11e8
-#define MC_TXN_OVERRIDE_CONFIG_ETRW		0x1428
-#define MC_TXN_OVERRIDE_CONFIG_VICSWR		0x1368
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR		0x1158
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB		0x1338
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA		0x1300
-#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1	0x1508
-#define MC_TXN_OVERRIDE_CONFIG_ISPWB		0x1238
-#define MC_TXN_OVERRIDE_CONFIG_BPMPR		0x1498
-#define MC_TXN_OVERRIDE_CONFIG_APEW		0x13d8
-#define MC_TXN_OVERRIDE_CONFIG_SDMMCR		0x1310
-#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW	0x1268
-#define MC_TXN_OVERRIDE_CONFIG_TSECSRD		0x12a0
-#define MC_TXN_OVERRIDE_CONFIG_SCEW		0x14e0
-#define MC_TXN_OVERRIDE_CONFIG_MIU0R		0x1530
-#define MC_TXN_OVERRIDE_CONFIG_MIU0W		0x1538
-#define MC_TXN_OVERRIDE_CONFIG_MIU1R		0x1540
-#define MC_TXN_OVERRIDE_CONFIG_MIU1W		0x1548
-#define MC_TXN_OVERRIDE_CONFIG_MIU2R		0x1570
-#define MC_TXN_OVERRIDE_CONFIG_MIU2W		0x1578
-#define MC_TXN_OVERRIDE_CONFIG_MIU3R		0x1580
-#define MC_TXN_OVERRIDE_CONFIG_MIU3W		0x158C
-#define MC_TXN_OVERRIDE_CONFIG_VIFALR		0x15E4
-#define MC_TXN_OVERRIDE_CONFIG_VIFALW		0x15EC
-#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA		0x15F4
-#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB	0x15FC
-#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA		0x1604
-#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB	0x160C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA		0x1614
-#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB	0x161C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA		0x1624
-#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB	0x162C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA		0x1634
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB		0x163C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC		0x1644
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA		0x164C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB		0x1654
-#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC		0x165C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA		0x1664
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB		0x166C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC		0x1674
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA		0x167C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB		0x1684
-#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC		0x168C
-#define MC_TXN_OVERRIDE_CONFIG_RCER		0x1694
-#define MC_TXN_OVERRIDE_CONFIG_RCEW		0x169C
-#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR		0x16A4
-#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW		0x16AC
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD	0x16B4
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR	0x16BC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0R		0x16C4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0W		0x16CC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE1R		0x16D4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE1W		0x16DC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR		0x16E4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW		0x16EC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE3R		0x16F4
-#define MC_TXN_OVERRIDE_CONFIG_PCIE3W		0x16FC
-#define MC_TXN_OVERRIDE_CONFIG_PCIE4R		0x1704
-#define MC_TXN_OVERRIDE_CONFIG_PCIE4W		0x170C
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5R		0x1714
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5W		0x171C
-#define MC_TXN_OVERRIDE_CONFIG_ISPFALW		0x1724
-#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1		0x174C
-#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1		0x1754
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1		0x175C
-#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1		0x1764
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1		0x176C
-#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1		0x1774
-#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1		0x177C
-#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1	0x1784
-#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1	0x178C
-#define MC_TXN_OVERRIDE_CONFIG_ISPRA1		0x1794
-#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1		0x179C
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD	0x17CC
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1	0x17D4
-#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR	0x17DC
-
-/*******************************************************************************
- * Array to hold stream_id override config register offsets
- ******************************************************************************/
-const static uint32_t mc_streamid_override_regs[] = {
-	MC_STREAMID_OVERRIDE_CFG_HDAR,
-	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
-	MC_STREAMID_OVERRIDE_CFG_SATAR,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
-	MC_STREAMID_OVERRIDE_CFG_HDAW,
-	MC_STREAMID_OVERRIDE_CFG_SATAW,
-	MC_STREAMID_OVERRIDE_CFG_ISPRA,
-	MC_STREAMID_OVERRIDE_CFG_ISPFALR,
-	MC_STREAMID_OVERRIDE_CFG_ISPWA,
-	MC_STREAMID_OVERRIDE_CFG_ISPWB,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
-	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
-	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD,
-	MC_STREAMID_OVERRIDE_CFG_VICSWR,
-	MC_STREAMID_OVERRIDE_CFG_VIW,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
-	MC_STREAMID_OVERRIDE_CFG_APER,
-	MC_STREAMID_OVERRIDE_CFG_APEW,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
-	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
-	MC_STREAMID_OVERRIDE_CFG_SESRD,
-	MC_STREAMID_OVERRIDE_CFG_SESWR,
-	MC_STREAMID_OVERRIDE_CFG_AXIAPR,
-	MC_STREAMID_OVERRIDE_CFG_AXIAPW,
-	MC_STREAMID_OVERRIDE_CFG_ETRR,
-	MC_STREAMID_OVERRIDE_CFG_ETRW,
-	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
-	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
-	MC_STREAMID_OVERRIDE_CFG_AXISR,
-	MC_STREAMID_OVERRIDE_CFG_AXISW,
-	MC_STREAMID_OVERRIDE_CFG_EQOSR,
-	MC_STREAMID_OVERRIDE_CFG_EQOSW,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
-	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPW,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
-	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
-	MC_STREAMID_OVERRIDE_CFG_AONR,
-	MC_STREAMID_OVERRIDE_CFG_AONW,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
-	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
-	MC_STREAMID_OVERRIDE_CFG_SCER,
-	MC_STREAMID_OVERRIDE_CFG_SCEW,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
-	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
-	MC_STREAMID_OVERRIDE_CFG_VIFALR,
-	MC_STREAMID_OVERRIDE_CFG_VIFALW,
-	MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
-	MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
-	MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
-	MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
-	MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
-	MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
-	MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
-	MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
-	MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
-	MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
-	MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
-	MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
-	MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
-	MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
-	MC_STREAMID_OVERRIDE_CFG_RCER,
-	MC_STREAMID_OVERRIDE_CFG_RCEW,
-	MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
-	MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
-	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
-	MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
-	MC_STREAMID_OVERRIDE_CFG_PCIE0R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE0W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE1R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE1W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
-	MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
-	MC_STREAMID_OVERRIDE_CFG_PCIE3R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE3W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE4R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE4W,
-	MC_STREAMID_OVERRIDE_CFG_PCIE5R,
-	MC_STREAMID_OVERRIDE_CFG_PCIE5W,
-	MC_STREAMID_OVERRIDE_CFG_ISPFALW,
-	MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
-	MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
-	MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
-	MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
-	MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
-	MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
-	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
-	MC_STREAMID_OVERRIDE_CFG_ISPRA1,
-	MC_STREAMID_OVERRIDE_CFG_MIU0R,
-	MC_STREAMID_OVERRIDE_CFG_MIU0W,
-	MC_STREAMID_OVERRIDE_CFG_MIU1R,
-	MC_STREAMID_OVERRIDE_CFG_MIU1W,
-	MC_STREAMID_OVERRIDE_CFG_MIU2R,
-	MC_STREAMID_OVERRIDE_CFG_MIU2W,
-	MC_STREAMID_OVERRIDE_CFG_MIU3R,
-	MC_STREAMID_OVERRIDE_CFG_MIU3W
-};
-
-/*******************************************************************************
- * Array to hold the security configs for stream IDs
- ******************************************************************************/
-const static mc_streamid_security_cfg_t mc_streamid_sec_cfgs[] = {
-	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
-};
-
-/*******************************************************************************
- * Array to hold the transaction override configs
- ******************************************************************************/
-const static mc_txn_override_cfg_t mc_txn_override_cfgs[] = {
-	mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
-	mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
-};
-
-#endif //__MEMCTRL_PLAT_CONFIG_H
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/se.h b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
new file mode 100644
index 0000000..6e656f6
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/se.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SE_H__
+#define __SE_H__
+
+int32_t tegra_se_suspend(void);
+void tegra_se_resume(void);
+
+#endif /* __SE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index 1fe4620..cc0da80 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -19,257 +19,315 @@
  * occur when there is only new functionality.
  */
 enum {
-    TEGRA_NVG_VERSION_MAJOR = 6,
-    TEGRA_NVG_VERSION_MINOR = 0,
+	TEGRA_NVG_VERSION_MAJOR = 6,
+	TEGRA_NVG_VERSION_MINOR = 4
 };
 
 typedef enum {
-    TEGRA_NVG_CHANNEL_VERSION = 0,
-    TEGRA_NVG_CHANNEL_POWER_PERF = 1,
-    TEGRA_NVG_CHANNEL_POWER_MODES = 2,
-    TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
-    TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
-    TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
-    TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
-    // Value 7 reserved
-    TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
-    // Value 9 reserved
-    TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
-    TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
-    // Values 12-42 reserved
-    TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
-    TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
-    TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
-    TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
-    TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51,
-    // 52 FREQ FEEDBACK
-    TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
-    TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
-    TEGRA_NVG_CHANNEL_LAST_INDEX,
+	TEGRA_NVG_CHANNEL_VERSION			=  0,
+	TEGRA_NVG_CHANNEL_POWER_PERF			=  1,
+	TEGRA_NVG_CHANNEL_POWER_MODES			=  2,
+	TEGRA_NVG_CHANNEL_WAKE_TIME			=  3,
+	TEGRA_NVG_CHANNEL_CSTATE_INFO			=  4,
+	TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND	=  5,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND	=  6,
+	TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND	=  8,
+	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST	= 10,
+	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE	= 11,
+	TEGRA_NVG_CHANNEL_SHUTDOWN			= 42,
+	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED		= 43,
+	TEGRA_NVG_CHANNEL_ONLINE_CORE			= 44,
+	TEGRA_NVG_CHANNEL_CC3_CTRL			= 45,
+	TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL		= 49,
+	TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC		= 50,
+	TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL		= 53,
+	TEGRA_NVG_CHANNEL_SECURITY_CONFIG		= 54,
+	TEGRA_NVG_CHANNEL_DEBUG_CONFIG			= 55,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_MCF			= 56,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD1			= 57,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD2			= 58,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD3			= 59,
+	TEGRA_NVG_CHANNEL_DDA_MCF_ISO			= 60,
+	TEGRA_NVG_CHANNEL_DDA_MCF_SISO			= 61,
+	TEGRA_NVG_CHANNEL_DDA_MCF_NISO			= 62,
+	TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE		= 63,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO		= 64,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO		= 65,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO		= 66,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE	= 67,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL		= 68,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR		= 69,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA	= 70,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA	= 71,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL		= 72,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL			= 73,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D		= 74,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD		= 75,
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR		= 76,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL		= 77,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL	= 78,
+	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79,
+
+	TEGRA_NVG_CHANNEL_LAST_INDEX
 } tegra_nvg_channel_id_t;
 
-
 typedef enum {
-    // Value 0 reserved
-    NVG_STAT_QUERY_SC7_ENTRIES = 1,
-    // Values 2-5 reserved
-    NVG_STAT_QUERY_CC6_ENTRIES = 6,
-    NVG_STAT_QUERY_CG7_ENTRIES = 7,
-    // Values 8-9 reserved
-    NVG_STAT_QUERY_C6_ENTRIES = 10,
-    // Values 11-13 reserved
-    NVG_STAT_QUERY_C7_ENTRIES = 14,
-    // Values 15-31 reserved
-    NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
-    NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41,
-    NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46,
-    NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51,
-    NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56,
+	NVG_STAT_QUERY_SC7_ENTRIES		=  1,
+	NVG_STAT_QUERY_CC6_ENTRIES		=  6,
+	NVG_STAT_QUERY_CG7_ENTRIES		=  7,
+	NVG_STAT_QUERY_C6_ENTRIES		= 10,
+	NVG_STAT_QUERY_C7_ENTRIES		= 14,
+	NVG_STAT_QUERY_SC7_RESIDENCY_SUM	= 32,
+	NVG_STAT_QUERY_CC6_RESIDENCY_SUM	= 41,
+	NVG_STAT_QUERY_CG7_RESIDENCY_SUM	= 46,
+	NVG_STAT_QUERY_C6_RESIDENCY_SUM		= 51,
+	NVG_STAT_QUERY_C7_RESIDENCY_SUM		= 56,
+	NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM	= 60,
+	NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM	= 61,
+	NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM	= 62,
+	NVG_STAT_QUERY_C6_ENTRY_TIME_SUM	= 63,
+	NVG_STAT_QUERY_C7_ENTRY_TIME_SUM	= 64,
+	NVG_STAT_QUERY_SC7_EXIT_TIME_SUM	= 70,
+	NVG_STAT_QUERY_CC6_EXIT_TIME_SUM	= 71,
+	NVG_STAT_QUERY_CG7_EXIT_TIME_SUM	= 72,
+	NVG_STAT_QUERY_C6_EXIT_TIME_SUM		= 73,
+	NVG_STAT_QUERY_C7_EXIT_TIME_SUM		= 74,
+	NVG_STAT_QUERY_SC7_ENTRY_LAST		= 80,
+	NVG_STAT_QUERY_CC6_ENTRY_LAST		= 81,
+	NVG_STAT_QUERY_CG7_ENTRY_LAST		= 82,
+	NVG_STAT_QUERY_C6_ENTRY_LAST		= 83,
+	NVG_STAT_QUERY_C7_ENTRY_LAST		= 84,
+	NVG_STAT_QUERY_SC7_EXIT_LAST		= 90,
+	NVG_STAT_QUERY_CC6_EXIT_LAST		= 91,
+	NVG_STAT_QUERY_CG7_EXIT_LAST		= 92,
+	NVG_STAT_QUERY_C6_EXIT_LAST		= 93,
+	NVG_STAT_QUERY_C7_EXIT_LAST		= 94
 } tegra_nvg_stat_query_t;
 
-
 typedef enum {
-    TEGRA_NVG_CORE_C0 = 0,
-    TEGRA_NVG_CORE_C1 = 1,
-    TEGRA_NVG_CORE_C6 = 6,
-    TEGRA_NVG_CORE_C7 = 7,
-    TEGRA_NVG_CORE_WARMRSTREQ = 8,
+	TEGRA_NVG_CORE_C0 = 0,
+	TEGRA_NVG_CORE_C1 = 1,
+	TEGRA_NVG_CORE_C6 = 6,
+	TEGRA_NVG_CORE_C7 = 7,
+	TEGRA_NVG_CORE_WARMRSTREQ = 8
 } tegra_nvg_core_sleep_state_t;
 
 typedef enum {
-    TEGRA_NVG_CLUSTER_CC0 = 0,
-    TEGRA_NVG_CLUSTER_CC6 = 6,
+	TEGRA_NVG_CLUSTER_CC0 = 0,
+	TEGRA_NVG_CLUSTER_CC6 = 6
 } tegra_nvg_cluster_sleep_state_t;
 
 typedef enum {
-    TEGRA_NVG_CCPLEX_CG0 = 0,
-    TEGRA_NVG_CCPLEX_CG7 = 1,
-
+	TEGRA_NVG_CG_CG0 = 0,
+	TEGRA_NVG_CG_CG7 = 7
 } tegra_nvg_cluster_group_sleep_state_t;
 
 typedef enum {
-    TEGRA_NVG_SYSTEM_SC0 = 0,
-    TEGRA_NVG_SYSTEM_SC7 = 7,
-    TEGRA_NVG_SYSTEM_SC8 = 8,
+	TEGRA_NVG_SYSTEM_SC0 = 0,
+	TEGRA_NVG_SYSTEM_SC7 = 7,
+	TEGRA_NVG_SYSTEM_SC8 = 8
 } tegra_nvg_system_sleep_state_t;
 
 // ---------------------------------------------------------------------------
 // NVG Data subformats
 // ---------------------------------------------------------------------------
 
-typedef union
-{
-    uint64_t flat;
-    struct nvg_version_channel_t {
-        uint64_t minor_version : 32;
-        uint64_t major_version : 32;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_version_channel_t {
+		uint32_t minor_version	: 32;
+		uint32_t major_version	: 32;
+	} bits;
 } nvg_version_data_t;
 
-typedef union nvg_channel_1_data_u
-{
-    uint64_t flat;
-    struct nvg_channel_1_data_s
-    {
-        uint64_t perf_per_watt_mode : 1;
-        uint64_t reserved_63_1 : 63;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_power_perf_channel_t {
+		uint32_t perf_per_watt	: 1;
+		uint32_t reserved_31_1	: 31;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_power_perf_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_power_modes_channel_t {
+		uint32_t low_battery	: 1;
+		uint32_t reserved_1_1	: 1;
+		uint32_t battery_save	: 1;
+		uint32_t reserved_31_3	: 29;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_power_modes_channel_t;
+
+typedef union nvg_channel_1_data_u {
+	uint64_t flat;
+	struct nvg_channel_1_data_s {
+		uint32_t perf_per_watt_mode	: 1;
+		uint32_t reserved_31_1		: 31;
+		uint32_t reserved_63_32		: 32;
+	} bits;
 } nvg_channel_1_data_t;
 
-typedef union nvg_channel_2_data_u
-{
-    uint64_t flat;
-    struct nvg_channel_2_data_s
-    {
-        uint64_t reserved_1_0 : 2;
-        uint64_t battery_saver_mode : 1;
-        uint64_t reserved_63_3 : 61;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_ccplex_cache_control_channel_t {
+		uint32_t gpu_ways	: 5;
+		uint32_t reserved_7_5	: 3;
+		uint32_t gpu_only_ways	: 5;
+		uint32_t reserved_31_13	: 19;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_ccplex_cache_control_channel_t;
+
+typedef union nvg_channel_2_data_u {
+	uint64_t flat;
+	struct nvg_channel_2_data_s {
+		uint32_t reserved_1_0		: 2;
+		uint32_t battery_saver_mode	: 1;
+		uint32_t reserved_31_3		: 29;
+		uint32_t reserved_63_32		: 32;
+	} bits;
 } nvg_channel_2_data_t;
 
-typedef union
-{
-    uint64_t flat;
-    struct nvg_wake_time_channel_t {
-        uint64_t wake_time : 32;
-        uint64_t reserved_63_32 : 32;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_wake_time_channel_t {
+		uint32_t wake_time	: 32;
+		uint32_t reserved_63_32	: 32;
+	} bits;
 } nvg_wake_time_channel_t;
 
-typedef union
-{
-    uint64_t flat;
-    struct nvg_cstate_info_channel_t {
-        uint64_t cluster_state : 3;
-        uint64_t reserved_6_3 : 4;
-        uint64_t update_cluster : 1;
-        uint64_t cg_cstate : 3;
-        uint64_t reserved_14_11 : 4;
-        uint64_t update_cg : 1;
-        uint64_t system_cstate : 4;
-        uint64_t reserved_22_20 : 3;
-        uint64_t update_system : 1;
-        uint64_t reserved_30_24 : 7;
-        uint64_t update_wake_mask : 1;
-        uint64_t wake_mask : 32;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_cstate_info_channel_t {
+		uint32_t cluster_state	: 3;
+		uint32_t reserved_6_3	: 4;
+		uint32_t update_cluster	: 1;
+		uint32_t cg_cstate	: 3;
+		uint32_t reserved_14_11	: 4;
+		uint32_t update_cg	: 1;
+		uint32_t system_cstate	: 4;
+		uint32_t reserved_22_20	: 3;
+		uint32_t update_system	: 1;
+		uint32_t reserved_30_24	: 7;
+		uint32_t update_wake_mask : 1;
+		uint32_t wake_mask	: 32;
+	} bits;
 } nvg_cstate_info_channel_t;
 
-typedef union
-{
-    uint64_t flat;
-    struct nvg_lower_bound_channel_t {
-        uint64_t crossover_value : 32;
-        uint64_t reserved_63_32 : 32;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_lower_bound_channel_t {
+		uint32_t crossover_value : 32;
+		uint32_t reserved_63_32	: 32;
+	} bits;
 } nvg_lower_bound_channel_t;
 
-
-typedef union
-{
-    uint64_t flat;
-    struct nvg_cstate_stat_query_channel_t {
-        uint64_t unit_id : 4;
-        uint64_t reserved_15_4 : 12;
-        uint64_t stat_id : 16;
-        uint64_t reserved_63_32 : 32;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_cstate_stat_query_channel_t {
+		uint32_t unit_id	: 4;
+		uint32_t reserved_15_4	: 12;
+		uint32_t stat_id	: 16;
+		uint32_t reserved_63_32	: 32;
+	} bits;
 } nvg_cstate_stat_query_channel_t;
 
-typedef union
-{
-    uint64_t flat;
-    struct nvg_is_sc7_allowed_channel_t {
-        uint64_t is_sc7_allowed : 1;
-        uint64_t reserved_63_32 : 63;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_is_sc7_allowed_channel_t {
+		uint32_t is_sc7_allowed	: 1;
+		uint32_t reserved_31_1	: 31;
+		uint32_t reserved_63_32	: 32;
+	} bits;
 } nvg_is_sc7_allowed_channel_t;
 
-
-typedef union
-{
-    uint64_t flat;
-    struct nvg_core_online_channel_t {
-        uint64_t core_id : 4;
-        uint64_t reserved_63_4 : 60;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_core_online_channel_t {
+		uint32_t core_id	: 4;
+		uint32_t reserved_31_4	: 28;
+		uint32_t reserved_63_32	: 32;
+	} bits;
 } nvg_core_online_channel_t;
 
-
-typedef union
-{
-    uint64_t flat;
-    struct nvg_cc3_control_channel_t {
-        uint64_t freq_req : 8;
-        uint64_t reserved_30_8 : 23;
-        uint64_t enable : 1;
-        uint64_t reserved_63_32 : 32;
-    } bits;
+typedef union {
+	uint64_t flat;
+	struct nvg_cc3_control_channel_t {
+		uint32_t freq_req	: 8;
+		uint32_t reserved_30_8	: 23;
+		uint32_t enable		: 1;
+		uint32_t reserved_63_32	: 32;
+	} bits;
 } nvg_cc3_control_channel_t;
 
-
-typedef union
-{
-    uint64_t flat;
-    struct nvg_update_gsc_channel_t {
-        uint64_t gsc_enum : 16;
-        uint64_t reserved_63_16 : 48;
-    } bits;
-} nvg_update_gsc_channel_t;
-
-
-typedef union
-{
-    uint64_t flat;
-    struct nvg_cache_inval_channel_t {
-        uint64_t cache_clean : 1;
-        uint64_t cache_clean_inval : 1;
-        uint64_t cache_clean_inval_tr : 1;
-        uint64_t reserved_63_3 : 61;
-    } bits;
-} nvg_cache_inval_channel_t;
-
-
-/* GSC type define */
 typedef enum {
-    TEGRA_NVG_GSC_ALL=0,
-    TEGRA_NVG_GSC_NVDEC=1,
-    TEGRA_NVG_GSC_WPR1=2,
-    TEGRA_NVG_GSC_WPR2=3,
-    TEGRA_NVG_GSC_TSECA=4,
-    TEGRA_NVG_GSC_TSECB=5,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL		=  0,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC		=  1,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1		=  2,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2		=  3,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA		=  4,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB		=  5,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP		=  6,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_APE		=  7,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE		=  8,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE		=  9,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_APR		=  10,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM		=  11,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC	=  12,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE	=  13,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE	=  14,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7		=  15,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE	=  16,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE		=  17,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP	=  18,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1		=  19,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP	=  20,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7		=  21,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW	=  23,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST	=  24,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB		=  25,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CV			=  26,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2		=  27,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW	=  28,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES	=  29,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_30			=  30,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_31			=  31,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM		=  32,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK		=  33,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS		=  34,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR		=  35,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
+} tegra_nvg_channel_update_gsc_gsc_enum_t;
 
-    TEGRA_NVG_GSC_BPMP=6,
-    TEGRA_NVG_GSC_APE=7,
-    TEGRA_NVG_GSC_SPE=8,
-    TEGRA_NVG_GSC_SCE=9,
-    TEGRA_NVG_GSC_APR=10,
-    TEGRA_NVG_GSC_TZRAM=11,
-    TEGRA_NVG_GSC_SE=12,
+typedef union {
+	uint64_t flat;
+	struct nvg_update_ccplex_gsc_channel_t {
+		uint32_t gsc_enum	: 16;
+		uint32_t reserved_31_16	: 16;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_update_ccplex_gsc_channel_t;
 
-    TEGRA_NVG_GSC_DMCE=13,
-    TEGRA_NVG_GSC_BPMP_TO_DMCE=14,
-    TEGRA_NVG_GSC_BPMP_TO_SPE=16,
-    TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18,
-    TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20,
-    TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22,
-    TEGRA_NVG_GSC_SC7_RESUME_FW=23,
+typedef union {
+	uint64_t flat;
+	struct nvg_security_config_channel_t {
+		uint32_t strict_checking_enabled : 1;
+		uint32_t strict_checking_locked	: 1;
+		uint32_t reserved_31_2		: 30;
+		uint32_t reserved_63_32		: 32;
+	} bits;
+} nvg_security_config_t;
 
-    TEGRA_NVG_GSC_VPR_RESIZE=24,
-    TEGRA_NVG_GSC_RCE=25,
-    TEGRA_NVG_GSC_CV=26,
+typedef union {
+	uint64_t flat;
+	struct nvg_shutdown_channel_t {
+		uint32_t reboot		: 1;
+		uint32_t reserved_31_1	: 31;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_shutdown_t;
 
-    TEGRA_NVG_GSC_BO_MTS_PACKAGE=28,
-    TEGRA_NVG_GSC_BO_MCE_PREBOOT=29,
-
-    TEGRA_NVG_GSC_TZ_DRAM_IDX=34,
-    TEGRA_NVG_GSC_VPR_IDX=35,
-} tegra_nvg_gsc_index_t;
-
-typedef enum {
-    TEGRA_NVG_CROSSOVER_C6 = 0,
-    TEGRA_NVG_CROSSOVER_CC6 = 1,
-    TEGRA_NVG_CROSSOVER_CG7 = 2,
-} tegra_nvg_crossover_index_t;
-
-#endif // T194_NVG_H
+#endif
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
index e6a6a99..3c47208 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
@@ -10,6 +10,9 @@
 	.globl	nvg_set_request_data
 	.globl	nvg_set_request
 	.globl	nvg_get_result
+	.globl	nvg_cache_clean
+	.globl	nvg_cache_clean_inval
+	.globl	nvg_cache_inval_all
 
 /* void nvg_set_request_data(uint64_t req, uint64_t data) */
 func nvg_set_request_data
@@ -29,3 +32,21 @@
 	mrs	x0, s3_0_c15_c1_3
 	ret
 endfunc nvg_get_result
+
+/* uint64_t nvg_cache_clean(void) */
+func nvg_cache_clean
+	mrs	x0, s3_0_c15_c3_5
+	ret
+endfunc nvg_cache_clean
+
+/* uint64_t nvg_cache_clean_inval(void) */
+func nvg_cache_clean_inval
+	mrs	x0, s3_0_c15_c3_6
+	ret
+endfunc nvg_cache_clean_inval
+
+/* uint64_t nvg_cache_inval_all(void) */
+func nvg_cache_inval_all
+	mrs	x0, s3_0_c15_c3_7
+	ret
+endfunc nvg_cache_inval_all
\ No newline at end of file
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 0a6515e..ba8436b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -14,13 +14,26 @@
 #include <denver.h>
 #include <mce.h>
 #include <mce_private.h>
-#include <mmio.h>
 #include <platform_def.h>
+#include <stdbool.h>
 #include <string.h>
 #include <errno.h>
 #include <t194_nvg.h>
 #include <tegra_def.h>
 #include <tegra_platform.h>
+#include <tegra_private.h>
+
+/* Handler to check if MCE firmware is supported */
+static bool mce_firmware_not_supported(void)
+{
+	bool status;
+
+	/* these platforms do not load MCE firmware */
+	status = tegra_platform_is_linsim() || tegra_platform_is_qt() ||
+		 tegra_platform_is_virt_dev_kit();
+
+	return status;
+}
 
 /*******************************************************************************
  * Common handler for all MCE commands
@@ -28,16 +41,10 @@
 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
 			uint64_t arg2)
 {
-	uint64_t ret64 = 0, arg3, arg4, arg5;
 	int32_t ret = 0;
-	cpu_context_t *ctx = cm_get_context(NON_SECURE);
-	gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
-
-	assert(ctx);
-	assert(gp_regs);
 
 	switch (cmd) {
-	case MCE_CMD_ENTER_CSTATE:
+	case (uint64_t)MCE_CMD_ENTER_CSTATE:
 		ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1);
 		if (ret < 0) {
 			ERROR("%s: enter_cstate failed(%d)\n", __func__, ret);
@@ -45,68 +52,15 @@
 
 		break;
 
-	case MCE_CMD_UPDATE_CSTATE_INFO:
-		/*
-		 * get the parameters required for the update cstate info
-		 * command
-		 */
-		arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4));
-		arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5));
-		arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6));
-
-		/* arg0 cluster
-		 * arg1 ccplex
-		 * arg2 system
-		 * arg3 sys_state_force => T19x not support
-		 * arg4 wake_mask
-		 * arg5 update_wake_mask
-		 */
-		nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1,
-				(uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5);
-
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3));
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4));
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5));
-
-		break;
-
-	case MCE_CMD_UPDATE_CROSSOVER_TIME:
-		ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1);
-		if (ret < 0) {
-			ERROR("%s: update_crossover_time failed(%d)\n",
-				__func__, ret);
-		}
-
-		break;
-
-	case MCE_CMD_READ_CSTATE_STATS:
-		ret64 = nvg_get_cstate_stat_query_value();
-
-		/* update context to return cstate stats value */
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64));
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64));
-
-		break;
-
-	case MCE_CMD_WRITE_CSTATE_STATS:
-		ret = nvg_set_cstate_stat_query_value(arg0);
-
-		break;
-
-	case MCE_CMD_IS_SC7_ALLOWED:
+	case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
 		ret = nvg_is_sc7_allowed();
 		if (ret < 0) {
 			ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret);
-			break;
 		}
 
-		/* update context to return SC7 status value */
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret));
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret));
-
 		break;
 
-	case MCE_CMD_ONLINE_CORE:
+	case (uint64_t)MCE_CMD_ONLINE_CORE:
 		ret = nvg_online_core((uint32_t)arg0);
 		if (ret < 0) {
 			ERROR("%s: online_core failed(%d)\n", __func__, ret);
@@ -114,55 +68,9 @@
 
 		break;
 
-	case MCE_CMD_CC3_CTRL:
-		ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2);
-		if (ret < 0) {
-			ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret);
-		}
-
-		break;
-
-	case MCE_CMD_READ_VERSIONS:
-		/* get the MCE firmware version */
-		ret64 = nvg_get_version();
-
-		/*
-		 * version = minor(63:32) | major(31:0). Update context
-		 * to return major and minor version number.
-		 */
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF));
-		write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32));
-
-		break;
-
-	case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
-		ret = nvg_roc_clean_cache_trbits();
-		if (ret < 0) {
-			ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
-				ret);
-		}
-
-		break;
-
-	case MCE_CMD_ROC_FLUSH_CACHE:
-		ret = nvg_roc_flush_cache();
-		if (ret < 0) {
-			ERROR("%s: flush cache failed(%d)\n", __func__, ret);
-		}
-
-		break;
-
-	case MCE_CMD_ROC_CLEAN_CACHE:
-		ret = nvg_roc_clean_cache();
-		if (ret < 0) {
-			ERROR("%s: clean cache failed(%d)\n", __func__, ret);
-		}
-
-		break;
-
 	default:
 		ERROR("unknown MCE command (%llu)\n", cmd);
-		ret = EINVAL;
+		ret = -EINVAL;
 		break;
 	}
 
@@ -174,7 +82,18 @@
  ******************************************************************************/
 int32_t mce_update_gsc_videomem(void)
 {
-	return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX);
+	int32_t ret;
+
+	/*
+	 * MCE firmware is not running on simulation platforms.
+	 */
+	if (mce_firmware_not_supported()) {
+		ret = -EINVAL;
+	} else {
+		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR);
+	}
+
+	return ret;
 }
 
 /*******************************************************************************
@@ -182,7 +101,18 @@
  ******************************************************************************/
 int32_t mce_update_gsc_tzdram(void)
 {
-	return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX);
+	int32_t ret;
+
+	/*
+	 * MCE firmware is not running on simulation platforms.
+	 */
+	if (mce_firmware_not_supported()) {
+		ret = -EINVAL;
+	} else {
+		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM);
+	}
+
+	return ret;
 }
 
 /*******************************************************************************
@@ -190,7 +120,18 @@
  ******************************************************************************/
 int32_t mce_update_gsc_tzram(void)
 {
-	return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM);
+	int32_t ret;
+
+	/*
+	 * MCE firmware is not running on simulation platforms.
+	 */
+	if (mce_firmware_not_supported()) {
+		ret = -EINVAL;
+	} else {
+		ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
+	}
+
+	return ret;
 }
 
 /*******************************************************************************
@@ -215,9 +156,7 @@
 	/*
 	 * MCE firmware is not running on simulation platforms.
 	 */
-	if ((tegra_platform_is_linsim() == 1U) ||
-		(tegra_platform_is_virt_dev_kit() == 1U) ||
-		(tegra_platform_is_qt() == 1U)) {
+	if (mce_firmware_not_supported()) {
 		return;
 	}
 
@@ -229,8 +168,8 @@
 	minor = (uint32_t)version;
 	major = (uint32_t)(version >> 32);
 
-	INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
-		0, 0);
+	INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor,
+		TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR);
 
 	/*
 	 * Verify that the MCE firmware version and the interface header
@@ -246,3 +185,53 @@
 		panic();
 	}
 }
+
+/*******************************************************************************
+ * Handler to enable the strict checking mode
+ ******************************************************************************/
+void mce_enable_strict_checking(void)
+{
+	uint64_t sctlr = read_sctlr_el3();
+	int32_t ret = 0;
+
+	if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+		/*
+		 * Step1: TZ-DRAM and TZRAM should be setup before the MMU is
+		 * enabled.
+		 *
+		 * The common code makes sure that TZDRAM/TZRAM are already
+		 * enabled before calling into this handler. If this is not the
+		 * case, the following sequence must be executed before moving
+		 * on to step 2.
+		 *
+		 * tlbialle1is();
+		 * tlbialle3is();
+		 * dsbsy();
+		 * isb();
+		 *
+		 */
+		if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) {
+			tlbialle1is();
+			tlbialle3is();
+			dsbsy();
+			isb();
+		}
+
+		/*
+		 * Step2: SCF flush - Clean and invalidate caches and clear the
+		 * TR-bits
+		 */
+		ret = nvg_roc_clean_cache_trbits();
+		if (ret < 0) {
+			ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
+				ret);
+			return;
+		}
+
+		/*
+		 * Step3: Issue the SECURITY_CONFIG request to MCE to enable
+		 * strict checking mode.
+		 */
+		nvg_enable_strict_checking_mode();
+	}
+}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 12dd6cb..1dd1f51 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -13,11 +13,10 @@
 #include <mce_private.h>
 #include <platform_def.h>
 #include <t194_nvg.h>
+#include <tegra_private.h>
 
-extern void nvg_set_request_data(uint64_t req, uint64_t data);
-extern void nvg_set_request(uint64_t req);
-extern uint64_t nvg_get_result(void);
-
+#define	ID_AFR0_EL1_CACHE_OPS_SHIFT	12
+#define	ID_AFR0_EL1_CACHE_OPS_MASK	0xFU
 /*
  * Reports the major and minor version of this interface.
  *
@@ -26,7 +25,7 @@
  */
 uint64_t nvg_get_version(void)
 {
-	nvg_set_request(TEGRA_NVG_CHANNEL_VERSION);
+	nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION);
 
 	return (uint64_t)nvg_get_result();
 }
@@ -38,7 +37,7 @@
  */
 int32_t nvg_enable_power_perf_mode(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
 
 	return 0;
 }
@@ -50,7 +49,7 @@
  */
 int32_t nvg_disable_power_perf_mode(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
 
 	return 0;
 }
@@ -62,7 +61,7 @@
  */
 int32_t nvg_enable_power_saver_modes(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
 
 	return 0;
 }
@@ -74,7 +73,7 @@
  */
 int32_t nvg_disable_power_saver_modes(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
 
 	return 0;
 }
@@ -88,7 +87,7 @@
 void nvg_set_wake_time(uint32_t wake_time)
 {
 	/* time (TSC ticks) until the core is expected to get a wake event */
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
 }
 
 /*
@@ -97,7 +96,7 @@
  *
  * NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE
  * NVGDATA[7]: SW(W), update cluster flag
- * NVGDATA[8:9]: SW(RW), CG_CSTATE
+ * NVGDATA[8:10]: SW(RW), CG_CSTATE
  * NVGDATA[15]: SW(W), update ccplex flag
  * NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE
  * NVGDATA[23]: SW(W), update system flag
@@ -136,77 +135,7 @@
 	val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT;
 
 	/* set the updated cstate info */
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
-}
-
-/*
- * Indices gives MTS the crossover point in TSC ticks for when it becomes
- * no longer viable to enter the named state
- *
- * Type 0 : NVGDATA[0:31]: C6 Lower bound
- * Type 1 : NVGDATA[0:31]: CC6 Lower bound
- * Type 2 : NVGDATA[0:31]: CG7 Lower bound
- */
-int32_t nvg_update_crossover_time(uint32_t type, uint32_t time)
-{
-	int32_t ret = 0;
-
-	switch (type) {
-	case TEGRA_NVG_CROSSOVER_C6:
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND,
-			(uint64_t)time);
-		break;
-
-	case TEGRA_NVG_CROSSOVER_CC6:
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND,
-			(uint64_t)time);
-		break;
-
-	case TEGRA_NVG_CROSSOVER_CG7:
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND,
-			(uint64_t)time);
-		break;
-
-	default:
-		ERROR("%s: unknown crossover type (%d)\n", __func__, type);
-		ret = EINVAL;
-		break;
-	}
-
-	return ret;
-}
-
-/*
- * These NVG calls allow ARM SW to access CSTATE statistical information
- *
- * NVGDATA[0:3]: SW(RW) Core/cluster/cg id
- * NVGDATA[16:31]: SW(RW) Stat id
- */
-int32_t nvg_set_cstate_stat_query_value(uint64_t data)
-{
-	int32_t ret = 0;
-
-	/* sanity check stat id */
-	if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) {
-		ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data);
-		ret = EINVAL;
-	} else {
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data);
-	}
-
-	return ret;
-}
-
-/*
- * The read-only value associated with the CSTATE_STAT_QUERY_REQUEST
- *
- * NVGDATA[0:63]: SW(R) Stat count
- */
-uint64_t nvg_get_cstate_stat_query_value(void)
-{
-	nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE);
-
-	return (uint64_t)nvg_get_result();
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
 }
 
 /*
@@ -217,7 +146,7 @@
 int32_t nvg_is_sc7_allowed(void)
 {
 	/* issue command to check if SC7 is allowed */
-	nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
+	nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
 
 	/* 1 = SC7 allowed, 0 = SC7 not allowed */
 	return (int32_t)nvg_get_result();
@@ -239,43 +168,14 @@
 		ret = EINVAL;
 	} else {
 		/* get a core online */
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE,
-								(uint64_t)core & MCE_CORE_ID_MASK);
+		nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
+					(uint64_t)core & MCE_CORE_ID_MASK);
 	}
 
 	return ret;
 }
 
 /*
- * Enables and controls the voltage/frequency hint for CC3. CC3 is disabled
- * by default.
- *
- * NVGDATA[7:0] SW(RW) frequency request
- * NVGDATA[31:31] SW(RW) enable bit
- */
-int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable)
-{
-	uint64_t val = 0;
-
-	/*
-	 * If the enable bit is cleared, Auto-CC3 will be disabled by setting
-	 * the SW visible frequency request registers for all non
-	 * floorswept cores valid independent of StandbyWFI and disabling
-	 * the IDLE frequency request register. If set, Auto-CC3
-	 * will be enabled by setting the ARM SW visible frequency
-	 * request registers for all non floorswept cores to be enabled by
-	 * StandbyWFI or the equivalent signal, and always keeping the IDLE
-	 * frequency request register enabled.
-	 */
-	if (enable != 0U) {
-		val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT;
-	}
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val);
-
-	return 0;
-}
-
-/*
  * MC GSC (General Security Carveout) register values are expected to be
  * changed by TrustZone ARM code after boot.
  *
@@ -283,14 +183,14 @@
  */
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
 {
-	int32_t ret = 0;
+	int32_t ret;
 
 	/* sanity check GSC ID */
-	if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) {
-		ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx);
+	if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
+		ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
 		ret = EINVAL;
 	} else {
-		nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
+		nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
 								(uint64_t)gsc_idx);
 	}
 
@@ -299,41 +199,62 @@
 
 /*
  * Cache clean operation for all CCPLEX caches.
- *
- * NVGDATA[0] cache_clean
  */
 int32_t nvg_roc_clean_cache(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
-							(uint64_t)CACHE_CLEAN_SET);
+	int32_t ret = 0;
 
-	return 0;
+	/* check if cache flush through mts is supported */
+	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+		if (nvg_cache_clean() == 0U) {
+			ERROR("%s: failed\n", __func__);
+			ret = EINVAL;
+		}
+	} else {
+		ret = EINVAL;
+	}
+	return ret;
 }
 
 /*
  * Cache clean and invalidate operation for all CCPLEX caches.
- *
- * NVGDATA[1] cache_clean_inval
  */
 int32_t nvg_roc_flush_cache(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
-							(uint64_t)CACHE_CLEAN_INVAL_SET);
+	int32_t ret = 0;
 
-	return 0;
+	/* check if cache flush through mts is supported */
+	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+		if (nvg_cache_clean_inval() == 0U) {
+			ERROR("%s: failed\n", __func__);
+			ret = EINVAL;
+		}
+	} else {
+		ret = EINVAL;
+	}
+	return ret;
 }
 
 /*
  * Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
- *
- * NVGDATA[2] cache_clean_inval_tr
  */
 int32_t nvg_roc_clean_cache_trbits(void)
 {
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
-							(uint64_t)CACHE_CLEAN_INVAL_TR_SET);
+	int32_t ret = 0;
 
-	return 0;
+	/* check if cache flush through mts is supported */
+	if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
+			ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
+		if (nvg_cache_inval_all() == 0U) {
+			ERROR("%s: failed\n", __func__);
+			ret = EINVAL;
+		}
+	} else {
+		ret = EINVAL;
+	}
+	return ret;
 }
 
 /*
@@ -342,6 +263,7 @@
 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
 {
 	int32_t ret = 0;
+	uint64_t val = 0ULL;
 
 	/* check for allowed power state */
 	if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
@@ -356,8 +278,22 @@
 		nvg_set_wake_time(wake_time);
 
 		/* set the core cstate */
-		write_actlr_el1(state);
+		val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
+		write_actlr_el1(val | (uint64_t)state);
 	}
 
 	return ret;
 }
+
+/*
+ * Enable strict checking mode
+ *
+ * NVGDATA[3] strict_check ON + lock
+ */
+void nvg_enable_strict_checking_mode(void)
+{
+	uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
+				     STRICT_CHECKING_LOCKED_SET);
+
+	nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
+}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
new file mode 100644
index 0000000..3df670c
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -0,0 +1,213 @@
+﻿/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <tegra_platform.h>
+
+#include "se_private.h"
+
+/*******************************************************************************
+ * Constants and Macros
+ ******************************************************************************/
+#define ERR_STATUS_SW_CLEAR	U(0xFFFFFFFF)
+#define INT_STATUS_SW_CLEAR	U(0xFFFFFFFF)
+#define MAX_TIMEOUT_MS		U(100)	/* Timeout in 100ms */
+#define NUM_SE_REGS_TO_SAVE	U(4)
+
+/*******************************************************************************
+ * Data structure and global variables
+ ******************************************************************************/
+static uint32_t se_regs[NUM_SE_REGS_TO_SAVE];
+
+/*
+ * Check that SE operation has completed after kickoff.
+ *
+ * This function is invoked after an SE operation has been started,
+ * and it checks the following conditions:
+ *
+ * 1. SE_STATUS = IDLE
+ * 2. AHB bus data transfer is complete.
+ * 3. SE_ERR_STATUS is clean.
+ */
+static bool tegra_se_is_operation_complete(void)
+{
+	uint32_t val = 0, timeout = 0, sha_status, aes_status;
+	int32_t ret = 0;
+	bool se_is_busy, txn_has_errors, txn_successful;
+
+	/*
+	 * Poll the status register to check if the operation
+	 * completed.
+	 */
+	do {
+		val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
+		se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY);
+
+		/* sleep until SE finishes */
+		if (se_is_busy) {
+			mdelay(1);
+			timeout++;
+		}
+
+	} while (se_is_busy && (timeout < MAX_TIMEOUT_MS));
+
+	/* any transaction errors? */
+	txn_has_errors = (tegra_se_read_32(SHA_ERR_STATUS) != 0U) ||
+			 (tegra_se_read_32(AES0_ERR_STATUS) != 0U);
+
+	/* transaction successful? */
+	sha_status = tegra_se_read_32(SHA_INT_STATUS) & SHA_SE_OP_DONE;
+	aes_status = tegra_se_read_32(AES0_INT_STATUS) & AES0_SE_OP_DONE;
+	txn_successful = (sha_status == SHA_SE_OP_DONE) &&
+			 (aes_status == AES0_SE_OP_DONE);
+
+	if ((timeout == MAX_TIMEOUT_MS) || txn_has_errors || !txn_successful) {
+		ERROR("%s: Atomic context save operation failed!\n",
+				__func__);
+		ret = -ECANCELED;
+	}
+
+	return (ret == 0);
+}
+
+/*
+ * Wait for SE engine to be idle and clear any pending interrupts, before
+ * starting the next SE operation.
+ */
+static bool tegra_se_is_ready(void)
+{
+	int32_t ret = 0;
+	uint32_t val = 0, timeout = 0;
+	bool se_is_ready;
+
+	/* Wait for previous operation to finish */
+	do {
+		val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
+		se_is_ready = (val == CTX_SAVE_AUTO_SE_READY);
+
+		/* sleep until SE is ready */
+		if (!se_is_ready) {
+			mdelay(1);
+			timeout++;
+		}
+
+	} while (!se_is_ready && (timeout < MAX_TIMEOUT_MS));
+
+	if (timeout == MAX_TIMEOUT_MS) {
+		ERROR("%s: SE is not ready!\n", __func__);
+		ret = -ETIMEDOUT;
+	}
+
+	/* Clear any pending interrupts from previous operation */
+	tegra_se_write_32(AES0_INT_STATUS, INT_STATUS_SW_CLEAR);
+	tegra_se_write_32(AES1_INT_STATUS, INT_STATUS_SW_CLEAR);
+	tegra_se_write_32(RSA_INT_STATUS, INT_STATUS_SW_CLEAR);
+	tegra_se_write_32(SHA_INT_STATUS, INT_STATUS_SW_CLEAR);
+
+	/* Clear error status for each engine seen from current port */
+	tegra_se_write_32(AES0_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+	tegra_se_write_32(AES1_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+	tegra_se_write_32(RSA_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+	tegra_se_write_32(SHA_ERR_STATUS, ERR_STATUS_SW_CLEAR);
+
+	return (ret == 0);
+}
+
+/*
+ * During System Suspend, this handler triggers the hardware context
+ * save operation.
+ */
+static int32_t tegra_se_save_context(void)
+{
+	int32_t ret = -ECANCELED;
+
+	/*
+	 * 1. Ensure all SE Driver including RNG1/PKA1 are shut down.
+	 *    TSEC/R5s are powergated/idle. All tasks on SE1~SE4, RNG1,
+	 *    PKA1 are wrapped up. SE0 is ready for use.
+	 * 2. Clear interrupt/error in SE0 status register.
+	 * 3. Scrub SE0 register to avoid false failure for illegal
+	 *    configuration. Probably not needed, dependent on HW
+	 *    implementation.
+	 * 4. Check SE is ready for HW CTX_SAVE by polling
+	 *    SE_CTX_SAVE_AUTO_STATUS.SE_READY.
+	 *
+	 *    Steps 1-4 are executed by tegra_se_is_ready().
+	 *
+	 * 5. Issue context save command.
+	 * 6. Check SE is busy with CTX_SAVE, the command in step5 was not
+	 *    dropped for ongoing traffic in any of SE port/engine.
+	 * 7. Poll SE register or wait for SE APB interrupt for task completion
+	 *    a. Polling: Read SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE
+	 *    b. Interrupt: After receiving interrupt from SE APB, read
+	 *       SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE.
+	 * 8. Check AES0 and SHA ERR_STATUS to ensure no error case.
+	 * 9. Check AES0 and SHA INT_STATUS to ensure operation has successfully
+	 *    completed.
+	 *
+	 *    Steps 6-9 are executed by tegra_se_is_operation_complete().
+	 */
+	if (tegra_se_is_ready()) {
+
+		/* Issue context save command */
+		tegra_se_write_32(AES0_OPERATION, SE_OP_CTX_SAVE);
+
+		/* Wait for operation to finish */
+		if (tegra_se_is_operation_complete()) {
+			ret = 0;
+		}
+	}
+
+	return ret;
+}
+
+/*
+ * Handler to power down the SE hardware blocks - SE, RNG1 and PKA1. This
+ * needs to be called only during System Suspend.
+ */
+int32_t tegra_se_suspend(void)
+{
+	int32_t ret = 0;
+
+	/* save SE registers */
+	se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
+	se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL);
+	se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT);
+	se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT);
+
+	/* Save SE context. The BootROM restores it during System Resume */
+	ret = tegra_se_save_context();
+	if (ret != 0) {
+		ERROR("%s: context save failed (%d)\n", __func__, ret);
+	}
+
+	return ret;
+}
+
+/*
+ * Handler to power up the SE hardware block(s) during System Resume.
+ */
+void tegra_se_resume(void)
+{
+	/*
+	 * When TZ takes over after System Resume, TZ should first reconfigure
+	 * SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT,
+	 * RNG1_MUTEX_WATCHDOG_NS_LIMIT and SE_ENTROPY_SRC_AGE_CTRL before
+	 * other operations.
+	 */
+	mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]);
+	mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]);
+	mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]);
+	mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
+}
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
new file mode 100644
index 0000000..7d531bb
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
@@ -0,0 +1,84 @@
+﻿/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SE_PRIVATE_H__
+#define __SE_PRIVATE_H__
+
+#include <lib/utils_def.h>
+
+/* SE0_INT_ENABLE_0 */
+#define SE0_INT_ENABLE				U(0x88)
+#define  SE0_DISABLE_ALL_INT			U(0x0)
+
+/* SE0_INT_STATUS_0 */
+#define SE0_INT_STATUS				U(0x8C)
+#define  SE0_CLEAR_ALL_INT_STATUS		U(0x3F)
+
+/* SE0_SHA_INT_STATUS_0 */
+#define SHA_INT_STATUS				U(0x184)
+#define  SHA_SE_OP_DONE				(U(1) << 4)
+
+/* SE0_SHA_ERR_STATUS_0 */
+#define SHA_ERR_STATUS				U(0x18C)
+
+/* SE0_AES0_INT_STATUS_0 */
+#define AES0_INT_STATUS				U(0x2F0)
+#define  AES0_SE_OP_DONE			(U(1) << 4)
+
+/* SE0_AES0_ERR_STATUS_0 */
+#define AES0_ERR_STATUS				U(0x2F8)
+
+/* SE0_AES1_INT_STATUS_0 */
+#define AES1_INT_STATUS				U(0x4F0)
+
+/* SE0_AES1_ERR_STATUS_0 */
+#define AES1_ERR_STATUS				U(0x4F8)
+
+/* SE0_RSA_INT_STATUS_0 */
+#define RSA_INT_STATUS				U(0x758)
+
+/* SE0_RSA_ERR_STATUS_0 */
+#define RSA_ERR_STATUS				U(0x760)
+
+/* SE0_AES0_OPERATION_0 */
+#define AES0_OPERATION				U(0x238)
+#define  OP_MASK_BITS				U(0x7)
+#define  SE_OP_CTX_SAVE				U(0x3)
+
+/* SE0_AES0_CTX_SAVE_CONFIG_0 */
+#define	CTX_SAVE_CONFIG				U(0x2D4)
+
+/* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */
+#define CTX_SAVE_AUTO_STATUS			U(0x300)
+#define  CTX_SAVE_AUTO_SE_READY			U(0xFF)
+#define	 CTX_SAVE_AUTO_SE_BUSY			(U(0x1) << 31)
+
+/* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */
+#define CTX_SAVE_AUTO_CTRL			U(0x304)
+#define	 SE_CTX_SAVE_AUTO_EN			(U(0x1) << 0)
+#define	 SE_CTX_SAVE_AUTO_LOCK_EN		(U(0x1) << 1)
+
+/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */
+#define CTX_SAVE_AUTO_START_ADDR		U(0x308)
+
+/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */
+#define CTX_SAVE_AUTO_START_ADDR_HI		U(0x30C)
+
+/*******************************************************************************
+ * Inline functions definition
+ ******************************************************************************/
+
+static inline uint32_t tegra_se_read_32(uint32_t offset)
+{
+	return mmio_read_32(TEGRA_SE0_BASE + offset);
+}
+
+static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
+{
+	mmio_write_32(TEGRA_SE0_BASE + offset, val);
+}
+
+#endif /* __SE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
new file mode 100644
index 0000000..54dbe7c
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -0,0 +1,674 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/bl_common.h>
+#include <mce.h>
+#include <memctrl_v2.h>
+#include <tegra_mc_def.h>
+#include <tegra_platform.h>
+
+/*******************************************************************************
+ * Array to hold stream_id override config register offsets
+ ******************************************************************************/
+const static uint32_t tegra194_streamid_override_regs[] = {
+	MC_STREAMID_OVERRIDE_CFG_HDAR,
+	MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
+	MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
+	MC_STREAMID_OVERRIDE_CFG_SATAR,
+	MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
+	MC_STREAMID_OVERRIDE_CFG_HDAW,
+	MC_STREAMID_OVERRIDE_CFG_SATAW,
+	MC_STREAMID_OVERRIDE_CFG_ISPRA,
+	MC_STREAMID_OVERRIDE_CFG_ISPFALR,
+	MC_STREAMID_OVERRIDE_CFG_ISPWA,
+	MC_STREAMID_OVERRIDE_CFG_ISPWB,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
+	MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
+	MC_STREAMID_OVERRIDE_CFG_TSECSRD,
+	MC_STREAMID_OVERRIDE_CFG_TSECSWR,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCR,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCW,
+	MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
+	MC_STREAMID_OVERRIDE_CFG_VICSRD,
+	MC_STREAMID_OVERRIDE_CFG_VICSWR,
+	MC_STREAMID_OVERRIDE_CFG_VIW,
+	MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
+	MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
+	MC_STREAMID_OVERRIDE_CFG_APER,
+	MC_STREAMID_OVERRIDE_CFG_APEW,
+	MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
+	MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
+	MC_STREAMID_OVERRIDE_CFG_SESRD,
+	MC_STREAMID_OVERRIDE_CFG_SESWR,
+	MC_STREAMID_OVERRIDE_CFG_AXIAPR,
+	MC_STREAMID_OVERRIDE_CFG_AXIAPW,
+	MC_STREAMID_OVERRIDE_CFG_ETRR,
+	MC_STREAMID_OVERRIDE_CFG_ETRW,
+	MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
+	MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
+	MC_STREAMID_OVERRIDE_CFG_AXISR,
+	MC_STREAMID_OVERRIDE_CFG_AXISW,
+	MC_STREAMID_OVERRIDE_CFG_EQOSR,
+	MC_STREAMID_OVERRIDE_CFG_EQOSW,
+	MC_STREAMID_OVERRIDE_CFG_UFSHCR,
+	MC_STREAMID_OVERRIDE_CFG_UFSHCW,
+	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
+	MC_STREAMID_OVERRIDE_CFG_BPMPR,
+	MC_STREAMID_OVERRIDE_CFG_BPMPW,
+	MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
+	MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
+	MC_STREAMID_OVERRIDE_CFG_AONR,
+	MC_STREAMID_OVERRIDE_CFG_AONW,
+	MC_STREAMID_OVERRIDE_CFG_AONDMAR,
+	MC_STREAMID_OVERRIDE_CFG_AONDMAW,
+	MC_STREAMID_OVERRIDE_CFG_SCER,
+	MC_STREAMID_OVERRIDE_CFG_SCEW,
+	MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
+	MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
+	MC_STREAMID_OVERRIDE_CFG_APEDMAR,
+	MC_STREAMID_OVERRIDE_CFG_APEDMAW,
+	MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
+	MC_STREAMID_OVERRIDE_CFG_VICSRD1,
+	MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
+	MC_STREAMID_OVERRIDE_CFG_VIFALR,
+	MC_STREAMID_OVERRIDE_CFG_VIFALW,
+	MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
+	MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
+	MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
+	MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
+	MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
+	MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
+	MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
+	MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
+	MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
+	MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
+	MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
+	MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
+	MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
+	MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
+	MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
+	MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
+	MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
+	MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
+	MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
+	MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
+	MC_STREAMID_OVERRIDE_CFG_RCER,
+	MC_STREAMID_OVERRIDE_CFG_RCEW,
+	MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
+	MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
+	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
+	MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
+	MC_STREAMID_OVERRIDE_CFG_PCIE0R,
+	MC_STREAMID_OVERRIDE_CFG_PCIE0W,
+	MC_STREAMID_OVERRIDE_CFG_PCIE1R,
+	MC_STREAMID_OVERRIDE_CFG_PCIE1W,
+	MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
+	MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
+	MC_STREAMID_OVERRIDE_CFG_PCIE3R,
+	MC_STREAMID_OVERRIDE_CFG_PCIE3W,
+	MC_STREAMID_OVERRIDE_CFG_PCIE4R,
+	MC_STREAMID_OVERRIDE_CFG_PCIE4W,
+	MC_STREAMID_OVERRIDE_CFG_PCIE5R,
+	MC_STREAMID_OVERRIDE_CFG_PCIE5W,
+	MC_STREAMID_OVERRIDE_CFG_ISPFALW,
+	MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
+	MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
+	MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
+	MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
+	MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
+	MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
+	MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
+	MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
+	MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
+	MC_STREAMID_OVERRIDE_CFG_ISPRA1,
+	MC_STREAMID_OVERRIDE_CFG_MIU0R,
+	MC_STREAMID_OVERRIDE_CFG_MIU0W,
+	MC_STREAMID_OVERRIDE_CFG_MIU1R,
+	MC_STREAMID_OVERRIDE_CFG_MIU1W,
+	MC_STREAMID_OVERRIDE_CFG_MIU2R,
+	MC_STREAMID_OVERRIDE_CFG_MIU2W,
+	MC_STREAMID_OVERRIDE_CFG_MIU3R,
+	MC_STREAMID_OVERRIDE_CFG_MIU3W
+};
+
+/*******************************************************************************
+ * Array to hold the security configs for stream IDs
+ ******************************************************************************/
+const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
+	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPWA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPWB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VIW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AXIAPR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AXIAPW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VIFALR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VIFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA0FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA0FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA1FALRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA1FALWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1RDA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1RDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1RDC, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1WRA, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1WRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1WRC, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(RCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(RCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(RCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(RCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENC1SRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENC1SWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE0R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE0W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE1R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE1W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE2AR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE2AW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE3R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE3W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE4R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE4W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE5R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE5W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPFALW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(DLA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA0RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1RDA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PVA1RDB1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(PCIE5R1, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENCSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVENC1SRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ISPRA1, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU0R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU0W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU1R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU1W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU2R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU2W, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU3R, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MIU3W, NON_SECURE, OVERRIDE, ENABLE),
+};
+
+/*******************************************************************************
+ * Array to hold the transaction override configs
+ ******************************************************************************/
+const static mc_txn_override_cfg_t tegra194_txn_override_cfgs[] = {
+	mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
+	mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
+};
+
+/* To be called by common memctrl_v2.c */
+static void tegra194_memctrl_reconfig_mss_clients(void)
+{
+	uint32_t reg_val, wdata_0, wdata_1, wdata_2;
+
+	wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB;
+	if (tegra_platform_is_silicon()) {
+		wdata_0 |= MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB;
+	}
+
+	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
+
+	/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+	do {
+		reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
+	} while ((reg_val & wdata_0) != wdata_0);
+
+	wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB|
+		  MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB |
+		  MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB;
+	if (tegra_platform_is_silicon()) {
+		wdata_1 |= MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL1_RCE_FLUSH_ENB;
+	}
+	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
+	/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+	do {
+		reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
+	} while ((reg_val & wdata_1) != wdata_1);
+
+	wdata_2 = MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
+		MC_CLIENT_HOTRESET_CTRL2_AONDMA_FLUSH_ENB |
+		MC_CLIENT_HOTRESET_CTRL2_BPMPDMA_FLUSH_ENB |
+		MC_CLIENT_HOTRESET_CTRL2_SCEDMA_FLUSH_ENB;
+	if (tegra_platform_is_silicon()) {
+		wdata_2 |= MC_CLIENT_HOTRESET_CTRL2_RCEDMA_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE5A_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE3A_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE3_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE0A_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE0A2_FLUSH_ENB |
+			MC_CLIENT_HOTRESET_CTRL2_PCIE4A_FLUSH_ENB;
+	}
+	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+	/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
+	do {
+		reg_val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS2);
+	} while ((reg_val & wdata_2) != wdata_2);
+
+	/*
+	 * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
+	 * strongly ordered MSS clients.
+	 *
+	 * MC clients with default SO_DEV override still enabled at TSA:
+	 * EQOSW, SATAW, XUSB_DEVW, XUSB_HOSTW, PCIe0w, PCIe1w, PCIe2w,
+	 * PCIe3w, PCIe4w and PCIe5w.
+	 */
+	mc_set_tsa_w_passthrough(AONDMAW);
+	mc_set_tsa_w_passthrough(AONW);
+	mc_set_tsa_w_passthrough(APEDMAW);
+	mc_set_tsa_w_passthrough(APEW);
+	mc_set_tsa_w_passthrough(AXISW);
+	mc_set_tsa_w_passthrough(BPMPDMAW);
+	mc_set_tsa_w_passthrough(BPMPW);
+	mc_set_tsa_w_passthrough(ETRW);
+	mc_set_tsa_w_passthrough(SCEDMAW);
+	mc_set_tsa_w_passthrough(RCEDMAW);
+	mc_set_tsa_w_passthrough(RCEW);
+	mc_set_tsa_w_passthrough(SDMMCW);
+	mc_set_tsa_w_passthrough(SDMMCWA);
+	mc_set_tsa_w_passthrough(SDMMCWAB);
+	mc_set_tsa_w_passthrough(TSECSWR);
+	mc_set_tsa_w_passthrough(TSECSWRB);
+	mc_set_tsa_w_passthrough(UFSHCW);
+	mc_set_tsa_w_passthrough(VICSWR);
+	mc_set_tsa_w_passthrough(VIFALW);
+
+	/* Ordered MC Clients on Xavier are EQOS, SATA, XUSB, PCIe1 and PCIe3
+	 * ISO clients(DISP, VI, EQOS) should never snoop caches and
+	 *     don't need ROC/PCFIFO ordering.
+	 * ISO clients(EQOS) that need ordering should use PCFIFO ordering
+	 *     and bypass ROC ordering by using FORCE_NON_COHERENT path.
+	 * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
+	 *     over SMMU attributes.
+	 * Force all Normal memory transactions from ISO and non-ISO to be
+	 *     non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
+	 * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
+	 *     non-coherent path and enable MC PCFIFO interlock for ordering.
+	 * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
+	 *     XUSB, SATA) to coherent so that the transactions are
+	 *     ordered by ROC.
+	 * PCFIFO ensure write ordering.
+	 * Read after Write ordering is maintained/enforced by MC clients.
+	 * Clients that need PCIe type write ordering must
+	 *     go through ROC ordering.
+	 * Ordering enable for Read clients is not necessary.
+	 * R5's and A9 would get necessary ordering from AXI and
+	 *     don't need ROC ordering enable:
+	 *     - MMIO ordering is through dev mapping and MMIO
+	 *       accesses bypass SMMU.
+	 *     - Normal memory is accessed through SMMU and ordering is
+	 *       ensured by client and AXI.
+	 *     - Ack point for Normal memory is WCAM in MC.
+	 *     - MMIO's can be early acked and AXI ensures dev memory ordering,
+	 *       Client ensures read/write direction change ordering.
+	 *     - See Bug 200312466 for more details.
+	 *
+	 * CGID_TAG_ADR is only present from T186 A02. As this code is common
+	 *    between A01 and A02, tegra_memctrl_set_overrides() programs
+	 *    CGID_TAG_ADR for the necessary clients on A02.
+	 */
+	mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+	mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+	mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
+	mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+	mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(RCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(RCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(RCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(RCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE);
+	mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_COHERENT_SNOOP, NO_OVERRIDE);
+	mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(VIFALR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(VIFALW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+			     FORCE_COHERENT_SNOOP);
+	mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+			    FORCE_COHERENT_SNOOP);
+	mc_set_txn_override(PCIE0R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(PCIE0R1, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(PCIE0W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+			    FORCE_COHERENT_SNOOP);
+	mc_set_txn_override(PCIE1R, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
+	mc_set_txn_override(PCIE1W, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT,
+			    FORCE_COHERENT_SNOOP);
+	if (tegra_platform_is_silicon()) {
+		mc_set_txn_override(PCIE2AR, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    NO_OVERRIDE, NO_OVERRIDE);
+		mc_set_txn_override(PCIE2AW, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+		mc_set_txn_override(PCIE3R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    NO_OVERRIDE, NO_OVERRIDE);
+		mc_set_txn_override(PCIE3W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+		mc_set_txn_override(PCIE4R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    NO_OVERRIDE, NO_OVERRIDE);
+		mc_set_txn_override(PCIE4W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+		mc_set_txn_override(PCIE5R, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    NO_OVERRIDE, NO_OVERRIDE);
+		mc_set_txn_override(PCIE5W, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    FORCE_NON_COHERENT, FORCE_COHERENT_SNOOP);
+		mc_set_txn_override(PCIE5R1, CGID_TAG_DEFAULT, SO_DEV_ZERO,
+				    NO_OVERRIDE, NO_OVERRIDE);
+	}
+	/*
+	 * At this point, ordering can occur at ROC. So, remove PCFIFO's
+	 * control over ordering requests.
+	 *
+	 * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
+	 * boot and strongly ordered MSS clients
+	 */
+	/* SATAW is ordered client */
+	reg_val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL |
+		mc_set_pcfifo_ordered_boot_so_mss(1, SATAW);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, reg_val);
+
+	reg_val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
+		mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
+		mc_set_pcfifo_unordered_boot_so_mss(2, TSECSWR);
+	/* XUSB_DEVW has PCFIFO enabled. */
+	reg_val |= mc_set_pcfifo_ordered_boot_so_mss(2, XUSB_DEVW);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, reg_val);
+
+	reg_val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
+		mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWA) &
+		mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCW) &
+		mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB) &
+		mc_set_pcfifo_unordered_boot_so_mss(3, VICSWR) &
+		mc_set_pcfifo_unordered_boot_so_mss(3, APEW);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, reg_val);
+
+	reg_val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
+		mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, TSECSWRB) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, BPMPW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, AONW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, SCEW) &
+		mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
+	/* EQOSW has PCFIFO order enabled. */
+	reg_val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, reg_val);
+
+	reg_val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
+		mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW) &
+		mc_set_pcfifo_unordered_boot_so_mss(5, VIFALW);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, reg_val);
+
+	reg_val = MC_PCFIFO_CLIENT_CONFIG6_RESET_VAL &
+		mc_set_pcfifo_unordered_boot_so_mss(6, RCEW) &
+		mc_set_pcfifo_unordered_boot_so_mss(6, RCEDMAW) &
+		mc_set_pcfifo_unordered_boot_so_mss(6, PCIE0W);
+	/* PCIE1, PCIE2 and PCI3 has PCFIFO enabled. */
+	reg_val |= mc_set_pcfifo_ordered_boot_so_mss(6, PCIE1W) |
+		mc_set_pcfifo_ordered_boot_so_mss(6, PCIE2W) |
+		mc_set_pcfifo_ordered_boot_so_mss(6, PCIE3W);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG6, reg_val);
+
+	reg_val = MC_PCFIFO_CLIENT_CONFIG7_RESET_VAL &
+		mc_set_pcfifo_unordered_boot_so_mss(7, PCIE4W) &
+		mc_set_pcfifo_unordered_boot_so_mss(7, PCIE5W);
+	tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG7, reg_val);
+
+	/* Set Order Id only for the clients having non zero order id */
+	reg_val = MC_CLIENT_ORDER_ID_9_RESET_VAL &
+		mc_client_order_id(9, XUSB_HOSTW);
+	tegra_mc_write_32(MC_CLIENT_ORDER_ID_9, reg_val);
+
+	reg_val = MC_CLIENT_ORDER_ID_27_RESET_VAL &
+		mc_client_order_id(27, PCIE0W);
+	tegra_mc_write_32(MC_CLIENT_ORDER_ID_27, reg_val);
+
+	reg_val = MC_CLIENT_ORDER_ID_28_RESET_VAL &
+		mc_client_order_id(28, PCIE4W) &
+		mc_client_order_id(28, PCIE5W);
+	tegra_mc_write_32(MC_CLIENT_ORDER_ID_28, reg_val);
+
+	/* Set VC Id only for the clients having different reset values */
+	reg_val = MC_HUB_PC_VC_ID_0_RESET_VAL &
+		/*
+		 * SDMMCRAB, SDMMCWAB, SESRD, SESWR, TSECSRD,TSECSRDB,
+		 * TSECSWR and TSECSWRB clients
+		 */
+		mc_hub_vc_id(0, APB);
+	tegra_mc_write_32(MC_HUB_PC_VC_ID_0, reg_val);
+
+	reg_val = MC_HUB_PC_VC_ID_2_RESET_VAL &
+	/* SDMMCRAB and SDMMCWAB clients */
+		mc_hub_vc_id(2, SD);
+	tegra_mc_write_32(MC_HUB_PC_VC_ID_2, reg_val);
+
+	reg_val = MC_HUB_PC_VC_ID_4_RESET_VAL &
+	 /* AXIR and AXIW clients */
+		mc_hub_vc_id(4, NIC);
+	tegra_mc_write_32(MC_HUB_PC_VC_ID_4, reg_val);
+
+	wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
+	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
+
+	wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
+	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
+
+	wdata_2 = MC_CLIENT_HOTRESET_CTRL2_RESET_VAL;
+	tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL2, wdata_2);
+}
+
+/*******************************************************************************
+ * Struct to hold the memory controller settings
+ ******************************************************************************/
+static tegra_mc_settings_t tegra194_mc_settings = {
+	.streamid_override_cfg = tegra194_streamid_override_regs,
+	.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
+	.streamid_security_cfg = tegra194_streamid_sec_cfgs,
+	.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
+	.txn_override_cfg = tegra194_txn_override_cfgs,
+	.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_txn_override_cfgs),
+	.reconfig_mss_clients = tegra194_memctrl_reconfig_mss_clients
+};
+
+/*******************************************************************************
+ * Handler to return the pointer to the memory controller's settings struct
+ ******************************************************************************/
+tegra_mc_settings_t *tegra_get_mc_settings(void)
+{
+	return &tegra194_mc_settings;
+}
+
+/*******************************************************************************
+ * Handler to program the scratch registers with TZDRAM settings for the
+ * resume firmware
+ ******************************************************************************/
+void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
+{
+	uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
+
+	/*
+	 * Check TZDRAM carveout register access status. Setup TZDRAM fence
+	 * only if access is enabled.
+	 */
+	if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
+	     SECURITY_CFG_WRITE_ACCESS_ENABLE) {
+
+		/*
+		 * Setup the Memory controller to allow only secure accesses to
+		 * the TZDRAM carveout
+		 */
+		INFO("Configuring TrustZone DRAM Memory Carveout\n");
+
+		tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
+		tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
+		tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
+
+		/*
+		 * MCE propagates the security configuration values across the
+		 * CCPLEX.
+		 */
+		(void)mce_update_gsc_tzdram();
+	}
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index e53d594..948fade 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -5,58 +5,65 @@
  */
 
 #include <arch.h>
-#include <arch_helpers.h>
 #include <assert.h>
-#include <common/bl_common.h>
-#include <context.h>
-#include <lib/el3_runtime/context_mgmt.h>
-#include <common/debug.h>
-#include <denver.h>
-#include <mce.h>
-#include <plat/common/platform.h>
-#include <lib/psci/psci.h>
-#include <smmu.h>
+#include <stdbool.h>
 #include <string.h>
-#include <tegra_private.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <context.h>
+#include <denver.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/psci/psci.h>
+#include <mce.h>
+#include <mce_private.h>
+#include <plat/common/platform.h>
+#include <se.h>
+#include <smmu.h>
 #include <t194_nvg.h>
+#include <tegra194_private.h>
+#include <tegra_platform.h>
+#include <tegra_private.h>
 
-extern void prepare_core_pwr_dwn(void);
-
-extern uint8_t tegra_fake_system_suspend;
-
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-extern void tegra186_cpu_reset_handler(void);
-extern uint32_t __tegra186_cpu_reset_handler_data,
-		__tegra186_cpu_reset_handler_end;
+extern void tegra194_cpu_reset_handler(void);
+extern uint32_t __tegra194_cpu_reset_handler_data,
+		__tegra194_cpu_reset_handler_end;
 
 /* TZDRAM offset for saving SMMU context */
-#define TEGRA186_SMMU_CTX_OFFSET	16
-#endif
+#define TEGRA194_SMMU_CTX_OFFSET	16U
 
 /* state id mask */
-#define TEGRA186_STATE_ID_MASK		0xF
+#define TEGRA194_STATE_ID_MASK		0xFU
 /* constants to get power state's wake time */
-#define TEGRA186_WAKE_TIME_MASK		0x0FFFFFF0
-#define TEGRA186_WAKE_TIME_SHIFT	4
+#define TEGRA194_WAKE_TIME_MASK		0x0FFFFFF0U
+#define TEGRA194_WAKE_TIME_SHIFT	4U
 /* default core wake mask for CPU_SUSPEND */
-#define TEGRA186_CORE_WAKE_MASK		0x180c
-/* context size to save during system suspend */
-#define TEGRA186_SE_CONTEXT_SIZE	3
+#define TEGRA194_CORE_WAKE_MASK		0x180cU
 
-static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
-static struct t18x_psci_percpu_data {
-	unsigned int wake_time;
-} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT];
+static struct t19x_psci_percpu_data {
+	uint32_t wake_time;
+} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
 
-int32_t tegra_soc_validate_power_state(unsigned int power_state,
+/*
+ * tegra_fake_system_suspend acts as a boolean var controlling whether
+ * we are going to take fake system suspend code or normal system suspend code
+ * path. This variable is set inside the sip call handlers, when the kernel
+ * requests an SIP call to set the suspend debug flags.
+ */
+bool tegra_fake_system_suspend;
+
+int32_t tegra_soc_validate_power_state(uint32_t power_state,
 					psci_power_state_t *req_state)
 {
-	int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK;
-	int cpu = plat_my_core_pos();
+	uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) &
+			   TEGRA194_STATE_ID_MASK;
+	uint32_t cpu = plat_my_core_pos();
+	int32_t ret = PSCI_E_SUCCESS;
 
 	/* save the core wake time (in TSC ticks)*/
-	percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK)
-			<< TEGRA186_WAKE_TIME_SHIFT;
+	t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK)
+			<< TEGRA194_WAKE_TIME_SHIFT;
 
 	/*
 	 * Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
@@ -65,8 +72,8 @@
 	 * from DRAM in that function, because the L2 cache is not flushed
 	 * unless the cluster is entering CC6/CC7.
 	 */
-	clean_dcache_range((uint64_t)&percpu_data[cpu],
-			sizeof(percpu_data[cpu]));
+	clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
+			sizeof(t19x_percpu_data[cpu]));
 
 	/* Sanity check the requested state id */
 	switch (state_id) {
@@ -81,148 +88,195 @@
 
 	default:
 		ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
-		return PSCI_E_INVALID_PARAMS;
+		ret = PSCI_E_INVALID_PARAMS;
+		break;
 	}
 
-	return PSCI_E_SUCCESS;
+	return ret;
 }
 
-int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
 	const plat_local_state_t *pwr_domain_state;
-	unsigned int stateid_afflvl0, stateid_afflvl2;
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
+	uint8_t stateid_afflvl0, stateid_afflvl2;
 	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
 	uint64_t smmu_ctx_base;
-#endif
 	uint32_t val;
-	mce_cstate_info_t cstate_info = { 0 };
+	mce_cstate_info_t sc7_cstate_info = {
+		.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
+		.system = (uint32_t)TEGRA_NVG_SYSTEM_SC7,
+		.system_state_force = 1U,
+		.update_wake_mask = 1U,
+	};
+	uint32_t cpu = plat_my_core_pos();
+	int32_t ret = 0;
 
 	/* get the state ID */
 	pwr_domain_state = target_state->pwr_domain_state;
 	stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
-		TEGRA186_STATE_ID_MASK;
+		TEGRA194_STATE_ID_MASK;
 	stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
-		TEGRA186_STATE_ID_MASK;
+		TEGRA194_STATE_ID_MASK;
 
 	if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
 	    (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
 
 		/* Enter CPU idle/powerdown */
+		val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
+			(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
+		ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
+				percpu_data[cpu].wake_time, 0);
+		assert(ret == 0);
 
 	} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 
-		/* save SE registers */
-		se_regs[0] = mmio_read_32(TEGRA_SE0_BASE +
-				SE_MUTEX_WATCHDOG_NS_LIMIT);
-		se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE +
-				RNG_MUTEX_WATCHDOG_NS_LIMIT);
-		se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE +
-				PKA_MUTEX_WATCHDOG_NS_LIMIT);
-
 		/* save 'Secure Boot' Processor Feature Config Register */
 		val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
-		mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val);
+		mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
 
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
 		/* save SMMU context */
 		smmu_ctx_base = params_from_bl2->tzdram_base +
-			((uintptr_t)&__tegra186_cpu_reset_handler_data -
-			 (uintptr_t)tegra186_cpu_reset_handler) +
-			TEGRA186_SMMU_CTX_OFFSET;
+				tegra194_get_smmu_ctx_offset();
 		tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
-#else
-		tegra_smmu_save_context(0);
-#endif
 
-		if (tegra_fake_system_suspend == 0U) {
+		/*
+		 * Suspend SE, RNG1 and PKA1 only on silcon and fpga,
+		 * since VDK does not support atomic se ctx save
+		 */
+		if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
+			ret = tegra_se_suspend();
+			assert(ret == 0);
+		}
+
+		if (!tegra_fake_system_suspend) {
 
 			/* Prepare for system suspend */
-			cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6;
-			cstate_info.system = TEGRA_NVG_SYSTEM_SC7;
-			cstate_info.system_state_force = 1;
-			cstate_info.update_wake_mask = 1;
-
-			mce_update_cstate_info(&cstate_info);
+			mce_update_cstate_info(&sc7_cstate_info);
 
 			do {
-				val = mce_command_handler(
-						MCE_CMD_IS_SC7_ALLOWED,
-						TEGRA_NVG_CORE_C7,
+				val = (uint32_t)mce_command_handler(
+						(uint32_t)MCE_CMD_IS_SC7_ALLOWED,
+						(uint32_t)TEGRA_NVG_CORE_C7,
 						MCE_CORE_SLEEP_TIME_INFINITE,
-						0);
-			} while (val == 0);
+						0U);
+			} while (val == 0U);
 
-	                /* Instruct the MCE to enter system suspend state */
-			(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
-			TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
+			/* Instruct the MCE to enter system suspend state */
+			ret = mce_command_handler(
+					(uint64_t)MCE_CMD_ENTER_CSTATE,
+					(uint64_t)TEGRA_NVG_CORE_C7,
+					MCE_CORE_SLEEP_TIME_INFINITE,
+					0U);
+			assert(ret == 0);
+
+			/* set system suspend state for house-keeping */
+			tegra194_set_system_suspend_entry();
 		}
+	} else {
+		; /* do nothing */
 	}
 
 	return PSCI_E_SUCCESS;
 }
 
 /*******************************************************************************
- * Platform handler to calculate the proper target power level at the
- * specified affinity level
+ * Helper function to check if this is the last ON CPU in the cluster
  ******************************************************************************/
-plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
-					     const plat_local_state_t *states,
-					     unsigned int ncpu)
+static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states,
+			uint32_t ncpu)
 {
-	plat_local_state_t target = *states;
-	int cluster_powerdn = 1;
-	int core_pos = read_mpidr() & MPIDR_CPU_MASK;
+	plat_local_state_t target;
+	bool last_on_cpu = true;
+	uint32_t num_cpus = ncpu, pos = 0;
 
-	/* get the current core's power state */
-	target = *(states + core_pos);
+	do {
+		target = states[pos];
+		if (target != PLAT_MAX_OFF_STATE) {
+			last_on_cpu = false;
+		}
+		--num_cpus;
+		pos++;
+	} while (num_cpus != 0U);
+
+	return last_on_cpu;
+}
+
+/*******************************************************************************
+ * Helper function to get target power state for the cluster
+ ******************************************************************************/
+static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states,
+			uint32_t ncpu)
+{
+	uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK;
+	plat_local_state_t target = states[core_pos];
+	mce_cstate_info_t cstate_info = { 0 };
 
 	/* CPU suspend */
-	if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) {
+	if (target == PSTATE_ID_CORE_POWERDN) {
 
 		/* Program default wake mask */
-
-		/* Check if CCx state is allowed. */
+		cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
+		cstate_info.update_wake_mask = 1;
+		mce_update_cstate_info(&cstate_info);
 	}
 
 	/* CPU off */
-	if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) {
-
-		/* find out the number of ON cpus in the cluster */
-		do {
-			target = *states++;
-			if (target != PLAT_MAX_OFF_STATE)
-				cluster_powerdn = 0;
-		} while (--ncpu);
+	if (target == PLAT_MAX_OFF_STATE) {
 
 		/* Enable cluster powerdn from last CPU in the cluster */
-		if (cluster_powerdn) {
+		if (tegra_last_on_cpu_in_cluster(states, ncpu)) {
 
-			/* Enable CC7 state and turn off wake mask */
+			/* Enable CC6 state and turn off wake mask */
+			cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6;
+			cstate_info.update_wake_mask = 1U;
+			mce_update_cstate_info(&cstate_info);
 
 		} else {
 
 			/* Turn off wake_mask */
+			cstate_info.update_wake_mask = 1U;
+			mce_update_cstate_info(&cstate_info);
+			target = PSCI_LOCAL_STATE_RUN;
 		}
 	}
 
-	/* System Suspend */
-	if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN))
-		return PSTATE_ID_SOC_POWERDN;
-
-	/* default state */
-	return PSCI_LOCAL_STATE_RUN;
+	return target;
 }
 
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
+/*******************************************************************************
+ * Platform handler to calculate the proper target power level at the
+ * specified affinity level
+ ******************************************************************************/
+plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
+					     const plat_local_state_t *states,
+					     uint32_t ncpu)
+{
+	plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
+	uint32_t cpu = plat_my_core_pos();
+
+	/* System Suspend */
+	if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) {
+		target = PSTATE_ID_SOC_POWERDN;
+	}
+
+	/* CPU off, CPU suspend */
+	if (lvl == (uint32_t)MPIDR_AFFLVL1) {
+		target = tegra_get_afflvl1_pwr_state(states, ncpu);
+	}
+
+	/* target cluster/system state */
+	return target;
+}
+
+int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
 {
 	const plat_local_state_t *pwr_domain_state =
 		target_state->pwr_domain_state;
 	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
-	unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
-		TEGRA186_STATE_ID_MASK;
+	uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
+		TEGRA194_STATE_ID_MASK;
 	uint64_t val;
+	u_register_t ns_sctlr_el1;
 
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 		/*
@@ -231,38 +285,64 @@
 		 * BL3-1 over to TZDRAM.
 		 */
 		val = params_from_bl2->tzdram_base +
-			((uintptr_t)&__tegra186_cpu_reset_handler_end -
-			 (uintptr_t)tegra186_cpu_reset_handler);
+		      tegra194_get_cpu_reset_handler_size();
 		memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
 		       (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
+
+		/*
+		 * In fake suspend mode, ensure that the loopback procedure
+		 * towards system suspend exit is started, instead of calling
+		 * WFI. This is done by disabling both MMU's of EL1 & El3
+		 * and calling tegra_secure_entrypoint().
+		 */
+		if (tegra_fake_system_suspend) {
+
+			/*
+			 * Disable EL1's MMU.
+			 */
+			ns_sctlr_el1 = read_sctlr_el1();
+			ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT));
+			write_sctlr_el1(ns_sctlr_el1);
+
+			/*
+			 * Disable MMU to power up the CPU in a "clean"
+			 * state
+			 */
+			disable_mmu_el3();
+			tegra_secure_entrypoint();
+			panic();
+		}
 	}
 
 	return PSCI_E_SUCCESS;
 }
-#endif
 
-int tegra_soc_pwr_domain_on(u_register_t mpidr)
+int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
 {
-	int target_cpu = mpidr & MPIDR_CPU_MASK;
-	int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
+	uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
+	uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
 			MPIDR_AFFINITY_BITS;
+	int32_t ret = 0;
 
-	if (target_cluster > MPIDR_AFFLVL1) {
+	if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) {
 		ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr);
 		return PSCI_E_NOT_PRESENT;
 	}
 
 	/* construct the target CPU # */
-	target_cpu |= (target_cluster << 2);
+	target_cpu += (target_cluster << 1U);
 
-	mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0);
+	ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U);
+	if (ret < 0) {
+		return PSCI_E_DENIED;
+	}
 
 	return PSCI_E_SUCCESS;
 }
 
-int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
-	int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
+	uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
 
 	/*
 	 * Reset power state info for CPUs when onlining, we set
@@ -278,14 +358,17 @@
 	 */
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 
-		mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
-			se_regs[0]);
-		mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,
-			se_regs[1]);
-		mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT,
-			se_regs[2]);
+		/*
+		 * Enable strict checking after programming the GSC for
+		 * enabling TZSRAM and TZDRAM
+		 */
+		mce_enable_strict_checking();
 
 		/* Init SMMU */
+		tegra_smmu_init();
+
+		/* Resume SE, RNG1 and PKA1 */
+		tegra_se_resume();
 
 		/*
 		 * Reset power state info for the last core doing SC7
@@ -298,15 +381,22 @@
 	return PSCI_E_SUCCESS;
 }
 
-int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
+int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 {
-	int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+	uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+	int32_t ret = 0;
+
+	(void)target_state;
 
 	/* Disable Denver's DCO operations */
-	if (impl == DENVER_IMPL)
+	if (impl == DENVER_IMPL) {
 		denver_disable_dco();
+	}
 
 	/* Turn off CPU */
+	ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
+			(uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
+	assert(ret == 0);
 
 	return PSCI_E_SUCCESS;
 }
@@ -325,7 +415,7 @@
 	}
 }
 
-int tegra_soc_prepare_system_reset(void)
+int32_t tegra_soc_prepare_system_reset(void)
 {
 	return PSCI_E_SUCCESS;
 }
diff --git a/plat/nvidia/tegra/soc/t194/plat_secondary.c b/plat/nvidia/tegra/soc/t194/plat_secondary.c
index f5e56b9..c397c91 100644
--- a/plat/nvidia/tegra/soc/t194/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t194/plat_secondary.c
@@ -9,21 +9,14 @@
 #include <lib/mmio.h>
 #include <mce.h>
 #include <string.h>
+#include <tegra194_private.h>
 #include <tegra_def.h>
 #include <tegra_private.h>
 
-#define MISCREG_CPU_RESET_VECTOR	0x2000
-#define MISCREG_AA64_RST_LOW		0x2004
-#define MISCREG_AA64_RST_HIGH		0x2008
+#define MISCREG_AA64_RST_LOW		0x2004U
+#define MISCREG_AA64_RST_HIGH		0x2008U
 
-#define CPU_RESET_MODE_AA64		1
-
-extern void tegra_secure_entrypoint(void);
-
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-extern void tegra186_cpu_reset_handler(void);
-extern uint64_t __tegra186_smmu_ctx_start;
-#endif
+#define CPU_RESET_MODE_AA64		1U
 
 /*******************************************************************************
  * Setup secondary CPU vectors
@@ -31,32 +24,33 @@
 void plat_secondary_setup(void)
 {
 	uint32_t addr_low, addr_high;
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
 	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
-	uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base;
-#else
-	uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
-#endif
+	uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
 
 	INFO("Setting up secondary CPU boot\n");
 
-#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
-	memcpy((void *)((uintptr_t)cpu_reset_handler_base),
-		 (void *)(uintptr_t)tegra186_cpu_reset_handler,
-		 (uintptr_t)&__tegra186_smmu_ctx_start -
-		 (uintptr_t)tegra186_cpu_reset_handler);
-#endif
+	/*
+	 * The BL31 code resides in the TZSRAM which loses state
+	 * when we enter System Suspend. Copy the wakeup trampoline
+	 * code to TZDRAM to help us exit from System Suspend.
+	 */
+	cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base();
+	cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size();
+	memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base),
+		(void *)((uintptr_t)cpu_reset_handler_base),
+		cpu_reset_handler_size);
 
-	addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
-	addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff);
+	/* TZDRAM base will be used as the "resume" address */
+	addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
+	addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
 
 	/* write lower 32 bits first, then the upper 11 bits */
 	mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
 	mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
 
 	/* save reset vector to be used during SYSTEM_SUSPEND exit */
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO,
+	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
 			addr_low);
-	mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI,
+	mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
 			addr_high);
 }
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index a3a2515..8c57105 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -19,19 +19,25 @@
 #include <drivers/arm/gicv2.h>
 #include <bl31/interrupt_mgmt.h>
 #include <mce.h>
+#include <mce_private.h>
 #include <plat/common/platform.h>
+#include <spe.h>
 #include <tegra_def.h>
+#include <tegra_mc_def.h>
 #include <tegra_platform.h>
 #include <tegra_private.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 
+/* ID for spe-console */
+#define TEGRA_CONSOLE_SPE_ID		0xFE
+
 /*******************************************************************************
  * The Tegra power domain tree has a single system level power domain i.e. a
  * single root node. The first entry in the power domain descriptor specifies
  * the number of power domains at the highest power level.
  *******************************************************************************
  */
-const unsigned char tegra_power_domain_tree_desc[] = {
+static const uint8_t tegra_power_domain_tree_desc[] = {
 	/* No of root nodes */
 	1,
 	/* No of clusters */
@@ -39,13 +45,17 @@
 	/* No of CPU cores - cluster0 */
 	PLATFORM_MAX_CPUS_PER_CLUSTER,
 	/* No of CPU cores - cluster1 */
+	PLATFORM_MAX_CPUS_PER_CLUSTER,
+	/* No of CPU cores - cluster2 */
+	PLATFORM_MAX_CPUS_PER_CLUSTER,
+	/* No of CPU cores - cluster3 */
 	PLATFORM_MAX_CPUS_PER_CLUSTER
 };
 
 /*******************************************************************************
  * This function returns the Tegra default topology tree information.
  ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
+const uint8_t *plat_get_power_domain_tree_desc(void)
 {
 	return tegra_power_domain_tree_desc;
 }
@@ -54,44 +64,52 @@
  * Table of regions to map using the MMU.
  */
 static const mmap_region_t tegra_mmap[] = {
-	MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
-	MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */
-			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#if !ENABLE_CONSOLE_SPE
+	MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#endif
+	MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#if ENABLE_CONSOLE_SPE
+	MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+#endif
+	MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
+	MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */
+			(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
 	{0}
 };
 
@@ -107,20 +125,21 @@
 /*******************************************************************************
  * Handler to get the System Counter Frequency
  ******************************************************************************/
-unsigned int plat_get_syscnt_freq2(void)
+uint32_t plat_get_syscnt_freq2(void)
 {
 	return 31250000;
 }
 
+#if !ENABLE_CONSOLE_SPE
 /*******************************************************************************
  * Maximum supported UART controllers
  ******************************************************************************/
-#define TEGRA186_MAX_UART_PORTS		7
+#define TEGRA194_MAX_UART_PORTS		7
 
 /*******************************************************************************
  * This variable holds the UART port base addresses
  ******************************************************************************/
-static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
+static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
 	0,	/* undefined - treated as an error case */
 	TEGRA_UARTA_BASE,
 	TEGRA_UARTB_BASE,
@@ -128,18 +147,49 @@
 	TEGRA_UARTD_BASE,
 	TEGRA_UARTE_BASE,
 	TEGRA_UARTF_BASE,
-	TEGRA_UARTG_BASE,
+	TEGRA_UARTG_BASE
 };
+#endif
 
 /*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
  ******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
 {
-	if (id > TEGRA186_MAX_UART_PORTS)
-		return 0;
+	uint32_t console_clock = 0U;
 
-	return tegra186_uart_addresses[id];
+#if ENABLE_CONSOLE_SPE
+	static console_spe_t spe_console;
+
+	if (id == TEGRA_CONSOLE_SPE_ID) {
+		(void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
+					   console_clock,
+					   TEGRA_CONSOLE_BAUDRATE,
+					   &spe_console);
+		console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+	}
+#else
+	static console_16550_t uart_console;
+
+	if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
+		/*
+		 * Reference clock used by the FPGAs is a lot slower.
+		 */
+		if (tegra_platform_is_fpga()) {
+			console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+		} else {
+			console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+		}
+
+		(void)console_16550_register(tegra194_uart_addresses[id],
+					     console_clock,
+					     TEGRA_CONSOLE_BAUDRATE,
+					     &uart_console);
+		console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+	}
+#endif
 }
 
 /*******************************************************************************
@@ -151,40 +201,61 @@
 	/* sanity check MCE firmware compatibility */
 	mce_verify_firmware_version();
 
+	/* Program XUSB STREAMIDs
+	 * Xavier XUSB has support for XUSB virtualization. It will have one
+	 * physical function (PF) and four Virtual function (VF)
+	 *
+	 * There were below two SIDs for XUSB until T186.
+	 * 1) #define TEGRA_SID_XUSB_HOST    0x1bU
+	 * 2) #define TEGRA_SID_XUSB_DEV    0x1cU
+	 *
+	 * We have below four new SIDs added for VF(s)
+	 * 3) #define TEGRA_SID_XUSB_VF0    0x5dU
+	 * 4) #define TEGRA_SID_XUSB_VF1    0x5eU
+	 * 5) #define TEGRA_SID_XUSB_VF2    0x5fU
+	 * 6) #define TEGRA_SID_XUSB_VF3    0x60U
+	 *
+	 * When virtualization is enabled then we have to disable SID override
+	 * and program above SIDs in below newly added SID registers in XUSB
+	 * PADCTL MMIO space. These registers are TZ protected and so need to
+	 * be done in ATF.
+	 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
+	 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0  (0x139cU)
+	 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
+	 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
+	 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
+	 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
+	 *
+	 * This change disables SID override and programs XUSB SIDs in
+	 * above registers to support both virtualization and non-virtualization
+	 *
+	 * Known Limitations:
+	 * If xusb interface disables SMMU in XUSB DT in non-virtualization
+	 * setup then there will be SMMU fault. We need to use WAR at
+	 * https:\\git-master.nvidia.com/r/1529227/ to the issue.
+	 *
+	 * More details can be found in the bug 1971161
+	 */
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
+	mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
+		XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
 }
 
-/* Secure IRQs for Tegra186 */
-static const irq_sec_cfg_t tegra186_sec_irqs[] = {
-	[0] = {
-		TEGRA186_BPMP_WDT_IRQ,
-		TEGRA186_SEC_IRQ_TARGET_MASK,
-		INTR_TYPE_EL3,
-	},
-	[1] = {
-		TEGRA186_BPMP_WDT_IRQ,
-		TEGRA186_SEC_IRQ_TARGET_MASK,
-		INTR_TYPE_EL3,
-	},
-	[2] = {
-		TEGRA186_SPE_WDT_IRQ,
-		TEGRA186_SEC_IRQ_TARGET_MASK,
-		INTR_TYPE_EL3,
-	},
-	[3] = {
-		TEGRA186_SCE_WDT_IRQ,
-		TEGRA186_SEC_IRQ_TARGET_MASK,
-		INTR_TYPE_EL3,
-	},
-	[4] = {
-		TEGRA186_TOP_WDT_IRQ,
-		TEGRA186_SEC_IRQ_TARGET_MASK,
-		INTR_TYPE_EL3,
-	},
-	[5] = {
-		TEGRA186_AON_WDT_IRQ,
-		TEGRA186_SEC_IRQ_TARGET_MASK,
-		INTR_TYPE_EL3,
-	},
+/* Secure IRQs for Tegra194 */
+static const interrupt_prop_t tegra194_interrupt_props[] = {
+	INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
+			GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+	INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
+			GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
 };
 
 /*******************************************************************************
@@ -192,15 +263,13 @@
  ******************************************************************************/
 void plat_gic_setup(void)
 {
-	tegra_gic_setup(tegra186_sec_irqs,
-		sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
+	tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
+	tegra_gic_init();
 
 	/*
-	 * Initialize the FIQ handler only if the platform supports any
-	 * FIQ interrupt sources.
+	 * Initialize the FIQ handler
 	 */
-	if (sizeof(tegra186_sec_irqs) > 0)
-		tegra_fiq_handler_setup();
+	tegra_fiq_handler_setup();
 }
 
 /*******************************************************************************
@@ -210,7 +279,7 @@
 {
 	uint32_t val;
 
-	val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
+	val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
 
 	return (struct tegra_bl31_params *)(uintptr_t)val;
 }
@@ -222,7 +291,16 @@
 {
 	uint32_t val;
 
-	val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
+	val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
 
 	return (plat_params_from_bl2_t *)(uintptr_t)val;
 }
+
+void plat_late_platform_setup(void)
+{
+	/*
+	 * Enable strict checking after programming the GSC for
+	 * enabling TZSRAM and TZDRAM
+	 */
+	mce_enable_strict_checking();
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index eaad73a..8873358 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -15,38 +15,20 @@
 #include <memctrl.h>
 #include <common/runtime_svc.h>
 #include <tegra_private.h>
+#include <tegra_platform.h>
+#include <stdbool.h>
 
-extern uint32_t tegra186_system_powerdn_state;
+extern bool tegra_fake_system_suspend;
 
 /*******************************************************************************
- * Tegra186 SiP SMCs
+ * Tegra194 SiP SMCs
  ******************************************************************************/
-#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE			0xC2FFFE01
-#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS		0xC2FFFE02
-#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE			0xC2FFFF00
-#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO		0xC2FFFF01
-#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME		0xC2FFFF02
-#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS		0xC2FFFF03
-#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS		0xC2FFFF04
-#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED		0xC2FFFF05
-#define TEGRA_SIP_MCE_CMD_ONLINE_CORE			0xC2FFFF06
-#define TEGRA_SIP_MCE_CMD_CC3_CTRL			0xC2FFFF07
-#define TEGRA_SIP_MCE_CMD_ECHO_DATA			0xC2FFFF08
-#define TEGRA_SIP_MCE_CMD_READ_VERSIONS			0xC2FFFF09
-#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES			0xC2FFFF0A
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS	0xC2FFFF0B
-#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA			0xC2FFFF0C
-#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA		0xC2FFFF0D
-#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE		0xC2FFFF0E
-#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE		0xC2FFFF0F
-#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC			0xC2FFFF10
-#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ		0xC2FFFF11
-#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX			0xC2FFFF12
+#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND		0xC2FFFE03U
 
 /*******************************************************************************
- * This function is responsible for handling all T186 SiP calls
+ * This function is responsible for handling all T194 SiP calls
  ******************************************************************************/
-int plat_sip_handler(uint32_t smc_fid,
+int32_t plat_sip_handler(uint32_t smc_fid,
 		     uint64_t x1,
 		     uint64_t x2,
 		     uint64_t x3,
@@ -55,64 +37,27 @@
 		     void *handle,
 		     uint64_t flags)
 {
-	int mce_ret;
+	int32_t ret = -ENOTSUP;
 
-	/*
-	 * Convert SMC FID to SMC64 until the linux driver uses
-	 * SMC64 encoding.
-	 */
-	smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
+	(void)x1;
+	(void)x4;
+	(void)cookie;
+	(void)flags;
 
-	switch (smc_fid) {
-
-	/*
-	 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
-	 * 0x82FFFFFF SiP SMC space
-	 */
-	case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
-	case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
-	case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
-	case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
-	case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
-	case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
-	case TEGRA_SIP_MCE_CMD_CC3_CTRL:
-	case TEGRA_SIP_MCE_CMD_ECHO_DATA:
-	case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
-	case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
-	case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
-	case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
-	case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
-	case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
-	case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
-	case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
-	case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
-	case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
-
-		/* clean up the high bits */
-		smc_fid &= MCE_CMD_MASK;
-
-		/* execute the command and store the result */
-		mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
-		write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
-
-		return 0;
-
-	case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
-
-		/* clean up the high bits */
-		x1 = (uint32_t)x1;
-
+	if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) {
 		/*
-		 * SC8 is a special Tegra186 system state where the CPUs and
-		 * DRAM are powered down but the other subsystem is still
-		 * alive.
+		 * System suspend mode is set if the platform ATF is
+		 * running on VDK and there is a debug SIP call. This mode
+		 * ensures that the debug path is exercised, instead of
+		 * regular code path to suit the pre-silicon platform needs.
+		 * This includes replacing the call to WFI, with calls to
+		 * system suspend exit procedures.
 		 */
-
-		return 0;
-
-	default:
-		break;
+		if (tegra_platform_is_virt_dev_kit()) {
+			tegra_fake_system_suspend = true;
+			ret = 0;
+		}
 	}
 
-	return -ENOTSUP;
+	return ret;
 }
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h b/plat/nvidia/tegra/soc/t194/plat_smmu.c
similarity index 88%
rename from plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
rename to plat/nvidia/tegra/soc/t194/plat_smmu.c
index fc8669a..1696d59 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/smmu_plat_config.h
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -4,14 +4,25 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __SMMU_PLAT_CONFIG_H
-#define __SMMU_PLAT_CONFIG_H
-
-#include <mmio.h>
-#include <tegra_def.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
 #include <smmu.h>
+#include <tegra_def.h>
+#include <tegra_mc_def.h>
 
-static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
+#define BOARD_SYSTEM_FPGA_BASE		U(1)
+#define BASE_CONFIG_SMMU_DEVICES	U(2)
+#define MAX_NUM_SMMU_DEVICES		U(3)
+
+static uint32_t tegra_misc_read_32(uint32_t off)
+{
+	return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off);
+}
+
+/*******************************************************************************
+ * Array to hold SMMU context for Tegra194
+ ******************************************************************************/
+static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	_START_OF_TABLE_,
 	mc_make_sid_security_cfg(HDAR),
 	mc_make_sid_security_cfg(HOST1XDMAR),
@@ -400,29 +411,29 @@
 	_END_OF_TABLE_,
 };
 
-static inline uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
+/*******************************************************************************
+ * Handler to return the pointer to the SMMU's context struct
+ ******************************************************************************/
+smmu_regs_t *plat_get_smmu_ctx(void)
 {
-	if (smmu_id == 0)
-		return mmio_read_32(TEGRA_SMMU0_BASE + off);
-	else if (smmu_id == 1)
-		return mmio_read_32(TEGRA_SMMU1_BASE + off);
-	else if (smmu_id == 2)
-		return mmio_read_32(TEGRA_SMMU2_BASE + off);
-	else
-		panic();
+	/* index of _END_OF_TABLE_ */
+	tegra194_smmu_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_smmu_context) - 1U;
+
+	return tegra194_smmu_context;
 }
 
-static inline void tegra_smmu_write_32(uint32_t smmu_id,
-			uint32_t off, uint32_t val)
+/*******************************************************************************
+ * Handler to return the support SMMU devices number
+ ******************************************************************************/
+uint32_t plat_get_num_smmu_devices(void)
 {
-	if (smmu_id == 0)
-		mmio_write_32(TEGRA_SMMU0_BASE + off, val);
-	else if (smmu_id == 1)
-		mmio_write_32(TEGRA_SMMU1_BASE + off, val);
-	else if (smmu_id == 2)
-		mmio_write_32(TEGRA_SMMU2_BASE + off, val);
-	else
-		panic();
-}
+	uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
+	uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
+							BOARD_SHIFT_BITS) & BOARD_MASK_BITS);
 
-#endif //__SMMU_PLAT_CONFIG_H
+	if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
+		ret_num = BASE_CONFIG_SMMU_DEVICES;
+	}
+
+	return ret_num;
+}
diff --git a/plat/nvidia/tegra/soc/t194/plat_trampoline.S b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
index e3ee5e5..33c7e6f 100644
--- a/plat/nvidia/tegra/soc/t194/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t194/plat_trampoline.S
@@ -10,27 +10,36 @@
 #include <memctrl_v2.h>
 #include <tegra_def.h>
 
-#define TEGRA186_SMMU_CTX_SIZE		0x490
+#define TEGRA194_STATE_SYSTEM_SUSPEND	0x5C7
+#define TEGRA194_STATE_SYSTEM_RESUME	0x600D
+#define TEGRA194_SMMU_CTX_SIZE		0x490
 
 	.align 4
-	.globl	tegra186_cpu_reset_handler
+	.globl	tegra194_cpu_reset_handler
 
 /* CPU reset handler routine */
-func tegra186_cpu_reset_handler
-	/*
-	 * The TZRAM loses state during System Suspend. We use this
-	 * information to decide if the reset handler is running after a
-	 * System Suspend. Resume from system suspend requires restoring
-	 * the entire state from TZDRAM to TZRAM.
-	 */
-	mov	x0, #BL31_BASE
-	ldr	x0, [x0]
-	cbnz	x0, boot_cpu
+func tegra194_cpu_reset_handler
+	/* check if we are exiting system suspend state */
+	adr	x0, __tegra194_system_suspend_state
+	ldr	x1, [x0]
+	mov	x2, #TEGRA194_STATE_SYSTEM_SUSPEND
+	lsl	x2, x2, #16
+	add	x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
+	cmp	x1, x2
+	bne	boot_cpu
 
-	/* resume from system suspend */
+	/* set system resume state */
+	mov	x1, #TEGRA194_STATE_SYSTEM_RESUME
+	lsl	x1, x1, #16
+	mov	x2, #TEGRA194_STATE_SYSTEM_RESUME
+	add	x1, x1, x2
+	str	x1, [x0]
+	dsb	sy
+
+	/* prepare to relocate to TZSRAM */
 	mov	x0, #BL31_BASE
-	adr	x1, __tegra186_cpu_reset_handler_end
-	adr	x2, __tegra186_cpu_reset_handler_data
+	adr	x1, __tegra194_cpu_reset_handler_end
+	adr	x2, __tegra194_cpu_reset_handler_data
 	ldr	x2, [x2, #8]
 
 	/* memcpy16 */
@@ -50,13 +59,13 @@
 	b.ne	m_loop1
 
 boot_cpu:
-	adr	x0, __tegra186_cpu_reset_handler_data
+	adr	x0, __tegra194_cpu_reset_handler_data
 	ldr	x0, [x0]
 	br	x0
-endfunc tegra186_cpu_reset_handler
+endfunc tegra194_cpu_reset_handler
 
 	/*
-	 * Tegra186 reset data (offset 0x0 - 0x2490)
+	 * Tegra194 reset data (offset 0x0 - 0x2490)
 	 *
 	 * 0x0000: secure world's entrypoint
 	 * 0x0008: BL31 size (RO + RW)
@@ -65,19 +74,71 @@
 	 */
 
 	.align 4
-	.type	__tegra186_cpu_reset_handler_data, %object
-	.globl	__tegra186_cpu_reset_handler_data
-__tegra186_cpu_reset_handler_data:
+	.type	__tegra194_cpu_reset_handler_data, %object
+	.globl	__tegra194_cpu_reset_handler_data
+__tegra194_cpu_reset_handler_data:
 	.quad	tegra_secure_entrypoint
 	.quad	__BL31_END__ - BL31_BASE
-	.globl	__tegra186_smmu_ctx_start
-__tegra186_smmu_ctx_start:
-	.rept	TEGRA186_SMMU_CTX_SIZE
+
+	.globl	__tegra194_system_suspend_state
+__tegra194_system_suspend_state:
 	.quad	0
-	.endr
-	.size	__tegra186_cpu_reset_handler_data, \
-		. - __tegra186_cpu_reset_handler_data
 
 	.align 4
-	.globl	__tegra186_cpu_reset_handler_end
-__tegra186_cpu_reset_handler_end:
+__tegra194_smmu_context:
+	.rept	TEGRA194_SMMU_CTX_SIZE
+	.quad	0
+	.endr
+	.size	__tegra194_cpu_reset_handler_data, \
+		. - __tegra194_cpu_reset_handler_data
+
+	.align 4
+	.globl	__tegra194_cpu_reset_handler_end
+__tegra194_cpu_reset_handler_end:
+
+	.globl tegra194_get_cpu_reset_handler_size
+	.globl tegra194_get_cpu_reset_handler_base
+	.globl tegra194_get_smmu_ctx_offset
+	.globl tegra194_set_system_suspend_entry
+
+/* return size of the CPU reset handler */
+func tegra194_get_cpu_reset_handler_size
+	adr	x0, __tegra194_cpu_reset_handler_end
+	adr	x1, tegra194_cpu_reset_handler
+	sub	x0, x0, x1
+	ret
+endfunc tegra194_get_cpu_reset_handler_size
+
+/* return the start address of the CPU reset handler */
+func tegra194_get_cpu_reset_handler_base
+	adr	x0, tegra194_cpu_reset_handler
+	ret
+endfunc tegra194_get_cpu_reset_handler_base
+
+/* return the size of the SMMU context */
+func tegra194_get_smmu_ctx_offset
+	adr	x0, __tegra194_smmu_context
+	adr	x1, tegra194_cpu_reset_handler
+	sub	x0, x0, x1
+	ret
+endfunc tegra194_get_smmu_ctx_offset
+
+/* set system suspend state before SC7 entry */
+func tegra194_set_system_suspend_entry
+	mov	x0, #TEGRA_MC_BASE
+	mov	x3, #MC_SECURITY_CFG3_0
+	ldr	w1, [x0, x3]
+	lsl	x1, x1, #32
+	mov	x3, #MC_SECURITY_CFG0_0
+	ldr	w2, [x0, x3]
+	orr	x3, x1, x2			/* TZDRAM base */
+	adr	x0, __tegra194_system_suspend_state
+	adr	x1, tegra194_cpu_reset_handler
+	sub	x2, x0, x1			/* offset in TZDRAM */
+	mov	x0, #TEGRA194_STATE_SYSTEM_SUSPEND
+	lsl	x0, x0, #16
+	add	x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND
+	str	x0, [x3, x2]			/* set value in TZDRAM */
+	dsb	sy
+	ret
+endfunc tegra194_set_system_suspend_entry
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index b6bc442..5ec1af2 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -5,15 +5,12 @@
 #
 
 # platform configs
-ENABLE_AFI_DEVICE			:= 0
-$(eval $(call add_define,ENABLE_AFI_DEVICE))
+ENABLE_CONSOLE_SPE			:= 0
+$(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
 ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS	:= 0
 $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
 
-ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM	:= 1
-$(eval $(call add_define,ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM))
-
 RELOCATE_TO_BL31_BASE			:= 1
 $(eval $(call add_define,RELOCATE_TO_BL31_BASE))
 
@@ -23,9 +20,6 @@
 ENABLE_SMMU_DEVICE			:= 1
 $(eval $(call add_define,ENABLE_SMMU_DEVICE))
 
-NUM_SMMU_DEVICES			:= 3
-$(eval $(call add_define,NUM_SMMU_DEVICES))
-
 RESET_TO_BL31				:= 1
 
 PROGRAMMABLE_RESET_ADDRESS		:= 1
@@ -36,32 +30,37 @@
 TZDRAM_BASE				:= 0x40000000
 $(eval $(call add_define,TZDRAM_BASE))
 
-PLATFORM_CLUSTER_COUNT			:= 2
+PLATFORM_CLUSTER_COUNT			:= 4
 $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
 
-PLATFORM_MAX_CPUS_PER_CLUSTER		:= 4
+PLATFORM_MAX_CPUS_PER_CLUSTER		:= 2
 $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
 
-MAX_XLAT_TABLES				:= 24
+MAX_XLAT_TABLES				:= 25
 $(eval $(call add_define,MAX_XLAT_TABLES))
 
-MAX_MMAP_REGIONS			:= 24
+MAX_MMAP_REGIONS			:= 30
 $(eval $(call add_define,MAX_MMAP_REGIONS))
 
 # platform files
 PLAT_INCLUDES		+=	-I${SOC_DIR}/drivers/include
 
-BL31_SOURCES		+=	lib/cpus/aarch64/denver.S		\
+BL31_SOURCES		+=	drivers/ti/uart/aarch64/16550_console.S \
+				lib/cpus/aarch64/denver.S		\
 				${COMMON_DIR}/drivers/memctrl/memctrl_v2.c	\
 				${COMMON_DIR}/drivers/smmu/smmu.c	\
 				${SOC_DIR}/drivers/mce/mce.c		\
 				${SOC_DIR}/drivers/mce/nvg.c		\
 				${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
+				${SOC_DIR}/drivers/se/se.c		\
+				${SOC_DIR}/plat_memctrl.c		\
 				${SOC_DIR}/plat_psci_handlers.c		\
 				${SOC_DIR}/plat_setup.c			\
 				${SOC_DIR}/plat_secondary.c		\
-				${SOC_DIR}/plat_sip_calls.c
+				${SOC_DIR}/plat_sip_calls.c		\
+				${SOC_DIR}/plat_smmu.c			\
+				${SOC_DIR}/plat_trampoline.S
 
-ifeq (${ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM}, 1)
-BL31_SOURCES		+=	${SOC_DIR}/plat_trampoline.S
+ifeq (${ENABLE_CONSOLE_SPE},1)
+BL31_SOURCES		+=	${COMMON_DIR}/drivers/spe/shared_console.S
 endif
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index 2a2d102..bfa8184 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -114,14 +114,30 @@
 };
 
 /*******************************************************************************
- * Retrieve the UART controller base to be used as the console
+ * Enable console corresponding to the console ID
  ******************************************************************************/
-uint32_t plat_get_console_from_id(int id)
+void plat_enable_console(int32_t id)
 {
-	if (id > TEGRA210_MAX_UART_PORTS)
-		return 0;
+	static console_16550_t uart_console;
+	uint32_t console_clock;
 
-	return tegra210_uart_addresses[id];
+	if ((id > 0) && (id < TEGRA210_MAX_UART_PORTS)) {
+		/*
+		 * Reference clock used by the FPGAs is a lot slower.
+		 */
+		if (tegra_platform_is_fpga()) {
+			console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
+		} else {
+			console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
+		}
+
+		(void)console_16550_register(tegra210_uart_addresses[id],
+					     console_clock,
+					     TEGRA_CONSOLE_BAUDRATE,
+					     &uart_console);
+		console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
+			CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+	}
 }
 
 /*******************************************************************************
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index 8c2e5e9..b2fd201 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -6,6 +6,7 @@
 
 #include <assert.h>
 #include <errno.h>
+#include <limits.h>
 #include <string.h>
 
 #include <lib/bl_aux_params/bl_aux_params.h>
@@ -21,8 +22,8 @@
 #include <plat_params.h>
 #include <plat_private.h>
 
-static struct bl_aux_gpio_info rst_gpio;
-static struct bl_aux_gpio_info poweroff_gpio;
+static struct bl_aux_gpio_info rst_gpio = { .index = UINT_MAX } ;
+static struct bl_aux_gpio_info poweroff_gpio = { .index = UINT_MAX };
 static struct bl_aux_gpio_info suspend_gpio[10];
 uint32_t suspend_gpio_cnt;
 static struct bl_aux_rk_apio_info suspend_apio;
@@ -174,11 +175,17 @@
 
 struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
 {
+	if (rst_gpio.index == UINT_MAX)
+		return NULL;
+
 	return &rst_gpio;
 }
 
 struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void)
 {
+	if (poweroff_gpio.index == UINT_MAX)
+		return NULL;
+
 	return &poweroff_gpio;
 }
 
diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h
index 2284970..c80aef6 100644
--- a/plat/st/stm32mp1/include/boot_api.h
+++ b/plat/st/stm32mp1/include/boot_api.h
@@ -124,7 +124,7 @@
 /* Closed = OTP_CFG0[6] */
 #define BOOT_API_OTP_MODE_CLOSED_BIT_POS			6
 
-#define BOOT_API_RETURN_OK					0x66U
+#define BOOT_API_RETURN_OK					0x77U
 
 /*
  * Boot Context related definitions