tree 32a666532d4fc74fcd96a032b998258c31ee1558
parent 21803491175d6be209a5b9db7b8d27f8174cd111
author Aditya Angadi <aditya.angadi@arm.com> 1613567782 +0530
committer Thomas Abraham <thomas.abraham@arm.com> 1617034008 +0530

board/rdv1mc: initialize tzc400 controllers

A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.

For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.

Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1