Optimize EL3 register state stored in cpu_context structure
This patch further optimizes the EL3 register state stored in
cpu_context. The 2 registers which are removed from cpu_context are:
* cntfrq_el0 is the system timer register which is writable
only in EL3 and it can be programmed during cold/warm boot. Hence
it need not be saved to cpu_context.
* cptr_el3 controls access to Trace, Floating-point, and Advanced
SIMD functionality and it is programmed every time during cold
and warm boot. The current BL3-1 implementation does not need to
modify the access controls during normal execution and hence
they are expected to remain static.
Fixes ARM-software/tf-issues#197
Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
diff --git a/bl31/aarch64/context.S b/bl31/aarch64/context.S
index 79b5d19..1117026 100644
--- a/bl31/aarch64/context.S
+++ b/bl31/aarch64/context.S
@@ -35,45 +35,6 @@
/* -----------------------------------------------------
* The following function strictly follows the AArch64
* PCS to use x9-x17 (temporary caller-saved registers)
- * to save essential EL3 system register context. It
- * assumes that 'x0' is pointing to a 'el1_sys_regs'
- * structure where the register context will be saved.
- * -----------------------------------------------------
- */
- .global el3_sysregs_context_save
-func el3_sysregs_context_save
-
- mrs x10, cptr_el3
- mrs x11, cntfrq_el0
- stp x10, x11, [x0, #CTX_CPTR_EL3]
-
- ret
-
-/* -----------------------------------------------------
- * The following function strictly follows the AArch64
- * PCS to use x9-x17 (temporary caller-saved registers)
- * to restore essential EL3 system register context. It
- * assumes that 'x0' is pointing to a 'el1_sys_regs'
- * structure from where the register context will be
- * restored.
- *
- * Note that the sequence differs from that of the save
- * function as we want the MMU to be enabled last
- * -----------------------------------------------------
- */
- .global el3_sysregs_context_restore
-func el3_sysregs_context_restore
-
- ldp x13, x14, [x0, #CTX_CPTR_EL3]
- msr cptr_el3, x13
- msr cntfrq_el0, x14
- isb
-
- ret
-
-/* -----------------------------------------------------
- * The following function strictly follows the AArch64
- * PCS to use x9-x17 (temporary caller-saved registers)
* to save EL1 system register context. It assumes that
* 'x0' is pointing to a 'el1_sys_regs' structure where
* the register context will be saved.
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c
index 4502e5d..489d454 100644
--- a/bl31/context_mgmt.c
+++ b/bl31/context_mgmt.c
@@ -259,30 +259,10 @@
}
/*******************************************************************************
- * The next four functions are used by runtime services to save and restore EL3
- * and EL1 contexts on the 'cpu_context' structure for the specified security
+ * The next four functions are used by runtime services to save and restore
+ * EL1 context on the 'cpu_context' structure for the specified security
* state.
******************************************************************************/
-void cm_el3_sysregs_context_save(uint32_t security_state)
-{
- cpu_context_t *ctx;
-
- ctx = cm_get_context(security_state);
- assert(ctx);
-
- el3_sysregs_context_save(get_el3state_ctx(ctx));
-}
-
-void cm_el3_sysregs_context_restore(uint32_t security_state)
-{
- cpu_context_t *ctx;
-
- ctx = cm_get_context(security_state);
- assert(ctx);
-
- el3_sysregs_context_restore(get_el3state_ctx(ctx));
-}
-
void cm_el1_sysregs_context_save(uint32_t security_state)
{
cpu_context_t *ctx;