diff --git a/.gitignore b/.gitignore index ac9a11d..e07d997 100644 --- a/.gitignore +++ b/.gitignore
@@ -22,6 +22,7 @@ tools/renesas/rzg_layout_create/*.elf tools/fiptool/fiptool tools/fiptool/fiptool.exe +tools/memory/memory/__pycache__/ tools/cert_create/src/*.o tools/cert_create/src/**/*.o tools/cert_create/cert_create
diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 6207066..7b6a1f5 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml
@@ -15,6 +15,7 @@ python: "3.10" apt_packages: - plantuml + - librsvg2-bin jobs: post_create_environment: - pip install poetry=="1.3.2" @@ -24,3 +25,8 @@ sphinx: configuration: docs/conf.py + +# Auxiliary formats to export to (in addition to the default HTML output). +formats: + - pdf +
diff --git a/.versionrc.js b/.versionrc.js index 9e54c7b..c7ee4a2 100644 --- a/.versionrc.js +++ b/.versionrc.js
@@ -94,7 +94,6 @@ return contents.replace(/^(version\s=\s")((\d).?)*$/m, _ver) } - }, }, { @@ -102,6 +101,25 @@ "type": "json" }, { + "filename": "docs/conf.py", + "updater": { + "readVersion": function (contents) { + const _ver = contents.match(/version\s=.*"(\d)\.(\d)\.(\d)/); + + return `${_ver[1]}.${_ver[2]}.${_ver[2]}`; + }, + + "writeVersion": function (contents, version) { + const _ver = 'version = "' + version + '"' + const _rel = 'release = "' + version + '"' + + contents = contents.replace(/^(version\s=\s")((\d).?)*$/m, _ver) + contents = contents.replace(/^(release\s=\s")((\d).?)*$/m, _rel) + return contents + } + }, + }, + { "filename": "tools/conventional-changelog-tf-a/package.json", "type": "json" }, @@ -111,16 +129,19 @@ "readVersion": function (contents) { const major = contents.match(/^VERSION_MAJOR\s*:=\s*(\d+?)$/m)[1]; const minor = contents.match(/^VERSION_MINOR\s*:=\s*(\d+?)$/m)[1]; + const patch = contents.match(/^VERSION_PATCH\s*:=\s*(\d+?)$/m)[1]; - return `${major}.${minor}.0`; + return `${major}.${minor}.${patch}`; }, "writeVersion": function (contents, version) { const major = version.split(".")[0]; const minor = version.split(".")[1]; + const patch = version.split(".")[2]; contents = contents.replace(/^(VERSION_MAJOR\s*:=\s*)(\d+?)$/m, `$1${major}`); contents = contents.replace(/^(VERSION_MINOR\s*:=\s*)(\d+?)$/m, `$1${minor}`); + contents = contents.replace(/^(VERSION_PATCH\s*:=\s*)(\d+?)$/m, `$1${patch}`); return contents; }
diff --git a/Makefile b/Makefile index 2c5748f..97c3c15 100644 --- a/Makefile +++ b/Makefile
@@ -8,8 +8,9 @@ # Trusted Firmware Version # VERSION_MAJOR := 2 -VERSION_MINOR := 9 -VERSION := ${VERSION_MAJOR}.${VERSION_MINOR} +VERSION_MINOR := 10 +VERSION_PATCH := 0 # Only used for LTS releases +VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH} # Default goal is build all images .DEFAULT_GOAL := all @@ -40,10 +41,6 @@ CHECKCODE_ARGS := --no-patch # Do not check the coding style on imported library files or documentation files -INC_ARM_DIRS_TO_CHECK := $(sort $(filter-out \ - include/drivers/arm/cryptocell, \ - $(wildcard include/drivers/arm/*))) -INC_ARM_DIRS_TO_CHECK += include/drivers/arm/cryptocell/*.h INC_DRV_DIRS_TO_CHECK := $(sort $(filter-out \ include/drivers/arm, \ $(wildcard include/drivers/*))) @@ -74,114 +71,27 @@ ${INC_DRV_DIRS_TO_CHECK} \ ${INC_ARM_DIRS_TO_CHECK} - ################################################################################ # Process build options ################################################################################ # Verbose flag ifeq (${V},0) - Q:=@ - ECHO:=@echo - CHECKCODE_ARGS += --no-summary --terse + Q:=@ + ECHO:=@echo + CHECKCODE_ARGS += --no-summary --terse else - Q:= - ECHO:=$(ECHO_QUIET) + Q:= + ECHO:=$(ECHO_QUIET) endif ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),) - Q:=@ - ECHO:=$(ECHO_QUIET) + Q:=@ + ECHO:=$(ECHO_QUIET) endif export Q ECHO -# The cert_create tool cannot generate certificates individually, so we use the -# target 'certificates' to create them all -ifneq (${GENERATE_COT},0) - FIP_DEPS += certificates - FWU_FIP_DEPS += fwu_certificates -endif - -# Process BRANCH_PROTECTION value and set -# Pointer Authentication and Branch Target Identification flags -ifeq (${BRANCH_PROTECTION},0) - # Default value turns off all types of branch protection - BP_OPTION := none -else ifneq (${ARCH},aarch64) - $(error BRANCH_PROTECTION requires AArch64) -else ifeq (${BRANCH_PROTECTION},1) - # Enables all types of branch protection features - BP_OPTION := standard - ENABLE_BTI := 1 - ENABLE_PAUTH := 1 -else ifeq (${BRANCH_PROTECTION},2) - # Return address signing to its standard level - BP_OPTION := pac-ret - ENABLE_PAUTH := 1 -else ifeq (${BRANCH_PROTECTION},3) - # Extend the signing to include leaf functions - BP_OPTION := pac-ret+leaf - ENABLE_PAUTH := 1 -else ifeq (${BRANCH_PROTECTION},4) - # Turn on branch target identification mechanism - BP_OPTION := bti - ENABLE_BTI := 1 -else - $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION}) -endif - -# FEAT_RME -ifeq (${ENABLE_RME},1) -# RME doesn't support PIE -ifneq (${ENABLE_PIE},0) - $(error ENABLE_RME does not support PIE) -endif -# RME doesn't support BRBE -ifneq (${ENABLE_BRBE_FOR_NS},0) - $(error ENABLE_RME does not support BRBE.) -endif -# RME requires AARCH64 -ifneq (${ARCH},aarch64) - $(error ENABLE_RME requires AArch64) -endif -# RME requires el2 context to be saved for now. -CTX_INCLUDE_EL2_REGS := 1 -CTX_INCLUDE_AARCH32_REGS := 0 -ARM_ARCH_MAJOR := 8 -ARM_ARCH_MINOR := 5 -ENABLE_FEAT_ECV = 1 -ENABLE_FEAT_FGT = 1 - -# RME enables CSV2_2 extension by default. -ENABLE_FEAT_CSV2_2 = 1 - -endif - -# USE_SPINLOCK_CAS requires AArch64 build -ifeq (${USE_SPINLOCK_CAS},1) -ifneq (${ARCH},aarch64) - $(error USE_SPINLOCK_CAS requires AArch64) -endif -endif - -# USE_DEBUGFS experimental feature recommended only in debug builds -ifeq (${USE_DEBUGFS},1) -ifeq (${DEBUG},1) - $(warning DEBUGFS experimental feature is enabled.) -else - $(warning DEBUGFS experimental, recommended in DEBUG builds ONLY) -endif -endif - -ifneq (${DECRYPTION_SUPPORT},none) -ENC_ARGS += -f ${FW_ENC_STATUS} -ENC_ARGS += -k ${ENC_KEY} -ENC_ARGS += -n ${ENC_NONCE} -FIP_DEPS += enctool -FWU_FIP_DEPS += enctool -endif - ################################################################################ # Toolchain ################################################################################ @@ -206,83 +116,69 @@ LINKER := ${LINKER}.bfd endif +################################################################################ +# Auxiliary tools (fiptool, cert_create, etc) +################################################################################ + +# Variables for use with Certificate Generation Tool +CRTTOOLPATH ?= tools/cert_create +CRTTOOL ?= ${CRTTOOLPATH}/cert_create${BIN_EXT} + +# Variables for use with Firmware Encryption Tool +ENCTOOLPATH ?= tools/encrypt_fw +ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT} + +# Variables for use with Firmware Image Package +FIPTOOLPATH ?= tools/fiptool +FIPTOOL ?= ${FIPTOOLPATH}/fiptool${BIN_EXT} + +# Variables for use with sptool +SPTOOLPATH ?= tools/sptool +SPTOOL ?= ${SPTOOLPATH}/sptool.py +SP_MK_GEN ?= ${SPTOOLPATH}/sp_mk_generator.py +SP_DTS_LIST_FRAGMENT ?= ${BUILD_PLAT}/sp_list_fragment.dts + +# Variables for use with ROMLIB +ROMLIBPATH ?= lib/romlib + +# Variable for use with Python +PYTHON ?= python3 + +# Variables for use with documentation build using Sphinx tool +DOCS_PATH ?= docs + +################################################################################ +# Compiler Configuration based on ARCH_MAJOR and ARCH_MINOR flags +################################################################################ ifeq (${ARM_ARCH_MAJOR},7) -target32-directive = -target arm-none-eabi -# Will set march32-directive from platform configuration + target32-directive = -target arm-none-eabi +# Will set march-directive from platform configuration else -target32-directive = -target armv8a-none-eabi + target32-directive = -target armv8a-none-eabi +endif #(ARM_ARCH_MAJOR) -# Set the compiler's target architecture profile based on -# ARM_ARCH_MAJOR ARM_ARCH_MINOR options -ifeq (${ARM_ARCH_MINOR},0) -march32-directive = -march=armv${ARM_ARCH_MAJOR}-a -march64-directive = -march=armv${ARM_ARCH_MAJOR}-a -else -march32-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a -march64-directive = -march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a -endif -endif - -# Memory tagging is supported in architecture Armv8.5-A AArch64 and onwards -ifeq ($(ARCH), aarch64) -# Check if revision is greater than or equal to 8.5 -ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -mem_tag_arch_support = yes -endif -endif - -# Get architecture feature modifiers +################################################################################ +# Get Architecture Feature Modifiers +################################################################################ arch-features = ${ARM_ARCH_FEATURE} -# Enable required options for memory stack tagging. -# Currently, these options are enabled only for clang and armclang compiler. -ifeq (${SUPPORT_STACK_MEMTAG},yes) -ifdef mem_tag_arch_support -# Check for armclang and clang compilers -ifneq ( ,$(filter $(notdir $(CC)),armclang clang)) -# Add "memtag" architecture feature modifier if not specified -ifeq ( ,$(findstring memtag,$(arch-features))) -arch-features := $(arch-features)+memtag -endif # memtag -ifeq ($(notdir $(CC)),armclang) -TF_CFLAGS += -mmemtag-stack -else ifeq ($(notdir $(CC)),clang) -TF_CFLAGS += -fsanitize=memtag -endif # armclang -endif # armclang clang -else -$(error "Error: stack memory tagging is not supported for architecture \ - ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a") -endif # mem_tag_arch_support -endif # SUPPORT_STACK_MEMTAG - # Set the compiler's architecture feature modifiers ifneq ($(arch-features), none) -# Strip "none+" from arch-features -arch-features := $(subst none+,,$(arch-features)) -ifeq ($(ARCH), aarch32) -march32-directive := $(march32-directive)+$(arch-features) -else -march64-directive := $(march64-directive)+$(arch-features) -endif + # Strip "none+" from arch-features + arch-features := $(subst none+,,$(arch-features)) + march-directive := $(march-directive)+$(arch-features) # Print features -$(info Arm Architecture Features specified: $(subst +, ,$(arch-features))) -endif # arch-features - -# Determine if FEAT_RNG is supported -ENABLE_FEAT_RNG = $(if $(findstring rng,${arch-features}),1,0) - -# Determine if FEAT_SB is supported -ENABLE_FEAT_SB = $(if $(findstring sb,${arch-features}),1,0) + $(info Arm Architecture Features specified: $(subst +, ,$(arch-features))) +endif #(arch-features) ifneq ($(findstring clang,$(notdir $(CC))),) ifneq ($(findstring armclang,$(notdir $(CC))),) - TF_CFLAGS_aarch32 := -target arm-arm-none-eabi $(march32-directive) - TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi $(march64-directive) + TF_CFLAGS_aarch32 := -target arm-arm-none-eabi + TF_CFLAGS_aarch64 := -target aarch64-arm-none-eabi LD := $(LINKER) else - TF_CFLAGS_aarch32 = $(target32-directive) $(march32-directive) - TF_CFLAGS_aarch64 := -target aarch64-elf $(march64-directive) + TF_CFLAGS_aarch32 = $(target32-directive) + TF_CFLAGS_aarch64 := -target aarch64-elf LD := $(shell $(CC) --print-prog-name ld.lld) AR := $(shell $(CC) --print-prog-name llvm-ar) @@ -294,62 +190,56 @@ PP := $(CC) -E $(TF_CFLAGS_$(ARCH)) AS := $(CC) -c -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) else ifneq ($(findstring gcc,$(notdir $(CC))),) -TF_CFLAGS_aarch32 = $(march32-directive) -TF_CFLAGS_aarch64 = $(march64-directive) -ifeq ($(ENABLE_LTO),1) - # Enable LTO only for aarch64 - ifeq (${ARCH},aarch64) - LTO_CFLAGS = -flto - # Use gcc as a wrapper for the ld, recommended for LTO - LINKER := ${CROSS_COMPILE}gcc + ifeq ($(ENABLE_LTO),1) + # Enable LTO only for aarch64 + ifeq (${ARCH},aarch64) + LTO_CFLAGS = -flto + # Use gcc as a wrapper for the ld, recommended for LTO + LINKER := ${CROSS_COMPILE}gcc + endif endif -endif -LD = $(LINKER) + LD = $(LINKER) else -TF_CFLAGS_aarch32 = $(march32-directive) -TF_CFLAGS_aarch64 = $(march64-directive) -LD = $(LINKER) -endif + LD = $(LINKER) +endif #(clang) # Process Debug flag $(eval $(call add_define,DEBUG)) ifneq (${DEBUG}, 0) - BUILD_TYPE := debug - TF_CFLAGS += -g -gdwarf-4 - ASFLAGS += -g -Wa,-gdwarf-4 + BUILD_TYPE := debug + TF_CFLAGS += -g -gdwarf-4 + ASFLAGS += -g -Wa,-gdwarf-4 - # Use LOG_LEVEL_INFO by default for debug builds - LOG_LEVEL := 40 + # Use LOG_LEVEL_INFO by default for debug builds + LOG_LEVEL := 40 else - BUILD_TYPE := release - # Use LOG_LEVEL_NOTICE by default for release builds - LOG_LEVEL := 20 -endif + BUILD_TYPE := release + # Use LOG_LEVEL_NOTICE by default for release builds + LOG_LEVEL := 20 +endif #(Debug) # Default build string (git branch and commit) ifeq (${BUILD_STRING},) - BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null) + BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null) endif VERSION_STRING := v${VERSION}(${BUILD_TYPE}):${BUILD_STRING} ifeq (${AARCH32_INSTRUCTION_SET},A32) -TF_CFLAGS_aarch32 += -marm + TF_CFLAGS_aarch32 += -marm else ifeq (${AARCH32_INSTRUCTION_SET},T32) -TF_CFLAGS_aarch32 += -mthumb + TF_CFLAGS_aarch32 += -mthumb else -$(error Error: Unknown AArch32 instruction set ${AARCH32_INSTRUCTION_SET}) -endif + $(error Error: Unknown AArch32 instruction set ${AARCH32_INSTRUCTION_SET}) +endif #(AARCH32_INSTRUCTION_SET) TF_CFLAGS_aarch32 += -mno-unaligned-access TF_CFLAGS_aarch64 += -mgeneral-regs-only -mstrict-align -ifneq (${BP_OPTION},none) -TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION} -endif +ASFLAGS += $(march-directive) -ASFLAGS_aarch32 = $(march32-directive) -ASFLAGS_aarch64 = $(march64-directive) - +############################################################################## +# WARNINGS Configuration +############################################################################### # General warnings WARNINGS := -Wall -Wmissing-include-dirs -Wunused \ -Wdisabled-optimization -Wvla -Wshadow \ @@ -395,18 +285,18 @@ # outside of the contributor's control. Don't fail the build on them so warnings # can be seen and hopefully addressed ifdef W -ifneq (${W},0) -E ?= 0 -endif + ifneq (${W},0) + E ?= 0 + endif endif ifeq (${W},1) -WARNINGS += $(WARNING1) + WARNINGS += $(WARNING1) else ifeq (${W},2) -WARNINGS += $(WARNING1) $(WARNING2) + WARNINGS += $(WARNING1) $(WARNING2) else ifeq (${W},3) -WARNINGS += $(WARNING1) $(WARNING2) $(WARNING3) -endif + WARNINGS += $(WARNING1) $(WARNING2) $(WARNING3) +endif #(W) # Compiler specific warnings ifeq ($(findstring clang,$(notdir $(CC))),) @@ -422,30 +312,32 @@ # using clang WARNINGS += -Wshift-overflow -Wshift-sign-overflow \ -Wlogical-op-parentheses -endif +endif #(Clang Warning) ifneq (${E},0) -ERRORS := -Werror -endif + ERRORS := -Werror +endif #(E) +################################################################################ +# Compiler and Linker Directives +################################################################################ CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ $(ERRORS) $(WARNINGS) -ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ +ASFLAGS += $(CPPFLAGS) \ -ffreestanding -Wa,--fatal-warnings TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ -ffunction-sections -fdata-sections \ -ffreestanding -fno-builtin -fno-common \ -Os -std=gnu99 -$(eval $(call add_define,SVE_VECTOR_LEN)) - ifeq (${SANITIZE_UB},on) -TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover -endif + TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover +endif #(${SANITIZE_UB},on) + ifeq (${SANITIZE_UB},trap) -TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover \ + TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover \ -fsanitize-undefined-trap-on-error -endif +endif #(${SANITIZE_UB},trap) GCC_V_OUTPUT := $(shell $(CC) -v 2>&1) @@ -453,60 +345,67 @@ # LD = armlink ifneq ($(findstring armlink,$(notdir $(LD))),) -TF_LDFLAGS += --diag_error=warning --lto_level=O1 -TF_LDFLAGS += --remove --info=unused,unusedsymbols -TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) + TF_LDFLAGS += --diag_error=warning --lto_level=O1 + TF_LDFLAGS += --remove --info=unused,unusedsymbols + TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) # LD = gcc (used when GCC LTO is enabled) else ifneq ($(findstring gcc,$(notdir $(LD))),) -# Pass ld options with Wl or Xlinker switches -TF_LDFLAGS += -Wl,--fatal-warnings -O1 -TF_LDFLAGS += -Wl,--gc-sections + # Pass ld options with Wl or Xlinker switches + TF_LDFLAGS += -Wl,--fatal-warnings -O1 + TF_LDFLAGS += -Wl,--gc-sections -TF_LDFLAGS += -Wl,-z,common-page-size=4096 # Configure page size constants -TF_LDFLAGS += -Wl,-z,max-page-size=4096 + TF_LDFLAGS += -Wl,-z,common-page-size=4096 #Configure page size constants + TF_LDFLAGS += -Wl,-z,max-page-size=4096 -ifeq ($(ENABLE_LTO),1) - ifeq (${ARCH},aarch64) - TF_LDFLAGS += -flto -fuse-linker-plugin - endif -endif + ifeq ($(ENABLE_LTO),1) + ifeq (${ARCH},aarch64) + TF_LDFLAGS += -flto -fuse-linker-plugin + endif + endif #(ENABLE_LTO) + # GCC automatically adds fix-cortex-a53-843419 flag when used to link # which breaks some builds, so disable if errata fix is not explicitly enabled -ifneq (${ERRATA_A53_843419},1) - TF_LDFLAGS += -mno-fix-cortex-a53-843419 -endif -TF_LDFLAGS += -nostdlib -TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) + ifeq (${ARCH},aarch64) + ifneq (${ERRATA_A53_843419},1) + TF_LDFLAGS += -mno-fix-cortex-a53-843419 + endif + endif + TF_LDFLAGS += -nostdlib + TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) # LD = gcc-ld (ld) or llvm-ld (ld.lld) or other else # With ld.bfd version 2.39 and newer new warnings are added. Skip those since we # are not loaded by a elf loader. -TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments) -TF_LDFLAGS += -O1 -TF_LDFLAGS += --gc-sections + TF_LDFLAGS += $(call ld_option, --no-warn-rwx-segments) + TF_LDFLAGS += -O1 + TF_LDFLAGS += --gc-sections -TF_LDFLAGS += -z common-page-size=4096 # Configure page size constants -TF_LDFLAGS += -z max-page-size=4096 + TF_LDFLAGS += -z common-page-size=4096 # Configure page size constants + TF_LDFLAGS += -z max-page-size=4096 # ld.lld doesn't recognize the errata flags, # therefore don't add those in that case. # ld.lld reports section type mismatch warnings, # therefore don't add --fatal-warnings to it. -ifeq ($(findstring ld.lld,$(notdir $(LD))),) -TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) --fatal-warnings -endif -endif + ifeq ($(findstring ld.lld,$(notdir $(LD))),) + TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) --fatal-warnings + endif -DTC_FLAGS += -I dts -O dtb -DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef \ - -x assembler-with-cpp $(DEFINES) +endif #(LD = armlink) + +################################################################################ +# Setup ARCH_MAJOR/MINOR before parsing arch_features. +################################################################################ +ifeq (${ENABLE_RME},1) + ARM_ARCH_MAJOR := 8 + ARM_ARCH_MINOR := 6 +endif ################################################################################ # Common sources and include directories ################################################################################ -include ${MAKE_HELPERS_DIRECTORY}arch_features.mk include lib/compiler-rt/compiler-rt.mk BL_COMMON_SOURCES += common/bl_common.c \ @@ -515,25 +414,19 @@ drivers/console/multi_console.c \ lib/${ARCH}/cache_helpers.S \ lib/${ARCH}/misc_helpers.S \ + lib/extensions/pmuv3/${ARCH}/pmuv3.c \ plat/common/plat_bl_common.c \ plat/common/plat_log_common.c \ plat/common/${ARCH}/plat_common.c \ plat/common/${ARCH}/platform_helpers.S \ ${COMPILER_RT_SRCS} -# Pointer Authentication sources -ifeq (${ENABLE_PAUTH}, 1) -# arm/common/aarch64/arm_pauth.c contains a sample platform hook to complete the -# Pauth support. As it's not secure, it must be reimplemented for real platforms -BL_COMMON_SOURCES += lib/extensions/pauth/pauth_helpers.S -endif - ifeq ($(notdir $(CC)),armclang) -BL_COMMON_SOURCES += lib/${ARCH}/armclang_printf.S + BL_COMMON_SOURCES += lib/${ARCH}/armclang_printf.S endif ifeq (${SANITIZE_UB},on) -BL_COMMON_SOURCES += plat/common/ubsan.c + BL_COMMON_SOURCES += plat/common/ubsan.c endif INCLUDES += -Iinclude \ @@ -543,12 +436,15 @@ ${PLAT_INCLUDES} \ ${SPD_INCLUDES} +DTC_FLAGS += -I dts -O dtb +DTC_CPPFLAGS += -P -nostdinc $(INCLUDES) -Ifdts -undef \ + -x assembler-with-cpp $(DEFINES) + include common/backtrace/backtrace.mk ################################################################################ # Generic definitions ################################################################################ - include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk ifeq (${BUILD_BASE},) @@ -561,102 +457,237 @@ # Platforms providing their own TBB makefile may override this value INCLUDE_TBBR_MK := 1 - ################################################################################ # Include SPD Makefile if one has been specified ################################################################################ ifneq (${SPD},none) - ifeq (${ARCH},aarch32) - $(error "Error: SPD is incompatible with AArch32.") - endif + ifeq (${ARCH},aarch32) + $(error "Error: SPD is incompatible with AArch32.") + endif - ifdef EL3_PAYLOAD_BASE - $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.") - $(warning "The SPD and its BL32 companion will be present but ignored.") - endif + ifdef EL3_PAYLOAD_BASE + $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.") + $(warning "The SPD and its BL32 companion will be present but \ + ignored.") + endif - ifeq (${SPD},spmd) - # SPMD is located in std_svc directory - SPD_DIR := std_svc + ifeq (${SPD},spmd) + # SPMD is located in std_svc directory + SPD_DIR := std_svc - ifeq ($(SPMD_SPM_AT_SEL2),1) - CTX_INCLUDE_EL2_REGS := 1 - ifeq ($(SPMC_AT_EL3),1) - $(error SPM cannot be enabled in both S-EL2 and EL3.) - endif - endif + ifeq ($(SPMD_SPM_AT_SEL2),1) + CTX_INCLUDE_EL2_REGS := 1 + ifeq ($(SPMC_AT_EL3),1) + $(error SPM cannot be enabled in both S-EL2 and EL3.) + endif + endif - ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp) - DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG - endif + ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp) + DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG + endif - ifeq ($(TS_SP_FW_CONFIG),1) - DTC_CPPFLAGS += -DTS_SP_FW_CONFIG - endif + ifeq ($(TS_SP_FW_CONFIG),1) + DTC_CPPFLAGS += -DTS_SP_FW_CONFIG + endif - ifneq ($(ARM_BL2_SP_LIST_DTS),) - DTC_CPPFLAGS += -DARM_BL2_SP_LIST_DTS=$(ARM_BL2_SP_LIST_DTS) - endif + ifneq ($(ARM_BL2_SP_LIST_DTS),) + DTC_CPPFLAGS += -DARM_BL2_SP_LIST_DTS=$(ARM_BL2_SP_LIST_DTS) + endif - ifneq ($(SP_LAYOUT_FILE),) - BL2_ENABLE_SP_LOAD := 1 - endif - else - # All other SPDs in spd directory - SPD_DIR := spd - endif + ifneq ($(SP_LAYOUT_FILE),) + BL2_ENABLE_SP_LOAD := 1 + endif - # We expect to locate an spd.mk under the specified SPD directory - SPD_MAKE := $(wildcard services/${SPD_DIR}/${SPD}/${SPD}.mk) + ifeq ($(SPMC_AT_EL3_SEL0_SP),1) + ifneq ($(SPMC_AT_EL3),1) + $(error SEL0 SP cannot be enabled without SPMC at EL3) + endif + endif + else + # All other SPDs in spd directory + SPD_DIR := spd + endif #(SPD) - ifeq (${SPD_MAKE},) - $(error Error: No services/${SPD_DIR}/${SPD}/${SPD}.mk located) - endif - $(info Including ${SPD_MAKE}) - include ${SPD_MAKE} + # We expect to locate an spd.mk under the specified SPD directory + SPD_MAKE := $(wildcard services/${SPD_DIR}/${SPD}/${SPD}.mk) - # If there's BL32 companion for the chosen SPD, we expect that the SPD's - # Makefile would set NEED_BL32 to "yes". In this case, the build system - # supports two mutually exclusive options: - # * BL32 is built from source: then BL32_SOURCES must contain the list - # of source files to build BL32 - # * BL32 is a prebuilt binary: then BL32 must point to the image file - # that will be included in the FIP - # If both BL32_SOURCES and BL32 are defined, the binary takes precedence - # over the sources. -endif + ifeq (${SPD_MAKE},) + $(error Error: No services/${SPD_DIR}/${SPD}/${SPD}.mk located) + endif + $(info Including ${SPD_MAKE}) + include ${SPD_MAKE} -ifeq (${CTX_INCLUDE_EL2_REGS}, 1) -ifeq (${SPD},none) -ifeq (${ENABLE_RME},0) - $(error CTX_INCLUDE_EL2_REGS is available only when SPD or RME is enabled) -endif -endif -endif + # If there's BL32 companion for the chosen SPD, we expect that the SPD's + # Makefile would set NEED_BL32 to "yes". In this case, the build system + # supports two mutually exclusive options: + # * BL32 is built from source: then BL32_SOURCES must contain the list + # of source files to build BL32 + # * BL32 is a prebuilt binary: then BL32 must point to the image file + # that will be included in the FIP + # If both BL32_SOURCES and BL32 are defined, the binary takes precedence + # over the sources. +endif #(SPD=none) -################################################################################ -# Include rmmd Makefile if RME is enabled -################################################################################ - -ifneq (${ENABLE_RME},0) -ifneq (${ARCH},aarch64) - $(error ENABLE_RME requires AArch64) +ifeq (${ENABLE_SPMD_LP}, 1) +ifneq (${SPD},spmd) + $(error Error: ENABLE_SPMD_LP requires SPD=spmd.) endif ifeq ($(SPMC_AT_EL3),1) - $(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.) + $(error SPMC at EL3 not supported when enabling SPMD Logical partitions.) endif -include services/std_svc/rmmd/rmmd.mk -$(warning "RME is an experimental feature") +endif + +################################################################################ +# Process BRANCH_PROTECTION value and set +# Pointer Authentication and Branch Target Identification flags +################################################################################ +ifeq (${BRANCH_PROTECTION},0) + # Default value turns off all types of branch protection + BP_OPTION := none +else ifneq (${ARCH},aarch64) + $(error BRANCH_PROTECTION requires AArch64) +else ifeq (${BRANCH_PROTECTION},1) + # Enables all types of branch protection features + BP_OPTION := standard + ENABLE_BTI := 1 + ENABLE_PAUTH := 1 +else ifeq (${BRANCH_PROTECTION},2) + # Return address signing to its standard level + BP_OPTION := pac-ret + ENABLE_PAUTH := 1 +else ifeq (${BRANCH_PROTECTION},3) + # Extend the signing to include leaf functions + BP_OPTION := pac-ret+leaf + ENABLE_PAUTH := 1 +else ifeq (${BRANCH_PROTECTION},4) + # Turn on branch target identification mechanism + BP_OPTION := bti + ENABLE_BTI := 1 +else + $(error Unknown BRANCH_PROTECTION value ${BRANCH_PROTECTION}) +endif #(BRANCH_PROTECTION) + +ifeq ($(ENABLE_PAUTH),1) + CTX_INCLUDE_PAUTH_REGS := 1 +endif +ifneq (${BP_OPTION},none) + TF_CFLAGS_aarch64 += -mbranch-protection=${BP_OPTION} +endif #(BP_OPTION) + +# Pointer Authentication sources +ifeq (${ENABLE_PAUTH}, 1) +# arm/common/aarch64/arm_pauth.c contains a sample platform hook to complete the +# Pauth support. As it's not secure, it must be reimplemented for real platforms + BL_COMMON_SOURCES += lib/extensions/pauth/pauth_helpers.S endif ################################################################################ # Include the platform specific Makefile after the SPD Makefile (the platform # makefile may use all previous definitions in this file) ################################################################################ - include ${PLAT_MAKEFILE_FULL} +################################################################################ +# Setup arch_features based on ARM_ARCH_MAJOR, ARM_ARCH_MINOR provided from +# platform. +################################################################################ +include ${MAKE_HELPERS_DIRECTORY}arch_features.mk + +#################################################### +# Enable required options for Memory Stack Tagging. +#################################################### + +# Currently, these options are enabled only for clang and armclang compiler. +ifeq (${SUPPORT_STACK_MEMTAG},yes) + ifdef mem_tag_arch_support + # Check for armclang and clang compilers + ifneq ( ,$(filter $(notdir $(CC)),armclang clang)) + # Add "memtag" architecture feature modifier if not specified + ifeq ( ,$(findstring memtag,$(arch-features))) + arch-features := $(arch-features)+memtag + endif # memtag + ifeq ($(notdir $(CC)),armclang) + TF_CFLAGS += -mmemtag-stack + else ifeq ($(notdir $(CC)),clang) + TF_CFLAGS += -fsanitize=memtag + endif # armclang + endif + else + $(error "Error: stack memory tagging is not supported for \ + architecture ${ARCH},armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a") + endif #(mem_tag_arch_support) +endif #(SUPPORT_STACK_MEMTAG) + +################################################################################ +# RME dependent flags configuration, Enable optional features for RME. +################################################################################ +# FEAT_RME +ifeq (${ENABLE_RME},1) + # RME doesn't support BRBE + ENABLE_BRBE_FOR_NS := 0 + + # RME doesn't support PIE + ifneq (${ENABLE_PIE},0) + $(error ENABLE_RME does not support PIE) + endif + + # RME doesn't support BRBE + ifneq (${ENABLE_BRBE_FOR_NS},0) + $(error ENABLE_RME does not support BRBE.) + endif + + # RME requires AARCH64 + ifneq (${ARCH},aarch64) + $(error ENABLE_RME requires AArch64) + endif + + # RME requires el2 context to be saved for now. + CTX_INCLUDE_EL2_REGS := 1 + CTX_INCLUDE_AARCH32_REGS := 0 + CTX_INCLUDE_PAUTH_REGS := 1 + + # RME enables CSV2_2 extension by default. + ENABLE_FEAT_CSV2_2 = 1 +endif #(FEAT_RME) + +################################################################################ +# Include rmmd Makefile if RME is enabled +################################################################################ +ifneq (${ENABLE_RME},0) + ifneq (${ARCH},aarch64) + $(error ENABLE_RME requires AArch64) + endif + ifeq ($(SPMC_AT_EL3),1) + $(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.) + endif + + ifneq (${SPD}, none) + ifneq (${SPD}, spmd) + $(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd) + endif + endif +include services/std_svc/rmmd/rmmd.mk +$(warning "RME is an experimental feature") +endif + +ifeq (${CTX_INCLUDE_EL2_REGS}, 1) + ifeq (${SPD},none) + ifeq (${ENABLE_RME},0) + $(error CTX_INCLUDE_EL2_REGS is available only when SPD \ + or RME is enabled) + endif + endif +endif + +################################################################################ +# Platform specific Makefile might provide us ARCH_MAJOR/MINOR use that to come +# up with appropriate march values for compiler. +################################################################################ +include ${MAKE_HELPERS_DIRECTORY}march.mk + +TF_CFLAGS += $(march-directive) + # This internal flag is common option which is set to 1 for scenarios # when the BL2 is running in EL3 level. This occurs in two scenarios - # 4 world system running BL2 at EL3 and two world system without BL1 running @@ -664,15 +695,24 @@ ifeq (${RESET_TO_BL2},1) BL2_RUNS_AT_EL3 := 1 - ifeq (${ENABLE_RME},1) - $(error RESET_TO_BL2=1 and ENABLE_RME=1 configuration is not supported at the moment.) - endif + ifeq (${ENABLE_RME},1) + $(error RESET_TO_BL2=1 and ENABLE_RME=1 configuration is not \ + supported at the moment.) + endif else ifeq (${ENABLE_RME},1) BL2_RUNS_AT_EL3 := 1 else BL2_RUNS_AT_EL3 := 0 endif +# This internal flag is set to 1 when Firmware First handling of External aborts +# is required by lowe ELs. Currently only NS requires this support. +ifeq ($(HANDLE_EA_EL3_FIRST_NS),1) + FFH_SUPPORT := 1 +else + FFH_SUPPORT := 0 +endif + $(eval $(call MAKE_PREREQ_DIR,${BUILD_PLAT})) ifeq (${ARM_ARCH_MAJOR},7) @@ -685,7 +725,7 @@ ifneq ($(findstring gcc,$(notdir $(LD))),) TF_LDFLAGS += -no-pie endif -endif +endif #(PIE_FOUND) ifneq ($(findstring gcc,$(notdir $(LD))),) PIE_LDFLAGS += -Wl,-pie -Wl,--no-dynamic-linker @@ -694,13 +734,13 @@ endif ifeq ($(ENABLE_PIE),1) -ifeq ($(RESET_TO_BL2),1) -ifneq ($(BL2_IN_XIP_MEM),1) - BL2_CPPFLAGS += -fpie - BL2_CFLAGS += -fpie - BL2_LDFLAGS += $(PIE_LDFLAGS) -endif -endif + ifeq ($(RESET_TO_BL2),1) + ifneq ($(BL2_IN_XIP_MEM),1) + BL2_CPPFLAGS += -fpie + BL2_CFLAGS += -fpie + BL2_LDFLAGS += $(PIE_LDFLAGS) + endif #(BL2_IN_XIP_MEM) + endif #(RESET_TO_BL2) BL31_CPPFLAGS += -fpie BL31_CFLAGS += -fpie BL31_LDFLAGS += $(PIE_LDFLAGS) @@ -708,18 +748,25 @@ BL32_CPPFLAGS += -fpie BL32_CFLAGS += -fpie BL32_LDFLAGS += $(PIE_LDFLAGS) -endif +endif #(ENABLE_PIE) -ifeq (${ARCH},aarch64) +BL1_CPPFLAGS += -DREPORT_ERRATA=${DEBUG} +BL31_CPPFLAGS += -DREPORT_ERRATA=${DEBUG} +BL32_CPPFLAGS += -DREPORT_ERRATA=${DEBUG} + BL1_CPPFLAGS += -DIMAGE_AT_EL3 ifeq ($(RESET_TO_BL2),1) -BL2_CPPFLAGS += -DIMAGE_AT_EL3 + BL2_CPPFLAGS += -DIMAGE_AT_EL3 else -BL2_CPPFLAGS += -DIMAGE_AT_EL1 -endif -BL2U_CPPFLAGS += -DIMAGE_AT_EL1 -BL31_CPPFLAGS += -DIMAGE_AT_EL3 -BL32_CPPFLAGS += -DIMAGE_AT_EL1 + BL2_CPPFLAGS += -DIMAGE_AT_EL1 +endif #(RESET_TO_BL2) + +ifeq (${ARCH},aarch64) + BL2U_CPPFLAGS += -DIMAGE_AT_EL1 + BL31_CPPFLAGS += -DIMAGE_AT_EL3 + BL32_CPPFLAGS += -DIMAGE_AT_EL1 +else + BL32_CPPFLAGS += -DIMAGE_AT_EL3 endif # Include the CPU specific operations makefile, which provides default @@ -727,25 +774,23 @@ # This can be overridden by the platform. include lib/cpus/cpu-ops.mk -ifeq (${ARCH},aarch32) -NEED_BL32 := yes - ################################################################################ # Build `AARCH32_SP` as BL32 image for AArch32 ################################################################################ -ifneq (${AARCH32_SP},none) -# We expect to locate an sp.mk under the specified AARCH32_SP directory -AARCH32_SP_MAKE := $(wildcard bl32/${AARCH32_SP}/${AARCH32_SP}.mk) +ifeq (${ARCH},aarch32) + NEED_BL32 := yes -ifeq (${AARCH32_SP_MAKE},) - $(error Error: No bl32/${AARCH32_SP}/${AARCH32_SP}.mk located) -endif + ifneq (${AARCH32_SP},none) + # We expect to locate an sp.mk under the specified AARCH32_SP directory + AARCH32_SP_MAKE := $(wildcard bl32/${AARCH32_SP}/${AARCH32_SP}.mk) -$(info Including ${AARCH32_SP_MAKE}) -include ${AARCH32_SP_MAKE} -endif - -endif + ifeq (${AARCH32_SP_MAKE},) + $(error Error: No bl32/${AARCH32_SP}/${AARCH32_SP}.mk located) + endif + $(info Including ${AARCH32_SP_MAKE}) + include ${AARCH32_SP_MAKE} + endif +endif #(ARCH=aarch32) ################################################################################ # Include libc if not overridden @@ -755,217 +800,255 @@ endif ################################################################################ -# Check incompatible options +# Check incompatible options and dependencies ################################################################################ -ifdef EL3_PAYLOAD_BASE - ifdef PRELOADED_BL33_BASE - $(warning "PRELOADED_BL33_BASE and EL3_PAYLOAD_BASE are \ - incompatible build options. EL3_PAYLOAD_BASE has priority.") +# USE_DEBUGFS experimental feature recommended only in debug builds +ifeq (${USE_DEBUGFS},1) + ifeq (${DEBUG},1) + $(warning DEBUGFS experimental feature is enabled.) + else + $(warning DEBUGFS experimental, recommended in DEBUG builds ONLY) endif - ifneq (${GENERATE_COT},0) - $(error "GENERATE_COT and EL3_PAYLOAD_BASE are incompatible build options.") +endif #(USE_DEBUGFS) + +# USE_SPINLOCK_CAS requires AArch64 build +ifeq (${USE_SPINLOCK_CAS},1) + ifneq (${ARCH},aarch64) + $(error USE_SPINLOCK_CAS requires AArch64) endif - ifneq (${TRUSTED_BOARD_BOOT},0) - $(error "TRUSTED_BOARD_BOOT and EL3_PAYLOAD_BASE are incompatible build options.") - endif +endif #(USE_SPINLOCK_CAS) + +# The cert_create tool cannot generate certificates individually, so we use the +# target 'certificates' to create them all +ifneq (${GENERATE_COT},0) + FIP_DEPS += certificates + FWU_FIP_DEPS += fwu_certificates endif +ifneq (${DECRYPTION_SUPPORT},none) + ENC_ARGS += -f ${FW_ENC_STATUS} + ENC_ARGS += -k ${ENC_KEY} + ENC_ARGS += -n ${ENC_NONCE} + FIP_DEPS += enctool + FWU_FIP_DEPS += enctool +endif #(DECRYPTION_SUPPORT) + +ifdef EL3_PAYLOAD_BASE + ifdef PRELOADED_BL33_BASE + $(warning "PRELOADED_BL33_BASE and EL3_PAYLOAD_BASE are \ + incompatible build options. EL3_PAYLOAD_BASE has priority.") + endif + ifneq (${GENERATE_COT},0) + $(error "GENERATE_COT and EL3_PAYLOAD_BASE are incompatible \ + build options.") + endif + ifneq (${TRUSTED_BOARD_BOOT},0) + $(error "TRUSTED_BOARD_BOOT and EL3_PAYLOAD_BASE are \ + incompatible \ build options.") + endif +endif #(EL3_PAYLOAD_BASE) + ifeq (${NEED_BL33},yes) - ifdef EL3_PAYLOAD_BASE + ifdef EL3_PAYLOAD_BASE $(warning "BL33 image is not needed when option \ BL33_PAYLOAD_BASE is used and won't be added to the FIP file.") - endif - ifdef PRELOADED_BL33_BASE + endif + ifdef PRELOADED_BL33_BASE $(warning "BL33 image is not needed when option \ - PRELOADED_BL33_BASE is used and won't be added to the FIP \ - file.") - endif -endif + PRELOADED_BL33_BASE is used and won't be added to the FIP file.") + endif +endif #(NEED_BL33) # When building for systems with hardware-assisted coherency, there's no need to # use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. ifeq ($(HW_ASSISTED_COHERENCY)-$(USE_COHERENT_MEM),1-1) -$(error USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY) + $(error USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY) endif #For now, BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is 1. ifeq ($(RESET_TO_BL2)-$(BL2_IN_XIP_MEM),0-1) -$(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled") + $(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled") endif # RAS_EXTENSION is deprecated, provide alternate build options ifeq ($(RAS_EXTENSION),1) - $(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS and RAS_FFH_SUPPORT instead") + $(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS \ + and HANDLE_EA_EL3_FIRST_NS instead") endif -# RAS firmware first handling requires that EAs are handled in EL3 first -ifeq ($(RAS_FFH_SUPPORT),1) - ifneq ($(ENABLE_FEAT_RAS),1) - $(error For RAS_FFH_SUPPORT, ENABLE_FEAT_RAS must also be 1) - endif - ifneq ($(HANDLE_EA_EL3_FIRST_NS),1) - $(error For RAS_FFH_SUPPORT, HANDLE_EA_EL3_FIRST_NS must also be 1) - endif -endif + + # When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled ifeq ($(FAULT_INJECTION_SUPPORT),1) - ifeq ($(ENABLE_FEAT_RAS),0) - $(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0) - endif -endif + ifeq ($(ENABLE_FEAT_RAS),0) + $(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0) + endif +endif #(FAULT_INJECTION_SUPPORT) # DYN_DISABLE_AUTH can be set only when TRUSTED_BOARD_BOOT=1 ifeq ($(DYN_DISABLE_AUTH), 1) - ifeq (${TRUSTED_BOARD_BOOT}, 0) - $(error "TRUSTED_BOARD_BOOT must be enabled for DYN_DISABLE_AUTH to be set.") - endif -endif + ifeq (${TRUSTED_BOARD_BOOT}, 0) + $(error "TRUSTED_BOARD_BOOT must be enabled for DYN_DISABLE_AUTH \ + to be set.") + endif +endif #(DYN_DISABLE_AUTH) ifeq ($(MEASURED_BOOT)-$(TRUSTED_BOARD_BOOT),1-1) # Support authentication verification and hash calculation - CRYPTO_SUPPORT := 3 + CRYPTO_SUPPORT := 3 else ifeq ($(DRTM_SUPPORT)-$(TRUSTED_BOARD_BOOT),1-1) # Support authentication verification and hash calculation - CRYPTO_SUPPORT := 3 + CRYPTO_SUPPORT := 3 else ifneq ($(filter 1,${MEASURED_BOOT} ${DRTM_SUPPORT}),) # Support hash calculation only - CRYPTO_SUPPORT := 2 + CRYPTO_SUPPORT := 2 else ifeq (${TRUSTED_BOARD_BOOT},1) # Support authentication verification only - CRYPTO_SUPPORT := 1 + CRYPTO_SUPPORT := 1 else - CRYPTO_SUPPORT := 0 -endif + CRYPTO_SUPPORT := 0 +endif #($(MEASURED_BOOT)-$(TRUSTED_BOARD_BOOT)) # SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled. ifeq ($(SDEI_SUPPORT)-$(SDEI_IN_FCONF),0-1) -$(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled") + $(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled") endif # If pointer authentication is used in the firmware, make sure that all the # registers associated to it are also saved and restored. # Not doing it would leak the value of the keys used by EL3 to EL1 and S-EL1. ifeq ($(ENABLE_PAUTH),1) - ifeq ($(CTX_INCLUDE_PAUTH_REGS),0) - $(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS=1) - endif -endif + ifeq ($(CTX_INCLUDE_PAUTH_REGS),0) + $(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS=1) + endif +endif #(ENABLE_PAUTH) ifeq ($(CTX_INCLUDE_PAUTH_REGS),1) - ifneq (${ARCH},aarch64) - $(error CTX_INCLUDE_PAUTH_REGS requires AArch64) - endif -endif + ifneq (${ARCH},aarch64) + $(error CTX_INCLUDE_PAUTH_REGS requires AArch64) + endif +endif #(CTX_INCLUDE_PAUTH_REGS) ifeq ($(CTX_INCLUDE_MTE_REGS),1) - ifneq (${ARCH},aarch64) - $(error CTX_INCLUDE_MTE_REGS requires AArch64) - endif -endif + ifneq (${ARCH},aarch64) + $(error CTX_INCLUDE_MTE_REGS requires AArch64) + endif +endif #(CTX_INCLUDE_MTE_REGS) ifeq ($(PSA_FWU_SUPPORT),1) - $(info PSA_FWU_SUPPORT is an experimental feature) -endif + $(info PSA_FWU_SUPPORT is an experimental feature) +endif #(PSA_FWU_SUPPORT) ifeq ($(FEATURE_DETECTION),1) - $(info FEATURE_DETECTION is an experimental feature) -endif + $(info FEATURE_DETECTION is an experimental feature) +endif #(FEATURE_DETECTION) ifneq ($(ENABLE_SME2_FOR_NS), 0) - ifeq (${ENABLE_SME_FOR_NS}, 0) - $(warning "ENABLE_SME2_FOR_NS requires ENABLE_SME_FOR_NS also to be set") - $(warning "Forced ENABLE_SME_FOR_NS=1") - override ENABLE_SME_FOR_NS := 1 - endif -endif + ifeq (${ENABLE_SME_FOR_NS}, 0) + $(warning "ENABLE_SME2_FOR_NS requires ENABLE_SME_FOR_NS also \ + to be set") + $(warning "Forced ENABLE_SME_FOR_NS=1") + override ENABLE_SME_FOR_NS := 1 + endif +endif #(ENABLE_SME2_FOR_NS) ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1) - ifeq (${ALLOW_RO_XLAT_TABLES}, 1) - $(error "ALLOW_RO_XLAT_TABLES requires translation tables library v2") - endif -endif + ifeq (${ALLOW_RO_XLAT_TABLES}, 1) + $(error "ALLOW_RO_XLAT_TABLES requires translation tables \ + library v2") + endif +endif #(ARM_XLAT_TABLES_LIB_V1) ifneq (${DECRYPTION_SUPPORT},none) - ifeq (${TRUSTED_BOARD_BOOT}, 0) - $(error TRUSTED_BOARD_BOOT must be enabled for DECRYPTION_SUPPORT to be set) - endif -endif + ifeq (${TRUSTED_BOARD_BOOT}, 0) + $(error TRUSTED_BOARD_BOOT must be enabled for DECRYPTION_SUPPORT \ + to be set) + endif +endif #(DECRYPTION_SUPPORT) # Ensure that no Aarch64-only features are enabled in Aarch32 build ifeq (${ARCH},aarch32) - # SME/SVE only supported on AArch64 - ifneq (${ENABLE_SME_FOR_NS},0) - $(error "ENABLE_SME_FOR_NS cannot be used with ARCH=aarch32") - endif + # SME/SVE only supported on AArch64 + ifneq (${ENABLE_SME_FOR_NS},0) + $(error "ENABLE_SME_FOR_NS cannot be used with ARCH=aarch32") + endif - ifeq (${ENABLE_SVE_FOR_NS},1) - # Warning instead of error due to CI dependency on this - $(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32") - endif + ifeq (${ENABLE_SVE_FOR_NS},1) + # Warning instead of error due to CI dependency on this + $(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32") + endif - # BRBE is not supported in AArch32 - ifeq (${ENABLE_BRBE_FOR_NS},1) - $(error "ENABLE_BRBE_FOR_NS cannot be used with ARCH=aarch32") - endif + # BRBE is not supported in AArch32 + ifeq (${ENABLE_BRBE_FOR_NS},1) + $(error "ENABLE_BRBE_FOR_NS cannot be used with ARCH=aarch32") + endif - # FEAT_RNG_TRAP is not supported in AArch32 - ifeq (${ENABLE_FEAT_RNG_TRAP},1) - $(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32") - endif -endif - -# Ensure ENABLE_RME is not used with SME -ifeq (${ENABLE_RME},1) - ifneq (${ENABLE_SME_FOR_NS},0) - $(error "ENABLE_SME_FOR_NS cannot be used with ENABLE_RME") - endif -endif + # FEAT_RNG_TRAP is not supported in AArch32 + ifeq (${ENABLE_FEAT_RNG_TRAP},1) + $(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32") + endif +endif #(ARCH=aarch32) ifneq (${ENABLE_SME_FOR_NS},0) - ifeq (${ENABLE_SVE_FOR_NS},0) - $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS") - endif -endif + ifeq (${ENABLE_SVE_FOR_NS},0) + $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS") + endif +endif #(ENABLE_SME_FOR_NS) # Secure SME/SVE requires the non-secure component as well ifeq (${ENABLE_SME_FOR_SWD},1) - ifeq (${ENABLE_SME_FOR_NS},0) - $(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS") - endif - ifeq (${ENABLE_SVE_FOR_SWD},0) - $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD") - endif -endif + ifeq (${ENABLE_SME_FOR_NS},0) + $(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS") + endif + ifeq (${ENABLE_SVE_FOR_SWD},0) + $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD") + endif +endif #(ENABLE_SME_FOR_SWD) + ifeq (${ENABLE_SVE_FOR_SWD},1) - ifeq (${ENABLE_SVE_FOR_NS},0) - $(error "ENABLE_SVE_FOR_SWD requires ENABLE_SVE_FOR_NS") - endif -endif + ifeq (${ENABLE_SVE_FOR_NS},0) + $(error "ENABLE_SVE_FOR_SWD requires ENABLE_SVE_FOR_NS") + endif +endif #(ENABLE_SVE_FOR_SWD) # SVE and SME cannot be used with CTX_INCLUDE_FPREGS since secure manager does # its own context management including FPU registers. ifeq (${CTX_INCLUDE_FPREGS},1) - ifneq (${ENABLE_SME_FOR_NS},0) - $(error "ENABLE_SME_FOR_NS cannot be used with CTX_INCLUDE_FPREGS") - endif + ifneq (${ENABLE_SME_FOR_NS},0) + $(error "ENABLE_SME_FOR_NS cannot be used with CTX_INCLUDE_FPREGS") + endif - ifeq (${ENABLE_SVE_FOR_NS},1) - # Warning instead of error due to CI dependency on this - $(warning "ENABLE_SVE_FOR_NS cannot be used with CTX_INCLUDE_FPREGS") - $(warning "Forced ENABLE_SVE_FOR_NS=0") - override ENABLE_SVE_FOR_NS := 0 - endif -endif + ifeq (${ENABLE_SVE_FOR_NS},1) + # Warning instead of error due to CI dependency on this + $(warning "ENABLE_SVE_FOR_NS cannot be used with CTX_INCLUDE_FPREGS") + $(warning "Forced ENABLE_SVE_FOR_NS=0") + override ENABLE_SVE_FOR_NS := 0 + endif +endif #(CTX_INCLUDE_FPREGS) ifeq ($(DRTM_SUPPORT),1) - $(info DRTM_SUPPORT is an experimental feature) + $(info DRTM_SUPPORT is an experimental feature) +endif + +ifeq (${TRANSFER_LIST},1) + $(info TRANSFER_LIST is an experimental feature) endif ifeq (${ENABLE_RME},1) - ifneq (${SEPARATE_CODE_AND_RODATA},1) - $(error `ENABLE_RME=1` requires `SEPARATE_CODE_AND_RODATA=1`) - endif + ifneq (${SEPARATE_CODE_AND_RODATA},1) + $(error `ENABLE_RME=1` requires `SEPARATE_CODE_AND_RODATA=1`) + endif +endif + +# Determine if FEAT_RNG is supported +ENABLE_FEAT_RNG = $(if $(findstring rng,${arch-features}),1,0) + +# Determine if FEAT_SB is supported +ENABLE_FEAT_SB = $(if $(findstring sb,${arch-features}),1,0) + +ifeq ($(PSA_CRYPTO),1) + $(info PSA_CRYPTO is an experimental feature) endif ################################################################################ @@ -973,8 +1056,8 @@ ################################################################################ ifdef BL1_SOURCES -NEED_BL1 := yes -endif + NEED_BL1 := yes +endif #(BL1_SOURCES) ifdef BL2_SOURCES NEED_BL2 := yes @@ -982,64 +1065,64 @@ # Using BL2 implies that a BL33 image also needs to be supplied for the FIP and # Certificate generation tools. This flag can be overridden by the platform. ifdef EL3_PAYLOAD_BASE - # If booting an EL3 payload there is no need for a BL33 image - # in the FIP file. - NEED_BL33 := no - else - ifdef PRELOADED_BL33_BASE - # If booting a BL33 preloaded image there is no need of - # another one in the FIP file. - NEED_BL33 := no - else - NEED_BL33 ?= yes - endif - endif -endif + # If booting an EL3 payload there is no need for a BL33 image + # in the FIP file. + NEED_BL33 := no + else + ifdef PRELOADED_BL33_BASE + # If booting a BL33 preloaded image there is no need of + # another one in the FIP file. + NEED_BL33 := no + else + NEED_BL33 ?= yes + endif + endif +endif #(BL2_SOURCES) ifdef BL2U_SOURCES -NEED_BL2U := yes -endif + NEED_BL2U := yes +endif #(BL2U_SOURCES) # If SCP_BL2 is given, we always want FIP to include it. ifdef SCP_BL2 - NEED_SCP_BL2 := yes -endif + NEED_SCP_BL2 := yes +endif #(SCP_BL2) # For AArch32, BL31 is not currently supported. ifneq (${ARCH},aarch32) - ifdef BL31_SOURCES - # When booting an EL3 payload, there is no need to compile the BL31 image nor - # put it in the FIP. - ifndef EL3_PAYLOAD_BASE - NEED_BL31 := yes - endif - endif -endif + ifdef BL31_SOURCES + # When booting an EL3 payload, there is no need to compile the BL31 + # image nor put it in the FIP. + ifndef EL3_PAYLOAD_BASE + NEED_BL31 := yes + endif + endif +endif #(ARCH=aarch64) # Process TBB related flags ifneq (${GENERATE_COT},0) - # Common cert_create options - ifneq (${CREATE_KEYS},0) + # Common cert_create options + ifneq (${CREATE_KEYS},0) $(eval CRT_ARGS += -n) $(eval FWU_CRT_ARGS += -n) - ifneq (${SAVE_KEYS},0) + ifneq (${SAVE_KEYS},0) $(eval CRT_ARGS += -k) $(eval FWU_CRT_ARGS += -k) - endif - endif - # Include TBBR makefile (unless the platform indicates otherwise) - ifeq (${INCLUDE_TBBR_MK},1) + endif + endif + # Include TBBR makefile (unless the platform indicates otherwise) + ifeq (${INCLUDE_TBBR_MK},1) include make_helpers/tbbr/tbbr_tools.mk - endif -endif + endif +endif #(GENERATE_COT) ifneq (${FIP_ALIGN},0) -FIP_ARGS += --align ${FIP_ALIGN} -endif + FIP_ARGS += --align ${FIP_ALIGN} +endif #(FIP_ALIGN) ifdef FDT_SOURCES -NEED_FDT := yes -endif + NEED_FDT := yes +endif #(FDT_SOURCES) ################################################################################ # Include libraries' Makefile that are used in all BL @@ -1048,44 +1131,6 @@ include lib/stack_protector/stack_protector.mk ################################################################################ -# Auxiliary tools (fiptool, cert_create, etc) -################################################################################ - -# Variables for use with Certificate Generation Tool -CRTTOOLPATH ?= tools/cert_create -CRTTOOL ?= ${CRTTOOLPATH}/cert_create${BIN_EXT} - -# Variables for use with Firmware Encryption Tool -ENCTOOLPATH ?= tools/encrypt_fw -ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT} - -# Variables for use with Firmware Image Package -FIPTOOLPATH ?= tools/fiptool -FIPTOOL ?= ${FIPTOOLPATH}/fiptool${BIN_EXT} - -# Variables for use with sptool -SPTOOLPATH ?= tools/sptool -SPTOOL ?= ${SPTOOLPATH}/sptool.py -SP_MK_GEN ?= ${SPTOOLPATH}/sp_mk_generator.py - -# Variables for use with ROMLIB -ROMLIBPATH ?= lib/romlib - -# Variable for use with Python -PYTHON ?= python3 - -# Variables for use with PRINT_MEMORY_MAP -PRINT_MEMORY_MAP_PATH ?= tools/memory -PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py -INVERTED_MEMMAP ?= 0 - -# Variables for use with documentation build using Sphinx tool -DOCS_PATH ?= docs - -# Defination of SIMICS flag -SIMICS_BUILD ?= 0 - -################################################################################ # Include BL specific makefiles ################################################################################ @@ -1109,132 +1154,139 @@ # Build options checks ################################################################################ +# Boolean_Flags $(eval $(call assert_booleans,\ $(sort \ - ALLOW_RO_XLAT_TABLES \ - BL2_ENABLE_SP_LOAD \ - COLD_BOOT_SINGLE_CPU \ - CREATE_KEYS \ - CTX_INCLUDE_AARCH32_REGS \ - CTX_INCLUDE_FPREGS \ - CTX_INCLUDE_EL2_REGS \ - DEBUG \ - DISABLE_MTPMU \ - DYN_DISABLE_AUTH \ - EL3_EXCEPTION_HANDLING \ - ENABLE_AMU_AUXILIARY_COUNTERS \ - ENABLE_AMU_FCONF \ - AMU_RESTRICT_COUNTERS \ - ENABLE_ASSERTIONS \ - ENABLE_FEAT_SB \ - ENABLE_PIE \ - ENABLE_PMF \ - ENABLE_PSCI_STAT \ - ENABLE_RUNTIME_INSTRUMENTATION \ - ENABLE_SME_FOR_SWD \ - ENABLE_SVE_FOR_SWD \ - ERROR_DEPRECATED \ - FAULT_INJECTION_SUPPORT \ - GENERATE_COT \ - GICV2_G0_FOR_EL3 \ - HANDLE_EA_EL3_FIRST_NS \ - HW_ASSISTED_COHERENCY \ - INVERTED_MEMMAP \ - MEASURED_BOOT \ - DRTM_SUPPORT \ - NS_TIMER_SWITCH \ - OVERRIDE_LIBC \ - PL011_GENERIC_UART \ - PLAT_RSS_NOT_SUPPORTED \ - PROGRAMMABLE_RESET_ADDRESS \ - PSCI_EXTENDED_STATE_ID \ - PSCI_OS_INIT_MODE \ - RESET_TO_BL31 \ - SAVE_KEYS \ - SEPARATE_CODE_AND_RODATA \ - SEPARATE_BL2_NOLOAD_REGION \ - SEPARATE_NOBITS_REGION \ - SPIN_ON_BL1_EXIT \ - SPM_MM \ - SPMC_AT_EL3 \ - SPMD_SPM_AT_SEL2 \ - TRUSTED_BOARD_BOOT \ - USE_COHERENT_MEM \ - USE_DEBUGFS \ - ARM_IO_IN_DTB \ - SDEI_IN_FCONF \ - SEC_INT_DESC_IN_FCONF \ - USE_ROMLIB \ - USE_TBBR_DEFS \ - WARMBOOT_ENABLE_DCACHE_EARLY \ - RESET_TO_BL2 \ - BL2_IN_XIP_MEM \ - BL2_INV_DCACHE \ - USE_SPINLOCK_CAS \ - ENCRYPT_BL31 \ - ENCRYPT_BL32 \ - ERRATA_SPECULATIVE_AT \ - RAS_TRAP_NS_ERR_REC_ACCESS \ - COT_DESC_IN_DTB \ - USE_SP804_TIMER \ - PSA_FWU_SUPPORT \ - ENABLE_MPMM \ - ENABLE_MPMM_FCONF \ - SIMICS_BUILD \ - FEATURE_DETECTION \ + ALLOW_RO_XLAT_TABLES \ + BL2_ENABLE_SP_LOAD \ + COLD_BOOT_SINGLE_CPU \ + CREATE_KEYS \ + CTX_INCLUDE_AARCH32_REGS \ + CTX_INCLUDE_FPREGS \ + CTX_INCLUDE_EL2_REGS \ + DEBUG \ + DYN_DISABLE_AUTH \ + EL3_EXCEPTION_HANDLING \ + ENABLE_AMU_AUXILIARY_COUNTERS \ + ENABLE_AMU_FCONF \ + AMU_RESTRICT_COUNTERS \ + ENABLE_ASSERTIONS \ + ENABLE_FEAT_SB \ + ENABLE_PIE \ + ENABLE_PMF \ + ENABLE_PSCI_STAT \ + ENABLE_RUNTIME_INSTRUMENTATION \ + ENABLE_SME_FOR_SWD \ + ENABLE_SVE_FOR_SWD \ + ENABLE_FEAT_RAS \ + FFH_SUPPORT \ + ERROR_DEPRECATED \ + FAULT_INJECTION_SUPPORT \ + GENERATE_COT \ + GICV2_G0_FOR_EL3 \ + HANDLE_EA_EL3_FIRST_NS \ + HW_ASSISTED_COHERENCY \ + MEASURED_BOOT \ + DRTM_SUPPORT \ + NS_TIMER_SWITCH \ + OVERRIDE_LIBC \ + PL011_GENERIC_UART \ + PLAT_RSS_NOT_SUPPORTED \ + PROGRAMMABLE_RESET_ADDRESS \ + PSCI_EXTENDED_STATE_ID \ + PSCI_OS_INIT_MODE \ + RESET_TO_BL31 \ + SAVE_KEYS \ + SEPARATE_CODE_AND_RODATA \ + SEPARATE_BL2_NOLOAD_REGION \ + SEPARATE_NOBITS_REGION \ + SPIN_ON_BL1_EXIT \ + SPM_MM \ + SPMC_AT_EL3 \ + SPMC_AT_EL3_SEL0_SP \ + SPMD_SPM_AT_SEL2 \ + ENABLE_SPMD_LP \ + TRANSFER_LIST \ + TRUSTED_BOARD_BOOT \ + USE_COHERENT_MEM \ + USE_DEBUGFS \ + ARM_IO_IN_DTB \ + SDEI_IN_FCONF \ + SEC_INT_DESC_IN_FCONF \ + USE_ROMLIB \ + USE_TBBR_DEFS \ + WARMBOOT_ENABLE_DCACHE_EARLY \ + RESET_TO_BL2 \ + BL2_IN_XIP_MEM \ + BL2_INV_DCACHE \ + USE_SPINLOCK_CAS \ + ENCRYPT_BL31 \ + ENCRYPT_BL32 \ + ERRATA_SPECULATIVE_AT \ + RAS_TRAP_NS_ERR_REC_ACCESS \ + COT_DESC_IN_DTB \ + USE_SP804_TIMER \ + PSA_FWU_SUPPORT \ + ENABLE_MPMM \ + ENABLE_MPMM_FCONF \ + FEATURE_DETECTION \ TRNG_SUPPORT \ ERRATA_ABI_SUPPORT \ ERRATA_NON_ARM_INTERCONNECT \ CONDITIONAL_CMO \ - RAS_FFH_SUPPORT \ + PSA_CRYPTO \ + ENABLE_CONSOLE_GETC \ + INIT_UNUSED_NS_EL2 \ ))) +# Numeric_Flags $(eval $(call assert_numerics,\ $(sort \ - ARM_ARCH_MAJOR \ - ARM_ARCH_MINOR \ - BRANCH_PROTECTION \ - CTX_INCLUDE_PAUTH_REGS \ - CTX_INCLUDE_MTE_REGS \ - CTX_INCLUDE_NEVE_REGS \ - CRYPTO_SUPPORT \ - ENABLE_BRBE_FOR_NS \ - ENABLE_TRBE_FOR_NS \ - ENABLE_BTI \ - ENABLE_PAUTH \ - ENABLE_FEAT_AMU \ - ENABLE_FEAT_AMUv1p1 \ - ENABLE_FEAT_CSV2_2 \ - ENABLE_FEAT_RAS \ - ENABLE_FEAT_DIT \ - ENABLE_FEAT_ECV \ - ENABLE_FEAT_FGT \ - ENABLE_FEAT_HCX \ - ENABLE_FEAT_PAN \ - ENABLE_FEAT_RNG \ - ENABLE_FEAT_RNG_TRAP \ - ENABLE_FEAT_SEL2 \ - ENABLE_FEAT_TCR2 \ - ENABLE_FEAT_S2PIE \ - ENABLE_FEAT_S1PIE \ - ENABLE_FEAT_S2POE \ - ENABLE_FEAT_S1POE \ - ENABLE_FEAT_GCS \ - ENABLE_FEAT_VHE \ - ENABLE_MPAM_FOR_LOWER_ELS \ - ENABLE_RME \ - ENABLE_SPE_FOR_NS \ - ENABLE_SYS_REG_TRACE_FOR_NS \ - ENABLE_SME_FOR_NS \ - ENABLE_SME2_FOR_NS \ - ENABLE_SVE_FOR_NS \ - ENABLE_TRF_FOR_NS \ - FW_ENC_STATUS \ - NR_OF_FW_BANKS \ - NR_OF_IMAGES_IN_FW_BANK \ - TWED_DELAY \ - ENABLE_FEAT_TWED \ - SVE_VECTOR_LEN \ + ARM_ARCH_MAJOR \ + ARM_ARCH_MINOR \ + BRANCH_PROTECTION \ + CTX_INCLUDE_PAUTH_REGS \ + CTX_INCLUDE_MTE_REGS \ + CTX_INCLUDE_NEVE_REGS \ + CRYPTO_SUPPORT \ + DISABLE_MTPMU \ + ENABLE_BRBE_FOR_NS \ + ENABLE_TRBE_FOR_NS \ + ENABLE_BTI \ + ENABLE_PAUTH \ + ENABLE_FEAT_AMU \ + ENABLE_FEAT_AMUv1p1 \ + ENABLE_FEAT_CSV2_2 \ + ENABLE_FEAT_DIT \ + ENABLE_FEAT_ECV \ + ENABLE_FEAT_FGT \ + ENABLE_FEAT_HCX \ + ENABLE_FEAT_PAN \ + ENABLE_FEAT_RNG \ + ENABLE_FEAT_RNG_TRAP \ + ENABLE_FEAT_SEL2 \ + ENABLE_FEAT_TCR2 \ + ENABLE_FEAT_S2PIE \ + ENABLE_FEAT_S1PIE \ + ENABLE_FEAT_S2POE \ + ENABLE_FEAT_S1POE \ + ENABLE_FEAT_GCS \ + ENABLE_FEAT_VHE \ + ENABLE_FEAT_MTE_PERM \ + ENABLE_FEAT_MPAM \ + ENABLE_RME \ + ENABLE_SPE_FOR_NS \ + ENABLE_SYS_REG_TRACE_FOR_NS \ + ENABLE_SME_FOR_NS \ + ENABLE_SME2_FOR_NS \ + ENABLE_SVE_FOR_NS \ + ENABLE_TRF_FOR_NS \ + FW_ENC_STATUS \ + NR_OF_FW_BANKS \ + NR_OF_IMAGES_IN_FW_BANK \ + TWED_DELAY \ + ENABLE_FEAT_TWED \ + SVE_VECTOR_LEN \ IMPDEF_SYSREG_TRAP \ ))) @@ -1254,162 +1306,169 @@ $(eval $(call add_defines,\ $(sort \ - ALLOW_RO_XLAT_TABLES \ - ARM_ARCH_MAJOR \ - ARM_ARCH_MINOR \ - BL2_ENABLE_SP_LOAD \ - COLD_BOOT_SINGLE_CPU \ - CTX_INCLUDE_AARCH32_REGS \ - CTX_INCLUDE_FPREGS \ - CTX_INCLUDE_PAUTH_REGS \ - EL3_EXCEPTION_HANDLING \ - CTX_INCLUDE_MTE_REGS \ - CTX_INCLUDE_EL2_REGS \ - CTX_INCLUDE_NEVE_REGS \ - DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \ - DISABLE_MTPMU \ - ENABLE_FEAT_AMU \ - ENABLE_AMU_AUXILIARY_COUNTERS \ - ENABLE_AMU_FCONF \ - AMU_RESTRICT_COUNTERS \ - ENABLE_ASSERTIONS \ - ENABLE_BTI \ - ENABLE_MPAM_FOR_LOWER_ELS \ - ENABLE_PAUTH \ - ENABLE_PIE \ - ENABLE_PMF \ - ENABLE_PSCI_STAT \ - ENABLE_RME \ - ENABLE_RUNTIME_INSTRUMENTATION \ - ENABLE_SME_FOR_NS \ - ENABLE_SME2_FOR_NS \ - ENABLE_SME_FOR_SWD \ - ENABLE_SPE_FOR_NS \ - ENABLE_SVE_FOR_NS \ - ENABLE_SVE_FOR_SWD \ - ENCRYPT_BL31 \ - ENCRYPT_BL32 \ - ERROR_DEPRECATED \ - FAULT_INJECTION_SUPPORT \ - GICV2_G0_FOR_EL3 \ - HANDLE_EA_EL3_FIRST_NS \ - HW_ASSISTED_COHERENCY \ - LOG_LEVEL \ - MEASURED_BOOT \ - DRTM_SUPPORT \ - NS_TIMER_SWITCH \ - PL011_GENERIC_UART \ - PLAT_${PLAT} \ - PLAT_RSS_NOT_SUPPORTED \ - PROGRAMMABLE_RESET_ADDRESS \ - PSCI_EXTENDED_STATE_ID \ - PSCI_OS_INIT_MODE \ - ENABLE_FEAT_RAS \ - RAS_FFH_SUPPORT \ - RESET_TO_BL31 \ - SEPARATE_CODE_AND_RODATA \ - SEPARATE_BL2_NOLOAD_REGION \ - SEPARATE_NOBITS_REGION \ - RECLAIM_INIT_CODE \ - SPD_${SPD} \ - SPIN_ON_BL1_EXIT \ - SPM_MM \ - SPMC_AT_EL3 \ - SPMD_SPM_AT_SEL2 \ - TRUSTED_BOARD_BOOT \ - CRYPTO_SUPPORT \ - TRNG_SUPPORT \ - ERRATA_ABI_SUPPORT \ + ALLOW_RO_XLAT_TABLES \ + ARM_ARCH_MAJOR \ + ARM_ARCH_MINOR \ + BL2_ENABLE_SP_LOAD \ + COLD_BOOT_SINGLE_CPU \ + CTX_INCLUDE_AARCH32_REGS \ + CTX_INCLUDE_FPREGS \ + CTX_INCLUDE_PAUTH_REGS \ + EL3_EXCEPTION_HANDLING \ + CTX_INCLUDE_MTE_REGS \ + CTX_INCLUDE_EL2_REGS \ + CTX_INCLUDE_NEVE_REGS \ + DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \ + DISABLE_MTPMU \ + ENABLE_FEAT_AMU \ + ENABLE_AMU_AUXILIARY_COUNTERS \ + ENABLE_AMU_FCONF \ + AMU_RESTRICT_COUNTERS \ + ENABLE_ASSERTIONS \ + ENABLE_BTI \ + ENABLE_FEAT_MPAM \ + ENABLE_PAUTH \ + ENABLE_PIE \ + ENABLE_PMF \ + ENABLE_PSCI_STAT \ + ENABLE_RME \ + ENABLE_RUNTIME_INSTRUMENTATION \ + ENABLE_SME_FOR_NS \ + ENABLE_SME2_FOR_NS \ + ENABLE_SME_FOR_SWD \ + ENABLE_SPE_FOR_NS \ + ENABLE_SVE_FOR_NS \ + ENABLE_SVE_FOR_SWD \ + ENABLE_FEAT_RAS \ + FFH_SUPPORT \ + ENCRYPT_BL31 \ + ENCRYPT_BL32 \ + ERROR_DEPRECATED \ + FAULT_INJECTION_SUPPORT \ + GICV2_G0_FOR_EL3 \ + HANDLE_EA_EL3_FIRST_NS \ + HW_ASSISTED_COHERENCY \ + LOG_LEVEL \ + MEASURED_BOOT \ + DRTM_SUPPORT \ + NS_TIMER_SWITCH \ + PL011_GENERIC_UART \ + PLAT_${PLAT} \ + PLAT_RSS_NOT_SUPPORTED \ + PROGRAMMABLE_RESET_ADDRESS \ + PSCI_EXTENDED_STATE_ID \ + PSCI_OS_INIT_MODE \ + RESET_TO_BL31 \ + SEPARATE_CODE_AND_RODATA \ + SEPARATE_BL2_NOLOAD_REGION \ + SEPARATE_NOBITS_REGION \ + RECLAIM_INIT_CODE \ + SPD_${SPD} \ + SPIN_ON_BL1_EXIT \ + SPM_MM \ + SPMC_AT_EL3 \ + SPMC_AT_EL3_SEL0_SP \ + SPMD_SPM_AT_SEL2 \ + TRANSFER_LIST \ + TRUSTED_BOARD_BOOT \ + CRYPTO_SUPPORT \ + TRNG_SUPPORT \ + ERRATA_ABI_SUPPORT \ ERRATA_NON_ARM_INTERCONNECT \ - USE_COHERENT_MEM \ - USE_DEBUGFS \ - ARM_IO_IN_DTB \ - SDEI_IN_FCONF \ - SEC_INT_DESC_IN_FCONF \ - USE_ROMLIB \ - USE_TBBR_DEFS \ - WARMBOOT_ENABLE_DCACHE_EARLY \ - RESET_TO_BL2 \ - BL2_RUNS_AT_EL3 \ - BL2_IN_XIP_MEM \ - BL2_INV_DCACHE \ - USE_SPINLOCK_CAS \ - ERRATA_SPECULATIVE_AT \ - RAS_TRAP_NS_ERR_REC_ACCESS \ - COT_DESC_IN_DTB \ - USE_SP804_TIMER \ - ENABLE_FEAT_RNG \ - ENABLE_FEAT_RNG_TRAP \ - ENABLE_FEAT_SB \ - ENABLE_FEAT_DIT \ - NR_OF_FW_BANKS \ - NR_OF_IMAGES_IN_FW_BANK \ - PSA_FWU_SUPPORT \ - ENABLE_BRBE_FOR_NS \ - ENABLE_TRBE_FOR_NS \ - ENABLE_SYS_REG_TRACE_FOR_NS \ - ENABLE_TRF_FOR_NS \ - ENABLE_FEAT_HCX \ - ENABLE_MPMM \ - ENABLE_MPMM_FCONF \ - ENABLE_FEAT_FGT \ - ENABLE_FEAT_ECV \ - SIMICS_BUILD \ - ENABLE_FEAT_AMUv1p1 \ - ENABLE_FEAT_SEL2 \ - ENABLE_FEAT_VHE \ - ENABLE_FEAT_CSV2_2 \ - ENABLE_FEAT_PAN \ - ENABLE_FEAT_TCR2 \ - ENABLE_FEAT_S2PIE \ - ENABLE_FEAT_S1PIE \ - ENABLE_FEAT_S2POE \ - ENABLE_FEAT_S1POE \ - ENABLE_FEAT_GCS \ - FEATURE_DETECTION \ - TWED_DELAY \ - ENABLE_FEAT_TWED \ + USE_COHERENT_MEM \ + USE_DEBUGFS \ + ARM_IO_IN_DTB \ + SDEI_IN_FCONF \ + SEC_INT_DESC_IN_FCONF \ + USE_ROMLIB \ + USE_TBBR_DEFS \ + WARMBOOT_ENABLE_DCACHE_EARLY \ + RESET_TO_BL2 \ + BL2_RUNS_AT_EL3 \ + BL2_IN_XIP_MEM \ + BL2_INV_DCACHE \ + USE_SPINLOCK_CAS \ + ERRATA_SPECULATIVE_AT \ + RAS_TRAP_NS_ERR_REC_ACCESS \ + COT_DESC_IN_DTB \ + USE_SP804_TIMER \ + ENABLE_FEAT_RNG \ + ENABLE_FEAT_RNG_TRAP \ + ENABLE_FEAT_SB \ + ENABLE_FEAT_DIT \ + NR_OF_FW_BANKS \ + NR_OF_IMAGES_IN_FW_BANK \ + PSA_FWU_SUPPORT \ + ENABLE_BRBE_FOR_NS \ + ENABLE_TRBE_FOR_NS \ + ENABLE_SYS_REG_TRACE_FOR_NS \ + ENABLE_TRF_FOR_NS \ + ENABLE_FEAT_HCX \ + ENABLE_MPMM \ + ENABLE_MPMM_FCONF \ + ENABLE_FEAT_FGT \ + ENABLE_FEAT_ECV \ + ENABLE_FEAT_AMUv1p1 \ + ENABLE_FEAT_SEL2 \ + ENABLE_FEAT_VHE \ + ENABLE_FEAT_CSV2_2 \ + ENABLE_FEAT_PAN \ + ENABLE_FEAT_TCR2 \ + ENABLE_FEAT_S2PIE \ + ENABLE_FEAT_S1PIE \ + ENABLE_FEAT_S2POE \ + ENABLE_FEAT_S1POE \ + ENABLE_FEAT_GCS \ + ENABLE_FEAT_MTE_PERM \ + FEATURE_DETECTION \ + TWED_DELAY \ + ENABLE_FEAT_TWED \ CONDITIONAL_CMO \ IMPDEF_SYSREG_TRAP \ + SVE_VECTOR_LEN \ + ENABLE_SPMD_LP \ + PSA_CRYPTO \ + ENABLE_CONSOLE_GETC \ + INIT_UNUSED_NS_EL2 \ ))) ifeq (${SANITIZE_UB},trap) $(eval $(call add_define,MONITOR_TRAPS)) -endif +endif #(SANITIZE_UB) # Define the EL3_PAYLOAD_BASE flag only if it is provided. ifdef EL3_PAYLOAD_BASE $(eval $(call add_define,EL3_PAYLOAD_BASE)) else - # Define the PRELOADED_BL33_BASE flag only if it is provided and - # EL3_PAYLOAD_BASE is not defined, as it has priority. - ifdef PRELOADED_BL33_BASE +# Define the PRELOADED_BL33_BASE flag only if it is provided and +# EL3_PAYLOAD_BASE is not defined, as it has priority. + ifdef PRELOADED_BL33_BASE $(eval $(call add_define,PRELOADED_BL33_BASE)) - endif -endif + endif +endif #(EL3_PAYLOAD_BASE) # Define the DYN_DISABLE_AUTH flag only if set. ifeq (${DYN_DISABLE_AUTH},1) -$(eval $(call add_define,DYN_DISABLE_AUTH)) + $(eval $(call add_define,DYN_DISABLE_AUTH)) endif ifneq ($(findstring armlink,$(notdir $(LD))),) -$(eval $(call add_define,USE_ARM_LINK)) + $(eval $(call add_define,USE_ARM_LINK)) endif # Generate and include sp_gen.mk if SPD is spmd and SP_LAYOUT_FILE is defined ifeq (${SPD},spmd) ifdef SP_LAYOUT_FILE - -include $(BUILD_PLAT)/sp_gen.mk - FIP_DEPS += sp - CRT_DEPS += sp - NEED_SP_PKG := yes + -include $(BUILD_PLAT)/sp_gen.mk + FIP_DEPS += sp + CRT_DEPS += sp + NEED_SP_PKG := yes else - ifeq (${SPMD_SPM_AT_SEL2},1) - $(error "SPMD with SPM at S-EL2 require SP_LAYOUT_FILE") - endif -endif -endif + ifeq (${SPMD_SPM_AT_SEL2},1) + $(error "SPMD with SPM at S-EL2 require SP_LAYOUT_FILE") + endif +endif #(SP_LAYOUT_FILE) +endif #(SPD) ################################################################################ # Build targets @@ -1430,7 +1489,7 @@ else CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp endif -endif # !ERROR_DEPRECATED +endif #(!ERROR_DEPRECATED) $(eval $(call MAKE_LIB_DIRS)) $(eval $(call MAKE_LIB,c)) @@ -1438,11 +1497,11 @@ # Expand build macros for the different images ifeq (${NEED_BL1},yes) BL1_SOURCES := $(sort ${BL1_SOURCES}) - $(eval $(call MAKE_BL,bl1)) -endif +endif #(NEED_BL1) ifeq (${NEED_BL2},yes) + ifeq (${RESET_TO_BL2}, 0) FIP_BL2_ARGS := tb-fw endif @@ -1451,11 +1510,12 @@ $(if ${BL2}, $(eval $(call TOOL_ADD_IMG,bl2,--${FIP_BL2_ARGS})),\ $(eval $(call MAKE_BL,bl2,${FIP_BL2_ARGS}))) -endif + +endif #(NEED_BL2) ifeq (${NEED_SCP_BL2},yes) $(eval $(call TOOL_ADD_IMG,scp_bl2,--scp-fw)) -endif +endif #(NEED_SCP_BL2) ifeq (${NEED_BL31},yes) BL31_SOURCES += ${SPD_SOURCES} @@ -1467,8 +1527,8 @@ else $(if ${BL31}, $(eval $(call TOOL_ADD_IMG,bl31,--soc-fw)),\ $(eval $(call MAKE_BL,bl31,soc-fw))) -endif -endif +endif #(DECRYPTION_SUPPORT) +endif #(NEED_BL31) # If a BL32 image is needed but neither BL32 nor BL32_SOURCES is defined, the # build system will call TOOL_ADD_IMG to print a warning message and abort the @@ -1484,8 +1544,8 @@ else $(if ${BUILD_BL32}, $(eval $(call MAKE_BL,bl32,tos-fw)),\ $(eval $(call TOOL_ADD_IMG,bl32,--tos-fw))) -endif -endif +endif #(DECRYPTION_SUPPORT) +endif #(NEED_BL32) # If RMM image is needed but RMM is not defined, Test Realm Payload (TRP) # needs to be built from RMM_SOURCES. @@ -1495,33 +1555,33 @@ BUILD_RMM := $(if $(RMM),,$(if $(RMM_SOURCES),1)) $(if ${BUILD_RMM}, $(eval $(call MAKE_BL,rmm,rmm-fw)),\ - $(eval $(call TOOL_ADD_IMG,rmm,--rmm-fw))) -endif + $(eval $(call TOOL_ADD_IMG,rmm,--rmm-fw))) +endif #(NEED_RMM) # Add the BL33 image if required by the platform ifeq (${NEED_BL33},yes) $(eval $(call TOOL_ADD_IMG,bl33,--nt-fw)) -endif +endif #(NEED_BL33) ifeq (${NEED_BL2U},yes) $(if ${BL2U}, $(eval $(call TOOL_ADD_IMG,bl2u,--ap-fwu-cfg,FWU_)),\ $(eval $(call MAKE_BL,bl2u,ap-fwu-cfg,FWU_))) -endif +endif #(NEED_BL2U) # Expand build macros for the different images ifeq (${NEED_FDT},yes) $(eval $(call MAKE_DTBS,$(BUILD_PLAT)/fdts,$(FDT_SOURCES))) -endif +endif #(NEED_FDT) # Add Secure Partition packages ifeq (${NEED_SP_PKG},yes) -$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT} - ${Q}${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} +$(BUILD_PLAT)/sp_gen.mk : ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT} + ${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} ${SP_DTS_LIST_FRAGMENT} sp: $(DTBS) $(BUILD_PLAT)/sp_gen.mk $(SP_PKGS) @${ECHO_BLANK_LINE} @echo "Built SP Images successfully" @${ECHO_BLANK_LINE} -endif +endif #(NEED_SP_PKG) locate-checkpatch: ifndef CHECKPATCH @@ -1530,7 +1590,7 @@ ifeq (,$(wildcard ${CHECKPATCH})) $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/scripts/checkpatch.pl") endif -endif +endif #(CHECKPATCH) clean: @echo " CLEAN" @@ -1541,7 +1601,7 @@ # Clear the MAKEFLAGS as we do not want # to pass the gnumake flags to nmake. ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) clean -endif +endif #(UNIX_MK) ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean @@ -1556,7 +1616,7 @@ # Clear the MAKEFLAGS as we do not want # to pass the gnumake flags to nmake. ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean -endif +endif #(UNIX_MK) ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean @@ -1610,7 +1670,7 @@ @echo "Built $@ successfully" @echo "Certificates can be found in ${BUILD_PLAT}" @${ECHO_BLANK_LINE} -endif +endif #(GENERATE_COT) ${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} $(eval ${CHECK_FIP_CMD}) @@ -1627,7 +1687,7 @@ @echo "Built $@ successfully" @echo "FWU certificates can be found in ${BUILD_PLAT}" @${ECHO_BLANK_LINE} -endif +endif #(GENERATE_COT) ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL} $(eval ${CHECK_FWU_FIP_CMD}) @@ -1648,14 +1708,19 @@ # Clear the MAKEFLAGS as we do not want # to pass the gnumake flags to nmake. ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) -endif +endif #(UNIX_MK) romlib.bin: libraries FORCE ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all -# Call print_memory_map tool memmap: all - ${Q}${PYTHON} ${PRINT_MEMORY_MAP} ${BUILD_PLAT} ${INVERTED_MEMMAP} +ifdef UNIX_MK + ${Q}PYTHONPATH=${CURDIR}/tools/memory \ + ${PYTHON} -m memory.memmap -sr ${BUILD_PLAT} +else + ${Q}set PYTHONPATH=${CURDIR}/tools/memory && \ + ${PYTHON} -m memory.memmap -sr ${BUILD_PLAT} +endif doc: @echo " BUILD DOCUMENTATION"
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 0a1cb30..f3de536 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c
@@ -17,19 +17,3 @@ /* Set the next EL to be AArch64 */ write_scr_el3(read_scr_el3() | SCR_RW_BIT); } - -/******************************************************************************* - * Set the Secure EL1 required architectural state - ******************************************************************************/ -void bl1_arch_next_el_setup(void) -{ - u_register_t next_sctlr; - - /* Use the same endianness than the current BL */ - next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); - - /* Set SCTLR Secure EL1 */ - next_sctlr |= SCTLR_EL1_RES1; - - write_sctlr_el1(next_sctlr); -}
diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index bec234b..49dda85 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,11 @@ } SECTIONS { + ROM_REGION_START = ORIGIN(ROM); + ROM_REGION_LENGTH = LENGTH(ROM); + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); + . = BL1_RO_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -36,6 +41,7 @@ *bl1_entrypoint.o(.text*) *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -67,6 +73,7 @@ * aligned and lld does not align the LMA to the alignment specified * on the .data section. */ + __RODATA_END_UNALIGNED__ = .; __RODATA_END__ = .; . = ALIGN(16); @@ -97,6 +104,7 @@ ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") + ROM_REGION_END = .; . = BL1_RW_BASE; ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), @@ -157,4 +165,5 @@ #endif /* USE_COHERENT_MEM */ ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") + RAM_REGION_END = .; }
diff --git a/bl1/bl1.mk b/bl1/bl1.mk index b1791b1..53946ab 100644 --- a/bl1/bl1.mk +++ b/bl1/bl1.mk
@@ -16,10 +16,6 @@ plat/common/${ARCH}/platform_up_stack.S \ ${MBEDTLS_SOURCES} -ifeq (${DISABLE_MTPMU},1) -BL1_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S -endif - ifeq (${ARCH},aarch64) BL1_SOURCES += lib/cpus/aarch64/dsu_helpers.S \ lib/el3_runtime/aarch64/context.S @@ -29,6 +25,10 @@ BL1_SOURCES += bl1/bl1_fwu.c endif +ifeq (${ENABLE_PMF},1) +BL1_SOURCES += lib/pmf/pmf_main.c +endif + ifneq ($(findstring gcc,$(notdir $(LD))),) BL1_LDFLAGS += -Wl,--sort-section=alignment else ifneq ($(findstring ld,$(notdir $(LD))),)
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 7399bc8..6fe5511 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,9 @@ #include <drivers/auth/auth_mod.h> #include <drivers/auth/crypto_mod.h> #include <drivers/console.h> -#include <lib/cpus/errata_report.h> +#include <lib/bootmarker_capture.h> +#include <lib/cpus/errata.h> +#include <lib/pmf/pmf.h> #include <lib/utils.h> #include <plat/common/platform.h> #include <smccc_helpers.h> @@ -31,6 +33,11 @@ uint64_t bl1_apiakey[2]; #endif +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, + BL_TOTAL_IDS, PMF_DUMP_ENABLE) +#endif + /******************************************************************************* * Helper utility to calculate the BL2 memory layout taking into consideration * the BL1 RW data assuming that it is at the top of the memory layout. @@ -81,6 +88,10 @@ { unsigned int image_id; +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT); +#endif + /* Announce our arrival */ NOTICE(FIRMWARE_WELCOME_STR); NOTICE("BL1: %s\n", version_string); @@ -156,6 +167,10 @@ bl1_prepare_next_image(image_id); +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT); +#endif + console_flush(); }
diff --git a/bl1/bl1_private.h b/bl1/bl1_private.h index e119ba7..61fb5be 100644 --- a/bl1/bl1_private.h +++ b/bl1/bl1_private.h
@@ -17,7 +17,6 @@ * Function prototypes *****************************************/ void bl1_arch_setup(void); -void bl1_arch_next_el_setup(void); void bl1_prepare_next_image(unsigned int image_id); void bl1_run_bl2_in_root(void);
diff --git a/bl2/aarch64/bl2_run_next_image.S b/bl2/aarch64/bl2_run_next_image.S index f0a8be8..1431a5f 100644 --- a/bl2/aarch64/bl2_run_next_image.S +++ b/bl2/aarch64/bl2_run_next_image.S
@@ -24,15 +24,6 @@ tlbi alle3 bl bl2_el3_plat_prepare_exit -#if ENABLE_PAUTH - /* --------------------------------------------- - * Disable pointer authentication before jumping - * to next boot image. - * --------------------------------------------- - */ - bl pauth_disable_el3 -#endif /* ENABLE_PAUTH */ - ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] msr elr_el3, x0 msr spsr_el3, x1
diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index 458a12b..db83a0c 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S
@@ -16,6 +16,8 @@ } SECTIONS { + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); . = BL2_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -33,6 +35,7 @@ *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -55,6 +58,7 @@ RODATA_COMMON + __RODATA_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; @@ -116,6 +120,7 @@ __RW_END__ = .; __BL2_END__ = .; + RAM_REGION_END = .; __BSS_SIZE__ = SIZEOF(.bss);
diff --git a/bl2/bl2.mk b/bl2/bl2.mk index 41bcd12..b70a3fb 100644 --- a/bl2/bl2.mk +++ b/bl2/bl2.mk
@@ -41,12 +41,7 @@ BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \ bl2/${ARCH}/bl2_el3_exceptions.S \ bl2/${ARCH}/bl2_run_next_image.S \ - lib/cpus/${ARCH}/cpu_helpers.S \ - lib/cpus/errata_report.c - -ifeq (${DISABLE_MTPMU},1) -BL2_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S -endif + lib/cpus/${ARCH}/cpu_helpers.S ifeq (${ARCH},aarch64) BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S @@ -54,3 +49,7 @@ BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2_el3.ld.S endif + +ifeq (${ENABLE_PMF},1) +BL2_SOURCES += lib/pmf/pmf_main.c +endif \ No newline at end of file
diff --git a/bl2/bl2_el3.ld.S b/bl2/bl2_el3.ld.S index aa457fa..4aa5cb0 100644 --- a/bl2/bl2_el3.ld.S +++ b/bl2/bl2_el3.ld.S
@@ -31,7 +31,12 @@ #endif /* !BL2_IN_XIP_MEM */ SECTIONS { + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); #if BL2_IN_XIP_MEM + ROM_REGION_START = ORIGIN(ROM); + ROM_REGION_LENGTH = LENGTH(ROM); + . = BL2_RO_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -43,6 +48,11 @@ "BL2_BASE address is not aligned on a page boundary.") #endif /* BL2_IN_XIP_MEM */ +#if SEPARATE_BL2_NOLOAD_REGION + RAM_NOLOAD_REGION_START = ORIGIN(RAM_NOLOAD); + RAM_NOLOAD_REGION_LENGTH = LENGTH(RAM_NOLOAD); +#endif + #if SEPARATE_CODE_AND_RODATA .text . : { __TEXT_START__ = .; @@ -55,6 +65,7 @@ *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -68,6 +79,7 @@ RODATA_COMMON + __RODATA_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; @@ -109,6 +121,7 @@ "cpu_ops not defined for this platform.") #if BL2_IN_XIP_MEM + ROM_REGION_END = .; . = BL2_RW_BASE; ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE), @@ -138,6 +151,7 @@ #if SEPARATE_BL2_NOLOAD_REGION __BL2_NOLOAD_END__ = .; + RAM_NOLOAD_REGION_END = .; . = SAVED_ADDR; #endif /* SEPARATE_BL2_NOLOAD_REGION */ @@ -198,6 +212,7 @@ __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; #endif /* USE_COHERENT_MEM */ + RAM_REGION_END = .; #if BL2_IN_XIP_MEM ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.") #else /* BL2_IN_XIP_MEM */
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c index ce83692..923a554 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c
@@ -16,7 +16,9 @@ #include <drivers/auth/crypto_mod.h> #include <drivers/console.h> #include <drivers/fwu/fwu.h> +#include <lib/bootmarker_capture.h> #include <lib/extensions/pauth.h> +#include <lib/pmf/pmf.h> #include <plat/common/platform.h> #include "bl2_private.h" @@ -27,6 +29,11 @@ #define NEXT_IMAGE "BL32" #endif +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, + BL_TOTAL_IDS, PMF_DUMP_ENABLE); +#endif + #if RESET_TO_BL2 /******************************************************************************* * Setup function for BL2 when RESET_TO_BL2=1 @@ -81,6 +88,10 @@ { entry_point_info_t *next_bl_ep_info; +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_ENTRY, PMF_CACHE_MAINT); +#endif + NOTICE("BL2: %s\n", version_string); NOTICE("BL2: %s\n", build_message); @@ -118,8 +129,6 @@ disable_mmu_icache_secure(); #endif /* !__aarch64__ */ - console_flush(); - #if ENABLE_PAUTH /* * Disable pointer authentication before running next boot image @@ -127,6 +136,12 @@ pauth_disable_el1(); #endif /* ENABLE_PAUTH */ +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT); +#endif + + console_flush(); + /* * Run next BL image via an SMC to BL1. Information on how to pass * control to the BL32 (if present) and BL33 software images will @@ -137,6 +152,9 @@ NOTICE("BL2: Booting " NEXT_IMAGE "\n"); print_entry_point_info(next_bl_ep_info); +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT); +#endif console_flush(); #if ENABLE_PAUTH
diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index 52a925b..7b1a101 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S
@@ -18,6 +18,8 @@ } SECTIONS { + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); . = BL2U_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -30,6 +32,7 @@ *bl2u_entrypoint.o(.text*) *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -51,6 +54,7 @@ RODATA_COMMON + __RODATA_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -115,4 +119,5 @@ __BSS_SIZE__ = SIZEOF(.bss); ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.") + RAM_REGION_END = .; }
diff --git a/bl31/aarch64/ea_delegate.S b/bl31/aarch64/ea_delegate.S index dd6b4dc..28d2187 100644 --- a/bl31/aarch64/ea_delegate.S +++ b/bl31/aarch64/ea_delegate.S
@@ -15,31 +15,11 @@ #include <cpu_macros.S> #include <context.h> - .globl handle_lower_el_ea_esb .globl handle_lower_el_sync_ea .globl handle_lower_el_async_ea - - + .globl handle_pending_async_ea /* - * Function to delegate External Aborts synchronized by ESB instruction at EL3 - * vector entry. This function assumes GP registers x0-x29 have been saved, and - * are available for use. It delegates the handling of the EA to platform - * handler, and returns only upon successfully handling the EA; otherwise - * panics. On return from this function, the original exception handler is - * expected to resume. - */ -func handle_lower_el_ea_esb - mov x0, #ERROR_EA_ESB - mrs x1, DISR_EL1 - b ea_proceed -endfunc handle_lower_el_ea_esb - - -/* - * This function forms the tail end of Synchronous Exception entry from lower - * EL, and expects to handle Synchronous External Aborts from lower EL and CPU - * Implementation Defined Exceptions. If any other kind of exception is detected, - * then this function reports unhandled exception. + * This function handles Synchronous External Aborts from lower EL. * * It delegates the handling of the EA to platform handler, and upon successfully * handling the EA, exits EL3; otherwise panics. @@ -57,27 +37,8 @@ cmp x30, #EC_DABORT_LOWER_EL b.eq 1f - /* Save GP registers */ - stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] - stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] - stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] - - /* Get the cpu_ops pointer */ - bl get_cpu_ops_ptr - - /* Get the cpu_ops exception handler */ - ldr x0, [x0, #CPU_E_HANDLER_FUNC] - - /* - * If the reserved function pointer is NULL, this CPU does not have an - * implementation defined exception handler function - */ - cbz x0, 2f - mrs x1, esr_el3 - ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH - blr x0 - b 2f - + /* EA other than above are unhandled exceptions */ + no_ret report_unhandled_exception 1: /* * Save general purpose and ARMv8.3-PAuth registers (if enabled). @@ -98,14 +59,6 @@ /* el3_exit assumes SP_EL0 on entry */ msr spsel, #MODE_SP_EL0 b el3_exit -2: - ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] - ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] - ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] - - /* Synchronous exceptions other than the above are assumed to be EA */ - ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] - no_ret report_unhandled_exception endfunc handle_lower_el_sync_ea @@ -140,6 +93,73 @@ b el3_exit endfunc handle_lower_el_async_ea +/* + * Handler for async EA from lower EL synchronized at EL3 entry in FFH mode. + * + * This scenario may arise when there is an error (EA) in the system which is not + * yet signaled to PE while executing in lower EL. During entry into EL3, the errors + * are synchronized either implicitly or explicitly causing async EA to pend at EL3. + * + * On detecting the pending EA (via ISR_EL1.A), if the EA routing model is Firmware + * First handling (FFH, SCR_EL3.EA = 1) this handler first handles the pending EA + * and then handles the original exception. + * + * This function assumes x30 has been saved. + */ +func handle_pending_async_ea + /* + * Prepare for nested handling of EA. Stash sysregs clobbered by nested + * exception and handler + */ + str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR] + mrs x30, esr_el3 + str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3] + mrs x30, spsr_el3 + str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3] + mrs x30, elr_el3 + str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] + + mov x30, #1 + str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] + /* + * Restore the original x30 saved as part of entering EL3. This is not + * required for the current function but for EL3 SError vector entry + * once PSTATE.A bit is unmasked. We restore x30 and then the same + * value is stored in EL3 SError vector entry. + */ + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + + /* + * After clearing PSTATE.A bit pending SError will trigger at current EL. + * Put explicit synchronization event to ensure newly unmasked interrupt + * is taken immediately. + */ + unmask_async_ea + + /* Restore the original exception information along with zeroing the storage */ + ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] + msr elr_el3, x30 + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] + ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3] + msr spsr_el3, x30 + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3] + ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3] + msr esr_el3, x30 + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3] + + /* + * If the original exception corresponds to SError from lower El, eret back + * to lower EL, otherwise return to vector table for original exception handling. + */ + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x30, #EC_SERROR + ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR] + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR] + b.eq 1f + ret +1: + exception_return +endfunc handle_pending_async_ea /* * Prelude for Synchronous External Abort handling. This function assumes that @@ -149,7 +169,7 @@ * x1: EA syndrome */ func delegate_sync_ea -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS /* * Check for Uncontainable error type. If so, route to the platform * fatal error handler rather than the generic EA one. @@ -179,7 +199,7 @@ * x1: EA syndrome */ func delegate_async_ea -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS /* Check Exception Class to ensure SError, as this function should * only be invoked for SError. If that is not the case, which implies * either an HW error or programming error, panic.
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S index 8bcf94e..ed48311 100644 --- a/bl31/aarch64/runtime_exceptions.S +++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,7 @@ #include <bl31/sync_handle.h> #include <common/runtime_svc.h> #include <context.h> +#include <cpu_macros.S> #include <el3_common_macros.S> #include <lib/el3_runtime/cpu_data.h> #include <lib/smccc.h> @@ -47,72 +48,30 @@ str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] .endm - /* - * Macro that prepares entry to EL3 upon taking an exception. - * - * With RAS_FFH_SUPPORT, this macro synchronizes pending errors with an - * ESB instruction. When an error is thus synchronized, the handling is - * delegated to platform EA handler. - * - * Without RAS_FFH_SUPPORT, this macro synchronizes pending errors using - * a DSB, unmasks Asynchronous External Aborts and saves X30 before - * setting the flag CTX_IS_IN_EL3. - */ - .macro check_and_unmask_ea -#if RAS_FFH_SUPPORT - /* Synchronize pending External Aborts */ - esb - - /* Unmask the SError interrupt */ - msr daifclr, #DAIF_ABT_BIT - - /* Check for SErrors synchronized by the ESB instruction */ - mrs x30, DISR_EL1 - tbz x30, #DISR_A_BIT, 1f + .macro restore_x30 + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + .endm /* - * Save general purpose and ARMv8.3-PAuth registers (if enabled). - * Also save PMCR_EL0 and set the PSTATE to a known state. + * Macro that synchronizes errors (EA) and checks for pending SError. + * On detecting a pending SError it either reflects it back to lower + * EL (KFH) or handles it in EL3 (FFH) based on EA routing model. */ - bl prepare_el3_entry - - bl handle_lower_el_ea_esb - - /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */ - bl restore_gp_pmcr_pauth_regs -1: -#else - /* - * Note 1: The explicit DSB at the entry of various exception vectors - * for handling exceptions from lower ELs can inadvertently trigger an - * SError exception in EL3 due to pending asynchronous aborts in lower - * ELs. This will end up being handled by serror_sp_elx which will - * ultimately panic and die. - * The way to workaround is to update a flag to indicate if the exception - * truly came from EL3. This flag is allocated in the cpu_context - * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3" - * This is not a bullet proof solution to the problem at hand because - * we assume the instructions following "isb" that help to update the - * flag execute without causing further exceptions. - */ - - /* - * For SoCs which do not implement RAS, use DSB as a barrier to - * synchronize pending external aborts. - */ - dsb sy - - /* Unmask the SError interrupt */ - msr daifclr, #DAIF_ABT_BIT - - /* Use ISB for the above unmask operation to take effect immediately */ - isb - - /* Refer Note 1. */ - mov x30, #1 - str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] - dmb sy + .macro sync_and_handle_pending_serror + synchronize_errors + mrs x30, ISR_EL1 + tbz x30, #ISR_A_SHIFT, 2f +#if FFH_SUPPORT + mrs x30, scr_el3 + tst x30, #SCR_EA_BIT + b.eq 1f + bl handle_pending_async_ea + b 2f #endif +1: + /* This function never returns, but need LR for decision making */ + bl reflect_pending_async_ea_to_lower_el +2: .endm /* --------------------------------------------------------------------- @@ -147,97 +106,21 @@ cmp x30, #EC_AARCH64_SYS b.eq sync_handler64 - /* Synchronous exceptions other than the above are assumed to be EA */ - ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + cmp x30, #EC_IMP_DEF_EL3 + b.eq imp_def_el3_handler + + /* If FFH Support then try to handle lower EL EA exceptions. */ +#if FFH_SUPPORT + mrs x30, scr_el3 + tst x30, #SCR_EA_BIT + b.eq 1f b handle_lower_el_sync_ea - .endm - - - /* --------------------------------------------------------------------- - * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS - * interrupts. - * --------------------------------------------------------------------- - */ - .macro handle_interrupt_exception label - - /* - * Save general purpose and ARMv8.3-PAuth registers (if enabled). - * Also save PMCR_EL0 and set the PSTATE to a known state. - */ - bl prepare_el3_entry - -#if ENABLE_PAUTH - /* Load and program APIAKey firmware key */ - bl pauth_load_bl31_apiakey #endif - - /* Save the EL3 system registers needed to return from this exception */ - mrs x0, spsr_el3 - mrs x1, elr_el3 - stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] - - /* Switch to the runtime stack i.e. SP_EL0 */ - ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] - mov x20, sp - msr spsel, #MODE_SP_EL0 - mov sp, x2 - - /* - * Find out whether this is a valid interrupt type. - * If the interrupt controller reports a spurious interrupt then return - * to where we came from. - */ - bl plat_ic_get_pending_interrupt_type - cmp x0, #INTR_TYPE_INVAL - b.eq interrupt_exit_\label - - /* - * Get the registered handler for this interrupt type. - * A NULL return value could be 'cause of the following conditions: - * - * a. An interrupt of a type was routed correctly but a handler for its - * type was not registered. - * - * b. An interrupt of a type was not routed correctly so a handler for - * its type was not registered. - * - * c. An interrupt of a type was routed correctly to EL3, but was - * deasserted before its pending state could be read. Another - * interrupt of a different type pended at the same time and its - * type was reported as pending instead. However, a handler for this - * type was not registered. - * - * a. and b. can only happen due to a programming error. The - * occurrence of c. could be beyond the control of Trusted Firmware. - * It makes sense to return from this exception instead of reporting an - * error. - */ - bl get_interrupt_type_handler - cbz x0, interrupt_exit_\label - mov x21, x0 - - mov x0, #INTR_ID_UNAVAILABLE - - /* Set the current security state in the 'flags' parameter */ - mrs x2, scr_el3 - ubfx x1, x2, #0, #1 - - /* Restore the reference to the 'handle' i.e. SP_EL3 */ - mov x2, x20 - - /* x3 will point to a cookie (not used now) */ - mov x3, xzr - - /* Call the interrupt type handler */ - blr x21 - -interrupt_exit_\label: - /* Return from exception, possibly in a different security state */ - b el3_exit - +1: + /* Synchronous exceptions other than the above are unhandled */ + b report_unhandled_exception .endm - vector_base runtime_exceptions /* --------------------------------------------------------------------- @@ -303,22 +186,33 @@ end_vector_entry fiq_sp_elx vector_entry serror_sp_elx -#if !RAS_FFH_SUPPORT +#if FFH_SUPPORT /* * This will trigger if the exception was taken due to SError in EL3 or * because of pending asynchronous external aborts from lower EL that got - * triggered due to explicit synchronization in EL3. Refer Note 1. + * triggered due to implicit/explicit synchronization in EL3 (SCR_EL3.EA=1) + * during EL3 entry. For the former case we continue with "plat_handle_el3_ea". + * The later case will occur when PSTATE.A bit is cleared in + * "handle_pending_async_ea". This means we are doing a nested + * exception in EL3. Call the handler for async EA which will eret back to + * original el3 handler if it is nested exception. Also, unmask EA so that we + * catch any further EA arise when handling this nested exception at EL3. */ - /* Assumes SP_EL3 on entry */ save_x30 - ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] - cbnz x30, 1f - - /* Handle asynchronous external abort from lower EL */ + ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] + cbz x30, 1f + /* + * This is nested exception handling, clear the flag to avoid taking this + * path for further exceptions caused by EA handling + */ + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] + unmask_async_ea b handle_lower_el_async_ea 1: + restore_x30 #endif no_ret plat_handle_el3_ea + end_vector_entry serror_sp_elx /* --------------------------------------------------------------------- @@ -334,34 +228,41 @@ */ save_x30 apply_at_speculative_wa - check_and_unmask_ea + sync_and_handle_pending_serror + unmask_async_ea handle_sync_exception end_vector_entry sync_exception_aarch64 vector_entry irq_aarch64 save_x30 apply_at_speculative_wa - check_and_unmask_ea - handle_interrupt_exception irq_aarch64 + sync_and_handle_pending_serror + unmask_async_ea + b handle_interrupt_exception end_vector_entry irq_aarch64 vector_entry fiq_aarch64 save_x30 apply_at_speculative_wa - check_and_unmask_ea - handle_interrupt_exception fiq_aarch64 + sync_and_handle_pending_serror + unmask_async_ea + b handle_interrupt_exception end_vector_entry fiq_aarch64 + /* + * Need to synchronize any outstanding SError since we can get a burst of errors. + * So reuse the sync mechanism to catch any further errors which are pending. + */ vector_entry serror_aarch64 +#if FFH_SUPPORT save_x30 apply_at_speculative_wa -#if RAS_FFH_SUPPORT - msr daifclr, #DAIF_ABT_BIT -#else - check_and_unmask_ea -#endif + sync_and_handle_pending_serror + unmask_async_ea b handle_lower_el_async_ea - +#else + b report_unhandled_exception +#endif end_vector_entry serror_aarch64 /* --------------------------------------------------------------------- @@ -377,34 +278,41 @@ */ save_x30 apply_at_speculative_wa - check_and_unmask_ea + sync_and_handle_pending_serror + unmask_async_ea handle_sync_exception end_vector_entry sync_exception_aarch32 vector_entry irq_aarch32 save_x30 apply_at_speculative_wa - check_and_unmask_ea - handle_interrupt_exception irq_aarch32 + sync_and_handle_pending_serror + unmask_async_ea + b handle_interrupt_exception end_vector_entry irq_aarch32 vector_entry fiq_aarch32 save_x30 apply_at_speculative_wa - check_and_unmask_ea - handle_interrupt_exception fiq_aarch32 + sync_and_handle_pending_serror + unmask_async_ea + b handle_interrupt_exception end_vector_entry fiq_aarch32 + /* + * Need to synchronize any outstanding SError since we can get a burst of errors. + * So reuse the sync mechanism to catch any further errors which are pending. + */ vector_entry serror_aarch32 +#if FFH_SUPPORT save_x30 apply_at_speculative_wa -#if RAS_FFH_SUPPORT - msr daifclr, #DAIF_ABT_BIT -#else - check_and_unmask_ea -#endif + sync_and_handle_pending_serror + unmask_async_ea b handle_lower_el_async_ea - +#else + b report_unhandled_exception +#endif end_vector_entry serror_aarch32 #ifdef MONITOR_TRAPS @@ -487,7 +395,7 @@ #if ENABLE_RME /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */ - ubfx x7, x18, #SCR_NSE_SHIFT, 1 + ubfx x7, x18, #SCR_NSE_SHIFT, #1 /* * Shift copied SCR_EL3.NSE bit by 5 to create space for @@ -519,7 +427,8 @@ * flags using the appropriate helper. */ 2: - bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK + and x16, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) + orr x7, x7, x16 bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT) /* Get the unique owning entity number */ @@ -610,6 +519,198 @@ endfunc sync_exception_handler /* --------------------------------------------------------------------- + * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS + * interrupts. + * + * Note that x30 has been explicitly saved and can be used here + * --------------------------------------------------------------------- + */ +func handle_interrupt_exception + /* + * Save general purpose and ARMv8.3-PAuth registers (if enabled). + * Also save PMCR_EL0 and set the PSTATE to a known state. + */ + bl prepare_el3_entry + +#if ENABLE_PAUTH + /* Load and program APIAKey firmware key */ + bl pauth_load_bl31_apiakey +#endif + + /* Save the EL3 system registers needed to return from this exception */ + mrs x0, spsr_el3 + mrs x1, elr_el3 + stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + + /* Switch to the runtime stack i.e. SP_EL0 */ + ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + mov x20, sp + msr spsel, #MODE_SP_EL0 + mov sp, x2 + + /* + * Find out whether this is a valid interrupt type. + * If the interrupt controller reports a spurious interrupt then return + * to where we came from. + */ + bl plat_ic_get_pending_interrupt_type + cmp x0, #INTR_TYPE_INVAL + b.eq interrupt_exit + + /* + * Get the registered handler for this interrupt type. + * A NULL return value could be 'cause of the following conditions: + * + * a. An interrupt of a type was routed correctly but a handler for its + * type was not registered. + * + * b. An interrupt of a type was not routed correctly so a handler for + * its type was not registered. + * + * c. An interrupt of a type was routed correctly to EL3, but was + * deasserted before its pending state could be read. Another + * interrupt of a different type pended at the same time and its + * type was reported as pending instead. However, a handler for this + * type was not registered. + * + * a. and b. can only happen due to a programming error. The + * occurrence of c. could be beyond the control of Trusted Firmware. + * It makes sense to return from this exception instead of reporting an + * error. + */ + bl get_interrupt_type_handler + cbz x0, interrupt_exit + mov x21, x0 + + mov x0, #INTR_ID_UNAVAILABLE + + /* Set the current security state in the 'flags' parameter */ + mrs x2, scr_el3 + ubfx x1, x2, #0, #1 + + /* Restore the reference to the 'handle' i.e. SP_EL3 */ + mov x2, x20 + + /* x3 will point to a cookie (not used now) */ + mov x3, xzr + + /* Call the interrupt type handler */ + blr x21 + +interrupt_exit: + /* Return from exception, possibly in a different security state */ + b el3_exit +endfunc handle_interrupt_exception + +func imp_def_el3_handler + /* Save GP registers */ + stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + + /* Get the cpu_ops pointer */ + bl get_cpu_ops_ptr + + /* Get the cpu_ops exception handler */ + ldr x0, [x0, #CPU_E_HANDLER_FUNC] + + /* + * If the reserved function pointer is NULL, this CPU does not have an + * implementation defined exception handler function + */ + cbz x0, el3_handler_exit + mrs x1, esr_el3 + ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH + blr x0 +el3_handler_exit: + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + restore_x30 + no_ret report_unhandled_exception +endfunc imp_def_el3_handler + +/* + * Handler for async EA from lower EL synchronized at EL3 entry in KFH mode. + * + * This scenario may arise when there is an error (EA) in the system which is not + * yet signaled to PE while executing in lower EL. During entry into EL3, the errors + * are synchronized either implicitly or explicitly causing async EA to pend at EL3. + * + * On detecting the pending EA (via ISR_EL1.A) and if the EA routing model is + * KFH (SCR_EL3.EA = 1) this handler reflects ther error back to lower EL. + * + * This function assumes x30 has been saved. + */ +func reflect_pending_async_ea_to_lower_el + /* + * As the original exception was not handled we need to ensure that we return + * back to the instruction which caused the exception. To acheive that, eret + * to "elr-4" (Label "subtract_elr_el3") for SMC or simply eret otherwise + * (Label "skip_smc_check"). + * + * LIMITATION: It could be that async EA is masked at the target exception level + * or the priority of async EA wrt to the EL3/secure interrupt is lower, which + * causes back and forth between lower EL and EL3. In case of back and forth between + * lower EL and EL3, we can track the loop count in "CTX_NESTED_EA_FLAG" and leverage + * previous ELR in "CTX_SAVED_ELR_EL3" to detect this cycle and further panic + * to indicate a problem here (Label "check_loop_ctr"). If we are in this cycle, loop + * counter retains its value but if we do a normal el3_exit this flag gets cleared. + * However, setting SCR_EL3.IESB = 1, should give priority to SError handling + * as per AArch64.TakeException pseudo code in Arm ARM. + * + * TODO: In future if EL3 gets a capability to inject a virtual SError to lower + * ELs, we can remove the el3_panic and handle the original exception first and + * inject SError to lower EL before ereting back. + */ + stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + ldr x29, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] + mrs x28, elr_el3 + cmp x29, x28 + b.eq check_loop_ctr + str x28, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3] + /* Zero the loop counter */ + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] + b skip_loop_ctr +check_loop_ctr: + ldr x29, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] + add x29, x29, #1 + str x29, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] + cmp x29, #ASYNC_EA_REPLAY_COUNTER + b.ge el3_panic +skip_loop_ctr: + /* + * Logic to distinguish if we came from SMC or any other exception. + * Use offsets in vector entry to get which exception we are handling. + * In each vector entry of size 0x200, address "0x0-0x80" is for sync + * exception and "0x80-0x200" is for async exceptions. + * Use vector base address (vbar_el3) and exception offset (LR) to + * calculate whether the address we came from is any of the following + * "0x0-0x80", "0x200-0x280", "0x400-0x480" or "0x600-0x680" + */ + mrs x29, vbar_el3 + sub x30, x30, x29 + and x30, x30, #0x1ff + cmp x30, #0x80 + b.ge skip_smc_check + /* Its a synchronous exception, Now check if it is SMC or not? */ + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x30, #EC_AARCH32_SMC + b.eq subtract_elr_el3 + cmp x30, #EC_AARCH64_SMC + b.eq subtract_elr_el3 + b skip_smc_check +subtract_elr_el3: + sub x28, x28, #4 +skip_smc_check: + msr elr_el3, x28 + ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + exception_return +endfunc reflect_pending_async_ea_to_lower_el + + /* --------------------------------------------------------------------- * The following code handles exceptions caused by BRK instructions. * Following a BRK instruction, the only real valid cause of action is * to print some information and panic, as the code that caused it is
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 5ac83fa..773b41d 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S
@@ -26,6 +26,8 @@ #endif /* PLAT_EXTRA_LD_SCRIPT */ SECTIONS { + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); . = BL31_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -40,6 +42,7 @@ *bl31_entrypoint.o(.text*) *(SORT_BY_ALIGNMENT(SORT(.text*))) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -60,6 +63,7 @@ . = ALIGN(8); # include <lib/el3_runtime/pubsub_events.h> + __RODATA_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -97,7 +101,7 @@ ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) # ifndef SPM_SHIM_EXCEPTIONS_VMA # define SPM_SHIM_EXCEPTIONS_VMA RAM # endif /* SPM_SHIM_EXCEPTIONS_VMA */ @@ -124,7 +128,7 @@ PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(.spm_shim_exceptions)); . = LOADADDR(.spm_shim_exceptions) + SIZEOF(.spm_shim_exceptions); -#endif /* SPM_MM */ +#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */ __RW_START__ = .; @@ -198,6 +202,7 @@ ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") #endif /* SEPARATE_NOBITS_REGION */ + RAM_REGION_END = .; /DISCARD/ : { *(.dynsym .dynstr .hash .gnu.hash)
diff --git a/bl31/bl31.mk b/bl31/bl31.mk index d7c9a52..f0776c4 100644 --- a/bl31/bl31.mk +++ b/bl31/bl31.mk
@@ -27,7 +27,6 @@ include lib/mpmm/mpmm.mk ifeq (${SPMC_AT_EL3},1) - $(warning "EL3 SPMC is an experimental feature") $(info Including EL3 SPMC makefile) include services/std_svc/spm/common/spm.mk include services/std_svc/spm/el3_spmc/spmc.mk @@ -39,7 +38,6 @@ bl31/interrupt_mgmt.c \ bl31/aarch64/bl31_entrypoint.S \ bl31/aarch64/crash_reporting.S \ - bl31/aarch64/ea_delegate.S \ bl31/aarch64/runtime_exceptions.S \ bl31/bl31_context_mgmt.c \ bl31/bl31_traps.c \ @@ -54,10 +52,6 @@ ${SPMC_SOURCES} \ ${SPM_SOURCES} -ifeq (${DISABLE_MTPMU},1) -BL31_SOURCES += lib/extensions/mtpmu/aarch64/mtpmu.S -endif - ifeq (${ENABLE_PMF}, 1) BL31_SOURCES += lib/pmf/pmf_main.c endif @@ -71,6 +65,10 @@ BL31_SOURCES += bl31/ehf.c endif +ifeq (${FFH_SUPPORT},1) +BL31_SOURCES += bl31/aarch64/ea_delegate.S +endif + ifeq (${SDEI_SUPPORT},1) ifeq (${EL3_EXCEPTION_HANDLING},0) $(error EL3_EXCEPTION_HANDLING must be 1 for SDEI support) @@ -110,7 +108,7 @@ BL31_SOURCES += lib/extensions/sve/sve.c endif -ifneq (${ENABLE_MPAM_FOR_LOWER_ELS},0) +ifneq (${ENABLE_FEAT_MPAM},0) BL31_SOURCES += lib/extensions/mpam/mpam.c endif
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c index e70eb55..925c6a6 100644 --- a/bl31/bl31_main.c +++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,7 @@ #include <common/feat_detect.h> #include <common/runtime_svc.h> #include <drivers/console.h> +#include <lib/bootmarker_capture.h> #include <lib/el3_runtime/context_mgmt.h> #include <lib/pmf/pmf.h> #include <lib/runtime_instr.h> @@ -24,8 +25,13 @@ #include <services/std_svc.h> #if ENABLE_RUNTIME_INSTRUMENTATION -PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID, - RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE) + PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID, + RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE) +#endif + +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, + BL_TOTAL_IDS, PMF_DUMP_ENABLE) #endif /******************************************************************************* @@ -112,6 +118,12 @@ ******************************************************************************/ void bl31_main(void) { + /* Init registers that never change for the lifetime of TF-A */ + cm_manage_extensions_el3(); + + /* Init per-world context registers for non-secure world */ + manage_extensions_nonsecure_per_world(); + NOTICE("BL31: %s\n", version_string); NOTICE("BL31: %s\n", build_message); @@ -120,6 +132,10 @@ detect_arch_features(); #endif /* FEATURE_DETECTION */ +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_ENTRY, PMF_CACHE_MAINT); +#endif + #ifdef SUPPORT_UNKNOWN_MPID if (unsupported_mpid_flag == 0) { NOTICE("Unsupported MPID detected!\n"); @@ -160,6 +176,7 @@ if (bl32_init != NULL) { INFO("BL31: Initializing BL32\n"); + console_flush(); int32_t rc = (*bl32_init)(); if (rc == 0) { @@ -175,6 +192,7 @@ if (rmm_init != NULL) { INFO("BL31: Initializing RMM\n"); + console_flush(); int32_t rc = (*rmm_init)(); if (rc == 0) { @@ -196,6 +214,11 @@ * from BL31 */ bl31_plat_runtime_setup(); + +#if ENABLE_RUNTIME_INSTRUMENTATION + PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_EXIT, PMF_CACHE_MAINT); + console_flush(); +#endif } /*******************************************************************************
diff --git a/bl31/ehf.c b/bl31/ehf.c index b328380..6f3d941 100644 --- a/bl31/ehf.c +++ b/bl31/ehf.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -458,7 +458,7 @@ int ret __unused; /* Ensure EL3 interrupts are supported */ - assert(plat_ic_has_interrupt_type(INTR_TYPE_EL3) != 0); + assert(plat_ic_has_interrupt_type(INTR_TYPE_EL3)); /* * Make sure that priority water mark has enough bits to represent the
diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c index b8cc3de..68c7f10 100644 --- a/bl31/interrupt_mgmt.c +++ b/bl31/interrupt_mgmt.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,9 +47,9 @@ ******************************************************************************/ static int32_t validate_interrupt_type(uint32_t type) { - if ((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_NS) || - (type == INTR_TYPE_EL3)) + if (plat_ic_has_interrupt_type(type)) { return 0; + } return -EINVAL; }
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index f102967..693dd4b 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,11 +62,8 @@ * The Cold boot/Reset entrypoint for SP_MIN */ func sp_min_entrypoint -#if !RESET_TO_SP_MIN /* --------------------------------------------------------------- - * Preceding bootloader has populated r0 with a pointer to a - * 'bl_params_t' structure & r1 with a pointer to platform - * specific structure + * Stash the previous bootloader arguments r0 - r3 for later use. * --------------------------------------------------------------- */ mov r9, r0 @@ -74,6 +71,7 @@ mov r11, r2 mov r12, r3 +#if !RESET_TO_SP_MIN /* --------------------------------------------------------------------- * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot @@ -91,11 +89,6 @@ _init_c_runtime=1 \ _exception_vectors=sp_min_vector_table \ _pie_fixup_size=FIXUP_SIZE - - /* --------------------------------------------------------------------- - * Relay the previous bootloader's arguments to the platform layer - * --------------------------------------------------------------------- - */ #else /* --------------------------------------------------------------------- * For RESET_TO_SP_MIN systems which have a programmable reset address, @@ -111,24 +104,16 @@ _init_c_runtime=1 \ _exception_vectors=sp_min_vector_table \ _pie_fixup_size=FIXUP_SIZE - - /* --------------------------------------------------------------------- - * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader - * to run so there's no argument to relay from a previous bootloader. - * Zero the arguments passed to the platform layer to reflect that. - * --------------------------------------------------------------------- - */ - mov r9, #0 - mov r10, #0 - mov r11, #0 - mov r12, #0 - #endif /* RESET_TO_SP_MIN */ #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r4 #endif + /* --------------------------------------------------------------------- + * Relay the previous bootloader's arguments to the platform layer + * --------------------------------------------------------------------- + */ mov r0, r9 mov r1, r10 mov r2, r11
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index 1695e1e..dd81973 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S
@@ -20,6 +20,8 @@ #endif /* PLAT_SP_MIN_EXTRA_LD_SCRIPT */ SECTIONS { + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); . = BL32_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -32,6 +34,7 @@ *entrypoint.o(.text*) *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -56,6 +59,7 @@ . = ALIGN(8); # include <lib/el3_runtime/pubsub_events.h> + __RODATA_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -149,4 +153,5 @@ } ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") + RAM_REGION_END = .; }
diff --git a/bl32/sp_min/sp_min.mk b/bl32/sp_min/sp_min.mk index ec75d88..065468c 100644 --- a/bl32/sp_min/sp_min.mk +++ b/bl32/sp_min/sp_min.mk
@@ -17,13 +17,10 @@ bl32/sp_min/aarch32/entrypoint.S \ common/runtime_svc.c \ plat/common/aarch32/plat_sp_min_common.c\ + services/arm_arch_svc/arm_arch_svc_setup.c \ services/std_svc/std_svc_setup.c \ ${PSCI_LIB_SOURCES} -ifeq (${DISABLE_MTPMU},1) -BL32_SOURCES += lib/extensions/mtpmu/aarch32/mtpmu.S -endif - ifeq (${ENABLE_PMF}, 1) BL32_SOURCES += lib/pmf/pmf_main.c endif
diff --git a/bl32/sp_min/sp_min_main.c b/bl32/sp_min/sp_min_main.c index f050160..26cf207 100644 --- a/bl32/sp_min/sp_min_main.c +++ b/bl32/sp_min/sp_min_main.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -134,6 +134,7 @@ assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); INFO("SP_MIN: Preparing exit to normal world\n"); + print_entry_point_info(next_image_info); psci_prepare_next_non_secure_ctx(next_image_info); smc_set_next_ctx(NON_SECURE);
diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index a6658dd..22bf11d 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S
@@ -16,6 +16,8 @@ } SECTIONS { + RAM_REGION_START = ORIGIN(RAM); + RAM_REGION_LENGTH = LENGTH(RAM); . = BL32_BASE; ASSERT(. == ALIGN(PAGE_SIZE), @@ -28,6 +30,7 @@ *tsp_entrypoint.o(.text*) *(.text*) *(.vectors) + __TEXT_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); @@ -41,6 +44,7 @@ RODATA_COMMON + __RODATA_END_UNALIGNED__ = .; . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; @@ -121,4 +125,5 @@ #endif /* USE_COHERENT_MEM */ ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") + RAM_REGION_END = .; }
diff --git a/bl32/tsp/tsp_ffa_main.c b/bl32/tsp/tsp_ffa_main.c index 268d329..1c8c68f 100644 --- a/bl32/tsp/tsp_ffa_main.c +++ b/bl32/tsp/tsp_ffa_main.c
@@ -91,7 +91,7 @@ smc_args_t ffa_forward_result; ffa_endpoint_id16_t receiver = arg5; - ffa_forward_result = ffa_msg_send_direct_req(ffa_endpoint_source(arg1), + ffa_forward_result = ffa_msg_send_direct_req(tsp_id, receiver, FF_A_ECHO_MESSAGE, arg4, 0, 0, 0);
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c index 0878ea4..1ab2260 100644 --- a/bl32/tsp/tsp_main.c +++ b/bl32/tsp/tsp_main.c
@@ -50,6 +50,8 @@ tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); + + console_flush(); return (uint64_t) &tsp_vector_table; }
diff --git a/changelog.yaml b/changelog.yaml index 0c4644d..1467ab4 100644 --- a/changelog.yaml +++ b/changelog.yaml
@@ -150,6 +150,10 @@ scope: trf - title: Platforms + scope: platforms + + deprecated: + - plat/common subsections: - title: Allwinner @@ -180,8 +184,8 @@ deprecated: - arm_fgpa - - arm_fpga - plat/arm_fpga + - arm/fpga - title: FVP scope: fvp @@ -244,9 +248,19 @@ - title: Corstone-1000 scope: corstone-1000 + - title: Aspeed + scope: aspeed + + subsections: + - title: AST2700 + scope: ast2700 + - title: Broadcom scope: brcm + - title: Cadence + scope: cadence + - title: HiSilicon scope: hisilicon @@ -399,6 +413,13 @@ - title: i.MX 8 scope: imx8 + - title: i.MX 9 + scope: imx9 + + subsections: + - title: i.MX93 + scope: imx93 + - title: Layerscape scope: layerscape @@ -485,6 +506,9 @@ - title: SBSA scope: qemu-sbsa + deprecated: + - qemu_sbsa + - title: QTI scope: qti @@ -575,6 +599,9 @@ - title: STM32MP15 scope: stm32mp15 + - title: STM32MP2 + scope: stm32mp2 + - title: Texas Instruments scope: ti @@ -592,6 +619,9 @@ - plat/xilinx subsections: + - title: DCC (Debug Communication Channel) + scope: dcc + - title: Versal scope: versal @@ -614,6 +644,13 @@ - plat/zynqmp - plat/xilinx/zynqmp + - title: Nuvoton + scope: nuvoton + + subsections: + - title: npcm845x + scope: npcm845x + - title: Bootloader Images scope: bl @@ -667,6 +704,9 @@ scope: spm subsections: + - title: EL3 SPM + scope: el3-spm + - title: EL3 SPMC scope: el3-spmc @@ -685,10 +725,14 @@ - title: TRNG scope: trng - - title: ERRATA_ABI - scope: errata_abi + - title: ERRATA ABI + scope: errata-abi + + deprecated: + - errata_abi - title: Libraries + scope: lib subsections: - title: CPU Support @@ -760,6 +804,9 @@ - title: Semihosting scope: semihosting + - title: Firmware Handoff + scope: handoff + - title: Drivers subsections: @@ -779,6 +826,9 @@ - title: mbedTLS scope: mbedtls + - title: mbedTLS-PSA + scope: mbedtls-psa + - title: Console scope: console @@ -875,6 +925,9 @@ - title: GIC-600AE scope: gic600ae + - title: GICv2 + scope: gicv2 + - title: SMMU scope: smmu @@ -1037,6 +1090,9 @@ - title: TZC-380 scope: nxp-tzc380 + - title: TRDC + scope: imx-trdc + - title: Renesas scope: renesas-drivers @@ -1201,6 +1257,9 @@ - title: STM32MP15 scope: stm32mp15-fdts + - title: STM32MP2 + scope: stm32mp2-fdts + - title: PIE scope: pie @@ -1301,6 +1360,9 @@ - title: Certificate Creation Tool scope: cert-create + - title: Memory Mapping Tool + scope: memmap + deprecated: - cert_create @@ -1323,5 +1385,8 @@ - title: Node Package Manager (NPM) scope: npm + - title: Poetry + scope: poetry + - title: zlib scope: zlib
diff --git a/common/feat_detect.c b/common/feat_detect.c index 50b74d0..be22c6e 100644 --- a/common/feat_detect.c +++ b/common/feat_detect.c
@@ -144,6 +144,14 @@ check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), "SB", 1, 1); check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), "CSV2_2", 2, 3); + /* + * Even though the PMUv3 is an OPTIONAL feature, it is always + * implemented and Arm prescribes so. So assume it will be there and do + * away with a flag for it. This is used to check minor PMUv3px + * revisions so that we catch them as they come along + */ + check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), + "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7); /* v8.1 features */ check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3); @@ -161,7 +169,7 @@ check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1); check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), "AMUv1", 1, 2); - check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(), + check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), "MPAM", 1, 17); check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), "NV2", 2, 2); @@ -184,11 +192,18 @@ check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), "TWED", 1, 1); + /* + * even though this is a "DISABLE" it does confusingly perform feature + * enablement duties like all other flags here. Check it against the HW + * feature when we intend to diverge from the default behaviour + */ + check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), "MTPMU", 1, 1); + /* v8.7 features */ check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), "HCX", 1, 1); /* v8.9 features */ - check_feature(ENABLE_FEAT_TCR2, read_feat_tcrx_id_field(), + check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), "TCR2", 1, 1); check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), "S2PIE", 1, 1); @@ -198,6 +213,8 @@ "S2POE", 1, 1); check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), "S1POE", 1, 1); + check_feature(ENABLE_FEAT_MTE_PERM, read_feat_mte_perm_id_field(), + "MTE_PERM", 1, 1); /* v9.0 features */ check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
diff --git a/docs/about/features.rst b/docs/about/features.rst index 4a2c77e..c12509d 100644 --- a/docs/about/features.rst +++ b/docs/about/features.rst
@@ -108,6 +108,28 @@ - Position-Independent Executable (PIE) support. +Experimental features +--------------------- + +A feature is considered experimental when still in development or isn't known +to the TF-A team as widely deployed or proven on end products. It is generally +advised such options aren't pulled into real deployments, or done with the +appropriate level of supplementary integration testing. + +A feature is no longer considered experimental when it is generally agreed +the said feature has reached a level of maturity and quality comparable to +other features that have been integrated into products. + +Experimental build options are found in following section +:ref:`build_options_experimental`. Their use through the build emits a warning +message. + +Additionally the following libraries are marked experimental when included +in a platform: + +- MPU translation library ``lib/xlat_mpu`` +- RSS comms driver ``drivers/arm/rss`` + Still to come -------------
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst index 02dae05..4531a03 100644 --- a/docs/about/maintainers.rst +++ b/docs/about/maintainers.rst
@@ -2,12 +2,11 @@ =================== Trusted Firmware-A (TF-A) is an open governance community project. All -contributions are ultimately merged by the maintainers listed below. Technical -ownership of most parts of the codebase falls on the code owners listed -below. An acknowledgement from these code owners is required before the -maintainers merge a contribution. +contributions are reviewed and merged by the community members listed below. -More details may be found in the `Project Maintenance Process`_ document. +For more details on the roles of `maintainers`, `code owners` and general +information about code reviews in TF-A project, please refer to the :ref:`Code +Review Guidelines`. .. |M| replace:: **Mail** .. |G| replace:: **GitHub ID** @@ -18,6 +17,10 @@ Maintainers ----------- +.. note:: + If you wish to become a maintainer for TF-A project, please refer to the + :ref:`Project Maintenance Processes`. + :|M|: Dan Handley <dan.handley@arm.com> :|G|: `danh-arm`_ :|M|: Soby Mathew <soby.mathew@arm.com> @@ -50,6 +53,8 @@ :|G|: `raghuncstate`_ :|M|: Manish Badarkhe <manish.badarkhe@arm.com> :|G|: `ManishVB-Arm`_ +:|M|: Yann Gautier <yann.gautier@st.com> +:|G|: `Yann-lms`_ LTS Maintainers --------------- @@ -62,6 +67,8 @@ :|G|: `bytefire`_ :|M|: Varun Wadekar <vwadekar@nvidia.com> :|G|: `vwadekar`_ +:|M|: Yann Gautier <yann.gautier@st.com> +:|G|: `Yann-lms`_ .. _code owners: @@ -191,12 +198,14 @@ JTAG DCC console driver ^^^^^^^^^^^^^^^^^^^^^^^ -:M: Michal Simek <michal.simek@amd.com> -:G: `michalsimek`_ -:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> -:G: `venkatesh`_ -:F: drivers/arm/dcc/ -:F: include/drivers/arm/dcc.h +:|M|: Michal Simek <michal.simek@amd.com> +:|G|: `michalsimek`_ +:|M|: Amit Nagal <amit.nagal@amd.com> +:|G|: `amit-nagal`_ +:|M|: Akshay Belsare <akshay.belsare@amd.com> +:|G|: `Akshay-Belsare`_ +:|F|: drivers/arm/dcc/ +:|F|: include/drivers/arm/dcc.h Power State Coordination Interface (PSCI) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -415,6 +424,15 @@ :|F|: lib/gpt_rme :|F|: include/lib/gpt_rme +Firmware Handoff Library (Transfer List) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Raymond Mao <raymond.mao@linaro.org> +:|G|: `raymo200915`_ +:|M|: Harrison Mutai <harrison.mutai@arm.com> +:|G|: `harrisonmutai-arm`_ +:|F|: lib/transfer_list +:|F|: include/lib/transfer_list.h + Platform Ports ~~~~~~~~~~~~~~ @@ -494,8 +512,8 @@ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> :|G|: `abdellatif-elkhlifi`_ -:|M|: Vishnu Banavath <vishnu.banavath@arm.com> -:|G|: `vishnu-banavath`_ +:|M|: Xueliang Zhong <xueliang.zhong@arm.com> +:|G|: `xueliang-zhong-arm`_ :|F|: plat/arm/board/corstone700 :|F|: plat/arm/board/a5ds :|F|: plat/arm/board/corstone1000 @@ -522,6 +540,15 @@ :|G|: `rupsin01`_ :|F|: plat/arm/board/tc +Aspeed platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Chia-Wei Wang <chiawei_wang@aspeedtech.com> +:|G|: `ChiaweiW`_ +:|M|: Neal Liu <neal_liu@aspeedtech.com> +:|G|: `Neal-liu`_ +:|F|: docs/plat/ast2700.rst +:|F|: plat/aspeed/ + HiSilicon HiKey and HiKey960 platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Haojian Zhuang <haojian.zhuang@linaro.org> @@ -569,6 +596,20 @@ :|F|: drivers/marvell/ :|F|: tools/marvell/ +Nuvoton npcm845x platform port +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com> +:|G|: `hilamirandakuzi1`_ +:|M|: Margarita Glushkin <rutigl@gmail.com> +:|G|: `rutigl`_ +:|M|: Avi Fishman <avi.fishman@nuvoton.com> +:|G|: `avifishman`_ +:|F|: docs/plat/npcm845x.rst +:|F|: drivers/nuvoton/ +:|F|: include/drivers/nuvoton/ +:|F|: include/plat/nuvoton/ +:|F|: plat/nuvoton/ + NVidia platform ports ^^^^^^^^^^^^^^^^^^^^^ :|M|: Varun Wadekar <vwadekar@nvidia.com> @@ -605,6 +646,13 @@ :|F|: docs/plat/imx8m.rst :|F|: plat/imx/imx8m/ +NXP i.MX9 platform port +^^^^^^^^^^^^^^^^^^^^^^^^ +:|M|: Jacky Bai <ping.bai@nxp.com> +:|G|: `JackyBai`_ +:|F|: docs/plat/imx9.rst +:|F|: plat/imx/imx93/ + NXP QorIQ Layerscape common code for platform ports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ :|M|: Pankaj Gupta <pankaj.gupta@nxp.com> @@ -684,7 +732,10 @@ :|M|: Nikita Travkin <nikita@trvn.ru> :|G|: `TravMurav`_ :|F|: docs/plat/qti-msm8916.rst +:|F|: plat/qti/mdm9607/ +:|F|: plat/qti/msm8909/ :|F|: plat/qti/msm8916/ +:|F|: plat/qti/msm8939/ Raspberry Pi 3 platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -708,8 +759,6 @@ Renesas rcar-gen3 platform port ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -:|M|: Jorge Ramirez-Ortiz <jramirez@baylibre.com> -:|G|: `ldts`_ :|M|: Marek Vasut <marek.vasut@gmail.com> :|G|: `marex`_ :|F|: docs/plat/rcar-gen3.rst @@ -749,6 +798,7 @@ ^^^^^^^^^^^^^^^^^^^^^^ :|M|: Yann Gautier <yann.gautier@st.com> :|G|: `Yann-lms`_ +:|F|: docs/plat/st/* :|F|: docs/plat/stm32mp1.rst :|F|: drivers/st/ :|F|: fdts/stm32\* @@ -781,8 +831,10 @@ ^^^^^^^^^^^^^^^^^^^^ :|M|: Michal Simek <michal.simek@amd.com> :|G|: `michalsimek`_ -:|M|: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> -:|G|: `venkatesh`_ +:|M|: Amit Nagal <amit.nagal@amd.com> +:|G|: `amit-nagal`_ +:|M|: Akshay Belsare <akshay.belsare@amd.com> +:|G|: `Akshay-Belsare`_ :|F|: docs/plat/xilinx\* :|F|: plat/xilinx/ @@ -916,7 +968,6 @@ .. _jwerner-chromium: https://github.com/jwerner-chromium .. _kostapr: https://github.com/kostapr .. _lachitp: https://github.com/lachitp -.. _ldts: https://github.com/ldts .. _marex: https://github.com/marex .. _masahir0y: https://github.com/masahir0y .. _michalsimek: https://github.com/michalsimek @@ -946,7 +997,6 @@ .. _TonyXie06: https://github.com/TonyXie06 .. _TravMurav: https://github.com/TravMurav .. _vwadekar: https://github.com/vwadekar -.. _venkatesh: https://github.com/vabbarap .. _Yann-lms: https://github.com/Yann-lms .. _manish-pandey-arm: https://github.com/manish-pandey-arm .. _mardyk01: https://github.com/mardyk01 @@ -978,5 +1028,13 @@ .. _bytefire: https://github.com/bytefire .. _rupsin01: https://github.com/rupsin01 .. _jimmy-brisson: https://github.com/theotherjimmy - -.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ +.. _ChiaweiW: https://github.com/chiaweiw +.. _Neal-liu: https://github.com/neal-liu +.. _amit-nagal: https://github.com/amit-nagal +.. _Akshay-Belsare: https://github.com/Akshay-Belsare +.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1 +.. _rutigl: https://github.com/rutigl +.. _avifishman: https://github.com/avifishman +.. _xueliang-zhong-arm: https://github.com/xueliang-zhong-arm +.. _raymo200915: https://github.com/raymo200915 +.. _harrisonmutai-arm: https://github.com/harrisonmutai-arm
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst index 0768e1f..654d65f 100644 --- a/docs/about/release-information.rst +++ b/docs/about/release-information.rst
@@ -25,6 +25,18 @@ code freeze ver w.x code freeze ver y.z +Version numbering +~~~~~~~~~~~~~~~~~ +TF-A version is given in Makefile, through several macros: + +- VERSION_MAJOR +- VERSION_MINOR +- VERSION_PATCH + +For example, TF-A v2.10 has VERSION_MAJOR=2, VERSION_MINOR=10 and VERSION_PATCH=0. + +This VERSION_PATCH macro is only increased for LTS releases. + Upcoming Releases ~~~~~~~~~~~~~~~~~ @@ -54,7 +66,7 @@ +-----------------+---------------------------+------------------------------+ | v2.9 | 4th week of May '23 | 2nd week of May '23 | +-----------------+---------------------------+------------------------------+ -| v3.0 | 2nd week of Nov '23 | 2nd week of Oct '23 | +| v2.10 | 4th week of Nov '23 | 2nd week of Nov '23 | +-----------------+---------------------------+------------------------------+ Removal of Deprecated Interfaces @@ -69,7 +81,9 @@ | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| None at this time | | | | +| Mbedtls-2.x | 2.10 | 2.10 | Support for TF-A builds with Mbedtls-2.x will be removed| ++--------------------------------+-------------+---------+---------------------------------------------------------+ +| STM32MP15_OPTEE_RSV_SHM | 2.10 | 3.0 | OP-TEE manages its own memory on STM32MP15 | +--------------------------------+-------------+---------+---------------------------------------------------------+ Removal of Deprecated Drivers @@ -84,9 +98,7 @@ | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| CryptoCell-712 | 2.9 | 3.0 | No longer maintained. | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| CryptoCell-713 | 2.9 | 3.0 | No longer maintained. | +| None at this time. | | | | +--------------------------------+-------------+---------+---------------------------------------------------------+ --------------
diff --git a/docs/change-log.md b/docs/change-log.md index b660c73..cfc8c56 100644 --- a/docs/change-log.md +++ b/docs/change-log.md
@@ -3,6 +3,985 @@ This document contains a summary of the new features, changes, fixes and known issues in each release of Trusted Firmware-A. +## [2.10.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.9.0..refs/tags/v2.10.0) (2023-11-21) + +### âš BREAKING CHANGES + +- **Architecture** + + - **Performance Monitors Extension (FEAT_PMUv3)** + + - This patch explicitly breaks the EL2 entry path. It is + currently unsupported. + + **See:** convert FEAT_MTPMU to C and move to persistent register init ([83a4dae](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83a4dae1af916b938659b39b7d0884359c638185)) + +- **Libraries** + + - **EL3 Runtime** + + - **Context Management** + + - Initialisation code for handoff from EL3 to NS-EL1 + disabled by default. Platforms which do that need to enable this macro + going forward + + **See:** introduce INIT_UNUSED_NS_EL2 macro ([183329a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/183329a5847df2bc6164ac8e9dbe7de4ca92836d)) + +- **Drivers** + + - **Authentication** + + - remove CryptoCell-712/713 support + + **See:** remove CryptoCell-712/713 support ([b65dfe4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b65dfe40aef550ee9ef7e869749013cb7f3c4cce)) + +### New Features + +- **Architecture** + + - **CPU feature / ID register handling in general** + + - add AArch32 PAN detection support ([d156c52](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d156c5220adb35971aafa0b0de922992e4b8aa66)) + - add memory retention bit define for CLUSTERPWRDN ([278beb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/278beb894aeda23278a01c3c6aff1f40b8ce0a34)) + - deny AArch64-only features when building for AArch32 ([733d112](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/733d112f05ecb29f7d8fce12c66a9721031970df)) + - initialize HFG*_EL2 registers ([4a530b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a530b4c6556c87deb22c027dfaf2c5d6c9997a3)) + + - **Memory Tagging Extension** + + - adds feature detection for MTE_PERM ([4d0b663](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d0b66323b242323ff738431c523aeb6d18dd3d5)) + + - **Performance Monitors Extension (FEAT_PMUv3)** + + - introduce pmuv3 lib/extensions folder ([c73686a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c73686a11cea8f9d22d7df3c5480f8824cfeec09)) + +- **Platforms** + + - **Allwinner** + + - use reset through scpi for warm/soft reset ([0cf5f08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0cf5f08a205e4877c9daef5d90e1086643590226)) + + - **Arm** + + - add IO policy to use backup gpt header ([3e6d245](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e6d245772ccb4b43f1ba6cd9d1bb8abe86a516c)) + - ecdsa p384/p256 full key support ([b8ae689](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b8ae68908de5560436c565ac22d59c0cbfc9a7df)) + - enable FHI PPI interrupt to report CPU errors ([f1e4a28](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1e4a28d3f9e4c5e7905f44d41c13de63d735864)) + - reuse SPM_MM specific defines for SPMC_AT_EL3 ([5df1dcc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5df1dccd0be06cc45e82a57dc01be5b6b5d1a21b)) + - save BL32 image base and size in entry point info ([821b01f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/821b01fa7521c0d6a0f16d02929fac3c44d14f86)) + - add memory map entry for CPER memory region ([4dc91ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4dc91ac9069271325ffd3552a6a146256f5d0da3)) + - firmware first error handling support for base RAMs ([5b77a0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b77a0e6759733d8a7de86e4492bd9b8628282d5)) + - update common platform RAS implementation ([7f15131](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f15131df42a42fef86cc594a56b6e7998dd2ba4)) + + - **FVP** + + - add mbedtls_asn1_get_len symbol in ROMlib ([0605060](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06050601d2a0ff06f92ca30ab988cbaf4e9929a1)) + - add public key-OID information in RSS metadata structure ([bfbb1cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfbb1cbaac3e74da37d906c9ce1d39993dce8b66)) + - add spmd logical partition ([5cf311f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cf311f3a41fc114289265305a6254a8fb412c0e)) + - allow configurable FVP Trusted SRAM size ([41e56f4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/41e56f422df47b8bc1a7699ff258999f900a6290)) + - capture timestamps in bl stages ([ed8f06d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed8f06ddda52bc0333f79e9ff798419e67771ae5)) + - implement platform function to measure and publish Public Key ([db55d23](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/db55d23d34b687cf6ce79c0723fedf10ef7227be)) + - increase BL1 RW area for PSA_CRYPTO implementation ([ce18938](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce189383dc816cf1a48c1a94329c00f44d8acdc3)) + - mock support for CCA NV ctr ([02552d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02552d45e526766e000f3e3ae91ef381d402dab1)) + - new SiP call to set an interrupt pending ([2032401](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20324013b17706751ecdd68f57c0ab95c522ca7e)) + - spmd logical partition smc handler ([a1a9a95](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1a9a950713468a734ef3d8da210baf97f7c1071)) + + - **Juno** + + - add mbedtls_asn1_get_len symbol in ROMlib ([ec8ba97](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ec8ba97e4ffde486670cb5a22ec4aac01409d92e)) + + - **Morello** + + - add cpuidle support ([4f7330d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f7330dc78ee620b8564a4bbc1ca2f2ae4cd1d9e)) + - add support for I2S audio ([6bcbe43](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6bcbe437909d3779111e19774f911c625e98f1b3)) + - add TF-A version string to NT_FW_CONFIG ([f4e64d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4e64d1f5e8277013c35dbd8e056b8071942f759)) + - fdts: add CoreSight DeviceTree bindings ([3e6cfa7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e6cfa7bd05521935c7753401dad823d044bfa23)) + - set NT_FW_CONFIG properties for MCC, PCC and SCP version ([10fd85d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10fd85d8f4a8f338942616ed403a1e02a388a16f)) + + - **RD** + + - **RD-N2** + + - enable base element RAM RAS support on RD-N2 platform ([0288632](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02886326659db3e4f46c0abd10be91a2de82cc90)) + - add defines needed for spmc-el3 ([b4bed4b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b4bed4b769e907c8431b07f698da24660dfe0059)) + - add plat hook for memory transaction ([f99dcba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99dcbace7015169ac5d230b8007686d144962fb)) + - enable Neoverse N2 CPU error handling support ([e802748](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e80274880bf694fd0b0e869a6ceb67e95e547544)) + - introduce accessor function to obtain datastore ([f458934](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f45893426546703d9e21970889e6333ca30c0dd7)) + - introduce platform handler for Group0 interrupt ([c47d049](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c47d0491ed078cfa8ca400e182fd4a44acd8041a)) + + - **SGI** + + - remove RAS setup call from common code ([0f5e8eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f5e8eb4536e27f5fd99b1367b18710927b014b9)) + - firmware first error handling for Neoverse N2 CPU ([31d1e4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31d1e4ff8dd70dc0094ff44df0c1844d27430e77)) + - increase sp memmap size ([7c33bca](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c33bcab5973fb73b8278c674677663f5109948e)) + + - **TC** + + - define memory ranges for tc platform ([9be6b16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9be6b168fb482835a13ad39e7567721f74d513f9)) + - implement platform function to measure and publish Public Key ([eee9fb0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eee9fb02f7b2c29befa27a0f2f0b6cb966f6d7c5)) + - deprecate Arm TC1 FVP platform ([6a2b11c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a2b11c29da50eed969834f6c6ee97cdb90cb51e)) + + - **Aspeed** + + - **AST2700** + + - add Aspeed AST2700 platform support ([85f199b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85f199b774476706b21f793503b36d861cab0a14)) + + - **Intel** + + - add intel_rsu_update() to sip_svc_v2 ([e3c3a48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e3c3a48c85dd1478e311e2e773a22fecfda69ec5)) + - ccu driver for Agilex5 SoC FPGA ([02df499](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02df49900006ed44b4a0c239299dd45ca8509c17)) + - clock manager support for Agilex5 SoC FPGA ([1b1a3eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b1a3eb1edff99b49bb40ad4172073d04a230938)) + - cold/warm reset and smp support for Agilex5 SoC FPGA ([79626f4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79626f460f115cc32b0dbeb48e72828d2dbf662a)) + - ddr driver for Agilex5 SoC FPGA ([29461e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29461e4c880235532385c01f202e638fb5ba11de)) + - mailbox and SMC support for Agilex5 SoC FPGA ([8e59b9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e59b9f42374aaa641409b6469c8fe9245a33107)) + - memory controller support for Agilex5 SoC FPGA ([18adb4e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18adb4efa42946252b489d02f06cccb61ad0c867)) + - mmc support for Agilex5 SoC FPGA ([4a577da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4a577da6612ef6584695311e687ca00c57d68d53)) + - pinmux, peripheral and Handoff support for Agilex5 SoC FPGA ([fcbb5cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcbb5cf7eadb8b048149941b08f09d04a860fee0)) + - platform enablement for Agilex5 SoC FPGA ([7931d33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7931d3322dc137447981d261e900f5a62d2181ee)) + - power manager for Agilex5 SoC FPGA ([a8bf898](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8bf898f02185ed838d8039949800843146ab245)) + - reset manager support for Agilex5 SoC FPGA ([9b8d813](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9b8d813cc96173ce8ab7634dea17fb7f89b21626)) + - restructure sys mgr for Agilex ([6197dc9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6197dc98feba98c3e123256424d2d33d5de997b8)) + - restructure sys mgr for S10/N5X ([b653f3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b653f3caf0f5e624604564c8c89ac8f4b450ba20)) + - sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA ([ddaf02d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ddaf02d17142187d9f17acd4900aafa598666317)) + - setup SEU ERR read interface for FP8 ([91239f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/91239f2c05c5df041e4a570a9d29c0ccbc34269a)) + - system manager support for Agilex5 SoC FPGA ([7618403](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7618403110dad81c84822332225a7a687dc7f684)) + - uart support for Agilex5 SoC FPGA ([34971f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34971f816a777df5afb6672990b9eceda60e84b7)) + - vab support for Agilex5 SoC FPGA ([4754925](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4754925057b27d5992d4c913276602666d303b01)) + + - **MediaTek** + + - add APU bootup control smc call ([94a9e62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94a9e6243e3978b42017639dad93481267bcf6e4)) + - add APU watchdog timeout control ([baa0d45](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/baa0d45ced6b058681ade9213e30ab0e91f4f4fb)) + + - **MT8188** + + - add apusys ao devapc setting ([777e3b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/777e3b71bb0a37f98b4105af657d97c2afc2d0bc)) + - add backup/restore function when power on/off ([233d604](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/233d604f500b5693b0caa6bcfdf0e2f766fd4cbd)) + - add devapc setting of apusys rcx ([5986ae5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5986ae57aa4468b392d0f5fcb8b5bc04388fa3e2)) + - add DSB before udelay ([b254b98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b254b9815ee25c90264a2305940bc575910f55e4)) + - add emi mpu protection for APU secure memory ([176846a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/176846a50b73267ff787432f74a1d9607b57ed20)) + - add EMI MPU support for SCP and DSP ([013006f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/013006f1f889f5869502147af464e38619459463)) + - add support for SMC from OP-TEE ([34d9d61](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34d9d619f1c58549736b63aa5c5cddd7f171762e)) + - enable apusys domain remap ([b5900c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b5900c92a1579371ea6f40199c70673beb08b1ac)) + - enable apusys mailbox mpu protect ([ad7673a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad7673adef9bc5eaeef333ecaca8e85e82abe342)) + - increase TZRAM_SIZE from 192KB to 256KB ([aa1cb27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aa1cb279b62d82e3d6e7b6ec17b9eb71d598497e)) + - modify APU DAPC permission ([d06edab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d06edabfd14e0d196139fb1c780017f34366ae0d)) + - update return value in mtk_emi_mpu_sip_handler ([d07eee2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d07eee245b3fcc6b276969df34dc63ded1d4c8a2)) + + - **MT8195** + + - increase TZRAM ([4f79b67](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f79b67250641f67327c3e351d2f8339e8fd2d26)) + + - **NXP** + + - **i.MX** + + - add dummy 'plat_mboot_measure_key' function ([b9bceef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9bceef8eebf5c0f7f213921cca885a3f3c64ec1)) + + - **i.MX 8M** + + - add more dram pll setting ([8947404](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89474044a59d74cc088eb09292e99a3ca623fe33)) + - detect console base address during runtime ([df730d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/df730d94cb5850683371dd695e242a0c3817f070)) + - enable snvs privileged registers access ([8d150c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d150c9524b1459b61c9d881100e20da827c1bd0)) + - move the gpc reg & macro to a separate header file ([2a6ffa9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a6ffa99afb6091110231381d1263407e9d88c3f)) + + - **i.MX 8M Nano** + + - add workaround for errata ERR050362 ([8562564](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85625646692597ba8a1829efaadf56163450efaf)) + + - **i.MX 9** + + - **i.MX93** + + - add cpuidle and basic suspend support ([422d30c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/422d30c626beef689967b56d26a68f029e7b7cf9)) + - add OPTEE support ([27a0be7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/27a0be77a064cbc87aaefecbf45fe0a2b133b188)) + - add reset & poweroff support ([cf7ef4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf7ef4c762ddb573ffb6f1f434c04fdc52f6c2cf)) + - add the basic support ([2368d7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2368d7b157c169b84bc46d3d8a57d080507e81bd)) + - add the trdc driver ([2935291](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2935291009c2933714a027b7b5cd1c8e41f70aff)) + - allow SoC masters access to system TCM ([3d3b769](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d3b769a7c112bff9468dbb21e36ce44125a72c0)) + - protect OPTEE memory to secure access only ([f560f84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f560f843bdc0e33ef47918a6c10676fa6aff95ac)) + - update the ocram trdc config for did10 ([eb76a24](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb76a2416a9bd5239db7b55d846bd2a16eec417a)) + + - **QEMU** + + - add sdei support for QEMU ([cef76a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cef76a7c5df7056cb73667e4e0b83d022e1b50fa)) + - add "cortex-a710" cpu support ([4734a62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4734a62d2c22f5b6a1e2b0369248d42fb9eddd1b)) + - add "neoverse-n2" cpu support ([408f9cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/408f9cb485796a73c5b87da70644665a13c685e4)) + - add "neoverse-v1" cpu support ([6d8d7d2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d8d7d2380d5120b3235c6f00eddcab126c3d648)) + - add "neoverse-v1" cpu support ([214de62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/214de62c92b2fc4b7edda9d9d637b7a4c0ba1fa5)) + - add A55 cpu support for virt ([409c20c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/409c20c84dcfa61de68754152f331a7277609fb2)) + - add dummy plat_mboot_measure_key() BL1 function ([8e2fd6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e2fd6a84b17fde92cef48ecaccdc3b666ef0588)) + - add dummy plat_mboot_measure_key() function ([f0f11ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f0f11acd86650da04a41298acbf4ae38b7e25894)) + - implement firmware handoff on qemu ([322af23](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/322af23445fe7a86eaad335b8a0f2ed523f5c1df)) + + - **SBSA** + + - handle platform version ([c681d02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c681d02c6ce2652307a4fcef16bd5626135dfad9)) + - handle GIC base ([1e67b1b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1e67b1b17a1692dd653d31016ccd8fa18b5f8f67)) + - handle GIC ITS address ([4171e98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4171e981d13e6aa764c2520a2b513beafe449818)) + + - **QTI** + + - **MSM8916** + + - add port for MDM9607 ([78aac78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/78aac78ad246ac8a04e1946bb9cd41b5734ba909)) + - add port for MSM8909 ([cf0a75f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf0a75f04df8e90c7958304e6e0499a7d2e2519c)) + - add port for MSM8939 ([c28e96c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c28e96cd52f8fbdbbfd0bbc8bacef353ac65bfd6)) + - add SP_MIN port for AArch32 ([45b2bd0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45b2bd0acbf4678eb59d36eb0db7746f5286a868)) + - add Test Secure Payload (TSP) port ([6b8f9e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6b8f9e16a7849852abaf190f96130462f70eae17)) + - allow selecting which UART to use ([aad23f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/aad23f1a2c109fb853e498c17fa1e97fbdb6522c)) + - clear CACHE_LOCK for MMU-500 r2p0+ ([d9b0442](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d9b04423cfbf18cb510fb8e65ad02e7a1f4fe873)) + - initialize CCI-400 for multiple clusters ([1240dc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1240dc7ef11e850bdf7a4e66de3d858e26555842)) + - power on L2 caches for secondary clusters ([c822d26](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c822d26506a589d4fa017246eeb83627f2efb554)) + + - **ST** + + - add RCC registers list ([4cfbb84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4cfbb84aeb361d8e4d72f0b0652d02918168b55e)) + - allow AARCH64 compilation for common code ([dad7181](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dad718169815f7cec09144b770fc66c6d9c58d17)) + - introduce new platform STM32MP2 ([35527fb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/35527fb41829102083b488a5150c0c707c5ede15)) + - support gcc as linker ([7762531](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7762531216a599d98dcf88aef8f8e980e0db90ed)) + - update STM32MP DT files ([4c8e8ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c8e8ea772905c1420720a900dd3e7d94eefbc7e)) + + - **STM32MP1** + + - add FWU with boot from NOR-SPI ([dfbadfd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dfbadfd96b6f3d383e8f1c3c8b0c91ca2110ea2e)) + + - **STM32MP15** + + - disable OP-TEE shared memory ([fb1d3bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb1d3bd9330ce70f735a344dd4223faffb261118)) + + - **STM32MP2** + + - add console configuration ([87a940e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/87a940e027dd11d0ec03ec605f205374b18361ba)) + - generate stm32 file ([e5839ed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5839ed79e34b8aa8c7c94da8c79e8ee8a7467df)) + + - **Texas Instruments** + + - add TI-SCI query firmware capabilities command support ([7ab7828](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ab782801f8c78ae6a8293d25cad687c86a4ac4e)) + - query firmware for suspend capability ([ce1008f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ce1008fef1ace613bc36886fd1627164edfef245)) + - remove extra core counts in cluster 2 and 3 ([e986845](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9868458e6de2ffb3c08e2fafa444a812b895337)) + + - **Xilinx** + + - add support to get chipid ([0563601](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0563601f03f0404bbc57464d3458c07614f920ca)) + - clean macro names ([bfd0626](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfd0626554374dd94a0105a5633df0afeae731b1)) + - fix IPI calculation for Versal/NET ([69a5bee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/69a5bee4c3633fd963d97f90f3a98e95a640d2da)) + - move IPI related macros to plat_ipi.h ([b2258ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b2258ce30cf720d71b1022c9cbee135c879027c5)) + - remove crash console unused macros ([473ada6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/473ada6be65af7fdad85845336f42ed481eea11b)) + - setup local/remote id in header ([068b0bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/068b0bc6e39f1fc18f9450619942c711f860a7e2)) + - switch boot console to runtime ([9c1c8f0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c1c8f010143e179dee76381f3796f3801e6d220)) + - sync macro names ([04a4833](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04a483359fef61353d95619e84ec6b495b27adfb)) + - used console also as crash console ([3e6b96e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3e6b96e869238f21c8887b835c3bfed487dbe653)) + + - **Versal** + + - add support for SMCC ARCH SOC ID ([079c6e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/079c6e2403fd07db2b41f7c6e7e8c568467a2c6b)) + - add tsp support ([7ff4d4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ff4d4fbe58273541da86fa72786d4bd4604be9a)) + - ddr address reservation in dtb at runtime ([56d1857](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56d1857efc21cff5e75aa65bba21e333a8552d04)) + - enable assertion ([0375188](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0375188a3e114edf62a732e80ea0f08dde3bf0b0)) + - retrieval of console information from dtb ([7c36fbc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c36fbcc13793899390a01a9b4a623ff2fbf7ee1)) + + - **Versal NET** + + - add cluster check in handoff parameters ([01c8c6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/01c8c6a5542fbf09fa91bbdbc95b735bbc9f02d7)) + - add support for SMCC ARCH SOC ID ([1873e7f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1873e7f7d879c3d0aba54c3785df534b9a7037b7)) + - add the IPI CRC checksum macro support ([ba56b01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba56b012c8ba8e5c4e6f77ab8a921e494d040a44)) + - add tsp support ([639b367](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/639b3676cc30dcf3e3e4d478906e7f7f37a7f1e4)) + - ddr address reservation in dtb at runtime ([46a08aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/46a08aab4c56ad9e3f57b127a02fead1e6b8cf38)) + - enable assertion ([80cb4b1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/80cb4b14049c01df9a57cad9d1b94b10f904462f)) + - get the handoff params using IPI ([a36ac40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a36ac40c4e93e56380374301f558f508ad2cbf96)) + - remove empty crash console setup ([6a14246](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a14246ad469664b56f1fdb111433515ffcccaf6)) + - retrieval of console information from dtb ([a467e81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a467e813a362fae69484e70ecb26fd8b14489d38)) + + - **ZynqMP** + + - enable assertion ([2243ba3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2243ba3c38ae5bab894709a4e98f188815398ef1)) + - remove pm_ioctl_set_sgmii_mode api ([7414aaa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7414aaa1a1e31df66866f0e1c97ba7c9add2427f)) + - retrieval of console information from dtb ([3923462](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3923462239c9e54088bd5b01fd5df469b2758582)) + + - **Nuvoton** + + - added support for npcm845x chip ([edcece1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/edcece15c76423832fc1ffdb255528bf4c719516)) + +- **Bootloader Images** + + - **BL2** + + - add gpt support ([6ed98c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6ed98c45db01023d52a47eb4ede0ffb44de85f00)) + + - **BL31** + + - reuse SPM_MM specific defines for SPMC_AT_EL3 ([f5e1bed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f5e1bed2669cce46a1d7c6b8d3f8f884b4d589b3)) + + - **BL32** + + - print entry point before exiting SP_MIN ([94e1be2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94e1be2b2918d8e70ac33cc8551e913d75e86398)) + +- **Services** + + - **RME** + + - save PAuth context when RME is enabled ([13cc1aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/13cc1aa70a666bc8f768569e5481b3daf499b7d1)) + + - **RMMD** + + - enable SME for RMM ([f92eb7e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f92eb7e261bdaea54c10ad34451a7667a6eb4084)) + - pass SMCCCv1.3 SVE hint bit to RMM ([6788963](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/678896301b807cb1130ca27fa53acc66d57b855e)) + + - **RMM** + + - update RMI VERSION command as per EAC5 ([ade6000](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ade6000ff0b3aa41d581d5738ce42f5ea4d3b77d)) + + - **SPM** + + - separate StMM SP specifics to add support for a S-EL0 SP ([549bc04](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/549bc04f148f3b42ea0808b9ab0794a48d67007d)) + + - **EL3 SPMC** + + - add a flag to enable support to load SEL0 SP ([801cd3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/801cd3c84a7bb8a66c5a40de25e611ec6448239c)) + + - **SPMD** + + - add partition info get regs ([0b850e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b850e9e7c89667f9a12d49492a60baf44750dd9)) + - add spmd logical partitions ([890b508](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/890b5088203e990d683a9c837e976be62c6501aa)) + - el3 direct message API ([66bdfd6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66bdfd6e4e6d8e086a30397be6055dbb04846895)) + - get logical partitions info ([95f7f6d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/95f7f6d86a6aadc9d235684fd1aa57ddc4c56ea9)) + + - **ERRATA ABI** + + - add support for Cortex-X3 ([9c16521](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c16521606b1269ef13a69ec450b8d14ef92bde9)) + +- **Libraries** + + - **CPU Support** + + - add a concise way to implement AArch64 errata ([3f4c1e1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f4c1e1e7b976e6950cbcc4ddf8c32e989d837ac)) + - add a way to automatically report errata ([4f748cc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f748cc44cb12160dfca86d94a1075f38f7c99e4)) + - add errata framework helpers ([445f7b5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/445f7b5191992c760e1089f566b94473a0432a1e)) + - add more errata framework helpers ([94a75ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94a75ad456a8bda75ca1e4343f00be249a201a69)) + - add support for Gelas CPU ([02586e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/02586e0e28e590fbc5e8461cfdc03db08485c14f)) + - add support for hermes cpu ([a00e907](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a00e907696dd7dcae9ec221ea4ee49d4179a8e2a)) + - add support for Nevis CPU ([5497958](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/549795895cae55b11c1a7ce522aa6740de863fb4)) + - add support for Travis CPU ([a0594ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0594add2e2661a1b1e1f392bf015687004197bb)) + - conform DSU errata to errata framework PCS ([ee6d04d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee6d04d449d7a23840bab00f3d3ffd88c6c7bca6)) + - make revision procedure call optional ([4d22b0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d22b0e5ba01b423f9f5200e4702750102635145)) + - wrappers to propagate AArch32 errata info ([34c51f3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34c51f327d47653637cf3604b4cd20819e795f25)) + + - **EL3 Runtime** + + - modify vector entry paths ([d04c04a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d04c04a4e8d968f9f82de810a3c763474e3faeb7)) + + - **RAS** + + - reuse SPM_MM specific defines for SPMC_AT_EL3 ([6e92a82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e92a82c81d2b0e49df730f68c8312beec1d3b48)) + - use FEAT_IESB for error synchronization ([6597fcf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6597fcf169fa548d40f1e63391d12d207c491266)) + + - **Translation Tables** + + - detect 4KB and 16KB page support when FEAT_LPA2 is present ([bff074d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bff074dd941d4fb51d6abade5db4b636f977d6f7)) + + - **C Standard Library** + + - add %X to printf/snprintf ([483edc2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/483edc207a533a5eaf07fa1e2c47f29f1dc64e4a)) + - implement memcpy_s in lib ([f328bff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f328bff667c12099e82de6e94f3775a124ee78c7)) + + - **PSA** + + - interface with RSS for retrieving ROTPK ([50316e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/50316e226fbbe30b5eb4121225958a9b63e58bb1)) + + - **Firmware Handoff** + + - introduce firmware handoff library ([3ba2c15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ba2c15147cc0c86342a443cd0cbfab3d2931c06)) + - port BL31-BL33 interface to fw handoff framework ([94c90ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/94c90ac8168f4e257b67e138a53a2dbc612e4194)) + +- **Drivers** + + - **Authentication** + + - add CCA NV ctr to CCA CoT ([e3b1cc0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e3b1cc0c51c7b0bae6abd81e15e4c2a00442c5db)) + - add explicit entries for key OIDs ([0cffcdd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0cffcdd617986f0750b384620f5b960059d91fc9)) + - create a zero-OID for Subject Public Key ([9505d03](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9505d03e368d8e620c4defeb53dad846d5bc7e62)) + - ecdsa p384 key support ([557f7d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/557f7d806a62a460404f8d1bec84c9400585930b)) + - measure and publicise the Public Key ([9eaa5a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9eaa5a09ed5805ec6423bc751b4254fba19090c1)) + + - **mbedTLS** + + - update to 3.4.1 ([e686cdb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e686cdb450bbf01d42850457f83e45208a2655f8)) + - add deprecation notice ([267c106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/267c106f02e6996071985adbe695406a4978e97f)) + + - **mbedTLS-PSA** + + - initialise mbedtls psa crypto ([4eaaaa1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4eaaaa19299040cfee0585d7daa744dee716d398)) + - introduce PSA_CRYPTO build option ([5782b89](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5782b890d29646924d8bd3f46acdc73a6e02feb2)) + - mbedTLS PSA Crypto with ECDSA ([255ce97](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/255ce97d609a93ab5528a653735abc46c2627e8f)) + - register an ad-hoc PSA crypto driver ([38f8936](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/38f893692ad9b8edb5413f4b2b9cd15a9b485685)) + - use PSA crypto API during hash calculation ([484b586](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/484b58696d627c68869d86e2c401a9088392659e)) + - use PSA crypto API during signature verification ([eaa62e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eaa62e825e31fb22a6245d9a5ab9cf5c9f8c0e46)) + - use PSA crypto API for hash verification ([2ed061c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ed061c43525b8a9cd82b38d31277a8df594edd5)) + + - **Measured Boot** + + - introduce platform function to measure and publish Public Key ([2971bad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2971bad8d48c6f0ddb7436efd16375bd72ade6bd)) + + - **GUID Partition Tables Support** + + - add interface to init gpt ([f08460d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f08460dc085283f25fd6b5df792f263ccdf22421)) + - add support to use backup GPT header ([ad2dd65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ad2dd65871b4411c735271f98a4fa5102abb2a00)) + + - **Arm** + + - **Ethos-N** + + - update npu error handling ([4796d2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4796d2d9bb4a1c0ccaffa4f6b49dbb0f0304d1d1)) + + - **RSS** + + - set the signer-ID in the RSS metadata ([60861a0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/60861a04e06d98ba6a9ae984cc5565f064fac9d1)) + + - **ST** + + - **Clock** + + - allow aarch64 compilation of STGEN functions ([b1718c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b1718c6382cff096c46dd216b5c99586eb303d29)) + - stub fdt_get_rcc_secure_state ([19c3808](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19c38081d3cbb4062d8894e6c3ec3c4e1d01a767)) + + - **UART** + + - add AARCH64 stm32_console driver ([c6d070c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c6d070cdba2c9a37b2253354f4cc3ba7e127e35d)) + +- **Miscellaneous** + + - **AArch64** + + - add stack debug information to assembly routines ([f832885](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f8328853031ab6dfc57059ff181138babc7779a0)) + + - **DT Bindings** + + - add the STM32MP2 clock and reset bindings ([3ccb708](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ccb708ecede0858c3c8633942dd9ceec1511fa5)) + + - **FDTs** + + - **Morello** + + - add thermal framework ([0b22160](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b221603e909cd493feeaab96d9c6f5458c628a8)) + + - **STM32MP2** + + - add stm32mp257f-ev1 board ([9aa5371](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9aa5371f2fde18ed9ef466f3ee08e599bcdca2dd)) + - introduce stm32mp25 pinctrl files ([2c62cc4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c62cc4a879b3ca5414227a2ddcd965814f3d112)) + - introduce stm32mp25 SoCs family ([0dc283d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0dc283d29e4d962553046ea7ba30e90ea64f6d3d)) + + - **TBBR** + + - add image id for backup GPT ([1051606](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1051606c3df3b5a0ebd4e4dad1e5e4a57e2f4d69)) + - update PK_DER_LEN for ECDSA P-384 keys ([c1ec23d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1ec23dd60954582a9b5dd49e85b092e9ece0680)) + +- **Documentation** + + - introduce STM32MP2 doc ([ee5076f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee5076f9716591333f1f5aa73b02c130c57917db)) + - save BL32 image base and size in entry point info ([31dcf23](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31dcf2345172de50b098d7a080c65ee6faa87df8)) + - add a threat model for TF-A with Arm CCA ([4463541](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/446354122cea54255630d250064f5f889045acb0)) + - cover threats inherent to receiving data over UART ([348446a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/348446ad2a836f7fa0ab05cdf6142342a1c4a4b3)) + - add a section for experimental build options ([4885600](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48856003bfaf8c8d0ce7b29e2e1262f7f1dfbb5d)) + +- **Build System** + + - include plat header in fdt build ([e03dcc8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e03dcc8f5ee2c2c48732745c5c364951eb36ceec)) + - manage patch version in Makefile ([055ebec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/055ebeca1b642ae69885a95e3c102f95d567a11e)) + - march option selection ([7794d6c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7794d6c8f8c44acc14fbdc5ada5965310056be1e)) + - pass CCA NV ctr option to cert_create ([0f19b7a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f19b7aada428e0ca69d27ab016928b8fbc64a79)) + - .gitignore to include memory tools ([82257de](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82257de06df2f744b12907079d5224bd56704de1)) + - allow gcc linker on Aarch32 platforms ([cfe6767](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfe6767f7dd483f1bd76b2ba88a75809e013c5bd)) + - bump certifi to version 2023.7.22 ([6cbf432](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cbf43204f3ca7cc6db621652da182743748af3f)) + - convert tabs and ifdef comparisons ([72f027c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/72f027c335a9e20e479e0d684132401546685616)) + - convert tabs to spaces ([1ca73b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ca73b4f4a0f6929a6649b4eb12e4ce45644a892)) + - disable ENABLE_FEAT_MPAM for Aarch32 ([a07b459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a07b4590dd06c9e27ec6d403003bcf55afa9dc27)) + - include Cortex-A78AE cpu file for FVP ([b996db1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b996db168dcdac89245bb2cb60212e3e1b3ad061)) + - pass parameters through response files ([430be43](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/430be4396bbf779c9d2cac0ed8fefd07c7b8fde2)) + - remove duplicated include order ([c189adb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c189adbd5559a31078749fd3ddd483337ad609f6)) + - remove handling of mandatory options ([1ca902a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1ca902a537d622b9f7f53f872586120ae75e2603)) + +- **Tools** + + - **Firmware Image Package Tool** + + - add ability to build statically ([4d4fec2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d4fec281861066ab2249bc3db7c2decdd176f34)) + + - **Secure Partition Tool** + + - generate `ARM_BL2_SP_LIST_DTS` file from `sp_layout.json` ([20629b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20629b3153bccdda32116ed5c4861e61fa1fba95)) + + - **Certificate Creation Tool** + + - add new option for CCA NV ctr ([60753a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/60753a63290e255d6c4d34d0145ac00e8d69c9cf)) + - add pkcs11 engine support ([616b3ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/616b3ce27d9a8a83a189a16ff6a05698bc6df3c8)) + - ecdsa p384 key support ([c512c89](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c512c89cde91f10e1b283522ac956fa4da85a797)) + + - **Memory Mapping Tool** + + - add tabular memory use data ([d9d5eb1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d9d5eb138ded8d4abeaf0cd1341ddf451aa299b8)) + - add topological memory view ([cc60aba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc60aba227e74a171c924146a0b745450af72f3d)) + +### Resolved Issues + +- **Architecture** + + - **CPU feature / ID register handling in general** + + - move nested virtualization support to optionals ([8b2048c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b2048c1c019d799d1806926724c2fbbc399c4c1)) + + - **Memory Partitioning and Monitoring (MPAM) Extension (FEAT_MPAM)** + + - refine MPAM initialization and enablement process ([edebefb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/edebefbcbc01f4ab67a7838e0191736fd9ee0192)) + + - **Performance Monitors Extension (FEAT_PMUv3)** + + - make MDCR_EL3.MTPME=1 out of reset ([33815eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33815eb7194e662169676b2ce88ee4785aac9ccd)) + +- **Platforms** + + - register PLAT_SP_PRI only if not already registered ([bf01999](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bf01999aba3949e810b7c66d3a164c4e3a964bf8)) + + - **Arm** + + - add Event Log area behind Trustzone Controller ([d836df7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d836df71ea50e0863f7858f71b06653058e64140)) + - correct the SPMC_AT_EL3 condition ([a0ef1c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a0ef1c0ef030e8fee8ad8f8a5f4a0fa911403a7c)) + - fix GIC macros for GICv4.1 support ([f1df8f1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1df8f10c6906519c54483f1f7a67f5cc507ec31)) + - add RAS_FFH_SUPPORT check for RAS EHF priority ([1c01284](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1c012840cab6529edbbc1bc7e3bcba11477a6955)) + - do not program DSU CLUSTERPWRDN register ([3209b35](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3209b35d2a372e71b96f3efbd7631d32518dc9b7)) + + - **FPGA** + + - enable CPU features required for ARMv9.2 cores ([b321c24](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b321c243423b9341bc04e839a795ff31247eacd5)) + + - **FVP** + + - adjust BL2 maximum size as per total SRAM size ([965aace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/965aacea919525baa03308a5a08205e506be0bf4)) + - adjust BL31 maximum size as per total SRAM size ([24e224b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24e224b41cc6fda4b507861cf8e409d8e4a3f7cd)) + - conditionally increase XLAT and MMAP table entries ([03cf4e9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03cf4e9aad2774ce221ccfe6f345ffcc8aabee4a)) + - extract core id from mpidr for pwrc operations ([70bc744](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70bc74441b9901ee91ebb32be1def1e645374488)) + - increase maximum MMAP and XLAT entries count ([12fe591](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12fe591b3e05255c167c5a9e21eaac2a9946f55c)) + - increase the maximum size of Event Log ([f1dfaa4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1dfaa42cf1a93523501ce694260d88acee7c0c0)) + - resolve broken workaround reference ([bcb3ea9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcb3ea92f8626e48340bd65c7c3007953e0ee8f4)) + - update pwr_domain_suspend ([f51d277](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f51d277de3e5f84eafafb32596ca0b154d11c4d5)) + - update system suspend in OS-initiated mode ([e0ef05b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0ef05bb2c260e0441186dd8647dea531bb1daf3)) + + - **Morello** + + - configure platform specific secure SPIs ([80f8769](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/80f8769b26efcbce842d0ed62950603dfd83ef9b)) + + - **N1SDP** + + - configure platform specific secure SPIs ([7b0c95a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7b0c95abc8e399a4a676647f4cffffa7ed21b3e6)) + - fix spi_ids range for n1sdp multichip boot ([31f60a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31f60a968347497562b0129134928d7ac4767710)) + + - **SGI** + + - update PLAT_SP_PRI macro definition ([6f689a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f689a51a577f740b341744e62c667733a79df94)) + + - **TC** + + - Correct return type ([b0542b5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0542b58ca77b922cf879dfb7d38356b32399c56)) + - rename macro to match PSA spec ([1fc20d7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1fc20d7f523e5c4bafb23584b1309ca432307ea4)) + + - **Corstone-1000** + + - add cpu_helpers.S to platform.mk ([cb27274](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb27274c9964deab3b613a48c1f293c122126ee5)) + - modify boot device dependencies ([3ff5fc2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff5fc2b35638afea2fad3cd0c76dcadc1adb8c2)) + - removing the signature area ([5856a91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5856a91a641a4cd7403143bb90b098855a77ac16)) + + - **Aspeed** + + - **AST2700** + + - add device mapping for coherent memory ([cef2e92](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cef2e92568045da4e1d26a9ebfb38b0176b4ec33)) + + - **Broadcom** + + - fix misspelled header inclusion guard ([a9779c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a9779c11daa251abb9c523b4e01e6ef26c7d46fc)) + + - **Cadence** + + - update console flush uart driver ([e27bebb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e27bebb0fe84bf58eed1fb61a65da9280309f24e)) + + - **Intel** + + - fix ncore ccu snoop dvm enable bug ([106aa54](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/106aa54d922c8d0980c527530cbb417141fe3f83)) + - resolved coverity checking ([1af7bf7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1af7bf71c042add4f473c056f850a8a4792b6bbd)) + - update boot scratch cold register to use cold 8 ([655af4f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/655af4f49278476ebac6bb865e325eca865684f2)) + - update checking for memcpy and memset ([c418064](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c418064eb5ae2f223457e4a25a91f379e8cf5223)) + + - **MediaTek** + + - support saving/restoring GICR registers ([f73466e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f73466e9a2fe35fc31a7a58a2e24308a9db341d7)) + + - **NVIDIA** + + - **Tegra** + + - return correct error code for plat_core_pos_by_mpidr ([6bd79b1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6bd79b13f8a8566d047ff25da9110a887b4e36e7)) + + - **NXP** + + - **i.MX** + + - **i.MX 8M** + + - make IMX_BOOT_UART_BASE autodetection option more obvious ([101f070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/101f07022a0337b074c03e60078b94789bc766f6)) + - map BL32 memory only if SPD_opteed or SPD_trusty is enabled ([4827613](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4827613c9a8db6238e9411b508ef20bda3113146)) + + - **QEMU** + + - fix 32-bit builds with stack protector ([e57ca89](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e57ca899efe414bd685e89e335a21d15a25b04f8)) + + - **SBSA** + + - align FIP base to BL1 size ([408cde8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/408cde8a59080ac2caa11c4d99474b2ef09f90df)) + + - **QTI** + + - **SC7280** + + - update pwr_domain_suspend ([a43be0f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a43be0f61003df1d8cf01bd706d5af305428c022)) + - update system suspend in OS-initiated mode ([0a9270a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0a9270abe82b396bf6fa15c7eb39c3499452686a)) + + - **Renesas** + + - **R-Car** + + - add mandatory fields in 'reserved-memory' node ([f945498](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f945498faab3bd44f0f957931809de2f59517814)) + + - **R-Car 3** + + - fix CPG register code comment ([69c371b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/69c371bc16533eb97a1d9bc408f9f17da87ba641)) + - update Draak and Eagle board IDs ([281edfe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/281edfee02bc72d81aa4972d60216647f932f3df)) + + - **ST** + + - allow crypto lib compilation in aarch64 ([76e4fab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/76e4fab000825c4361b4b9843c6e0c2f4f6eb1fd)) + - enable RTC clock before accessing nv counter ([77ce6a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77ce6a561eae769419559632afa4d807a4fc33b6)) + - flush UART at the end of uart_read() ([a9cb7d0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a9cb7d002df4f09dce779b5b56640c2fdd77ba3b)) + - properly check LOADADDR ([9f72f5e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9f72f5eac81c23fe39415b2346b112f64fba8610)) + - reduce MMC block_buffer ([a2500ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a2500ab7aba27ed5d613718f5f15371bbe895ca6)) + - setting default KEY_SIZE ([6f3ca8a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f3ca8ada60addc601f685fa51619d2101d7406a)) + - update comment on encryption key ([5c506c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c506c73751cc3f51df88826b89b5f729d8955c5)) + - update dt_get_ddr_size() type ([2a4abe0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2a4abe0b37f8d1987019c3de30e3301d8f8958d7)) + + - **STM32MP1** + + - add void entry in plat_def_toc_entries ([8214ecd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8214ecdab22a72877dfff539eee31cfb92f36423)) + - properly check PSCI functions return ([241f874](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/241f8745459ae413ca22fcc0f1081da8de48796f)) + - use the BSEC nodes compatible for stm32mp13 ([2171bd9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2171bd9511258e7aebaa3ce2f9498093d3a3c63e)) + + - **Texas Instruments** + + - align static device region addresses to reduce MMU table count ([53a868f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53a868f676d9ad6ec37d69155241883b8e7bf0bf)) + - fix TISCI API changes during refactor ([d7a7135](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d7a7135d32a8c7da004c0c19b75bd4e2813f9759)) + - release lock in all TI-SCI xfer return paths ([e92375e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e92375e07cf54c2fbac6616e58116c98507ac177)) + - remove check for zero value in BL31 boot args ([44edd3b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44edd3bd7cfe1d5fb1599ab5eee9b81efea984e0)) + + - **Xilinx** + + - add headers to resolve compile time issue ([744d60a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/744d60aab4e0173e21564fde092884c10267a6cc)) + - dcache flush for dtb region ([93ed138](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93ed138006dc09e5b09222cabae8952dd5363ad2)) + - don't reserve 1 more byte ([c3b69bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3b69bf17bc0231b0dae613dc9e1e01e41f32236)) + - dynamic mmap region for dtb ([7ca7fb1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ca7fb1bf0873824531a6eee2da1214b61496b02)) + - remove clock_setrate and clock_getrate api ([e5955d7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5955d7c63291a736efe75fb93effbc3fefb19fb)) + - remove console error message ([f9820f2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f9820f21b8317fb3a08598452b252f7a6a2a4ad7)) + - update dtb when dtb address and tf-a ddr flow is used ([fdf8f92](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fdf8f929df078943c24154e25d9d7661139826b3)) + + - **DCC (Debug Communication Channel)** + + - add dcc console unregister function ([0936abe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0936abe9b235dd996e9466288415bb994acbbe8f)) + - enable DCC also for crash console ([c6d9186](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c6d9186f60a08b4a44b1ecf38071eacdc9553ef6)) + + - **Versal** + + - add missing irq mapping for wakeup src ([06b9c4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/06b9c4c87df0b2a052e4f3330b86cc572c7bf885)) + - fix BLXX memory limits for user defined values ([f123b91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f123b91fddfcc882577590bbf4a54e1497ef9a64)) + - make pmc ipi channel as secure ([96eaafa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/96eaafa3f855ea9e0b6ce13a44f37fa9f1026207)) + - type cast addresses to fix integer overflow ([bfe82cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfe82cff6f6ab8e557e7ad7db8eae573f1fb02f3)) + - use correct macro name for ocm base address ([56afab7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56afab73a852fd3e10e607d2d86dedc3bae3ff2d)) + + - **Versal NET** + + - add redundant call to avoid glitches ([cebb7cc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cebb7cc110e02281060ec854a28a3bee382d8efa)) + - change flag to increase security ([e8efb65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8efb65afb996c9832384c96b36aee3092b56a4b)) + - correct device node indexes ([66b5620](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/66b5620c873ef656f779a4c2d844b187ba474d9d)) + - don't clear pending interrupts ([fb73ea6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fb73ea6cc3f9f4f51195b416a0f803a72d81eff6)) + - fix BLXX memory limits for user defined values ([a80da38](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a80da3899a5eea6bc022c37101ac0b7d970846f7)) + - make pmc ipi channel as secure ([2c65b79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c65b79e256ea5ead117efeaa5d39c3e53c83bdc)) + - use correct macro name for uart baudrate ([e2ef1df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2ef1dfcdbef7e448e9dd96852ffb8489c187d34)) + + - **ZynqMP** + + - do not export apu_ipi ([237c5a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/237c5a74a295d6306529be024aaa3d6af4b32898)) + - fix BLXX memory limits for user defined values ([8ce2fbf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ce2fbffe37ddcab5071601f1b311ee82a56b7cc)) + - fix prepare_dtb() memory description ([3efee73](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3efee73d528578162b8eb046dce540f0c5f0041a)) + - fix sdei arm_validate_ns_entrypoint() ([3b3c70a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b3c70a418522176f3a55d8e266e3968f7d4f832)) + - handling of type el3 interrrupts ([e8d61f7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8d61f7d91901f577030f6a45a71cf389b96d9dc)) + - make zynqmp_devices structure smaller ([7e3e799](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e3e79995a3c02871211dd0e983fb6e886a9c518)) + - remove unused headers ([6288636](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62886363a16f0dcef3b6acdff0a96880cf9940ce)) + - resolve runtime error in TSP ([81ad3b1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81ad3b14b95e019eaa8d89d444680c14ede4d8ab)) + - type cast addresses to fix overflow issue ([9129163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/91291633a1c99736803f39edb21cad95a3517ee8)) + - validate clock_id to avoid OOB variable access ([abc79c2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abc79c275be764d76bd983837ffc487664182dac)) + + - **Nuvoton** + + - fix typo in platform.mk ([c7efb78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c7efb78f8edc8fa66bbe2f9bad390d29f6a43fb0)) + +- **Bootloader Images** + + - **BL2** + + - bl2 start address for RESET_TO_BL2+ENABLE_PIE ([d478ac1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d478ac16c9002114da1c4708a0efb083c494ce2f)) + + - **BL31** + + - resolve runtime console garbage in next stage ([889e3d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/889e3d1c68e37dc9f75ae432703fa8ffc7259546)) + + - **BL32** + + - always include arm_arch_svc in SP_MIN ([cd0786c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd0786c73e536a1d2507d77ce49e2ae2b8ee71a1)) + - avoid clearing argument registers in RESET_TO_SP_MIN case ([56055e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56055e87b0a756d4756a22ed26b855fbe7afe93c)) + + - **TSP** + + - fix destination ID in direct request ([ed23d27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed23d274fae0b2787421a1b2558d7c1e9ebb07ab)) + - flush uart console ([ae074b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae074b369a25747acf98a23389e9d67b39738c71)) + +- **Services** + + - **RME** + + - **RMMD** + + - enable sme using sme_enable_per_world ([c0e16d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0e16d30ab70c51737f7a01a6b365d27c1a94f3b)) + + - **SPM** + + - **EL3 SPM** + + - fix LSP direct message response ([c040621](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c040621dba5f4c097441e67c9fd99b9df174ba4e)) + - improve direct messaging validation ([48fe24c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48fe24c50cd4990a76f88e89b77e71b9a90aec6c)) + + - **EL3 SPMC** + + - avoid descriptor size calc overflow ([27c0242](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/27c02425089548786a18d355b15acccd51880676)) + - correctly account for emad_offset ([0c2583c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c2583c6fbfd03e70915554d4093e5f9148f3792)) + - fix incorrect CASSERT ([1dd79f9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1dd79f9e2316e5a7a78b0ad5a34ec50288338e6f)) + - only call spmc_shm_check_obj() on complete objects ([d781959](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d781959f81923bc3a59e77abd44df2fcc61f044e)) + - prevent total_page_count overflow ([2d4da8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d4da8e265660ce7580219b51d5e79fd99ce1458)) + - remove experimental flag ([630a06c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/630a06c4c64f3a6804dd633081190241b1e78484)) + - use uint64_t for 64-bit type ([43318e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/43318e4a4dcc79935150de75fe5dccbb615f4719)) + - use version-dependent minimum descriptor length ([52d8d50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52d8d506e715dbbeba0938cecd30ac6624d1dcfc)) + - validate descriptor headers ([56c052d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56c052d31126c93b3c6782ea8e0c3348b5299b75)) + - validate memory address alignment ([327b5b8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/327b5b8b74faedefc45e861c797197cf6fbd6def)) + - validate shmem descriptor alignment ([dd94372](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd94372d77ff107726a7be53318b5694f3309ddb)) + + - **SPMD** + + - coverity scan issues ([b04343f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b04343f3c912c8abc1a37b0ebe461ab574959ecd)) + - fix FFA_VERSION forwarding ([76d53ee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/76d53ee1aafca7ba908c7439670509107377b309)) + - perform G0 interrupt acknowledge and deactivation ([6c91fc4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6c91fc44580415aaca4cbd774d4373475f33deb2)) + - relax use of EHF with SPMC at S-EL2 ([bb6d0a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb6d0a174f76240728cd911130703e712520ce16)) + + - **ERRATA ABI** + + - added Neoverse N2 to Errata ABI list ([7e030b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e030b376329a0466ffe7676be215770bb46d10f)) + - fix the rev-var for Cortex-A710 ([5c8fcc0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c8fcc0ca7f5e6dc3aea947800e146fe0ffe9b84)) + - update the Cortex-A76 errata ABI struct ([92d5b50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/92d5b501d4ba7e00e2ddfd546dc90b786966a352)) + - update the Cortex-A78C errata ABI struct ([7f2caec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f2caecdbc64d1fbd34942285e1194e85c5e8614)) + - update the neoverse-N1 errata ABI struct ([56747a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56747a5caa50eedeb627795f1c37e0a14953c2bf)) + - update the Neoverse-N2 errata ABI struct ([80af87e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/80af87e476ec3dd1ad26d7a906da82268a29e2b5)) + +- **Libraries** + + - **CPU Support** + + - assert invalid cpu_ops obtained ([3f721c6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f721c6edd20cef11c241a3ef84d94c06f5bebb4)) + - check for SME presence in Gelas ([0bbd432](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bbd4329bf73b0da1ed69578c385dd36358e261e)) + - fix minor issue seen with a9 cpu ([af70470](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af704705c135f85b8b1eeda938e3dcdba3f6e561)) + - fix the rev-var for Cortex-A710 ([2bf7939](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2bf7939a7b313352deb6c6b77ee1316eff142a7c)) + - fix the rev-var of Cortex-X2 ([8ae66d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ae66d624e2f7cae9577ff8f99e0a45e21fb353d)) + - fix the rev-var of Neoverse-V1 ([ab2b56d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab2b56df266f73aa53ca348d7945b119e1ef71c7)) + - flush L2 cache for Cortex-A7/12/15/17 ([c5c160c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c5c160cdddd1c365a447c1fcd148fabb9014cce0)) + - integer suffix macro definition ([1a56ed4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a56ed4b357e9023637c74c39c6885c558a737d2)) + - reduce generic_errata_report()'s size ([f43e09a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f43e09a12e4f4f32185d3e2accceb65895d1f16b)) + - revert erroneous use of override_vector_table macro in Cortex-A73 ([9a0c812](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9a0c81257ff116b2ca33f5b6737e0a000fb7e551)) + - update the fix for Cortex-A78AE erratum 1941500 ([67a2ad1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/67a2ad171d1fb604d4cba8fa7f92ccb66d1ef3f9)) + - update the rev-var for Cortex-A78AE ([c814619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c814619a364aea3bd55b5ea238541864c0de7dab)) + - workaround for Cortex-A510 erratum 2080326 ([6e86475](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e86475d55fa2981bc342a0eb78b86be233d7718)) + - workaround for Cortex-A710 erratum 2742423 ([d7bc2cb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d7bc2cb4303088873a715bcaa2ac3e0096b9d7f2)) + - workaround for Cortex-X2 erratum 2742423 ([fe06e11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe06e118ab0837ff173f6b7e576dcc34b2d26bb1)) + - workaround for Cortex-X3 erratum 2070301 ([2454316](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2454316c2ae4411d0071d88c3db3c95598f12498)) + - workaround for Cortex-X3 erratum 2742421 ([5b0e443](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b0e4438d0e604e80ffff17d02e37cae0f4b2a8f)) + - workaround for Neoverse N2 erratum 2009478 ([74bfe31](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/74bfe31fd2c992d8e1e13bf396a9d5c136967ca5)) + - workaround for Neoverse N2 erratum 2340933 ([68085ad](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68085ad4827ac7daa39767d479d0565daa32cb47)) + - workaround for Neoverse N2 erratum 2346952 ([6cb8be1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cb8be17a53f4e11880ba13b78fca15895281cfe)) + - workaround for Neoverse N2 erratum 2743014 ([eb44035](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eb44035cdec5d47d7eb3c904c8e5d8443b9dfcba)) + - workaround for Neoverse N2 erratum 2779511 ([12d2806](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/12d28067c9e76a78b148ed6fb94faf96de5e8502)) + - workaround for Neoverse V2 erratum 2331132 ([8852fb5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8852fb5b7d94229475446c81cfa58851bc2204ff)) + - workaround for Neoverse V2 erratum 2719105 ([b011402](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b01140256b5c0620cbde8e98c0df0e95343a3c71)) + - workaround for Neoverse V2 erratum 2743011 ([58dd153](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/58dd153cc88e832a6b019f1d4c2e6d64986ea69d)) + - workaround for Neoverse V2 erratum 2779510 ([ff34264](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff342643bcfaf20d61148b90a068694fa1c44dca)) + - workaround for Neoverse V2 erratum 2801372 ([40c81ed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40c81ed5335191fbe32466e56aa4fb6db1da466c)) + + - **EL3 Runtime** + + - leverage generic interrupt controller helpers ([07f867b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07f867b12251235b8582bec38e9cf39a95703e77)) + - restrict lower el EA handlers in FFH mode ([6d22b08](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d22b089ffb1793d581fde4de76245397ad7d4ee)) + + - **Context Management** + + - make ICC_SRE_EL2 fixup generic to all worlds ([5e8cc72](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e8cc7278659820bcd64c243cbd89c131462314c)) + - set MDCR_EL3.{NSPBE, STE} explicitly ([99506fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99506face112410ae37cf617b6efa809b4eee0ee)) + + - **RAS** + + - remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT ([f87e54f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f87e54f73cfee5042df526af6185ac6d9653a8f5)) + - restrict ENABLE_FEAT_RAS to have only two states ([970a4a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/970a4a8d8c0d6894fe2fd483d06b6392639e8760)) + + - **PSCI** + + - add optional pwr_domain_validate_suspend to plat_psci_ops_t ([d348861](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d34886140c74c0afc48ab20e63523505fcfb4b7d)) + + - **SMCCC** + + - ensure that mpidr passed through SMC is valid ([e60c184](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e60c18471fc7488cc0bf1dc7eae3b43be77045a4)) + - pass SMCCCv1.3 SVE hint to internal flags ([b2d8517](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b2d851785f6c03cae4feb015fe69091582e18f5e)) + + - **Translation Tables** + + - fix defects on the xlat library reported by coverity scan ([2974ad8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2974ad87b8561706176e113e2ec4457c919cb99a)) + - set MAX_PHYS_ADDR to total mapped physical region ([1a38aaf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1a38aafbff93e478aa6f9e19af1ed76024062a73)) + +- **Drivers** + + - **Authentication** + + - allow hashes of different lengths ([22a5354](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/22a53545aa37c06a1ffd0f3c15e870b256a41cb7)) + - don't overwrite pk with converted pk when rotpk is hash ([1046b41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1046b41808b23b4079f04cad370646e05207ded5)) + + - **Measured Boot** + + - don't strip last non-0 char ([b85bcb8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b85bcb8ec92126c238572ed7d242115125e411e1)) + + - **MMC** + + - initialises response buffer with zeros ([b1a2c51](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b1a2c51a0820fce803431e6ee5bd078bb1a65b0d)) + + - **MTD** + + - **NAND** + + - reset the SLC NAND ([f4d765a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4d765a12815e3f4bd9c4dff5fd88661b3615114)) + + - **SPI NAND** + + - add Quad Enable management ([da7a33c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/da7a33cf2f27545d9d290ff0c2ee1ec333b061bb)) + + - **SCMI** + + - add parameter for plat_scmi_clock_rates_array ([ca9d6ed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ca9d6edc892165c38f1b2710b537c10d4a57062d)) + + - **UFS** + + - performs unsigned shift for doorbell ([e47d8a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e47d8a58b0d5745c943c36fad2ec8a98af709bea)) + - set data segment length ([9d6786c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9d6786cacee7c0eff33d1cec42c09c7002dd83d2)) + + - **Arm** + + - **GIC** + + - **GICv3** + + - map generic interrupt type to GICv3 group ([632e5ff](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/632e5ffeb8f50a98090065b63d9d071b72acd23c)) + - move invocation of gicv3_get_multichip_base function ([36704d0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36704d09c6b26045fe2d18530a020ed23d74593d)) + + - **GIC-600** + + - fix gic600 maximum SPI ID ([69ed7dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/69ed7dc2e964c66eb8ff926a63a47b701ae1f3c6)) + + - **Renesas** + + - **R-Car3** + + - update DDR setting ([138ddcb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/138ddcbf4d330d13a11576d973513014055f98c1)) + + - **ST** + + - **Clock** + + - disabling CKPER clock is not functional on stm32mp13 ([1bbcb58](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1bbcb58a69c4ee2ee13e9d5de4499438ca08b149)) + + - **Crypto** + + - do not read RNG data if it's not ready ([53092a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53092a7780fa3d1b926aae8666f1c5a19cb039f1)) + - use GENMASK_32 to define PKA registers masks ([379d77b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/379d77b3705b0f3a88332663bba956289cad5797)) + + - **DDR** + + - express memory size with size_t type ([b4e1e8f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b4e1e8fbf0dde5679d6b3717b8579f7a3343fdf8)) + + - **UART** + + - allow 64 bit compilation ([6fef0f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fef0f67e47b3b42fc9b5dbc55bdef00a970765d)) + - correctly check UART enabled in flush fonction ([a527380](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5273808aa1a4514f7849ca91b7859e15bf82bff)) + - skip console flush if UART is disabled ([b156d7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b156d7b1cca1542f0c1c6f5d4354c43e048dc4a0)) + +- **Miscellaneous** + + - **AArch32** + + - disable workaround discovery on aarch32 for now ([d1f2748](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1f2748ed25748237e894c68c5a163326a8c33b9)) + + - **FDTs** + + - **STM32MP1** + + - move /omit-if-no-ref/ to overlay files ([f351f91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f351f9110f29a33923780c40d0896832fdb0ac81)) + + - **STM32MP13** + + - correct the BSEC nodes compatible ([85c2ea8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/85c2ea8fd325797a44e814b575611aafae9e7613)) + - cosmetic fixes in PLL nodes ([8b82663](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b826636a39e0f20cc2c0557288b1eeab46fb923)) + + - **SDEI** + + - ensure that interrupt ID is valid ([a7eff34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a7eff3477dcf3624c74f5217419b1a27b7ebd2aa)) + + - **TBBR** + + - guard defines under MBEDTLS_CONFIG_FILE ([81c2e15](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81c2e1566dc4484c23d293961744489a9a6ea3f0)) + - unrecognised 'tos-fw-key-cert' option ([f1cb5bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1cb5bd19034407f2de7cad23f2cc52ca924e561)) + +- **Documentation** + + - match boot-order size to implementation ([fd1479d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fd1479d9194d3f3ec98d235e077c9d6e24276fa2)) + - add missing line in the fiptool command for stm32mp1 ([d526d00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d526d00a13f86bbd2c073c065b6e9aff339e1b41)) + - fix build errors for latexpdf ([443d6ea](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/443d6ea69992986f56246bcee44e537ab8dec069)) + - remove out-dated information about CI review comments ([74306b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/74306b2ac8971693d148b34d02c556d94b3e4926)) + - replace deprecated urls under tfa/docs ([5fdf198](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5fdf198c117a4b6dbcf5242f5136f7224ceff6ff)) + - update maintainers list ([9766f41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9766f41d3c4cae4cd515c2f9266bb7adb4725349)) + - updated certain Neoverse N2 erratum status in docs ([d6d34b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6d34b39132425dfa8c75352711c463d2989a216)) + - use rsvg-convert as the conversion backend ([c365476](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3654760033c08e7ffa9337e05c48336032eacb9)) + +- **Tools** + + - **Firmware Image Package Tool** + + - move juno plat_fiptool.mk ([570a230](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/570a23099c32cafcb63ecb6cc0516d76ea099daf)) + + - **Certificate Creation Tool** + + - fix key loading logic ([bb3b0c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bb3b0c0b09ff1d969ddd49b99642740ce2a07064)) + - key: Avoid having a temporary value for pkey in key_load ([ea6f845](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea6f8452f6eb561a0fa96a712da93fcdba40cd9c)) + + - **Memory Mapping Tool** + + - reintroduce support for GNU map files ([d0e3053](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0e3053c4f5b9d2bc70daf4db3c71f99c6da216d)) + ## [2.9.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.8.0..refs/tags/v2.9.0) (2023-05-16) ### âš BREAKING CHANGES
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst index 1061ca0..ee322ac 100644 --- a/docs/components/ffa-manifest-binding.rst +++ b/docs/components/ffa-manifest-binding.rst
@@ -91,7 +91,7 @@ - 0x2: 64k - boot-order - - value type: <u32> + - value type: <u16> - A unique number amongst all partitions that specifies if this partition must be booted before others. The partition with the smaller number will be booted first.
diff --git a/docs/components/platform-interrupt-controller-API.rst b/docs/components/platform-interrupt-controller-API.rst index 069c87b..4de39d1 100644 --- a/docs/components/platform-interrupt-controller-API.rst +++ b/docs/components/platform-interrupt-controller-API.rst
@@ -120,39 +120,39 @@ In case of Arm standard platforms using GIC, the implementation of the API writes to GIC *Priority Register* set interrupt priority. -Function: int plat_ic_has_interrupt_type(unsigned int type); [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Function: bool plat_ic_has_interrupt_type(unsigned int type); [optional] +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: Argument : unsigned int - Return : int + Return : bool This API should return whether the platform supports a given interrupt type. The parameter ``type`` shall be one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, or ``INTR_TYPE_NS``. In case of Arm standard platforms using GICv3, the implementation of the API -returns ``1`` for all interrupt types. +returns *true* for all interrupt types. -In case of Arm standard platforms using GICv2, the API always return ``1`` for +In case of Arm standard platforms using GICv2, the API always return *true* for ``INTR_TYPE_NS``. Return value for other types depends on the value of build option ``GICV2_G0_FOR_EL3``: - For interrupt type ``INTR_TYPE_EL3``: - - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns ``0``, indicating no support + - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns *false*, indicating no support for EL3 interrupts. - - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns ``1``, indicating support for + - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns *true*, indicating support for EL3 interrupts. - For interrupt type ``INTR_TYPE_S_EL1``: - - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns ``1``, indicating support for + - When ``GICV2_G0_FOR_EL3`` is ``0``, it returns *true*, indicating support for Secure EL1 interrupts. - - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns ``0``, indicating no support + - When ``GICV2_G0_FOR_EL3`` is ``1``, it returns *false*, indicating no support for Secure EL1 interrupts. Function: void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); [optional] @@ -306,4 +306,4 @@ -------------- -*Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/ras.rst b/docs/components/ras.rst index 8d00345..747367a 100644 --- a/docs/components/ras.rst +++ b/docs/components/ras.rst
@@ -10,6 +10,9 @@ Reference Manual and `RAS Supplement`_. The rest of this document assumes familiarity with architecture and terminology. +**IMPORTANT NOTE**: TF-A implementation assumes that if RAS extension is present +then FEAT_IESB is also implmented. + There are two philosophies for handling RAS errors from Non-secure world point of view. @@ -56,26 +59,87 @@ EA's originating/attributed to NS world are handled first in NS and Kernel navigates the std error records directly. -**KFH can be supported in a platform without TF-A being aware of it but there are few -corner cases where TF-A needs to have special handling, which is currently missing and -will be added in future** +- KFH is the default handling mode if platform does not explicitly enable FFH mode. +- KFH mode does not need any EL3 involvement except for the reflection of errors back + to lower EL. This happens when there is an error (EA) in the system which is not yet + signaled to PE while executing at lower EL. During entry into EL3 the errors (EA) are + synchronized causing async EA to pend at EL3. + +Error Syncronization at EL3 entry +================================= + +During entry to EL3 from lower EL, if there is any pending async EAs they are either +reflected back to lower EL (KFH) or handled in EL3 itself (FFH). + +|Image 1| TF-A build options ================== -- **ENABLE_FEAT_RAS**: Manage FEAT_RAS extension when switching the world. -- **RAS_FFH_SUPPORT**: Pull in necessary framework and platform hooks for Firmware first - handling(FFH) of RAS errors. +- **ENABLE_FEAT_RAS**: Enable RAS extension feature at EL3. +- **HANDLE_EA_EL3_FIRST_NS**: Required for FFH - **RAS_TRAP_NS_ERR_REC_ACCESS**: Trap Non-secure access of RAS error record registers. -- **RAS_EXTENSION**: Deprecated macro, equivalent to ENABLE_FEAT_RAS and RAS_FFH_SUPPORT - put together. +- **RAS_EXTENSION**: Deprecated macro, equivalent to ENABLE_FEAT_RAS and + HANDLE_EA_EL3_FIRST_NS put together. + +RAS internal macros + +- **FFH_SUPPORT**: Gets enabled if **HANDLE_EA_EL3_FIRST_NS** is enabled. RAS feature has dependency on some other TF-A build flags - **EL3_EXCEPTION_HANDLING**: Required for FFH -- **HANDLE_EA_EL3_FIRST_NS**: Required for FFH - **FAULT_INJECTION_SUPPORT**: Required for testing RAS feature on fvp platform +TF-A Tests +========== + +RAS functionality is regularly tested in TF-A CI using `RAS test group`_ which has multiple +configurations for testing lower EL External aborts. + +All the tests are written in TF-A tests which runs as NS-EL2 payload. + +- **FFH without RAS extension** + + *fvp-ea-ffh,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a-debug* + + Couple of tests, one each for sync EA and async EA from lower EL which gets handled in El3. + Inject External aborts(sync/async) which traps in EL3, FVP has a handler which gracefully + handles these errors and returns back to TF-A Tests + + Build Configs : **HANDLE_EA_EL3_FIRST_NS** , **PLATFORM_TEST_EA_FFH** + +- **FFH with RAS extension** + + Three Tests : + + - *fvp-ras-ffh,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi-debug* + + Inject an unrecoverable RAS error, which gets handled in EL3. + + - *fvp-ras-ffh,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi-debug* + + Inject uncontainable RAS errors which causes platform to panic. + + - *fvp-ras-ffh,fvp-ras-ffh-nested:fvp-tftf-fip.tftf-ras_ffh_nested-aemv8a.fi-debug* + + Test nested exception handling at El3 for synchronized async EAs. Inject an SError in lower EL + which remain pending until we enter EL3 through SMC call. At EL3 entry on encountering a pending + async EA it will handle the async EA first (nested exception) before handling the original SMC call. + +- **KFH with RAS extension** + + Couple of tests in the group : + + - *fvp-ras-kfh,fvp-ras-kfh:fvp-tftf-fip.tftf-aemv8a.fi-debug* + + Inject and handle RAS errors in TF-A tests (no El3 involvement) + + - *fvp-ras-kfh,fvp-ras-kfh-reflect:fvp-tftf-fip.tftf-ras_kfh_reflection-aemv8a.fi-debug* + + Reflection of synchronized errors from EL3 to TF-A tests, two tests one each for reflecting + in IRQ and SMC path. + RAS Framework ============= @@ -238,7 +302,7 @@ Enabling RAS support is a platform choice The RAS support in |TF-A| introduces a default implementation of -``plat_ea_handler``, the External Abort handler in EL3. When ``RAS_FFH_SUPPORT`` +``plat_ea_handler``, the External Abort handler in EL3. When ``ENABLE_FEAT_RAS`` is set to ``1``, it'll first call ``ras_ea_handler()`` function, which is the top-level RAS exception handler. ``ras_ea_handler`` is responsible for iterating to through platform-supplied error records, probe them, and when an error is @@ -277,3 +341,6 @@ *Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.* .. _RAS Supplement: https://developer.arm.com/documentation/ddi0587/latest +.. _RAS Test group: https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/group/tf-l3-boot-tests-ras?h=refs/heads/master + +.. |Image 1| image:: ../resources/diagrams/bl31-exception-entry-error-synchronization.png
diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst index 919eea5..f228e6b 100644 --- a/docs/components/realm-management-extension.rst +++ b/docs/components/realm-management-extension.rst
@@ -157,7 +157,7 @@ git clone https://git.trustedfirmware.org/TF-A/tf-a-tests.git cd tf-a-tests - make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 all pack_realm + make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 ENABLE_REALM_PAYLOAD_TESTS=1 all This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged and **sp_layout.json** in the **build/fvp/debug** directory.
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst index 6b57c0e..009ac28 100644 --- a/docs/components/rmm-el3-comms-spec.rst +++ b/docs/components/rmm-el3-comms-spec.rst
@@ -52,7 +52,7 @@ - ``RES0``: Bit 31 of the version number is reserved 0 as to maintain consistency with the versioning schemes used in other parts of RMM. -This document specifies the 0.1 version of Boot Interface ABI and RMM-EL3 +This document specifies the 0.2 version of Boot Interface ABI and RMM-EL3 services specification and the 0.2 version of the Boot Manifest. .. _rmm_el3_boot_interface: @@ -503,6 +503,10 @@ and it is the responsibility of RMM to preserve this or use this as a return argument. EL3 will always copy x0-x4 from Realm context to NS Context. +EL3 must save and restore the following as part of world switch: + #. EL2 system registers with the exception of ``zcr_el2`` register. + #. PAuth key registers (APIA, APIB, APDA, APDB, APGA). + EL3 will not save some registers as mentioned in the below list. It is the responsibility of RMM to ensure that these are appropriately saved if the Realm World makes use of them: @@ -510,10 +514,11 @@ #. FP/SIMD registers #. SVE registers #. SME registers - #. EL1/0 registers + #. EL1/0 registers with the exception of PAuth key registers as mentioned above. + #. zcr_el2 register. -It is the responsibility of EL3 that any other registers other than the ones mentioned above -will not be leaked to the NS Host and to maintain the confidentiality of the Realm World. +It is essential that EL3 honors this contract to maintain the Confidentiality and integrity +of the Realm world. SMCCC v1.3 allows NS world to specify whether SVE context is in use. In this case, RMM could choose to not save the incoming SVE context but must ensure
diff --git a/docs/components/secure-partition-manager-mm.rst b/docs/components/secure-partition-manager-mm.rst index 4cdb96c..d9b2b1b 100644 --- a/docs/components/secure-partition-manager-mm.rst +++ b/docs/components/secure-partition-manager-mm.rst
@@ -4,17 +4,10 @@ Foreword ======== -Two implementations of a Secure Partition Manager co-exist in the TF-A codebase: - -- SPM based on the FF-A specification (:ref:`Secure Partition Manager`). -- SPM based on the MM interface. - -Both implementations differ in their architectures and only one can be selected -at build time. - -This document describes the latter implementation where the Secure Partition Manager -resides at EL3 and management services run from isolated Secure Partitions at S-EL0. -The communication protocol is established through the Management Mode (MM) interface. +This document describes the implementation where the Secure Partition Manager +resides at EL3 and management services run from isolated Secure Partitions at +S-EL0. The communication protocol is established through the Management Mode +(MM) interface. Background ==========
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst index e61dc20..5d3adec 100644 --- a/docs/components/secure-partition-manager.rst +++ b/docs/components/secure-partition-manager.rst
@@ -152,6 +152,8 @@ exception level is set to S-EL1. ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine and exhaustive list of registers is visible at `[4]`_. +- **SPMC_AT_EL3_SEL0_SP**: this option enables the support to load SEL0 SP + when SPMC at EL3 support is enabled. - **SP_LAYOUT_FILE**: this option specifies a text description file providing paths to SP binary images and manifests in DTS format (see `Describing secure partitions`_). It @@ -203,6 +205,7 @@ Sample TF-A build command line when FEAT_SEL2 architecture extension is implemented and the SPMC is located at S-EL2: + .. code:: shell make \ @@ -220,6 +223,7 @@ Sample TF-A build command line when FEAT_SEL2 architecture extension is implemented, the SPMC is located at S-EL2, and enabling secure boot: + .. code:: shell make \ @@ -255,6 +259,22 @@ PLAT=fvp \ all fip +Sample TF-A build command line when the SPMC is located at EL3 and SEL0 SP is +enabled: + +.. code:: shell + + make \ + CROSS_COMPILE=aarch64-none-elf- \ + SPD=spmd \ + SPMD_SPM_AT_SEL2=0 \ + SPMC_AT_EL3=1 \ + SPMC_AT_EL3_SEL0_SP=1 \ + BL32=<path-to-tee-binary> \ + BL33=<path-to-bl33-binary> \ + PLAT=fvp \ + all fip + FVP model invocation ====================
diff --git a/docs/conf.py b/docs/conf.py index 371632a..d4e5423 100644 --- a/docs/conf.py +++ b/docs/conf.py
@@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (c) 2019-2021, Arm Limited. All rights reserved. +# Copyright (c) 2019-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -9,27 +9,34 @@ # # See the options documentation at http://www.sphinx-doc.org/en/master/config -import os # -- Project information ----------------------------------------------------- -project = 'Trusted Firmware-A' +project = "Trusted Firmware-A" +author = "Trusted Firmware-A contributors" +version = "2.10.0" +release = "2.10.0" # -- General configuration --------------------------------------------------- # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions = ['myst_parser', 'sphinx.ext.autosectionlabel', 'sphinxcontrib.plantuml'] +extensions = [ + "myst_parser", + "sphinx.ext.autosectionlabel", + "sphinxcontrib.plantuml", + "sphinxcontrib.rsvgconverter", +] # Add any paths that contain templates here, relative to this directory. -templates_path = ['_templates'] +templates_path = ["_templates"] # The suffix(es) of source filenames. -source_suffix = ['.md', '.rst'] +source_suffix = [".md", ".rst"] # The master toctree document. -master_doc = 'index' +master_doc = "index" # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -45,15 +52,16 @@ exclude_patterns = [".env", "env", ".venv", "venv"] # The name of the Pygments (syntax highlighting) style to use. -pygments_style = 'sphinx' +pygments_style = "sphinx" # Load the contents of the global substitutions file into the 'rst_prolog' -# variable. This ensures that the substitutions are all inserted into each page. -with open('global_substitutions.txt', 'r') as subs: - rst_prolog = subs.read() +# variable. This ensures that the substitutions are all inserted into each +# page. +with open("global_substitutions.txt", "r") as subs: + rst_prolog = subs.read() # Minimum version of sphinx required -needs_sphinx = '2.0' +needs_sphinx = "2.0" # -- Options for HTML output ------------------------------------------------- @@ -68,21 +76,21 @@ html_theme = "sphinx_rtd_theme" # The logo to display in the sidebar -html_logo = 'resources/TrustedFirmware-Logo_standard-white.png' +html_logo = "resources/TrustedFirmware-Logo_standard-white.png" # Options for the "sphinx-rtd-theme" theme html_theme_options = { - 'collapse_navigation': False, # Can expand and collapse sidebar entries - 'prev_next_buttons_location': 'both', # Top and bottom of the page - 'style_external_links': True # Display an icon next to external links + "collapse_navigation": False, # Can expand and collapse sidebar entries + "prev_next_buttons_location": "both", # Top and bottom of the page + "style_external_links": True, # Display an icon next to external links } # Path to _static directory -html_static_path = ['_static'] +html_static_path = ["_static"] # Path to css file relative to html_static_path html_css_files = [ - 'css/custom.css', + "css/custom.css", ] # -- Options for autosectionlabel -------------------------------------------- @@ -92,4 +100,13 @@ # -- Options for plantuml ---------------------------------------------------- -plantuml_output_format = 'svg_img' +plantuml_output_format = "svg_img" + +# -- Options for latexmk ---------------------------------------------------- + +latex_engine = "xelatex" +latex_elements = { + "maxlistdepth": "10", + "pointsize": "11pt", + "extraclassoptions": "openany" +}
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 758d62b..d03daf8 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst
@@ -53,7 +53,7 @@ errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` is for example ``A57`` for the ``Cortex_A57`` CPU. -Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to +Refer to :ref:`firmware_design_cpu_errata_implementation` for information on how to write errata workaround functions. All workarounds are disabled by default. The platform is responsible for @@ -117,7 +117,8 @@ - ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From - r0p4 and onwards, this errata is enabled by default in hardware. + r0p4 and onwards, this errata is enabled by default in hardware. Identical to + ``A53_DISABLE_NON_TEMPORAL_HINT``. - ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision @@ -334,26 +335,26 @@ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and it is still open. -For Cortex-A78 AE, the following errata build flags are defined : +For Cortex-A78AE, the following errata build flags are defined : - ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to - Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. + Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. - ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to - Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This + Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. - ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to - Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This - erratum is still open. + Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. + This erratum is still open. - ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to - Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This + Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. - ``ERRATA_A78_AE_2712574`` : This applies erratum 2712574 workaround to - Cortex-A78 AE CPU. This erratum affects system configurations that do not use + Cortex-A78AE CPU. This erratum affects system configurations that do not use an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. This erratum is still open. @@ -497,7 +498,8 @@ revision. It is still open. - ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 - CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. + CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of + the CPU. - ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. @@ -522,11 +524,31 @@ For Neoverse V2, the following errata build flags are defined : +- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2 + CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still + open. + - ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2 CPU, this affects system configurations that do not use and ARM interconnect IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed in r0p2. +- ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2 + CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in + r0p2. + +- ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2 + CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in + r0p2. + +- ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2 + CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in + r0p2. + +- ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2 + CPU, this affects all configurations. This needs to be enabled for revisions + r0p0 and r0p1. It has been fixed in r0p2. + For Cortex-A710, the following errata build flags are defined : - ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to @@ -551,7 +573,7 @@ - ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 - of the CPU and is still open. + and r2p1 of the CPU and is still open. - ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 @@ -590,6 +612,10 @@ interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and is still open. +- ``ERRATA_A710_2742423``: This applies errata 2742423 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and + r2p1 of the CPU and is still open. + - ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. @@ -597,47 +623,61 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. + +- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open. - ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 - CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1. - ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in r0p1. -- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 +- ``ERRATA_N2_2340933``: This applies errata 2340933 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in r0p1. +- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2 + CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU, + it is fixed in r0p3. + +- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open. + - ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in r0p1. +- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2 + CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed + in r0p3. + - ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed in r0p3. @@ -647,6 +687,10 @@ interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed in r0p3. +- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2 + CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed + in r0p3. + For Cortex-X2, the following errata build flags are defined : - ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 @@ -654,7 +698,7 @@ it is still open. - ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 - CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, + CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU, it is still open. - ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 @@ -689,12 +733,20 @@ This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is still open. +- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2 + CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the + CPU and is still open. + - ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU and is still open. For Cortex-X3, the following errata build flags are defined : +- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3 + CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of + the CPU and is still open. + - ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it is fixed in r1p1. @@ -703,6 +755,10 @@ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the CPU, it is still open. +- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to + Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and + r1p1. It is fixed in r1p2. + For Cortex-A510, the following errata build flags are defined : - ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to @@ -722,6 +778,11 @@ in r0p3. The issue is also present in r0p0 and r0p1 but there is no workaround for those revisions. +- ``ERRATA_A510_2080326``: This applies errata 2080326 workaround to + Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is + fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no + workaround for those revisions. + - ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index 14b273e..3fce393 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst
@@ -9,12 +9,12 @@ to the stage where it hands-off control to firmware running in the normal world in DRAM. This is the cold boot path. -TF-A also implements the `Power State Coordination Interface PDD`_ as a -runtime service. PSCI is the interface from normal world software to firmware -implementing power management use-cases (for example, secondary CPU boot, -hotplug and idle). Normal world software can access TF-A runtime services via -the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be -used as mandated by the SMC Calling Convention (`SMCCC`_). +TF-A also implements the `PSCI`_ as a runtime service. PSCI is the interface +from normal world software to firmware implementing power management use-cases +(for example, secondary CPU boot, hotplug and idle). Normal world software can +access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction. +The SMC instruction must be used as mandated by the SMC Calling Convention +(`SMCCC`_). TF-A implements a framework for configuring and managing interrupts generated in either security state. The details of the interrupt management framework @@ -25,12 +25,12 @@ :ref:`Translation (XLAT) Tables Library`. TF-A can be built to support either AArch64 or AArch32 execution state. -.. note:: - The descriptions in this chapter are for the Arm TrustZone architecture. - For changes to the firmware design for the - `Arm Confidential Compute Architecture (Arm CCA)`_ please refer to the - chapter :ref:`Realm Management Extension (RME)`. +.. note:: + The descriptions in this chapter are for the Arm TrustZone architecture. + For changes to the firmware design for the `Arm Confidential Compute + Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management + Extension (RME)`. Cold boot --------- @@ -130,6 +130,12 @@ - For other BL3x images, if the firmware configuration file is loaded by BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded then its address is passed in ``arg1``. + - In case SPMC_AT_EL3 is enabled, populate the BL32 image base, size and max + limit in the entry point information, since there is no platform function + to retrieve these in generic code. We choose ``arg2``, ``arg3`` and + ``arg4`` since the generic code uses ``arg1`` for stashing the SP manifest + size. The SPMC setup uses these arguments to update SP manifest with + actual SP's base address and it size. - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved from FW_CONFIG device tree. @@ -245,63 +251,6 @@ specific reset handler function (see the section: "CPU specific operations framework"). -- Control register setup (for AArch64) - - - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` - bit. Alignment and stack alignment checking is enabled by setting the - ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to - little-endian by clearing the ``SCTLR_EL3.EE`` bit. - - - ``SCR_EL3``. The register width of the next lower exception level is set - to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap - both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is - also set to disable instruction fetches from Non-secure memory when in - secure state. - - - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the - ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by - clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is - configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. - Instructions that access the registers associated with Floating Point - and Advanced SIMD execution are configured to not trap to EL3 by - clearing the ``CPTR_EL3.TFP`` bit. - - - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt - mask bit. - - - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and - ``MDCR_EL3.TPM``, are set so that accesses to the registers they control - do not trap to EL3. AArch64 Secure self-hosted debug is disabled by - setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to - disable AArch32 Secure self-hosted privileged debug from S-EL1. - -- Control register setup (for AArch32) - - - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. - Alignment checking is enabled by setting the ``SCTLR.A`` bit. - Exception endianness is set to little-endian by clearing the - ``SCTLR.EE`` bit. - - - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from - Non-secure memory when in secure state. - - - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, - by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality - is configured not to trap to undefined mode by clearing the - ``CPACR.TRCDIS`` bit. - - - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and - system register access to implemented trace registers. - - - ``FPEXC``. Enable access to the Advanced SIMD and floating-point - functionality from all Exception levels. - - - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing - the Asynchronous data abort interrupt mask bit. - - - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure - self-hosted privileged debug. - Platform initialization ^^^^^^^^^^^^^^^^^^^^^^^ @@ -457,8 +406,7 @@ memory with the entrypoint and Saved Program Status Register (``SPSR``) of the normal world software image. The entrypoint is the load address of the BL33 image. The ``SPSR`` is determined as specified in Section 5.13 of the -`Power State Coordination Interface PDD`_. This information is passed to the -EL3 Runtime Software. +`PSCI`_. This information is passed to the EL3 Runtime Software. AArch64 BL31 (EL3 Runtime Software) execution ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1009,8 +957,8 @@ The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification -`Power State Coordination Interface PDD`_ are implemented. The table lists -the PSCI v1.1 APIs and their support in generic code. +`PSCI`_ are implemented. The table lists the PSCI v1.1 APIs and their support +in generic code. An API implementation might have a dependency on platform code e.g. CPU_SUSPEND requires the platform to export a part of the implementation. Hence the level @@ -1176,6 +1124,65 @@ ``bl31_main()`` will set up the return to the normal world firmware BL33 and continue the boot process in the normal world. +Exception handling in BL31 +-------------------------- + +When exception occurs, PE must execute handler corresponding to exception. The +location in memory where the handler is stored is called the exception vector. +For ARM architecture, exception vectors are stored in a table, called the exception +vector table. + +Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base +of vector table. Refer to `AArch64 exception vector table`_ + +Current EL with SP_EL0 +~~~~~~~~~~~~~~~~~~~~~~ + +- Sync exception : Not expected except for BRK instruction, its debugging tool which + a programmer may place at specific points in a program, to check the state of + processor flags at these points in the code. + +- IRQ/FIQ : Unexpected exception, panic + +- SError : "plat_handle_el3_ea", defaults to panic + +Current EL with SP_ELx +~~~~~~~~~~~~~~~~~~~~~~ + +- Sync exception : Unexpected exception, panic + +- IRQ/FIQ : Unexpected exception, panic + +- SError : "plat_handle_el3_ea" Except for special handling of lower EL's SError exception + which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower + EL's EA is routed to EL3 (FFH_SUPPORT=1). + +Lower EL Exceptions +~~~~~~~~~~~~~~~~~~~ + +Applies to all the exceptions in both AArch64/AArch32 mode of lower EL. + +Before handling any lower EL exception, we synchronize the errors at EL3 entry to ensure +that any errors pertaining to lower EL is isolated/identified. If we continue without +identifying these errors early on then these errors will trigger in EL3 (as SError from +current EL) any time after PSTATE.A is unmasked. This is wrong because the error originated +in lower EL but exception happened in EL3. + +To solve this problem, synchronize the errors at EL3 entry and check for any pending +errors (async EA). If there is no pending error then continue with original exception. +If there is a pending error then, handle them based on routing model of EA's. Refer to +:ref:`Reliability, Availability, and Serviceability (RAS) Extensions` for details about +routing models. + +- KFH : Reflect it back to lower EL using **reflect_pending_async_ea_to_lower_el()** + +- FFH : Handle the synchronized error first using **handle_pending_async_ea()** after + that continue with original exception. It is the only scenario where EL3 is capable + of doing nested exception handling. + +After synchronizing and handling lower EL SErrors, unmask EA (PSTATE.A) to ensure +that any further EA's caused by EL3 are caught. + Crash Reporting in BL31 ----------------------- @@ -1302,8 +1309,9 @@ handling functions. Details for implementing a CPU specific reset handler can be found in -Section 8. Details for implementing a platform specific reset handler can be -found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). +:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a +platform specific reset handler can be found in the :ref:`Porting Guide` (see +the``plat_reset_handler()`` function). When adding functionality to a reset handler, keep in mind that if a different reset handling behavior is required between the first and the subsequent @@ -1397,12 +1405,38 @@ the platform makefile. The generic CPU specific operations framework code exists in ``lib/cpus/aarch64/cpu_helpers.S``. +CPU PCS +~~~~~~~ + +All assembly functions in CPU files are asked to follow a modified version of +the Procedure Call Standard (PCS) in their internals. This is done to ensure +calling these functions from outside the file doesn't unexpectedly corrupt +registers in the very early environment and to help the internals to be easier +to understand. Please see the :ref:`firmware_design_cpu_errata_implementation` +for any function specific restrictions. + ++--------------+---------------------------------+ +| register | use | ++==============+=================================+ +| x0 - x15 | scratch | ++--------------+---------------------------------+ +| x16, x17 | do not use (used by the linker) | ++--------------+---------------------------------+ +| x18 | do not use (platform register) | ++--------------+---------------------------------+ +| x19 - x28 | callee saved | ++--------------+---------------------------------+ +| x29, x30 | FP, LR | ++--------------+---------------------------------+ + +.. _firmware_design_cpu_specific_reset_handling: + CPU specific Reset Handling ~~~~~~~~~~~~~~~~~~~~~~~~~~~ After a reset, the state of the CPU when it calls generic reset handler is: -MMU turned off, both instruction and data caches turned off and not part -of any coherency domain. +MMU turned off, both instruction and data caches turned off, not part +of any coherency domain and no stack. The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow the platform to perform any system initialization required and any system @@ -1412,10 +1446,9 @@ in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in the returned ``cpu_ops`` is then invoked which executes the required reset handling for that CPU and also any errata workarounds enabled by the platform. -This function must preserve the values of general purpose registers x20 to x29. -Refer to Section "Guidelines for Reset Handlers" for general guidelines -regarding placement of code in a reset handler. +It should be defined using the ``cpu_reset_func_{start,end}`` macros and its +body may only clobber x0 to x14 with x14 being the cpu_rev parameter. CPU specific power down sequence ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1448,10 +1481,10 @@ be reported and a pointer to the ASCII list of register names in a format expected by the crash reporting framework. -.. _firmware_design_cpu_errata_reporting: +.. _firmware_design_cpu_errata_implementation: -CPU errata status reporting -~~~~~~~~~~~~~~~~~~~~~~~~~~~ +CPU errata implementation +~~~~~~~~~~~~~~~~~~~~~~~~~ Errata workarounds for CPUs supported in TF-A are applied during both cold and warm boots, shortly after reset. Individual Errata workarounds are enabled as @@ -1459,59 +1492,92 @@ therefore some are enabled by default, others not. Platform ports shall override build options to enable or disable errata as appropriate. The CPU drivers take care of applying errata workarounds that are enabled and applicable -to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more -information. +to a given CPU. -Functions in CPU drivers that apply errata workaround must follow the -conventions listed below. +Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form: +``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in +:ref:`arm_cpu_macros_errata_workarounds` on when it should apply. -The errata workaround must be authored as two separate functions: +Errata framework +^^^^^^^^^^^^^^^^ -- One that checks for errata. This function must determine whether that errata - applies to the current CPU. Typically this involves matching the current - CPUs revision and variant against a value that's known to be affected by the - errata. If the function determines that the errata applies to this CPU, it - must return ``ERRATA_APPLIES``; otherwise, it must return - ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and - ``cpu_rev_var_ls`` functions may come in handy for this purpose. +The errata framework is a convention and a small library to allow errata to be +automatically discovered. It enables compliant errata to be automatically +applied and reported at runtime (either by status reporting or the errata ABI). -For an errata identified as ``E``, the check function must be named -``check_errata_E``. +To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that +declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things: -This function will be invoked at different times, both from assembly and from -C run time. Therefore it must follow AAPCS, and must not use stack. +#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>`` -- Another one that applies the errata workaround. This function would call the - check function described above, and applies errata workaround if required. + It should check whether this erratum applies on this revision of this CPU. + It will be called with the CPU revision as its first parameter (x0) and + should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``. -CPU drivers that apply errata workaround can optionally implement an assembly -function that report the status of errata workarounds pertaining to that CPU. -For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` -macro, the errata reporting function, if it exists, must be named -``cpux_errata_report``. This function will always be called with MMU enabled; it -must follow AAPCS and may use stack. + It may only clobber x0 to x4. The rest should be treated as callee-saved. + +#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa`` + + It should obtain the cpu revision (with ``cpu_get_rev_var``), call its + revision checker, and perform the mitigation, should the erratum apply. + + It may only clobber x0 to x8. The rest should be treated as callee-saved. + +#. Register itself to the framework + + Do this with + ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>`` + where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described + above. + +See the next section on how to do this easily. + +.. note:: + + CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the + ``erratum_id`` for the checker and the workaround functions become the + ``number`` part of its name and the ``ERRATUM(<number>)`` part of the + registration should instead be ``CVE(<year>, <number>)``. In the extremely + unlikely scenario where a CVE and an erratum numbers clash, the CVE number + should be prefixed with a zero. + + Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``. + +.. note:: + + AArch32 uses the legacy convention. The checker function has the format + ``check_errata_<erratum_id>`` and the workaround has the format + ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform + letter and number name of the CPU. + + For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``. + +Errata framework helpers +^^^^^^^^^^^^^^^^^^^^^^^^ + +Writing these errata involves lots of boilerplate and repetitive code. On +AArch64 there are helpers to omit most of this. They are located in +``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement +errata. Please see their comments on how to use them. + +The most common type of erratum workaround, one that just sets a "chicken" bit +in some arbitrary register, would have an implementation for the Cortex-A77, +erratum #1925769 like:: + + workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 + sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 + workaround_reset_end cortex_a77, ERRATUM(1925769) + + check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) + +Status reporting +^^^^^^^^^^^^^^^^ In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the -runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata -status reporting function, if one exists, for that type of CPU. - -To report the status of each errata workaround, the function shall use the -assembler macro ``report_errata``, passing it: - -- The build option that enables the errata; - -- The name of the CPU: this must be the same identifier that CPU driver - registered itself with, using ``declare_cpu_ops``; - -- And the errata identifier: the identifier must match what's used in the - errata's check function described above. - -The errata status reporting function will be called once per CPU type/errata -combination during the software's active life time. - -It's expected that whenever an errata workaround is submitted to TF-A, the -errata reporting function is appropriately extended to report its status as -well. +runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic +errata status reporting function. It will read the ``errata_entries`` list of +that cpu and will report whether each known erratum was applied and, if not, +whether it should have been. Reporting the status of errata workaround is for informational purpose only; it has no functional significance. @@ -1616,8 +1682,10 @@ - ``__RO_START__`` - ``__RO_END__`` - ``__TEXT_START__`` +- ``__TEXT_END_UNALIGNED__`` - ``__TEXT_END__`` - ``__RODATA_START__`` +- ``__RODATA_END_UNALIGNED__`` - ``__RODATA_END__`` BL1's linker symbols @@ -2633,19 +2701,17 @@ architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included and unconditionally enabled by TF-A build system. -- Passed to compiler via "-march" option to generate binary target : Tell the - compiler to emit instructions upto ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` +- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility + this will try to come up with an appropriate -march value to be passed to compiler + by probing the compiler and checking what's supported by the compiler and what's best + that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used + directly and compiler probing will be skipped. The build system requires that the platform provides a valid numeric value based on CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. Subsequent Arm Architecture versions also support extensions which were introduced in previous versions. -**TO-DO** : Its planned to decouple the two functionalities and introduce a new macro -for compiler usage. The requirement for this decoupling arises becasue TF-A code -always provides support for the latest and greatest architecture features but this -is not the case for the target compiler. - .. seealso:: :ref:`Build Options` For details on the Architecture Extension and available features, please refer @@ -2730,12 +2796,12 @@ the toolchain target architecture directive. Platform may choose to not define straight the toolchain target architecture -directive by defining ``MARCH32_DIRECTIVE``. +directive by defining ``MARCH_DIRECTIVE``. I.e: .. code:: make - MARCH32_DIRECTIVE := -mach=armv7-a + MARCH_DIRECTIVE := -march=armv7-a Code Structure -------------- @@ -2786,7 +2852,7 @@ - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ -- `Power State Coordination Interface PDD`_ +- `PSCI`_ - `SMC Calling Convention`_ @@ -2796,13 +2862,12 @@ *Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* -.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _SMCCC: https://developer.arm.com/docs/den0028/latest -.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf -.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf +.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ .. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest .. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a .. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture +.. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table .. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png
diff --git a/docs/design/trusted-board-boot.rst b/docs/design/trusted-board-boot.rst index 46177d7..fed202a 100644 --- a/docs/design/trusted-board-boot.rst +++ b/docs/design/trusted-board-boot.rst
@@ -216,10 +216,11 @@ The ``cert_create`` tool is built and runs on the host machine as part of the TF-A build process when ``GENERATE_COT=1``. It takes the boot loader images -and keys as inputs (keys must be in PEM format) and generates the -certificates (in DER format) required to establish the CoT. New keys can be -generated by the tool in case they are not provided. The certificates are then -passed as inputs to the ``fiptool`` utility for creating the FIP. +and keys as inputs and generates the certificates (in DER format) required to +establish the CoT. The input keys must either be a file in PEM format or a +PKCS11 URI in case a HSM is used. New keys can be generated by the tool in +case they are not provided. The certificates are then passed as inputs to +the ``fiptool`` utility for creating the FIP. The certificates are also stored individually in the output build directory.
diff --git a/docs/design_documents/index.rst b/docs/design_documents/index.rst index d20fc58..ecc68b2 100644 --- a/docs/design_documents/index.rst +++ b/docs/design_documents/index.rst
@@ -11,6 +11,7 @@ drtm_poc rss psci_osi_mode + measured_boot --------------
diff --git a/docs/design_documents/measured_boot.rst b/docs/design_documents/measured_boot.rst new file mode 100644 index 0000000..c4e5213 --- /dev/null +++ b/docs/design_documents/measured_boot.rst
@@ -0,0 +1,234 @@ +Measured Boot Design +==================== + +This document briefly explains the Measured-Boot design implementation +in |TF-A|. + +Introduction +------------ + +Measured Boot is the process of computing and securely recording hashes of code +and critical data at each stage in the boot chain before the code/data is used. + +These measurements can be leveraged by other components in the system to +implement a complete attestation system. For example, they could be used to +enforce local attestation policies (such as releasing certain platform keys or +not), or they could be securely sent to a remote challenger a.k.a. `verifier` +after boot to attest to the state of the code and critical-data. + +Measured Boot does not authenticate the code or critical-data, but simply +records what code/critical-data was present on the system during boot. + +It is assumed that BL1 is implicitly trusted (by virtue of immutability) and +acts as the root of trust for measurement hence it is not measured. + +The Measured Boot implementation in TF-A supports multiple backends to securely +store measurements mentioned below in the :ref:`Measured Boot Backends` section. + +Critical data +------------- + +All firmware images - i.e. BLx images and their corresponding configuration +files, if any - must be measured. In addition to that, there might be specific +pieces of data which needs to be measured as well. These are typically different +on each platform. They are referred to as *critical data*. + +Critical data for the platform can be determined using the following criteria: + +#. Data that influence boot flow behaviour such as - + + - Configuration parameters that alter the boot flow path. + - Parameters that determine which firmware to load from NV-Storage to + SRAM/DRAM to pass the boot process successfully. + +#. Hardware configurations settings, debug settings and security policies + that need to be in a valid state for a device to maintain its security + posture during boot and runtime. +#. Security-sensitive data that is being updated by hardware. + +Examples of Critical data: + +#. The list of errata workarounds being applied at reset. +#. State of fuses such as whether an SoC is in secure mode. +#. NV counters that determine whether firmware is up-to-date and secure. + +Measurement slot +---------------- + +The measurement slot resides in a Trusted Module and can be either a secure +register or memory. +The measurement slot is used to provide a method to cryptographically record +(measure) images and critical data on a platform. +The measurement slot update calculation, called an **extend** operation, is +a one-way hash of all the previous measurements and the new measurement. It +is the only way to change the slot value, thus no measurements can ever be +removed or overwritten. + +.. _Measured Boot Backends: + +Measured Boot Backends +---------------------- + +The Measured Boot implementation in TF-A supports: + +#. Event Log + + The TCG Event Log holds a record of measurements made into the Measurement + Slot aka PCR (Platform Configuration Register). + + The `TCG EFI Protocol Specification`_ provides details on how to measure + components. The Arm document + `Arm® Server Base Security Guide`_ provides specific guidance for + measurements on an SBSA/SBBR server system. By considering these + specifications it is decided that - + + #. Use PCR0 for images measurements. + #. Use PCR1 for Critical data measurements. + + TCG has specified the architecture for the structure of this log in the + `TCG EFI Protocol Specification`_. The specification describes two event + log event records—the legacy, fixed size SHA1 structure called TCG_PCR_EVENT + and the variable length crypto agile structure called TCG_PCR_EVENT2. Event + Log driver implemented in TF-A covers later part. + +#. RSS + + It is one of physical backend to extend the measurements. Please refer this + document :ref:`Runtime Security Subsystem (RSS)` for more details. + +Platform Interface +------------------ + +Every image which gets successfully loaded in memory (and authenticated, if +trusted boot is enabled) then gets measured. In addition to that, platforms +can measure any relevant piece of critical data at any point during the boot. +The following diagram outlines the call sequence for Measured Boot platform +interfaces invoked from generic code: + +.. image:: ../resources/diagrams/measured_boot_design.png + +These platform interfaces are used by BL1 and BL2 only, and are declared in +``include/plat/common/platform.h``. +BL31 does not load and thus does not measure any image. + +Responsibilities of these platform interfaces are - + +#. **Function : blx_plat_mboot_init()** + + .. code-block:: c + + void bl1_plat_mboot_init(void); + void bl2_plat_mboot_init(void); + + Initialise all Measured Boot backends supported by the platform + (e.g. Event Log buffer, RSS). As these functions do not return any value, + the platform should deal with error management, such as logging the error + somewhere, or panicking the system if this is considered a fatal error. + + - On the Arm FVP port - + + - In BL1, this function is used to initialize the Event Log backend + driver, and also to write header information in the Event Log + buffer. + - In BL2, this function is used to initialize the Event Log buffer with + the information received from the BL1. It results in panic on + error. + +#. **Function : plat_mboot_measure_image()** + + .. code-block:: c + + int plat_mboot_measure_image(unsigned int image_id, + image_info_t *image_data); + + - Measure the image using a hash function of the crypto module. + + - Record the measurement in the corresponding backend - + + - If it is Event Log backend, then record the measurement in TCG Event Log + format. + - If it is a secure crypto-processor (like RSS), then extend the designated + PCR (or slot) with the given measurement. + - This function must return 0 on success, a signed integer error code + otherwise. + - On the Arm FVP port, this function measures the given image and then + records that measurement in the Event Log buffer. + The passed id is used to retrieve information about on how to measure + the image (e.g. PCR number). + +#. **Function : blx_plat_mboot_finish()** + + .. code-block:: c + + void bl1_plat_mboot_finish(void); + void bl2_plat_mboot_finish(void); + + - Do all teardown operations with respect to initialised Measured Boot backends. + This could be - + + - Pass the Event Log details (start address and size) to Normal world or to + Secure World using any platform implementation way. + - Measure all critical data if any. + - As these functions do not return any value, the platform should deal with + error management, such as logging the error somewhere, or panicking the + system if this is considered a fatal error. + + - On the Arm FVP port - + + - In BL1, this function is used to pass the base address of + the Event Log buffer and its size to BL2 via tb_fw_config to extend the + Event Log buffer with the measurement of various images loaded by BL2. + It results in panic on error. + - In BL2, this function is used to pass the Event Log buffer information + (base address and size) to non-secure(BL33) and trusted OS(BL32) via + nt_fw and tos_fw config respectively. + See :ref:`DTB binding for Event Log properties` for a description of the + bindings used for Event Log properties. + +#. **Function : plat_mboot_measure_critical_data()** + + .. code-block:: c + + int plat_mboot_measure_critical_data(unsigned int critical_data_id, + const void *base, + size_t size); + + This interface is not invoked by the generic code and it is up to the + platform layer to call it where appropriate. + + This function measures the given critical data structure and records its + measurement using the Measured Boot backend driver. + This function must return 0 on success, a signed integer error code + otherwise. + + In FVP, Non volatile counters get measured and recorded as Critical data + using the backend via this interface. + +#. **Function : plat_mboot_measure_key()** + + .. code-block:: c + + int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, + size_t pk_len); + + - This function is used by the platform to measure the passed key and + publicise it using any of the supported backends. + - The authentication module within the trusted boot framework calls this + function for every ROTPK involved in verifying the signature of a root + certificate and for every subsidiary key that gets extracted from a key + certificate for later authentication of a content certificate. + - A cookie, passed as the first argument, serves as a key-OID pointer + associated with the public key data, passed as the second argument. + - Public key data size is passed as the third argument to this function. + - This function must return 0 on success, a signed integer error code + otherwise. + - In FVP platform, this function is used to calculate the hash of the given + key and forward this hash to RSS alongside the measurement of the image + which the key signs. + +-------------- + +*Copyright (c) 2023, Arm Limited. All rights reserved.* + +.. _Arm® Server Base Security Guide: https://developer.arm.com/documentation/den0086/latest +.. _TCG EFI Protocol Specification: https://trustedcomputinggroup.org/wp-content/uploads/EFI-Protocol-Specification-rev13-160330final.pdf
diff --git a/docs/design_documents/measured_boot_poc.rst b/docs/design_documents/measured_boot_poc.rst index 7f73d7e..86cf4d1 100644 --- a/docs/design_documents/measured_boot_poc.rst +++ b/docs/design_documents/measured_boot_poc.rst
@@ -5,10 +5,12 @@ critical data used at boot time, for example using a TPM, so that the security state can be attested later. -The current implementation of the driver included in Trusted Firmware-A -(TF-A) stores the measurements into a `TCG event log`_ in secure -memory. No other means of recording measurements (such as a discrete TPM) is -supported right now. +The current implementation of the driver included in |TF-A| supports several +backends and each has a different means to store the measurements. +This section focuses on the `TCG event log`_ backend, which stores measurements +in secure memory. + +See details of :ref:`Measured Boot Design`. The driver also provides mechanisms to pass the Event Log to normal world if needed.
diff --git a/docs/design_documents/psci_osi_mode.rst b/docs/design_documents/psci_osi_mode.rst index 3296e27..a6e1bdf 100644 --- a/docs/design_documents/psci_osi_mode.rst +++ b/docs/design_documents/psci_osi_mode.rst
@@ -4,7 +4,7 @@ :Author: Maulik Shah & Wing Li :Organization: Qualcomm Innovation Center, Inc. & Google LLC :Contact: Maulik Shah <quic_mkshah@quicinc.com> & Wing Li <wingers@google.com> -:Status: RFC +:Status: Accepted .. contents:: Table of Contents @@ -367,9 +367,11 @@ ``psci_validate_state_coordination``. If validation fails, propagate the error up the call stack. -* Update the return type of the platform specific ``pwr_domain_suspend`` - handler from ``void`` to ``int``, to allow the platform to optionally perform - validations based on hardware states. +* Add a new optional member ``pwr_domain_validate_suspend`` to + ``plat_psci_ops_t`` to allow the platform to optionally perform validations + based on hardware states. + +* The platform specific ``pwr_domain_suspend`` handler remains unchanged. .. image:: ../resources/diagrams/psci-osi-mode.png
diff --git a/docs/design_documents/rss.rst b/docs/design_documents/rss.rst index 2be8067..18d5436 100644 --- a/docs/design_documents/rss.rst +++ b/docs/design_documents/rss.rst
@@ -134,12 +134,10 @@ - ``Delegated attestation``: Query the platform attestation token and derive a delegated attestation key. More info on the delegated attestation service in RSS can be found in the ``delegated_attestation_integration_guide`` [4]_ . -- ``OTP assets management``: RSS provides access for AP to assets in OTP. - These are keys for image signature verification and non-volatile counters - for anti-rollback protection. Only RSS has direct access to the OTP. Public - keys used by AP during the trusted boot process can be requested from RSS. - Furthermore, AP can request RSS to increase a non-volatile counter. Please - refer to the ``RSS key management`` [5]_ document for more details. +- ``OTP assets management``: Public keys used by AP during the trusted boot + process can be requested from RSS. Furthermore, AP can request RSS to + increase a non-volatile counter. Please refer to the + ``RSS key management`` [5]_ document for more details. Runtime service API ^^^^^^^^^^^^^^^^^^^ @@ -262,7 +260,8 @@ - ``SW type``: Optional. Short text description (e.g.: BL1, BL2, BL31, etc.) .. Note:: - Signer-id and version info is not implemented in TF-A yet. + Version info is not implemented in TF-A yet. + The caller must specify in which measurement slot to extend a certain measurement and metadata. A measurement slot can be extended by multiple @@ -321,9 +320,38 @@ size_t version_size; uint8_t sw_type[SW_TYPE_MAX_SIZE]; size_t sw_type_size; + void *pk_oid; bool lock_measurement; }; +Signer-ID API +^^^^^^^^^^^^^ + +This function calculates the hash of a public key (signer-ID) using the +``Measurement algorithm`` and stores it in the ``rss_mboot_metadata`` field +named ``signer_id``. +Prior to calling this function, the caller must ensure that the ``signer_id`` +field points to the zero-filled buffer. + +Defined here: + +- ``include/drivers/measured_boot/rss/rss_measured_boot.h`` + +.. code-block:: c + + int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr, + const void *pk_oid, + const void *pk_ptr, + size_t pk_len) + + +- First parameter is the pointer to the ``rss_mboot_metadata`` structure. +- Second parameter is the pointer to the key-OID of the public key. +- Third parameter is the pointer to the public key buffer. +- Fourth parameter is the size of public key buffer. +- This function returns 0 on success, a signed integer error code + otherwise. + Build time config options ^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -361,8 +389,8 @@ INFO: Image id=24 loaded: 0x4001300 - 0x400153a INFO: Measured boot extend measurement: INFO: - slot : 7 - INFO: - signer_id : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + INFO: - signer_id : b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 73 + INFO: : e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da INFO: - version : INFO: - version_size: 0 INFO: - sw_type : TB_FW_CONFIG @@ -377,8 +405,8 @@ INFO: Image id=1 loaded: 0x404d000 - 0x406412a INFO: Measured boot extend measurement: INFO: - slot : 8 - INFO: - signer_id : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + INFO: - signer_id : b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 73 + INFO: : e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da INFO: - version : INFO: - version_size: 0 INFO: - sw_type : BL_2 @@ -483,31 +511,31 @@ INFO: a2 6a df 34 c3 29 48 9a dc 38 04 67 31 2e 35 2e INFO: 30 2b 30 01 60 02 58 20 b8 01 65 a7 78 8b c6 59 INFO: 42 8d 33 10 85 d1 49 0a dc 9e c3 ee df 85 1b d2 - INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 00 00 00 04 60 01 6a + INFO: f0 73 73 6a 0c 07 11 b8 a4 05 58 20 b0 f3 82 09 + INFO: 12 97 d8 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 + INFO: 49 59 f6 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6a INFO: 46 57 5f 43 4f 4e 46 49 47 00 02 58 20 21 9e a0 INFO: 13 82 e6 d7 97 5a 11 13 a3 5f 45 39 68 b1 d9 a3 INFO: ea 6a ab 84 23 3b 8c 06 16 98 20 ba b9 a4 05 58 - INFO: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49 + INFO: 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec 32 + INFO: 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 9a + INFO: da 04 60 01 6d 54 42 5f 46 57 5f 43 4f 4e 46 49 INFO: 47 00 02 58 20 41 39 f6 c2 10 84 53 c5 17 ae 9a INFO: e5 be c1 20 7b cc 24 24 f3 9d 20 a8 fb c7 b3 10 - INFO: e3 ee af 1b 05 a4 05 58 20 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 04 60 01 65 42 4c 5f + INFO: e3 ee af 1b 05 a4 05 58 20 b0 f3 82 09 12 97 d8 + INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6 + INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 65 42 4c 5f INFO: 32 00 02 58 20 5c 96 20 e1 e3 3b 0f 2c eb c1 8e INFO: 1a 02 a6 65 86 dd 34 97 a7 4c 98 13 bf 74 14 45 - INFO: 2d 30 28 05 c3 a4 05 58 20 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 04 60 01 6e 53 45 43 + INFO: 2d 30 28 05 c3 a4 05 58 20 b0 f3 82 09 12 97 d8 + INFO: 3a 37 7a 72 47 1b ec 32 73 e9 92 32 e2 49 59 f6 + INFO: 5e 8b 4a 4a 46 d8 22 9a da 04 60 01 6e 53 45 43 INFO: 55 52 45 5f 52 54 5f 45 4c 33 00 02 58 20 f6 fb INFO: 62 99 a5 0c df db 02 0b 72 5b 1c 0b 63 6e 94 ee INFO: 66 50 56 3a 29 9c cb 38 f0 ec 59 99 d4 2e a4 05 - INFO: 58 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - INFO: 00 00 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00 + INFO: 58 20 b0 f3 82 09 12 97 d8 3a 37 7a 72 47 1b ec + INFO: 32 73 e9 92 32 e2 49 59 f6 5e 8b 4a 4a 46 d8 22 + INFO: 9a da 04 60 01 6a 48 57 5f 43 4f 4e 46 49 47 00 INFO: 02 58 20 98 5d 87 21 84 06 33 9d c3 1f 91 f5 68 INFO: 8d a0 5a f0 d7 7e 20 51 ce 3b f2 a5 c3 05 2e 3c INFO: 8b 52 31 19 01 09 78 1c 68 74 74 70 3a 2f 2f 61 @@ -559,31 +587,31 @@ "MEASUREMENT_VALUE": "b'B80165A7788BC659428D331085D1490ADC9EC3EEDF851BD2F073736A0C0711B8'" }, { - "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'", + "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'", "SW_COMPONENT_VERSION": "", "SW_COMPONENT_TYPE": "FW_CONFIG\u0000", "MEASUREMENT_VALUE": "b'219EA01382E6D7975A1113A35F453968B1D9A3EA6AAB84233B8C06169820BAB9'" }, { - "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'", + "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'", "SW_COMPONENT_VERSION": "", "SW_COMPONENT_TYPE": "TB_FW_CONFIG\u0000", "MEASUREMENT_VALUE": "b'4139F6C2108453C517AE9AE5BEC1207BCC2424F39D20A8FBC7B310E3EEAF1B05'" }, { - "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'", + "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'", "SW_COMPONENT_VERSION": "", "SW_COMPONENT_TYPE": "BL_2\u0000", "MEASUREMENT_VALUE": "b'5C9620E1E33B0F2CEBC18E1A02A66586DD3497A74C9813BF7414452D302805C3'" }, { - "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'", + "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'", "SW_COMPONENT_VERSION": "", "SW_COMPONENT_TYPE": "SECURE_RT_EL3\u0000", "MEASUREMENT_VALUE": "b'F6FB6299A50CDFDB020B725B1C0B636E94EE6650563A299CCB38F0EC5999D42E'" }, { - "SIGNER_ID": "b'0000000000000000000000000000000000000000000000000000000000000000'", + "SIGNER_ID": "b'b0f382091297d83a377a72471bec3273e99232e24959f65e8b4a4a46d8229ada'", "SW_COMPONENT_VERSION": "", "SW_COMPONENT_TYPE": "HW_CONFIG\u0000", "MEASUREMENT_VALUE": "b'985D87218406339DC31F91F5688DA05AF0D77E2051CE3BF2A5C3052E3C8B5231'" @@ -595,6 +623,57 @@ "CCA_PLATFORM_VERIFICATION_SERVICE": "www.trustedfirmware.org" } +RSS OTP Assets Management +------------------------- + +RSS provides access for AP to assets in OTP, which include keys for image +signature verification and non-volatile counters for anti-rollback protection. + +Non-Volatile Counter API +^^^^^^^^^^^^^^^^^^^^^^^^ + +AP/RSS interface for retrieving and incrementing non-volatile counters API is +as follows. + +Defined here: + +- ``include/lib/psa/rss_platform_api.h`` + +.. code-block:: c + + psa_status_t rss_platform_nv_counter_increment(uint32_t counter_id) + + psa_status_t rss_platform_nv_counter_read(uint32_t counter_id, + uint32_t size, uint8_t *val) + +Through this service, we can read/increment any of the 3 non-volatile +counters used on an Arm CCA platform: + +- ``Non-volatile counter for CCA firmware (BL2, BL31, RMM).`` +- ``Non-volatile counter for secure firmware.`` +- ``Non-volatile counter for non-secure firmware.`` + +Public Key API +^^^^^^^^^^^^^^ + +AP/RSS interface for reading the ROTPK is as follows. + +Defined here: + +- ``include/lib/psa/rss_platform_api.h`` + +.. code-block:: c + + psa_status_t rss_platform_key_read(enum rss_key_id_builtin_t key, + uint8_t *data, size_t data_size, size_t *data_length) + +Through this service, we can read any of the 3 ROTPKs used on an +Arm CCA platform: + +- ``ROTPK for CCA firmware (BL2, BL31, RMM).`` +- ``ROTPK for secure firmware.`` +- ``ROTPK for non-secure firmware.`` + References ----------
diff --git a/docs/getting_started/build-internals.rst b/docs/getting_started/build-internals.rst index a015d71..390c367 100644 --- a/docs/getting_started/build-internals.rst +++ b/docs/getting_started/build-internals.rst
@@ -12,3 +12,10 @@ interest when Armv8.4-SecEL2 or RME extension is implemented. Default is 0 (disabled). This option will be set to 1 (enabled) when ``SPD=spmd`` and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled). + +- ``FFH_SUPPORT``: This boolean option provides support to enable Firmware First + handling (FFH) of External aborts and SError interrupts originating from lower + ELs which gets trapped in EL3. This option will be set to 1 (enabled) if + ``HANDLE_EA_EL3_FIRST_NS`` is set. Currently only NS world routes EA to EL3 but + in future when Secure/Realm wants to use FFH then they can introduce new macros + which will enable this option implicitly.
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 4eafb39..80baf9c 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst
@@ -45,6 +45,12 @@ compiling TF-A. Its value must be a numeric, and defaults to 0. See also, *Armv8 Architecture Extensions* in :ref:`Firmware Design`. +- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded + SP nodes in tb_fw_config. + +- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the + SPMC Core manifest. Valid when ``SPD=spmd`` is selected. + - ``BL2``: This is an optional build option which specifies the path to BL2 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be built. @@ -74,9 +80,9 @@ BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built. -- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. +- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a + file that contains the BL31 private key in PEM format or a PKCS11 URI. If + ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. - ``BL32``: This is an optional build option which specifies the path to BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not @@ -88,16 +94,16 @@ - ``BL32_EXTRA2``: This is an optional build option which specifies the path to Trusted OS Extra2 image for the ``fip`` target. -- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. +- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a + file that contains the BL32 private key in PEM format or a PKCS11 URI. If + ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. - ``BL33``: Path to BL33 image in the host file system. This is mandatory for ``fip`` target in case TF-A BL2 is used. -- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. +- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a + file that contains the BL33 private key in PEM format or a PKCS11 URI. If + ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. @@ -207,10 +213,10 @@ of the binary image. If set to 1, then only the ELF image is built. 0 is the default. -- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented - (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms - that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, - check the latest Arm ARM. +- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded + PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. + This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default is ``0``. - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted Board Boot authentication at runtime. This option is meant to be enabled only @@ -302,6 +308,13 @@ flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. +- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for + ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to + memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural + feature available from v8.9 and upwards. This flag can take the values 0 to + 2, to align with the ``FEATURE_DETECTION`` mechanism. Default value is + ``0``. + - ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a permission fault for any privileged data access from EL1/EL2 to virtual @@ -384,7 +397,7 @@ support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0. -- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM +- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at various ELs can assign themselves to desired partition to control their @@ -395,7 +408,9 @@ access their own MPAM registers without trapping into EL3. This option doesn't make use of partitioning in EL3, however. Platform initialisation code should configure and use partitions in EL3 as required. This option - defaults to ``0``. + defaults to ``2`` since MPAM is enabled by default for NS world only. + The flag is automatically disabled when the target + architecture is AArch32. - ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power Mitigation Mechanism supported by certain Arm cores, which allows the SoC @@ -421,40 +436,12 @@ be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in software. -- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm - Management Extension. This flag can take the values 0 to 2, to align with - the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently - an experimental feature. - - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime instrumentation which injects timestamp collection points into TF-A to allow runtime performance to be measured. Currently, only PSCI is instrumented. Enabling this option enables the ``ENABLE_PMF`` build option as well. Default is 0. -- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension - (SME), SVE, and FPU/SIMD for the non-secure world only. These features share - registers so are enabled together. Using this option without - ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure - world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a - superset of SVE. SME is an optional architectural feature for AArch64 - and TF-A support is experimental. At this time, this build option cannot be - used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to - build with these options will fail. This flag can take the values 0 to 2, to - align with the ``FEATURE_DETECTION`` mechanism. Default is 0. - -- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension - version 2 (SME2) for the non-secure world only. SME2 is an optional - architectural feature for AArch64 and TF-A support is experimental. - This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME - accesses will still be trapped. This flag can take the values 0 to 2, to - align with the ``FEATURE_DETECTION`` mechanism. Default is 0. - -- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix - Extension for secure world. Used along with SVE and FPU/SIMD. - ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. - This is experimental. Default is 0. - - ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` @@ -506,6 +493,20 @@ Firmware as error. It can take the value 1 (flag the use of deprecated APIs as error) or 0. The default is 0. +- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can + configure an Arm® Ethos™-N NPU. To use this service the target platform's + ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only + the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform + only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. + +- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the + Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and + ``TRUSTED_BOARD_BOOT`` to be enabled. + +- ``ETHOSN_NPU_FW``: location of the NPU firmware binary + (```ethosn.bin```). This firmware image will be included in the FIP and + loaded at runtime. + - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions targeted at EL3. When set ``0`` (default), no exceptions are expected or handled at EL3, and a panic will result. The exception to this rule is when @@ -526,43 +527,6 @@ This feature is intended for testing purposes only, and is advisable to keep disabled for production images. -- ``FEATURE_DETECTION``: Boolean option to enable the architectural features - detection mechanism. It detects whether the Architectural features enabled - through feature specific build flags are supported by the PE or not by - validating them either at boot phase or at runtime based on the value - possessed by the feature flag (0 to 2) and report error messages at an early - stage. - - This prevents and benefits us from EL3 runtime exceptions during context save - and restore routines guarded by these build flags. Henceforth validating them - before their usage provides more control on the actions taken under them. - - The mechanism permits the build flags to take values 0, 1 or 2 and - evaluates them accordingly. - - Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: - - :: - - ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. - ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. - ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. - - In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to - 0, feature is disabled statically during compilation. If it is defined as 1, - feature is validated, wherein FEAT_HCX is detected at boot time. In case not - implemented by the PE, a hard panic is generated. Finally, if the flag is set - to 2, feature is validated at runtime. - - Note that the entire implementation is divided into two phases, wherein as - as part of phase-1 we are supporting the values 0,1. Value 2 is currently not - supported and is planned to be handled explicilty in phase-2 implementation. - - FEATURE_DETECTION macro is disabled by default, and is currently an - experimental procedure. Platforms can explicitly make use of this by - mechanism, by enabling it to validate whether they have set their build flags - properly at an early phase. - - ``FIP_NAME``: This is an optional build option which specifies the FIP filename for the ``fip`` target. Default is ``fip.bin``. @@ -647,12 +611,6 @@ invert this behavior. Lower addresses will be printed at the top and higher addresses at the bottom. -- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 - runtime software in AArch32 mode, which is required to run AArch32 on Juno. - By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in - AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable - images. - - ``KEY_ALG``: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` @@ -668,19 +626,15 @@ +---------------------------+------------------------------------+ | KEY_ALG | Possible key sizes | +===========================+====================================+ - | rsa | 1024 , 2048 (default), 3072, 4096* | + | rsa | 1024 , 2048 (default), 3072, 4096 | +---------------------------+------------------------------------+ - | ecdsa | unavailable | + | ecdsa | 256 (default), 384 | +---------------------------+------------------------------------+ | ecdsa-brainpool-regular | unavailable | +---------------------------+------------------------------------+ | ecdsa-brainpool-twisted | unavailable | +---------------------------+------------------------------------+ - - * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. - Only 3072 bits size is available with CryptoCell 712 SBROM release 2. - - ``HASH_ALG``: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. The default value of this flag is ``sha256``. @@ -710,18 +664,17 @@ This option defaults to 0. -- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust - for Measurement (DRTM). This feature has trust dependency on BL31 for taking - the measurements and recording them as per `PSA DRTM specification`_. For - platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can - be used and for the platforms which use ``RESET_TO_BL31`` platform owners - should have mechanism to authenticate BL31. This is an experimental feature. +- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build + options to the compiler. An example usage: - This option defaults to 0. + .. code:: make + + MARCH_DIRECTIVE := -march=armv8.5-a - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It - specifies the file that contains the Non-Trusted World private key in PEM - format. If ``SAVE_KEYS=1``, this file name will be used to save the key. + specifies a file that contains the Non-Trusted World private key in PEM + format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it + will be used to save the key. - ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it @@ -732,6 +685,10 @@ 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored. +- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in + tb_fw_config device tree. This flag is defined only when + ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. + - ``OVERRIDE_LIBC``: This option allows platforms to override the default libc for the BL image. It can be either 0 (include) or 1 (remove). The default value is 0. @@ -775,14 +732,12 @@ - ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI OS-initiated mode. This option defaults to 0. -- ``ENABLE_FEAT_RAS``: Numeric value to enable Armv8.2 RAS features. RAS features +- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 - or later CPUs. This flag can take the values 0 to 2, to align with the - ``FEATURE_DETECTION`` mechanism. - -- ``RAS_FFH_SUPPORT``: Support to enable Firmware first handling of RAS errors - originating from NS world. When ``RAS_FFH_SUPPORT`` is set to ``1``, - ``HANDLE_EA_EL3_FIRST_NS`` and ``ENABLE_FEAT_RAS`` must also be set to ``1``. + or later CPUs. This flag can take the values 0 or 1. The default value is 0. + NOTE: This flag enables use of IESB capability to reduce entry latency into + EL3 even when RAS error handling is not performed on the platform. Hence this + flag is recommended to be turned on Armv8.2 and later CPUs. - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 @@ -794,10 +749,10 @@ instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. -- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the ROT private key in PEM format and enforces public key - hash generation. If ``SAVE_KEYS=1``, this - file name will be used to save the key. +- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a + file that contains the ROT private key in PEM format or a PKCS11 URI and + enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is + accepted and it will be used to save the key. - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the certificate generation tool to save the keys used to establish the Chain of @@ -807,9 +762,9 @@ If a SCP_BL2 image is present then this option must be passed for the ``fip`` target. -- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the - file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, - this file name will be used to save the key. +- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a + file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. + If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. - ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it @@ -864,7 +819,11 @@ Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC component runs at the EL3 exception level. The default value is ``0`` ( disabled). This configuration supports pre-Armv8.4 platforms (aka not - implementing the ``FEAT_SEL2`` extension). This is an experimental feature. + implementing the ``FEAT_SEL2`` extension). + +- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when + ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This + option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. - ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to @@ -920,8 +879,9 @@ already exist in disk, they will be overwritten without further notice. - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It - specifies the file that contains the Trusted World private key in PEM - format. If ``SAVE_KEYS=1``, this file name will be used to save the key. + specifies a file that contains the Trusted World private key in PEM + format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and + it will be used to save the key. - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or synchronous, (see "Initializing a BL32 Image" section in @@ -941,6 +901,9 @@ When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` must also be set to ``1``. +- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and + internal-trusted-storage) as SP in tb_fw_config device tree. + - ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set this delay. It can take values in the range (0-15). Default value is ``0`` @@ -959,10 +922,6 @@ (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1. -- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature - exposing a virtual filesystem interface through BL31 as a SiP SMC function. - Default is 0. - - ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the firmware configuration framework. This will move the io_policies into a configuration device tree, instead of static structure in the code base. @@ -1136,6 +1095,12 @@ errata mitigation for platforms with a non-arm interconnect using the errata ABI. By default its disabled (``0``). +- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console + driver(s). By default it is disabled (``0``) because it constitutes an attack + vector into TF-A by potentially allowing an attacker to inject arbitrary data. + This option should only be enabled on a need basis if there is a use case for + reading characters from the console. + GICv3 driver options -------------------- @@ -1226,8 +1191,118 @@ # Resume execution continue +.. _build_options_experimental: + +Experimental build options +--------------------------- + +Common build options +~~~~~~~~~~~~~~~~~~~~ + +- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust + for Measurement (DRTM). This feature has trust dependency on BL31 for taking + the measurements and recording them as per `PSA DRTM specification`_. For + platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can + be used and for the platforms which use ``RESET_TO_BL31`` platform owners + should have mechanism to authenticate BL31. This option defaults to 0. + +- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm + Management Extension. This flag can take the values 0 to 2, to align with + the ``FEATURE_DETECTION`` mechanism. Default value is 0. + +- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension + (SME), SVE, and FPU/SIMD for the non-secure world only. These features share + registers so are enabled together. Using this option without + ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure + world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a + superset of SVE. SME is an optional architectural feature for AArch64. + At this time, this build option cannot be used on systems that have + SPD=spmd/SPM_MM and atempting to build with this option will fail. + This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` + mechanism. Default is 0. + +- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension + version 2 (SME2) for the non-secure world only. SME2 is an optional + architectural feature for AArch64. + This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME + accesses will still be trapped. This flag can take the values 0 to 2, to + align with the ``FEATURE_DETECTION`` mechanism. Default is 0. + +- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix + Extension for secure world. Used along with SVE and FPU/SIMD. + ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. + Default is 0. + +- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM + Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support + for logical partitions in EL3, managed by the SPMD as defined in the + FF-A v1.2 specification. This flag is disabled by default. This flag + must not be used if ``SPMC_AT_EL3`` is enabled. + +- ``FEATURE_DETECTION``: Boolean option to enable the architectural features + detection mechanism. It detects whether the Architectural features enabled + through feature specific build flags are supported by the PE or not by + validating them either at boot phase or at runtime based on the value + possessed by the feature flag (0 to 2) and report error messages at an early + stage. This flag will also enable errata ordering checking for ``DEBUG`` + builds. + + This prevents and benefits us from EL3 runtime exceptions during context save + and restore routines guarded by these build flags. Henceforth validating them + before their usage provides more control on the actions taken under them. + + The mechanism permits the build flags to take values 0, 1 or 2 and + evaluates them accordingly. + + Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: + + :: + + ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. + ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. + ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. + + In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to + 0, feature is disabled statically during compilation. If it is defined as 1, + feature is validated, wherein FEAT_HCX is detected at boot time. In case not + implemented by the PE, a hard panic is generated. Finally, if the flag is set + to 2, feature is validated at runtime. + + Note that the entire implementation is divided into two phases, wherein as + as part of phase-1 we are supporting the values 0,1. Value 2 is currently not + supported and is planned to be handled explicilty in phase-2 implementation. + + ``FEATURE_DETECTION`` macro is disabled by default. Platforms can explicitly + make use of this by mechanism, by enabling it to validate whether they have + set their build flags properly at an early phase. + +- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. + The platform will use PSA compliant Crypto APIs during authentication and + image measurement process by enabling this option. It uses APIs defined as + per the `PSA Crypto API specification`_. This feature is only supported if + using MbedTLS 3.x version. It is disabled (``0``) by default. + +- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware + Handoff using Transfer List defined in `Firmware Handoff specification`_. + This defaults to ``0``. Current implementation follows the Firmware Handoff + specification v0.9. + +- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem + interface through BL31 as a SiP SMC function. + Default is disabled (0). + Firmware update options ------------------------ +~~~~~~~~~~~~~~~~~~~~~~~ + +- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the + `PSA FW update specification`_. The default value is 0. + PSA firmware update implementation has few limitations, such as: + + - BL2 is not part of the protocol-updatable images. If BL2 needs to + be updated, then it should be done through another platform-defined + mechanism. + + - It assumes the platform's hardware supports CRC32 instructions. - ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used in defining the firmware update metadata structure. This flag is by default @@ -1239,14 +1314,6 @@ This flag is used in defining the firmware update metadata structure. This flag is by default set to '1'. -- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the - `PSA FW update specification`_. The default value is 0, and this is an - experimental feature. - PSA firmware update implementation has some limitations, such as BL2 is - not part of the protocol-updatable images, if BL2 needs to be updated, then - it should be done through another platform-defined mechanism, and it assumes - that the platform's hardware supports CRC32 instructions. - -------------- *Copyright (c) 2019-2023, Arm Limited. All rights reserved.* @@ -1256,3 +1323,5 @@ .. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a .. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html .. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html +.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 +.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst index aa8c2bb..50fff57 100644 --- a/docs/getting_started/docs-build.rst +++ b/docs/getting_started/docs-build.rst
@@ -74,6 +74,26 @@ poetry run make -C docs help +To build the documentation in PDF format, additionally ensure that the following +packages are installed: + +- FreeSerif font +- latexmk +- librsvg2-bin +- xelatex +- xindy + +Below is an example set of instructions to install the required packages +(tested on Ubuntu): + +.. code:: shell + + sudo apt install fonts-freefont-otf latexmk librsvg2-bin texlive-xetex xindy + +Once all the dependencies are installed, run the command ``poetry run make -C +docs latexpdf`` to build the documentation. Output from the build process +(``trustedfirmware-a.pdf``) can be found in ``docs/build/latex``. + Building rendered documentation from Poetry's virtual environment ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst index f4c3c28..573abdf 100644 --- a/docs/getting_started/prerequisites.rst +++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@ |TF-A| can be built with any of the following *cross-compiler* toolchains that target the Armv7-A or Armv8-A architectures: -- GCC >= 12.2.Rel1 (from the `Arm Developer website`_) +- TF-A has been tested with version 12.3.Rel1 (gcc 12.3) from the `Arm Developer website`_ You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for AArch32 and AArch64 builds respectively. @@ -77,7 +77,7 @@ The following libraries are required for Trusted Board Boot and Measured Boot support: -- mbed TLS == 3.4.0 (tag: ``mbedtls-3.4.0``) +- mbed TLS == 3.4.1 (tag: ``mbedtls-3.4.1``) These tools are optional:
diff --git a/docs/getting_started/psci-lib-integration-guide.rst b/docs/getting_started/psci-lib-integration-guide.rst index 4d690a9..7e4b0db 100644 --- a/docs/getting_started/psci-lib-integration-guide.rst +++ b/docs/getting_started/psci-lib-integration-guide.rst
@@ -3,7 +3,7 @@ This document describes the PSCI library interface with a focus on how to integrate with a suitable Trusted OS for an Armv8-A AArch32 system. The PSCI -Library implements the PSCI Standard as described in `PSCI spec`_ and is meant +Library implements the PSCI Standard as described in `PSCI`_ and is meant to be integrated with EL3 Runtime Software which invokes the PSCI Library interface appropriately. **EL3 Runtime Software** refers to software executing at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/ @@ -74,7 +74,7 @@ --------------------------- PSCI library is in charge of initializing/restoring the non-secure CPU system -registers according to `PSCI specification`_ during cold/warm boot. +registers according to `PSCI`_ during cold/warm boot. This is referred to as ``PSCI CPU Context Management``. Registers that need to be preserved across CPU power down/power up cycles are maintained in ``cpu_context_t`` data structure. The initialization of other non-secure CPU @@ -120,8 +120,8 @@ PSCI Library Interface ---------------------- -The PSCI library implements the `PSCI Specification`_. The interfaces -to this library are declared in ``psci_lib.h`` and are as listed below: +The PSCI library implements the `PSCI`_. The interfaces to this library are +declared in ``psci_lib.h`` and are as listed below: .. code:: c @@ -254,7 +254,7 @@ argument) determines the PSCI API to be called. The ``x1`` to ``x4`` (2nd to 5th arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4 (in AArch64) when the SMC is received. These are the arguments to PSCI API as -described in `PSCI spec`_. The 'flags' (8th argument) is a bit field parameter +described in `PSCI`_. The 'flags' (8th argument) is a bit field parameter and is detailed in 'smccc.h' header. It includes whether the call is from the secure or non-secure world. The ``cookie`` (6th argument) and the ``handle`` (7th argument) are not used and are reserved for future use. @@ -273,7 +273,7 @@ Return : void This function performs the warm boot initialization/restoration as mandated by -`PSCI spec`_. For AArch32, on wakeup from power down the CPU resets to secure SVC +`PSCI`_. For AArch32, on wakeup from power down the CPU resets to secure SVC mode and the EL3 Runtime Software must perform the prerequisite initializations mentioned at top of this section. This function must be called with Data cache disabled (unless build option ``HW_ASSISTED_COHERENCY`` is enabled) but with MMU @@ -496,7 +496,7 @@ This callback is called in response to PSCI_MIGRATE_INFO_TYPE or PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described - in `PSCI spec`_. If the secure payload is a Uniprocessor (UP) + in `PSCI`_. If the secure payload is a Uniprocessor (UP) implementation, then it must update the mpidr of the CPU it is resident in via ``resident_cpu`` (first argument). The updates to ``resident_cpu`` is ignored if the secure payload is a multiprocessor (MP) implementation. @@ -528,9 +528,7 @@ -------------- -*Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.* -.. _PSCI spec: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ .. _SMCCC: https://developer.arm.com/docs/den0028/latest -.. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf -.. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
diff --git a/docs/getting_started/rt-svc-writers-guide.rst b/docs/getting_started/rt-svc-writers-guide.rst index 5a4be4d..fe64558 100644 --- a/docs/getting_started/rt-svc-writers-guide.rst +++ b/docs/getting_started/rt-svc-writers-guide.rst
@@ -314,7 +314,7 @@ -------------- -*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.* .. _SMCCC: https://developer.arm.com/docs/den0028/latest -.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/index.rst b/docs/index.rst index d5ab8fc..a7a5993 100644 --- a/docs/index.rst +++ b/docs/index.rst
@@ -17,6 +17,7 @@ security_advisories/index design_documents/index threat_model/index + tools/index change-log glossary license @@ -89,7 +90,7 @@ .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php -.. _Power State Coordination Interface (PSCI): http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf +.. _Power State Coordination Interface (PSCI): https://developer.arm.com/documentation/den0022/latest/ .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a .. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf .. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
diff --git a/docs/perf/psci-performance-instr.rst b/docs/perf/psci-performance-instr.rst index 16f386f..41094b2 100644 --- a/docs/perf/psci-performance-instr.rst +++ b/docs/perf/psci-performance-instr.rst
@@ -13,16 +13,17 @@ Performance Measurement Framework --------------------------------- -The Performance Measurement Framework `PMF`_ is a framework that provides -mechanisms for collecting and retrieving timestamps at runtime from the -Performance Measurement Unit (`PMU`_). The PMU is a generalized abstraction for -accessing CPU hardware registers used to measure hardware events. This means, -for instance, that the PMU might be used to place instrumentation points at -logical locations in code for tracing purposes. +The Performance Measurement Framework :ref:`PMF <firmware_design_pmf>` +is a framework that provides mechanisms for collecting and retrieving timestamps +at runtime from the Performance Measurement Unit +(:ref:`PMU <Performance Monitoring Unit>`). +The PMU is a generalized abstraction for accessing CPU hardware registers used to +measure hardware events. This means, for instance, that the PMU might be used to +place instrumentation points at logical locations in code for tracing purposes. TF-A utilises the PMF as a backend for the two instrumentation services it provides--PSCI Statistics and Runtime Instrumentation. The PMF is used by -these services to facilitate collection and retrieval of timestamps. For +these services to facilitate collection and retrieval of timestamps. For instance, the PSCI Statistics service registers the PMF service ``psci_svc`` to track its residency statistics. @@ -112,6 +113,4 @@ *Copyright (c) 2023, Arm Limited. All rights reserved.* -.. _PMF: ../design/firmware-design.html#performance-measurement-framework -.. _PMU: performance-monitoring-unit.html .. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst index 7a484b8..bab1086 100644 --- a/docs/perf/psci-performance-juno.rst +++ b/docs/perf/psci-performance-juno.rst
@@ -34,8 +34,9 @@ - TF-A [`v2.9-rc0`_] - TFTF [`v2.9-rc0`_] -Please see the Runtime Instrumentation `Testing Methodology`_ page for more -details. +Please see the Runtime Instrumentation :ref:`Testing Methodology +<Runtime Instrumentation Methodology>` +page for more details. Procedure --------- @@ -72,83 +73,157 @@ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in - parallel + parallel (v2.9) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 243.76 | 239.92 | 6.32 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 663.5 | 30.32 | 167.82 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 105.12 | 22.84 | 5.88 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 384.16 | 19.06 | 4.7 | - +---------+------+-----------+---------+-------------+ - | 1 | 2 | 523.98 | 270.46 | 4.74 | - +---------+------+-----------+---------+-------------+ - | 1 | 3 | 950.54 | 220.9 | 89.2 | - +---------+------+-----------+---------+-------------+ + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 104.58 | 241.20 | 5.26 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 384.24 | 22.50 | 138.76 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 244.56 | 22.18 | 5.16 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 670.56 | 18.58 | 4.44 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 809.36 | 269.28 | 4.44 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 984.96 | 219.70 | 79.62 | + +---------+------+-----------+--------+-------------+ .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in - serial + parallel (v2.10) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 266.96 | 31.74 | 167.92 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 266.9 | 31.52 | 167.82 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 279.86 | 23.42 | 87.52 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 101.38 | 18.8 | 4.64 | - +---------+------+-----------+---------+-------------+ - | 1 | 2 | 101.18 | 19.28 | 4.64 | - +---------+------+-----------+---------+-------------+ - | 1 | 3 | 101.32 | 19.02 | 4.62 | - +---------+------+-----------+---------+-------------+ + +---------+------+-------------------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-------------------+--------+-------------+ + | 0 | 0 | 242.66 (+132.03%) | 245.1 | 5.4 | + +---------+------+-------------------+--------+-------------+ + | 0 | 1 | 522.08 (+35.87%) | 26.24 | 138.32 | + +---------+------+-------------------+--------+-------------+ + | 1 | 0 | 104.36 (-57.33%) | 27.1 | 5.32 | + +---------+------+-------------------+--------+-------------+ + | 1 | 1 | 382.56 (-42.95%) | 23.34 | 4.42 | + +---------+------+-------------------+--------+-------------+ + | 1 | 2 | 807.74 | 271.54 | 4.64 | + +---------+------+-------------------+--------+-------------+ + | 1 | 3 | 981.36 | 221.8 | 79.48 | + +---------+------+-------------------+--------+-------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in + serial (v2.9) + + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 236.56 | 23.24 | 138.18 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 236.86 | 23.28 | 138.10 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 281.04 | 22.80 | 77.24 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 100.28 | 18.52 | 4.54 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 100.12 | 18.78 | 4.50 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 100.36 | 18.94 | 4.44 | + +---------+------+-----------+--------+-------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in + serial (v2.10) + + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 236.84 | 27.1 | 138.36 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 236.96 | 27.1 | 138.32 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 280.06 | 26.94 | 77.5 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 100.76 | 23.42 | 4.36 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 100.02 | 23.42 | 4.44 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 100.08 | 23.2 | 4.4 | + +---------+------+-----------+--------+-------------+ ``CPU_SUSPEND`` to power level 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in - parallel + parallel (v2.9) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - +---------+------+-----------+---------+-------------+ - | 0 | 0 | 661.94 | 22.88 | 9.66 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 801.64 | 23.38 | 9.62 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 105.56 | 16.02 | 8.12 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 245.42 | 16.26 | 7.78 | - +---------+------+-----------+---------+-------------+ - | 1 | 2 | 384.42 | 16.1 | 7.84 | - +---------+------+-----------+---------+-------------+ - | 1 | 3 | 523.74 | 15.4 | 8.02 | - +---------+------+-----------+---------+-------------+ + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 662.34 | 15.22 | 8.08 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 802.00 | 15.50 | 8.16 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 385.22 | 15.74 | 7.88 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 106.16 | 16.06 | 7.44 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 524.38 | 15.64 | 7.34 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 246.00 | 15.78 | 7.72 | + +---------+------+-----------+--------+-------------+ -.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial +.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in + parallel (v2.10) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 102.16 | 23.64 | 6.7 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 101.66 | 23.78 | 6.6 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 277.74 | 15.96 | 4.66 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 98.0 | 15.88 | 4.64 | - +---------+------+-----------+---------+-------------+ - | 1 | 2 | 97.66 | 15.88 | 4.62 | - +---------+------+-----------+---------+-------------+ - | 1 | 3 | 97.76 | 15.38 | 4.64 | - +---------+------+-----------+---------+-------------+ + +---------+------+-------------------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-------------------+--------+-------------+ + | 0 | 0 | 801.04 | 18.66 | 8.22 | + +---------+------+-------------------+--------+-------------+ + | 0 | 1 | 661.28 | 19.08 | 7.88 | + +---------+------+-------------------+--------+-------------+ + | 1 | 0 | 105.9 (-72.51%) | 20.3 | 7.58 | + +---------+------+-------------------+--------+-------------+ + | 1 | 1 | 383.58 (+261.32%) | 20.4 | 7.42 | + +---------+------+-------------------+--------+-------------+ + | 1 | 2 | 523.52 | 20.1 | 7.74 | + +---------+------+-------------------+--------+-------------+ + | 1 | 3 | 244.5 | 20.16 | 7.56 | + +---------+------+-------------------+--------+-------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9) + + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 99.80 | 15.94 | 5.42 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 99.76 | 15.80 | 5.24 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 278.26 | 16.16 | 4.58 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 96.88 | 16.00 | 4.52 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 96.80 | 16.12 | 4.54 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 96.88 | 16.12 | 4.54 | + +---------+------+-----------+--------+-------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10) + + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 99.84 | 18.86 | 5.54 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 100.2 | 18.82 | 5.66 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 278.12 | 20.56 | 4.48 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 96.68 | 20.62 | 4.3 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 96.94 | 20.14 | 4.42 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 96.68 | 20.46 | 4.32 | + +---------+------+-----------+--------+-------------+ ``CPU_OFF`` on all non-lead CPUs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -156,44 +231,82 @@ ``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead core to the deepest power level. -.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs +.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 265.38 | 34.12 | 167.36 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 265.72 | 33.98 | 167.48 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 185.3 | 23.18 | 87.42 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 101.58 | 23.46 | 4.48 | - +---------+------+-----------+---------+-------------+ - | 1 | 2 | 101.66 | 22.02 | 4.72 | - +---------+------+-----------+---------+-------------+ - | 1 | 3 | 101.48 | 22.22 | 4.52 | - +---------+------+-----------+---------+-------------+ + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 235.76 | 26.14 | 137.80 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 235.40 | 25.72 | 137.62 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 174.70 | 22.40 | 77.26 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 100.92 | 24.04 | 4.52 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 100.68 | 22.44 | 4.36 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 101.36 | 22.70 | 4.52 | + +---------+------+-----------+--------+-------------+ + +.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10) + + +---------------------------------------------------+ + | test_rt_instr_cpu_off_serial (latest) | + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 236.04 | 30.02 | 137.9 | + +---------+------+-----------+--------+-------------+ + | 0 | 1 | 235.38 | 29.7 | 137.72 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 175.18 | 26.96 | 77.26 | + +---------+------+-----------+--------+-------------+ + | 1 | 1 | 100.56 | 28.34 | 4.32 | + +---------+------+-----------+--------+-------------+ + | 1 | 2 | 100.38 | 26.82 | 4.3 | + +---------+------+-----------+--------+-------------+ + | 1 | 3 | 100.86 | 26.98 | 4.42 | + +---------+------+-----------+--------+-------------+ ``CPU_VERSION`` in parallel ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores +.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.9) - +-------------+--------+--------------+ - | Cluster | Core | Latency | - +=============+========+==============+ - | 0 | 0 | 1.22 | - +-------------+--------+--------------+ - | 0 | 1 | 1.2 | - +-------------+--------+--------------+ - | 1 | 0 | 0.6 | - +-------------+--------+--------------+ - | 1 | 1 | 1.08 | - +-------------+--------+--------------+ - | 1 | 2 | 1.04 | - +-------------+--------+--------------+ - | 1 | 3 | 1.04 | - +-------------+--------+--------------+ + +-------------+--------+-------------+ + | Cluster | Core | Latency | + +-------------+--------+-------------+ + | 0 | 0 | 1.48 | + +-------------+--------+-------------+ + | 0 | 1 | 1.04 | + +-------------+--------+-------------+ + | 1 | 0 | 0.56 | + +-------------+--------+-------------+ + | 1 | 1 | 0.92 | + +-------------+--------+-------------+ + | 1 | 2 | 0.96 | + +-------------+--------+-------------+ + | 1 | 3 | 0.96 | + +-------------+--------+-------------+ + +.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.10) + + +-------------+--------+----------------------+ + | Cluster | Core | Latency | + +-------------+--------+----------------------+ + | 0 | 0 | 1.1 (-25.68%) | + +-------------+--------+----------------------+ + | 0 | 1 | 1.06 | + +-------------+--------+----------------------+ + | 1 | 0 | 0.58 | + +-------------+--------+----------------------+ + | 1 | 1 | 0.88 | + +-------------+--------+----------------------+ + | 1 | 2 | 0.92 | + +-------------+--------+----------------------+ + | 1 | 3 | 0.9 | + +-------------+--------+----------------------+ Annotated Historic Results -------------------------- @@ -418,4 +531,3 @@ .. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/ .. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d .. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0 -.. _Testing Methodology: ../perf/psci-performance-methodology.html
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst index 70a1436..fd3c9c9 100644 --- a/docs/perf/psci-performance-n1sdp.rst +++ b/docs/perf/psci-performance-n1sdp.rst
@@ -10,8 +10,8 @@ - TFTF [`v2.9-rc0`_] - SCP/MCP `Prebuilt Images`_ -Please see the Runtime Instrumentation `Testing Methodology`_ page for more -details. +Please see the Runtime Instrumentation :ref:`Testing Methodology +<Runtime Instrumentation Methodology>` page for more details. Procedure --------- @@ -93,66 +93,129 @@ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in - parallel + parallel (v2.9) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 3.44 | 10.04 | 0.4 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 4.98 | 12.72 | 0.16 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 3.58 | 15.42 | 0.2 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 5.24 | 17.78 | 0.18 | - +---------+------+-----------+---------+-------------+ + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 2.80 | 10.08 | 0.80 | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 4.14 | 15.92 | 0.16 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 3.68 | 12.96 | 0.16 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 3.36 | 18.58 | 0.18 | + +---------+------+-----------+--------+-------------+ .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in - serial + parallel (v2.10) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 1.82 | 9.98 | 0.32 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 1.96 | 9.96 | 0.18 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 2.0 | 10.5 | 0.16 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 2.22 | 10.56 | 0.16 | - +---------+------+-----------+---------+-------------+ + +---------+------+----------------+------------------+-----------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+----------------+------------------+-----------------+ + | 0 | 0 | 2.12 | 23.94 (+137.50%) | 0.42 (-47.50%) | + +---------+------+----------------+------------------+-----------------+ + | 0 | 0 | 3.52 | 42.08 (+164.32%) | 0.26 (+62.50%) | + +---------+------+----------------+------------------+-----------------+ + | 1 | 0 | 2.76 (-25.00%) | 38.3 (+195.52%) | 0.26 (+62.50%) | + +---------+------+----------------+------------------+-----------------+ + | 1 | 0 | 2.64 | 44.56 (+139.83%) | 0.36 (+100.00%) | + +---------+------+----------------+------------------+-----------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in + serial (v2.9) + + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 1.86 | 9.92 | 0.32 | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 2.70 | 10.48 | 0.36 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 1.78 | 9.72 | 0.16 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 1.94 | 10.44 | 0.16 | + +---------+------+-----------+--------+-------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in + serial (v2.10) + + +---------+------+-----------+------------------+----------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+------------------+----------------+ + | 0 | 0 | 1.74 | 23.7 (+138.91%) | 0.3 | + +---------+------+-----------+------------------+----------------+ + | 0 | 0 | 2.08 | 23.96 (+128.63%) | 0.26 (-27.78%) | + +---------+------+-----------+------------------+----------------+ + | 1 | 0 | 1.9 | 23.62 (+143.00%) | 0.28 (+75.00%) | + +---------+------+-----------+------------------+----------------+ + | 1 | 0 | 2.06 | 23.92 (+129.12%) | 0.26 (+62.50%) | + +---------+------+-----------+------------------+----------------+ ``CPU_SUSPEND`` to power level 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in - parallel + parallel (v2.9) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 1.52 | 11.84 | 0.34 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 1.1 | 13.66 | 0.14 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 2.18 | 9.48 | 0.18 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 2.06 | 14.4 | 0.16 | - +---------+------+-----------+---------+-------------+ + +---------------------------------------------------+ + | test_rt_instr_cpu_susp_parallel | + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 0.88 | 12.32 | 0.26 | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 2.12 | 14.62 | 0.26 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 1.86 | 14.14 | 0.16 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 1.92 | 9.44 | 0.18 | + +---------+------+-----------+--------+-------------+ -.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial +.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in + parallel (v2.10) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 1.54 | 9.34 | 0.3 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 1.88 | 9.5 | 0.16 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 1.86 | 9.86 | 0.2 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 2.02 | 9.64 | 0.18 | - +---------+------+-----------+---------+-------------+ + +---------+------+---------------+------------------+----------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+---------------+------------------+----------------+ + | 0 | 0 | 1.5 (+70.45%) | 35.02 (+184.25%) | 0.24 | + +---------+------+---------------+------------------+----------------+ + | 0 | 0 | 1.92 | 38.12 (+160.74%) | 0.28 | + +---------+------+---------------+------------------+----------------+ + | 1 | 0 | 1.88 | 38.1 (+169.45%) | 0.26 (+62.50%) | + +---------+------+---------------+------------------+----------------+ + | 1 | 0 | 2.04 | 23.1 (+144.70%) | 0.24 | + +---------+------+---------------+------------------+----------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9) + + +---------------------------------------------------+ + | test_rt_instr_cpu_susp_serial | + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 1.52 | 9.40 | 0.30 | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 1.92 | 9.80 | 0.18 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 2.20 | 9.60 | 0.14 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 1.82 | 9.78 | 0.18 | + +---------+------+-----------+--------+-------------+ + +.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10) + + +---------+------+-----------+------------------+-----------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+------------------+-----------------+ + | 0 | 0 | 1.52 | 23.08 (+145.53%) | 0.3 | + +---------+------+-----------+------------------+-----------------+ + | 0 | 0 | 1.98 | 23.68 (+141.63%) | 0.28 (+55.56%) | + +---------+------+-----------+------------------+-----------------+ + | 1 | 0 | 1.84 | 23.86 (+148.54%) | 0.28 (+100.00%) | + +---------+------+-----------+------------------+-----------------+ + | 1 | 0 | 1.98 | 23.68 (+142.13%) | 0.28 (+55.56%) | + +---------+------+-----------+------------------+-----------------+ ``CPU_OFF`` on all non-lead CPUs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -160,36 +223,68 @@ ``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead core to the deepest power level. -.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs +.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9) - +---------+------+-----------+---------+-------------+ - | Cluster | Core | Powerdown | Wakekup | Cache Flush | - +=========+======+===========+=========+=============+ - | 0 | 0 | 1.86 | 9.88 | 0.32 | - +---------+------+-----------+---------+-------------+ - | 0 | 1 | 21.1 | 12.44 | 0.42 | - +---------+------+-----------+---------+-------------+ - | 1 | 0 | 21.22 | 13.2 | 0.32 | - +---------+------+-----------+---------+-------------+ - | 1 | 1 | 21.56 | 13.18 | 0.54 | - +---------+------+-----------+---------+-------------+ + +---------+------+-----------+--------+-------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 1.84 | 9.94 | 0.32 | + +---------+------+-----------+--------+-------------+ + | 0 | 0 | 14.20 | 13.10 | 0.50 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 13.88 | 12.36 | 0.42 | + +---------+------+-----------+--------+-------------+ + | 1 | 0 | 14.40 | 13.26 | 0.52 | + +---------+------+-----------+--------+-------------+ + +.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10) + + +---------+------+-----------+------------------+----------------+ + | Cluster | Core | Powerdown | Wakeup | Cache Flush | + +---------+------+-----------+------------------+----------------+ + | 0 | 0 | 1.78 | 23.7 (+138.43%) | 0.3 | + +---------+------+-----------+------------------+----------------+ + | 0 | 0 | 13.96 | 31.16 (+137.86%) | 0.34 (-32.00%) | + +---------+------+-----------+------------------+----------------+ + | 1 | 0 | 13.54 | 30.24 (+144.66%) | 0.26 (-38.10%) | + +---------+------+-----------+------------------+----------------+ + | 1 | 0 | 14.46 | 31.12 (+134.69%) | 0.7 (+34.62%) | + +---------+------+-----------+------------------+----------------+ ``CPU_VERSION`` in parallel ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores +.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.9) - +-------------+--------+--------------+ - | Cluster | Core | Latency | - +=============+========+==============+ - | 0 | 0 | 0.08 | - +-------------+--------+--------------+ - | 0 | 1 | 0.22 | - +-------------+--------+--------------+ - | 1 | 0 | 0.28 | - +-------------+--------+--------------+ - | 1 | 1 | 0.26 | - +-------------+--------+--------------+ + +------------------------------------+ + | test_rt_instr_psci_version_parallel| + +-------------+--------+-------------+ + | Cluster | Core | Latency | + +-------------+--------+-------------+ + | 0 | 0 | 0.08 | + +-------------+--------+-------------+ + | 0 | 0 | 0.26 | + +-------------+--------+-------------+ + | 1 | 0 | 0.20 | + +-------------+--------+-------------+ + | 1 | 0 | 0.26 | + +-------------+--------+-------------+ + +.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.10) + + +----------------------------------------------+ + | test_rt_instr_psci_version_parallel (latest) | + +-------------+--------+-----------------------+ + | Cluster | Core | Latency | + +-------------+--------+-----------------------+ + | 0 | 0 | 0.14 (+75.00%) | + +-------------+--------+-----------------------+ + | 0 | 0 | 0.22 | + +-------------+--------+-----------------------+ + | 1 | 0 | 0.2 | + +-------------+--------+-----------------------+ + | 1 | 0 | 0.26 | + +-------------+--------+-----------------------+ -------------- @@ -200,4 +295,3 @@ .. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst .. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/ .. _N1SDP: https://developer.arm.com/documentation/101489/latest -.. _Testing Methodology: ../perf/psci-performance-methodology.html \ No newline at end of file
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst index e7e7ee7..3301067 100644 --- a/docs/plat/arm/arm-build-options.rst +++ b/docs/plat/arm/arm-build-options.rst
@@ -90,38 +90,6 @@ of the translation tables library instead of version 2. It is set to 0 by default, which selects version 2. -- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm® - TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm - platforms. If this option is specified, then the path to the CryptoCell - SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. - -- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can - configure an Arm® Ethos™-N NPU. To use this service the target platform's - ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only - the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform - only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. - -- ``ARM_ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the - Arm® Ethos™-N NPU. Requires ``ARM_ETHOSN_NPU_DRIVER`` and - ``TRUSTED_BOARD_BOOT`` to be enabled. - -- ``ARM_ETHOSN_NPU_FW``: location of the NPU firmware binary - (```ethosn.bin```). This firmware image will be included in the FIP and - loaded at runtime. - -- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the - SPMC Core manifest. Valid when ``SPD=spmd`` is selected. - -- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded - SP nodes in tb_fw_config. - -- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in tb_fw_config - device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest - file name contains pattern optee_sp. - -- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and - internal-trusted-storage) as SP in tb_fw_config device tree. - - ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of the various partitions present in the GPT image. This support is available only for the BL2 component, and it is disabled by default. @@ -169,6 +137,21 @@ require all the CPUs to execute the CPU specific power down sequence to complete a warm reboot sequence in which only the CPUs are power cycled. +Arm FVP Build Options +--------------------- + +- ``FVP_TRUSTED_SRAM_SIZE``: Size (in kilobytes) of the Trusted SRAM region to + utilize when building for the FVP platform. This option defaults to 256. + +Arm Juno Build Options +---------------------- + +- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 + runtime software in AArch32 mode, which is required to run AArch32 on Juno. + By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in + AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable + images. + -------------- .. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index 42c0eda..700020f 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst
@@ -12,7 +12,7 @@ (64-bit host machine only). .. note:: - The FVP models used are Version 11.19 Build 14, unless otherwise stated. + The FVP models used are Version 11.22 Build 14, unless otherwise stated. - ``Foundation_Platform`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21) @@ -41,19 +41,18 @@ - ``FVP_Base_Cortex-A76AE`` - ``FVP_Base_Cortex-A77`` - ``FVP_Base_Cortex-A78`` +- ``FVP_Base_Cortex-A78AE`` - ``FVP_Base_Cortex-A78C`` - ``FVP_Base_Cortex-X2x4`` (Version 11.17/21) - ``FVP_Base_Neoverse-E1`` - ``FVP_Base_Neoverse-N1`` -- ``FVP_Base_Neoverse-N2x4`` (Version 11.16/16) - ``FVP_Base_Neoverse-V1`` - ``FVP_Base_RevC-2xAEMvA`` -- ``FVP_Morello`` (Version 0.11/33) -- ``FVP_RD_E1_edge`` (Version 11.17/29) -- ``FVP_RD_V1`` (Version 11.17/29) -- ``FVP_TC0`` (Version 11.17/18) -- ``FVP_TC1`` (Version 11.17/33) -- ``FVP_TC2`` (Version 11.18/28) +- ``FVP_BaseR_AEMv8R`` +- ``FVP_Morello`` (Version 0.11/33) +- ``FVP_RD_V1`` +- ``FVP_TC1`` +- ``FVP_TC2`` (Version 11.20/24) The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded @@ -631,7 +630,7 @@ -------------- -*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* +*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* .. _FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_fw_config.dts .. _Arm's website: `FVP models`_
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst index ea7d11c..5320a3b 100644 --- a/docs/plat/arm/juno/index.rst +++ b/docs/plat/arm/juno/index.rst
@@ -249,4 +249,4 @@ .. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ .. _Juno Getting Started Guide: https://developer.arm.com/documentation/den0928/f/?lang=en -.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf +.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/plat/arm/morello/index.rst b/docs/plat/arm/morello/index.rst index b18001ca..91549c0 100644 --- a/docs/plat/arm/morello/index.rst +++ b/docs/plat/arm/morello/index.rst
@@ -12,9 +12,19 @@ Boot Sequence ------------- -The execution begins from SCP_BL1 which loads the SCP_BL2 and starts its -execution. SCP_BL2 powers up the AP which starts execution at AP_BL31. The AP -then continues executing and hands off execution to Non-secure world (UEFI). +The SCP initializes the RVBAR registers to point to the AP_BL1. Once RVBAR is +initialized, the primary core is powered on. The primary core boots the AP_BL1. +It performs minimum initialization necessary to load and authenticate the AP +firmware image (the FIP image) from the AP QSPI NOR Flash Memory into the +Trusted SRAM. + +AP_BL1 authenticates and loads the AP_BL2 image. AP_BL2 performs additional +initializations, and then authenticates and loads the AP_BL31 and AP_BL33. +AP_BL2 then transfers execution control to AP_BL31, which is the EL3 runtime +firmware. Execution is finally handed off to AP_BL33, which is the non-secure +world (UEFI). + +SCP -> AP_BL1 -> AP_BL2 -> AP_BL31 -> AP_BL33 Build Procedure (TF-A only) ~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -30,4 +40,4 @@ make PLAT=morello all -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst index df1847d..9469e9a 100644 --- a/docs/plat/arm/tc/index.rst +++ b/docs/plat/arm/tc/index.rst
@@ -17,10 +17,9 @@ (TARGET_PLATFORM=1), TC2 (TARGET_PLATFORM=2) platforms w.r.t to TF-A is the CPUs supported as below: -- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. -- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3. -- TC2 has support for Hayes and Hunter Arm CPUs. - +- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated) +- TC1 has support for Cortex A510, Cortex A715 and Cortex X3. (Note TC1 is now deprecated) +- TC2 has support for Cortex A520, Cortex A720 and Cortex x4. Boot Sequence ------------- @@ -58,6 +57,6 @@ -------------- -*Copyright (c) 2020-2022, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* .. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
diff --git a/docs/plat/ast2700.rst b/docs/plat/ast2700.rst new file mode 100644 index 0000000..6deade3 --- /dev/null +++ b/docs/plat/ast2700.rst
@@ -0,0 +1,17 @@ +Aspeed AST2700 +============== + +Aspeed AST2700 is a 64-bit ARM SoC with 4-cores Cortex-A35 integrated. +Each core operates at 1.6GHz. + +Boot Flow +--------- + + BootRom --> TF-A BL31 --> BL32 --> BL33 --> Linux Kernel + +How to build +------------ + +.. code:: shell + + make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700 SPD=opteed
diff --git a/docs/plat/imx9.rst b/docs/plat/imx9.rst new file mode 100644 index 0000000..4adaae3 --- /dev/null +++ b/docs/plat/imx9.rst
@@ -0,0 +1,60 @@ +NXP i.MX 9 Series +================== + +Building on the market-proven i.MX 6 and i.MX 8 series, i.MX 9 series applications +processors bring together higher performance applications cores, an independent +MCU-like real-time domain, Energy Flex architecture, state-of-the-art security +with EdgeLock® secure enclave and dedicated multi-sensory data processing engines +(graphics, image, display, audio and voice). The i.MX 9 series, part of the EdgeVerse™ +edge computing platform, integrates hardware neural processing units across many +members of the series for acceleration of machine learning applications at the edge +`i.MX9 Applications Processors`_. + +Boot Sequence +------------- + +BootROM --> SPL --> BL31 --> BL33(u-boot) --> Linux kernel + +How to build +------------ + +Build Procedure +~~~~~~~~~~~~~~~ + +- Prepare AARCH64 toolchain. + +- Get the ELE FW image from NXP linux SDK package + +- Build SPL and u-boot firstly, and get binary images: u-boot-spl.bin, + u-boot.bin and dtb + +- Build TF-A + + Build bl31: + + .. code:: shell + + CROSS_COMPILE=aarch64-linux-gnu- make PLAT=<Target_SoC> bl31 + + Target_SoC should be "imx93" for i.MX93 SoC. + +Deploy TF-A Images +~~~~~~~~~~~~~~~~~~ + +TF-A binary(bl31.bin), u-boot-spl.bin u-boot.bin, ELE FW image are combined +together to generate a binary file called flash.bin, the imx-mkimage tool is +used to generate flash.bin, and flash.bin needs to be flashed into SD card +with certain offset for BOOT ROM. + +Reference Documentation +~~~~~~~~~~~~~~~~~~~~~~~ + +Details on how to prepare, generate & deploy the boot image be found in following documents: + +- i.MX Linux User's Guide + `link <https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX>`__ +- i.MX Linux Reference Manual + `link <https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applications-processors:IMXLINUX>`__ + +.. _i.MX9 Applications Processors: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors:IMX9-PROCESSORS +
diff --git a/docs/plat/index.rst b/docs/plat/index.rst index 57c7303..b1ccaa5 100644 --- a/docs/plat/index.rst +++ b/docs/plat/index.rst
@@ -8,6 +8,7 @@ allwinner arm/index + ast2700 meson-axg meson-gxbb meson-gxl @@ -26,6 +27,8 @@ warp7 imx8 imx8m + imx9 + npcm845x nxp/index poplar qemu @@ -39,7 +42,7 @@ rockchip socionext-uniphier synquacer - stm32mp1 + st/index ti-k3 xilinx-versal-net xilinx-versal @@ -70,13 +73,15 @@ +----------------+----------------+--------------------+--------------------+ | mt6795 | MTK | 2.5 | 2.7 | +----------------+----------------+--------------------+--------------------+ -| sgi575 | Arm | 2.8 | 3.0 | +| sgi575 | Arm | 2.8 | TBD | +----------------+----------------+--------------------+--------------------+ -| rdn1edge | Arm | 2.8 | 3.0 | +| rdn1edge | Arm | 2.8 | TBD | +----------------+----------------+--------------------+--------------------+ -| tc0 | Arm | 2.8 | 3.0 | +| tc0 | Arm | 2.8 | 2.10 | +----------------+----------------+--------------------+--------------------+ -| rde1edge | Arm | 2.9 | 3.1 | +| tc1 | Arm | 2.10 | TBD | ++----------------+----------------+--------------------+--------------------+ +| rde1edge | Arm | 2.9 | 3.0 | +----------------+----------------+--------------------+--------------------+ --------------
diff --git a/docs/plat/npcm845x.rst b/docs/plat/npcm845x.rst new file mode 100644 index 0000000..91dbfd9 --- /dev/null +++ b/docs/plat/npcm845x.rst
@@ -0,0 +1,21 @@ +Nuvoton NPCM845X +================ + +Nuvoton NPCM845X is the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC. + +The Nuvoton Arbel NPCM845X SoC is a fourth-generation BMC. +The NPCM845X computing subsystem comprises a quadcore Arm Cortex-A35 CPU. + +This SoC includes secured components, i.e., bootblock stored in ROM, +u-boot, OPTEE-OS, trusted-firmware-a and Linux. +Every stage is measured and validated by the bootblock. +This SoC was tested on the Arbel NPCM845X evaluation board. + + +How to Build +------------ + +.. code:: shell + + make CROSS_COMPILE=aarch64-none-elf- PLAT=npcm845x all SPD=opteed +
diff --git a/docs/plat/qti-msm8916.rst b/docs/plat/qti-msm8916.rst index 09a79b7..3bc121a 100644 --- a/docs/plat/qti-msm8916.rst +++ b/docs/plat/qti-msm8916.rst
@@ -1,16 +1,27 @@ -Qualcomm Snapdragon 410 (MSM8916/APQ8016) -========================================= +Qualcomm MSM8916 +================ +The MSM8916 platform port in TF-A supports multiple similar Qualcomm SoCs: -The `Qualcomm Snapdragon 410`_ is Qualcomm's first 64-bit SoC, released in 2014 -with four ARM Cortex-A53 cores. There are differents variants (MSM8916, -APQ8016(E), ...) that are all very similar. A popular device based on APQ8016E -is the `DragonBoard 410c`_ single-board computer, but the SoC is also used in -various mid-range smartphones/tablets. ++-----------------------+----------------+-------------------+-----------------+ +| System-on-Chip (SoC) | TF-A Platform | Application CPU | Supports | ++=======================+================+===================+=================+ +| `Snapdragon 410`_ |``PLAT=msm8916``| 4x ARM Cortex-A53 | AArch64/AArch32 | +| (MSM8x16, APQ8016(E)) | | | | +| (`DragonBoard 410c`_) | | | | ++-----------------------+----------------+-------------------+-----------------+ +| `Snapdragon 615`_ |``PLAT=msm8939``| 4x ARM Cortex-A53 | AArch64/AArch32 | +| (MSM8x39, APQ8039) | | 4x ARM Cortex-A53 | | ++-----------------------+----------------+-------------------+-----------------+ +| `Snapdragon 210`_ |``PLAT=msm8909``| 4x ARM Cortex-A7 | AArch32 only | +| (MSM8x09, APQ8009) | | | | ++-----------------------+----------------+-------------------+-----------------+ +| `Snapdragon X5 Modem`_|``PLAT=mdm9607``| 1x ARM Cortex-A7 | AArch32 only | +| (MDM9x07) | | | | ++-----------------------+----------------+-------------------+-----------------+ -The TF-A/BL31 port for MSM8916 provides a minimal, community-maintained -EL3 firmware. It is primarily based on information from the public -`Snapdragon 410E Technical Reference Manual`_ combined with a lot of -trial and error to actually make it work. +It provides a minimal, community-maintained EL3 firmware and PSCI implementation, +based on information from the public `Snapdragon 410E Technical Reference Manual`_ +combined with a lot of trial and error to actually make it work. .. note:: Unlike the :doc:`QTI SC7180/SC7280 <qti>` ports, this port does **not** @@ -20,8 +31,7 @@ Functionality ------------- - -The BL31 port is much more minimal compared to the original firmware and +The TF-A port is much more minimal compared to the original firmware and therefore expects the non-secure world (e.g. Linux) to manage more hardware, such as the SMMUs and all remote processors (RPM, WCNSS, Venus, Modem). Everything except modem is currently functional with a slightly modified version @@ -41,28 +51,77 @@ Boot Flow --------- -BL31 replaces the original ``tz`` firmware in the boot flow:: +BL31 (AArch64) or BL32/SP_MIN (AArch32) replaces the original ``tz`` firmware +in the boot flow:: Boot ROM (PBL) -> SBL -> BL31 (EL3) -> U-Boot (EL2) -> Linux (EL2) -By default, BL31 enters the non-secure world in EL2 AArch64 state at address -``0x8f600000``. The original hypervisor firmware (``hyp``) is not used, you can -use KVM or another hypervisor. The entry address is fixed in the BL31 binary -but can be changed using the ``PRELOADED_BL33_BASE`` make file parameter. +After initialization the normal world starts at a fixed entry address in EL2/HYP +mode, configured using ``PRELOADED_BL33_BASE``. At runtime, it is expected that +the normal world bootloader was already loaded into RAM by a previous firmware +component (usually SBL) and that it is capable of running in EL2/HYP mode. -Using an AArch64 bootloader (such as `U-Boot for DragonBoard 410c`_) is -recommended. AArch32 bootloaders (such as the original Little Kernel bootloader -from Qualcomm) are not directly supported, although it is possible to use an EL2 -shim loader to temporarily switch to AArch32 state. +`U-Boot for DragonBoard 410c`_ is recommended if possible. The original Little +Kernel-based bootloader from Qualcomm does not support EL2/HYP, but can be +booted using an additional shim loader such as `tfalkstub`_. + +Build +----- +It is possible to build for either AArch64 or AArch32. Some platforms use 32-bit +CPUs that only support AArch32 (see table above). For all others AArch64 is the +preferred build option. + +AArch64 (BL31) +^^^^^^^^^^^^^^ +Setup the cross compiler for AArch64 and build BL31 for one of the platforms in +the table above:: + + $ make CROSS_COMPILE=aarch64-none-elf- PLAT=... + +The BL31 ELF image is generated in ``build/$PLAT/release/bl31/bl31.elf``. + +AArch32 (BL32/SP_MIN) +^^^^^^^^^^^^^^^^^^^^^ +Setup the cross compiler for AArch32 and build BL32 with SP_MIN for one of the +platforms in the table above:: + + $ make CROSS_COMPILE=arm-none-eabi- PLAT=... ARCH=aarch32 AARCH32_SP=sp_min + +The BL32 ELF image is generated in ``build/$PLAT/release/bl32/bl32.elf``. + +Build Options +------------- +Some options can be changed at build time by adding them to the make command line: + + * ``QTI_UART_NUM``: Number of UART controller to use for debug output and crash + reports. This must be the same UART as used by earlier boot firmware since + the UART controller does not get fully initialized at the moment. Defaults to + the usual debug UART used for the platform (see ``platform.mk``). + * ``QTI_RUNTIME_UART``: By default (``0``) the UART is only used for the boot + process and critical crashes. If set to ``1`` it is also used for runtime + messages. Note that this option can only be used if the UART is reserved in + the normal world and the necessary clocks remain enabled. + +The memory region used for the different firmware components is not fixed and +can be changed on the make command line. The default values match the addresses +used by the original firmware (see ``platform.mk``): + + * ``PRELOADED_BL33_BASE``: The entry address for the normal world. Usually + refers to the first bootloader (e.g. U-Boot). + * ``BL31_BASE``: Base address for the BL31 firmware component. Must point to + a 64K-aligned memory region with at least 128 KiB space that is permanently + reserved in the normal world. + * ``BL32_BASE``: Base address for the BL32 firmware component. + + * **AArch32:** BL32 is used in place of BL31, so the option is equivalent to + ``BL31_BASE``. + * **AArch64:** Secure-EL1 Payload. Defaults to using 128 KiB of space + directly after BL31. For testing only, the port is primarily intended as + a minimal PSCI implementation without a separate secure world. Installation ------------ -First, setup the cross compiler for AArch64 and build TF-A for ``msm8916``:: - - $ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=msm8916 - -The BL31 ELF image is generated in ``build/msm8916/release/bl31/bl31.elf``. -This image must be "signed" before flashing it, even if the board has secure +The ELF image must be "signed" before flashing it, even if the board has secure boot disabled. In this case the signature does not provide any security, but it provides the firmware with required metadata. @@ -75,6 +134,10 @@ Then install the resulting ``build/msm8916/release/bl31/bl31-test-signed.mbn`` to the ``tz`` partition on the device. BL31 should be running after a reboot. +.. note:: + On AArch32 the ELF image is called ``bl32.elf``. + The installation procedure is identical. + .. warning:: Do not flash incorrectly signed firmware on devices that have secure boot enabled! Make sure that you have a way to recover the board in case @@ -82,8 +145,11 @@ Boot Trace ---------- -BL31 prints some lines on the debug console UART2, which will usually look like -this (with ``DEBUG=1``, otherwise only the ``NOTICE`` lines are shown):: + +AArch64 (BL31) +^^^^^^^^^^^^^^ +BL31 prints some lines on the debug console, which will usually look like this +(with ``DEBUG=1``, otherwise only the ``NOTICE`` lines are shown):: ... S - DDR Frequency, 400 MHz @@ -109,8 +175,37 @@ Qualcomm-DragonBoard 410C ... -.. _Qualcomm Snapdragon 410: https://www.qualcomm.com/products/snapdragon-processors-410 +AArch32 (BL32/SP_MIN) +^^^^^^^^^^^^^^^^^^^^^ +BL32/SP_MIN prints some lines on the debug console, which will usually look like +this (with ``DEBUG=1``, otherwise only the ``NOTICE`` lines are shown):: + + ... + S - DDR Frequency, 400 MHz + NOTICE: SP_MIN: v2.8(debug):v2.8 + NOTICE: SP_MIN: Built : 23:03:31, Mar 31 2023 + INFO: SP_MIN: Platform setup start + INFO: ARM GICv2 driver initialized + INFO: SP_MIN: Platform setup done + INFO: SP_MIN: Initializing runtime services + INFO: BL32: cortex_a53: CPU workaround for 819472 was applied + INFO: BL32: cortex_a53: CPU workaround for 824069 was applied + INFO: BL32: cortex_a53: CPU workaround for 826319 was applied + INFO: BL32: cortex_a53: CPU workaround for 827319 was applied + INFO: BL32: cortex_a53: CPU workaround for disable_non_temporal_hint was applied + INFO: SP_MIN: Preparing exit to normal world + INFO: Entry point address = 0x86400000 + INFO: SPSR = 0x1da + Android Bootloader - UART_DM Initialized!!! + [0] welcome to lk + ... + +.. _Snapdragon 210: https://www.qualcomm.com/products/snapdragon-processors-210 +.. _Snapdragon 410: https://www.qualcomm.com/products/snapdragon-processors-410 +.. _Snapdragon 615: https://www.qualcomm.com/products/snapdragon-processors-615 +.. _Snapdragon X5 Modem: https://www.qualcomm.com/products/snapdragon-modems-4g-lte-x5 .. _DragonBoard 410c: https://www.96boards.org/product/dragonboard410c/ .. _Snapdragon 410E Technical Reference Manual: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf .. _U-Boot for DragonBoard 410c: https://u-boot.readthedocs.io/en/latest/board/qualcomm/dragonboard410c.html .. _qtestsign: https://github.com/msm8916-mainline/qtestsign +.. _tfalkstub: https://github.com/msm8916-mainline/tfalkstub
diff --git a/docs/plat/rpi3.rst b/docs/plat/rpi3.rst index 38c3dfa..5d97a88 100644 --- a/docs/plat/rpi3.rst +++ b/docs/plat/rpi3.rst
@@ -296,11 +296,6 @@ address by changing the file ``armstub8.bin``, so there's no point in using TF-A in this case. -- ``MULTI_CONSOLE_API=0``: The multi console API must be enabled. Note that the - crash console uses the internal 16550 driver functions directly in order to be - able to print error messages during early crashes before setting up the - multi console API. - Building the firmware for kernels that don't support PSCI ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/plat/st/index.rst b/docs/plat/st/index.rst new file mode 100644 index 0000000..95ec3d2 --- /dev/null +++ b/docs/plat/st/index.rst
@@ -0,0 +1,14 @@ +STMicroelectronics STM32 MPUs +============================= + +.. toctree:: + :maxdepth: 1 + :caption: Contents + + stm32mpus + stm32mp1 + stm32mp2 + +-------------- + +*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mp1.rst b/docs/plat/st/stm32mp1.rst new file mode 100644 index 0000000..b6e4b0d --- /dev/null +++ b/docs/plat/st/stm32mp1.rst
@@ -0,0 +1,220 @@ +STM32MP1 +======== + +STM32MP1 is a microprocessor designed by STMicroelectronics +based on Arm Cortex-A7. +It is an Armv7-A platform, using dedicated code from TF-A. +More information can be found on `STM32MP1 Series`_ page. + +For TF-A common configuration of STM32 MPUs, please check +:ref:`STM32 MPUs` page. + +STM32MP1 Versions +----------------- + +There are 2 variants for STM32MP1: STM32MP13 and STM32MP15 + +STM32MP13 Versions +~~~~~~~~~~~~~~~~~~ +The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible: + +- STM32MP131: Single Cortex-A7 core +- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 +- STM32MP135: STM32MP133 + DCMIPP, LTDC + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Cortex-A7 @ 650 MHz +- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz +- D Cortex-A7 @ 900 MHz +- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz + +STM32MP15 Versions +~~~~~~~~~~~~~~~~~~ +The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible: + +- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD +- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD +- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Basic + Cortex-A7 @ 650 MHz +- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz +- D Basic + Cortex-A7 @ 800 MHz +- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz + +The `STM32MP1 part number codification`_ page gives more information about part numbers. + +Memory mapping +-------------- + +:: + + 0x00000000 +-----------------+ + | | ROM + 0x00020000 +-----------------+ + | | + | ... | + | | + 0x2FFC0000 +-----------------+ \ + | BL32 DTB | | + 0x2FFC5000 +-----------------+ | + | BL32 | | + 0x2FFDF000 +-----------------+ | + | ... | | + 0x2FFE3000 +-----------------+ | + | BL2 DTB | | Embedded SRAM + 0x2FFEA000 +-----------------+ | + | BL2 | | + 0x2FFFF000 +-----------------+ | + | SCMI mailbox | | + 0x30000000 +-----------------+ / + | | + | ... | + | | + 0x40000000 +-----------------+ + | | + | | Devices + | | + 0xC0000000 +-----------------+ \ + | | | + 0xC0100000 +-----------------+ | + | BL33 | | Non-secure RAM (DDR) + | ... | | + | | | + 0xFFFFFFFF +-----------------+ / + + +Build Instructions +------------------ + +STM32MP1x specific flags +~~~~~~~~~~~~~~~~~~~~~~~~ + +Dedicated STM32MP1 flags: + +- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter. + | Default: 0 +- | ``STM32MP13``: to select STM32MP13 variant configuration. + | Default: 0 +- | ``STM32MP15``: to select STM32MP15 variant configuration. + | Default: 1 + + +Boot with FIP +~~~~~~~~~~~~~ +You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary. + +U-Boot +______ + +.. code:: bash + + cd <u-boot_directory> + make stm32mp15_trusted_defconfig + make DEVICE_TREE=stm32mp157c-ev1 all + +OP-TEE (optional) +_________________ + +.. code:: bash + + cd <optee_directory> + make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \ + CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts + + +TF-A BL32 (SP_min) +__________________ +If you choose not to use OP-TEE, you can use TF-A SP_min. +To build TF-A BL32, and its device tree file: + +.. code:: bash + + make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ + AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs + +TF-A BL2 +________ +To build TF-A BL2 with its STM32 header for SD-card boot: + +.. code:: bash + + make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ + DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1 + +For other boot devices, you have to replace STM32MP_SDMMC in the previous command +with the desired device flag. + +This BL2 is independent of the BL32 used (SP_min or OP-TEE) + + +FIP +___ +With BL32 SP_min: + +.. code:: bash + + make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ + AARCH32_SP=sp_min \ + DTB_FILE_NAME=stm32mp157c-ev1.dtb \ + BL33=<u-boot_directory>/u-boot-nodtb.bin \ + BL33_CFG=<u-boot_directory>/u-boot.dtb \ + fip + +With OP-TEE: + +.. code:: bash + + make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ + AARCH32_SP=optee \ + DTB_FILE_NAME=stm32mp157c-ev1.dtb \ + BL33=<u-boot_directory>/u-boot-nodtb.bin \ + BL33_CFG=<u-boot_directory>/u-boot.dtb \ + BL32=<optee_directory>/tee-header_v2.bin \ + BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin + BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin + fip + +Trusted Boot Board +__________________ + +.. code:: shell + + tools/cert_create/cert_create -n --rot-key build/stm32mp1/release/rot_key.pem \ + --tfw-nvctr 0 \ + --ntfw-nvctr 0 \ + --key-alg ecdsa --hash-alg sha256 \ + --trusted-key-cert build/stm32mp1/release/trusted_key.crt \ + --tos-fw <optee_directory>/tee-header_v2.bin \ + --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ + --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ + --tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \ + --tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \ + --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ + --nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \ + --nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \ + --hw-config <u-boot_directory>/u-boot.dtb \ + --fw-config build/stm32mp1/release/fdts/fw-config.dtb \ + --stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt + + tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \ + --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ + --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ + --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ + --hw-config <u-boot_directory>/u-boot.dtb \ + --fw-config build/stm32mp1/release/fdts/fw-config.dtb \ + --trusted-key-cert build/stm32mp1/release/trusted_key.crt \ + --tos-fw-cert build/stm32mp1/release/tos_fw_content.crt \ + --tos-fw-key-cert build/stm32mp1/release/tos_fw_key.crt \ + --nt-fw-cert build/stm32mp1/release/nt_fw_content.crt \ + --nt-fw-key-cert build/stm32mp1/release/nt_fw_key.crt \ + --stm32mp-cfg-cert build/stm32mp1/release/stm32mp_cfg_cert.crt \ + build/stm32mp1/release/stm32mp1.fip + + +.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html +.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification + +*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst new file mode 100644 index 0000000..43e131d --- /dev/null +++ b/docs/plat/st/stm32mp2.rst
@@ -0,0 +1,133 @@ +STM32MP2 +======== + +STM32MP2 is a microprocessor designed by STMicroelectronics +based on Arm Cortex-A35. + +For TF-A common configuration of STM32 MPUs, please check +:ref:`STM32 MPUs` page. + +STM32MP2 Versions +----------------- + +The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible: + +- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS +- STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI / NN - LVDS +- STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS +- STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Basic + Cortex-A35 @ 1GHz +- C Secure Boot + HW Crypto + Cortex-A35 @ 1GHz +- D Basic + Cortex-A35 @ 1.5GHz +- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz + +Memory mapping +-------------- + +:: + + 0x00000000 +-----------------+ + | | + | ... | + | | + 0x0E000000 +-----------------+ \ + | BL31 | | + +-----------------+ | + | ... | | + 0x0E012000 +-----------------+ | + | BL2 DTB | | Embedded SRAM + 0x0E016000 +-----------------+ | + | BL2 | | + 0x0E040000 +-----------------+ / + | | + | ... | + | | + 0x40000000 +-----------------+ + | | + | | Devices + | | + 0x80000000 +-----------------+ \ + | | | + | | | Non-secure RAM (DDR) + | | | + 0xFFFFFFFF +-----------------+ / + + +Build Instructions +------------------ + +STM32MP2x specific flags +~~~~~~~~~~~~~~~~~~~~~~~~ + +Dedicated STM32MP2 build flags: + +- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP. + | Default: 1 +- | ``STM32MP25``: to select STM32MP25 variant configuration. + | Default: 1 + +To compile the correct DDR driver, one flag must be set among: + +- | ``STM32MP_DDR3_TYPE``: to compile DDR3 driver and DT. + | Default: 0 +- | ``STM32MP_DDR4_TYPE``: to compile DDR4 driver and DT. + | Default: 0 +- | ``STM32MP_LPDDR4_TYPE``: to compile LpDDR4 driver and DT. + | Default: 0 + + +Boot with FIP +~~~~~~~~~~~~~ +You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) before building FIP binary. + +U-Boot +______ + +.. code:: bash + + cd <u-boot_directory> + make stm32mp25_defconfig + make DEVICE_TREE=stm32mp257f-ev1 all + +OP-TEE +______ + +.. code:: bash + + cd <optee_directory> + make CROSS_COMPILE64=aarch64-none-elf- CROSS_COMPILE32=arm-none-eabi- + ARCH=arm PLATFORM=stm32mp2 \ + CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts + +TF-A BL2 & BL31 +_______________ +To build TF-A BL2 with its STM32 header and BL31 for SD-card boot: + +.. code:: bash + + make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \ + STM32MP_DDR4_TYPE=1 SPD=opteed \ + DTB_FILE_NAME=stm32mp257f-ev1.dtb STM32MP_SDMMC=1 + +For other boot devices, you have to replace STM32MP_SDMMC in the previous command +with the desired device flag. + + +FIP +___ + +.. code:: bash + + make CROSS_COMPILE=aarch64-none-elf- PLAT=stm32mp2 \ + STM32MP_DDR4_TYPE=1 SPD=opteed \ + DTB_FILE_NAME=stm32mp257f-ev1.dtb \ + BL33=<u-boot_directory>/u-boot-nodtb.bin \ + BL33_CFG=<u-boot_directory>/u-boot.dtb \ + BL32=<optee_directory>/tee-header_v2.bin \ + BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin + fip + +*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/st/stm32mpus.rst b/docs/plat/st/stm32mpus.rst new file mode 100644 index 0000000..931dd57 --- /dev/null +++ b/docs/plat/st/stm32mpus.rst
@@ -0,0 +1,78 @@ +STM32 MPUs +========== + +STM32 MPUs are microprocessors designed by STMicroelectronics +based on Arm Cortex-A. This page presents the common configuration of STM32 +MPUs, more details and dedicated configuration can be found in each STM32 MPU +page (:ref:`STM32MP1` or :ref:`STM32MP2`) + +Design +------ +The STM32 MPU resets in the ROM code of the Cortex-A. +The primary boot core (core 0) executes the boot sequence while +secondary boot core (core 1) is kept in a holding pen loop. +The ROM code boot sequence loads the TF-A binary image from boot device +to embedded SRAM. + +The TF-A image must be properly formatted with a STM32 header structure +for ROM code is able to load this image. +Tool stm32image can be used to prepend this header to the generated TF-A binary. + +Boot +~~~~ +Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are +inside the FIP binary: BL31 (for Aarch64 platforms), BL32 (OP-TEE), U-Boot +and their respective device tree blobs. + +Boot sequence +~~~~~~~~~~~~~ + +ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot) + +Build Instructions +------------------ +Boot media(s) supported by BL2 must be specified in the build command. +Available storage medias are: + +- ``STM32MP_SDMMC`` +- ``STM32MP_EMMC`` +- ``STM32MP_RAW_NAND`` +- ``STM32MP_SPI_NAND`` +- ``STM32MP_SPI_NOR`` + +Serial boot devices: + +- ``STM32MP_UART_PROGRAMMER`` +- ``STM32MP_USB_PROGRAMMER`` + + +Other configuration flags: + +- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used. + | Default: stm32mp157c-ev1.dtb +- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP, + | default location (end of the first 128MB) is used when absent +- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup. + | Default: 0 (disabled) +- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2). + | Default: 0 (disabled) +- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate. + | Default: 115200 + + +Populate SD-card +---------------- + +Boot with FIP +~~~~~~~~~~~~~ +The SD-card has to be formatted with GPT. +It should contain at least those partitions: + +- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2) +- fip (GUID 19d5df83-11b0-457b-be2c-7559c13142a5): which contains the FIP binary + +Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. + +-------------- + +*Copyright (c) 2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index a983606..f2c8fd2 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst
@@ -1,280 +1,10 @@ -STMicroelectronics STM32MP1 -=========================== +:orphan: -STM32MP1 is a microprocessor designed by STMicroelectronics -based on Arm Cortex-A7. -It is an Armv7-A platform, using dedicated code from TF-A. -More information can be found on `STM32MP1 Series`_ page. +STMicroelectronics STM32MP1 (old page) +====================================== +Please check :ref:`STM32 MPUs` page for generic information about +STMicroelectronics STM32 microprocessors in TF-A, and :ref:`STM32MP1` page +for specificities on STM32MP1x platforms. -STM32MP1 Versions ------------------ - -There are 2 variants for STM32MP1: STM32MP13 and STM32MP15 - -STM32MP13 Versions -~~~~~~~~~~~~~~~~~~ -The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible: - -- STM32MP131: Single Cortex-A7 core -- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 -- STM32MP135: STM32MP133 + DCMIPP, LTDC - -Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: - -- A Cortex-A7 @ 650 MHz -- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz -- D Cortex-A7 @ 900 MHz -- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz - -STM32MP15 Versions -~~~~~~~~~~~~~~~~~~ -The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible: - -- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD -- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD -- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz - -Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: - -- A Basic + Cortex-A7 @ 650 MHz -- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz -- D Basic + Cortex-A7 @ 800 MHz -- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz - -The `STM32MP1 part number codification`_ page gives more information about part numbers. - -Design ------- -The STM32MP1 resets in the ROM code of the Cortex-A7. -The primary boot core (core 0) executes the boot sequence while -secondary boot core (core 1) is kept in a holding pen loop. -The ROM code boot sequence loads the TF-A binary image from boot device -to embedded SRAM. - -The TF-A image must be properly formatted with a STM32 header structure -for ROM code is able to load this image. -Tool stm32image can be used to prepend this header to the generated TF-A binary. - -Boot with FIP -~~~~~~~~~~~~~ -The use of FIP is now the recommended way to boot STM32MP1 platform. -Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are -inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective -device tree blobs. - - -Memory mapping -~~~~~~~~~~~~~~ - -:: - - 0x00000000 +-----------------+ - | | ROM - 0x00020000 +-----------------+ - | | - | ... | - | | - 0x2FFC0000 +-----------------+ \ - | BL32 DTB | | - 0x2FFC5000 +-----------------+ | - | BL32 | | - 0x2FFDF000 +-----------------+ | - | ... | | - 0x2FFE3000 +-----------------+ | - | BL2 DTB | | Embedded SRAM - 0x2FFEA000 +-----------------+ | - | BL2 | | - 0x2FFFF000 +-----------------+ | - | SCMI mailbox | | - 0x30000000 +-----------------+ / - | | - | ... | - | | - 0x40000000 +-----------------+ - | | - | | Devices - | | - 0xC0000000 +-----------------+ \ - | | | - 0xC0100000 +-----------------+ | - | BL33 | | Non-secure RAM (DDR) - | ... | | - | | | - 0xFFFFFFFF +-----------------+ / - - -Boot sequence -~~~~~~~~~~~~~ - -ROM code -> BL2(compiled with RESET_TO_BL2) -> BL32(SP_min)-> BL33(U-Boot) - -or if Op-TEE is used: - -ROM code -> BL2 (compiled with RESET_TO_BL2) -> OP-TEE -> BL33 (U-Boot) - - -Build Instructions ------------------- -Boot media(s) supported by BL2 must be specified in the build command. -Available storage medias are: - -- ``STM32MP_SDMMC`` -- ``STM32MP_EMMC`` -- ``STM32MP_RAW_NAND`` -- ``STM32MP_SPI_NAND`` -- ``STM32MP_SPI_NOR`` - -Serial boot devices: - -- ``STM32MP_UART_PROGRAMMER`` -- ``STM32MP_USB_PROGRAMMER`` - - -Other configuration flags: - -- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used. - | Default: stm32mp157c-ev1.dtb -- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP, - | default location (end of the first 128MB) is used when absent -- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup. - | Default: 0 (disabled) -- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2). - | Default: 0 (disabled) -- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate. - | Default: 115200 -- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter. - | Default: 0 -- | ``STM32MP13``: to select STM32MP13 variant configuration. - | Default: 0 -- | ``STM32MP15``: to select STM32MP15 variant configuration. - | Default: 1 - - -Boot with FIP -~~~~~~~~~~~~~ -You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary. - -U-Boot -______ - -.. code:: bash - - cd <u-boot_directory> - make stm32mp15_trusted_defconfig - make DEVICE_TREE=stm32mp157c-ev1 all - -OP-TEE (optional) -_________________ - -.. code:: bash - - cd <optee_directory> - make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \ - CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts - - -TF-A BL32 (SP_min) -__________________ -If you choose not to use OP-TEE, you can use TF-A SP_min. -To build TF-A BL32, and its device tree file: - -.. code:: bash - - make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs - -TF-A BL2 -________ -To build TF-A BL2 with its STM32 header for SD-card boot: - -.. code:: bash - - make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1 - -For other boot devices, you have to replace STM32MP_SDMMC in the previous command -with the desired device flag. - -This BL2 is independent of the BL32 used (SP_min or OP-TEE) - - -FIP -___ -With BL32 SP_min: - -.. code:: bash - - make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - AARCH32_SP=sp_min \ - DTB_FILE_NAME=stm32mp157c-ev1.dtb \ - BL33=<u-boot_directory>/u-boot-nodtb.bin \ - BL33_CFG=<u-boot_directory>/u-boot.dtb \ - fip - -With OP-TEE: - -.. code:: bash - - make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ - AARCH32_SP=optee \ - DTB_FILE_NAME=stm32mp157c-ev1.dtb \ - BL33=<u-boot_directory>/u-boot-nodtb.bin \ - BL33_CFG=<u-boot_directory>/u-boot.dtb \ - BL32=<optee_directory>/tee-header_v2.bin \ - BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin - BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin - fip - -Trusted Boot Board -__________________ - -.. code:: shell - - tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \ - --tfw-nvctr 0 \ - --ntfw-nvctr 0 \ - --key-alg ecdsa --hash-alg sha256 \ - --trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \ - --tos-fw <optee_directory>/tee-header_v2.bin \ - --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ - --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ - --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ - --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ - --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ - --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ - --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ - --hw-config <u-boot_directory>/u-boot.dtb \ - --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \ - --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt - - tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \ - --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ - --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ - --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ - --hw-config <u-boot_directory>/u-boot.dtb \ - --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \ - --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ - --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ - --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ - --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ - --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip - - - -Populate SD-card ----------------- - -Boot with FIP -~~~~~~~~~~~~~ -The SD-card has to be formatted with GPT. -It should contain at least those partitions: - -- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2) -- fip: which contains the FIP binary - -Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. - - -.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html -.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification +*Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved*
diff --git a/docs/plat/xilinx-versal-net.rst b/docs/plat/xilinx-versal-net.rst index 5d04639..1db7695 100644 --- a/docs/plat/xilinx-versal-net.rst +++ b/docs/plat/xilinx-versal-net.rst
@@ -14,6 +14,11 @@ make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net bl31 ``` +To build bl32 TSP you have to rebuild bl31 too +```bash +make CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SPD=tspd RESET_TO_BL31=1 bl31 bl32 +``` + To build TF-A for JTAG DCC console: ```bash make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31
diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst index 09a6ee2..b71776d 100644 --- a/docs/plat/xilinx-versal.rst +++ b/docs/plat/xilinx-versal.rst
@@ -19,6 +19,11 @@ make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31 ``` +To build bl32 TSP you have to rebuild bl31 too +```bash +make CROSS_COMPILE=aarch64-none-elf- PLAT=versal SPD=tspd RESET_TO_BL31=1 bl31 bl32 +``` + To build TF-A for JTAG DCC console ```bash make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index 1250071..7c66d11 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst
@@ -319,13 +319,6 @@ Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the FWU content certificate. -- **#define : PLAT_CRYPTOCELL_BASE** - - This defines the base address of Arm® TrustZone® CryptoCell and must be - defined if CryptoCell crypto driver is used for Trusted Board Boot. For - capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is - set. - If the AP Firmware Updater Configuration image, BL2U is used, the following must also be defined: @@ -591,32 +584,32 @@ If the platform port uses the Arm® Ethos™-N NPU driver with TZMP1 support enabled, the following constants and configuration must also be defined: -- **ARM_ETHOSN_NPU_PROT_FW_NSAID** +- **ETHOSN_NPU_PROT_FW_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use to access the protected memory that contains the NPU's firmware. -- **ARM_ETHOSN_NPU_PROT_DATA_RW_NSAID** +- **ETHOSN_NPU_PROT_DATA_RW_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read/write access to the protected memory that contains inference data. -- **ARM_ETHOSN_NPU_PROT_DATA_RO_NSAID** +- **ETHOSN_NPU_PROT_DATA_RO_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read-only access to the protected memory that contains inference data. -- **ARM_ETHOSN_NPU_NS_RW_DATA_NSAID** +- **ETHOSN_NPU_NS_RW_DATA_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read/write access to the non-protected memory. -- **ARM_ETHOSN_NPU_NS_RO_DATA_NSAID** +- **ETHOSN_NPU_NS_RO_DATA_NSAID** Defines the Non-secure Access IDentity (NSAID) that the NPU shall use for read-only access to the non-protected memory. -- **ARM_ETHOSN_NPU_FW_IMAGE_BASE** and **ARM_ETHOSN_NPU_FW_IMAGE_LIMIT** +- **ETHOSN_NPU_FW_IMAGE_BASE** and **ETHOSN_NPU_FW_IMAGE_LIMIT** Defines the physical address range that the NPU's firmware will be loaded into and executed from. @@ -634,10 +627,10 @@ - Add MMU mappings such that: - BL2 can write the NPU firmware into the region defined by - ``ARM_ETHOSN_NPU_FW_IMAGE_BASE`` and ``ARM_ETHOSN_NPU_FW_IMAGE_LIMIT`` + ``ETHOSN_NPU_FW_IMAGE_BASE`` and ``ETHOSN_NPU_FW_IMAGE_LIMIT`` - BL31 (SiP service) can read the NPU firmware from the same region -- Add the firmware image ID ``ARM_ETHOSN_NPU_FW_IMAGE_ID`` to the list of images +- Add the firmware image ID ``ETHOSN_NPU_FW_IMAGE_ID`` to the list of images loaded by BL2. Please see the reference implementation code for the Juno platform as an example. @@ -1509,43 +1502,6 @@ the SMCCC function specified in the argument; otherwise returns SMC_ARCH_CALL_NOT_SUPPORTED. -Function : plat_mboot_measure_image() -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : unsigned int, image_info_t * - Return : int - -When the MEASURED_BOOT flag is enabled: - -- This function measures the given image and records its measurement using - the measured boot backend driver. -- On the Arm FVP port, this function measures the given image using its - passed id and information and then records that measurement in the - Event Log buffer. -- This function must return 0 on success, a signed integer error code - otherwise. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - -Function : plat_mboot_measure_critical_data() -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : unsigned int, const void *, size_t - Return : int - -When the MEASURED_BOOT flag is enabled: - -- This function measures the given critical data structure and records its - measurement using the measured boot backend driver. -- This function must return 0 on success, a signed integer error code - otherwise. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - Function : plat_can_cmo() ~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1813,42 +1769,6 @@ The default implementation of this function asserts therefore platforms must override it when using the FWU feature. -Function : bl1_plat_mboot_init() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : void - -When the MEASURED_BOOT flag is enabled: - -- This function is used to initialize the backend driver(s) of measured boot. -- On the Arm FVP port, this function is used to initialize the Event Log - backend driver, and also to write header information in the Event Log buffer. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - -Function : bl1_plat_mboot_finish() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : void - -When the MEASURED_BOOT flag is enabled: - -- This function is used to finalize the measured boot backend driver(s), - and also, set the information for the next bootloader component to - extend the measurement if needed. -- On the Arm FVP port, this function is used to pass the base address of - the Event Log buffer and its size to BL2 via tb_fw_config to extend the - Event Log buffer with the measurement of various images loaded by BL2. - It results in panic on error. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - Boot Loader Stage 2 (BL2) ------------------------- @@ -1980,42 +1900,6 @@ must return 0, otherwise it must return 1. The default implementation of this always returns 0. -Function : bl2_plat_mboot_init() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : void - -When the MEASURED_BOOT flag is enabled: - -- This function is used to initialize the backend driver(s) of measured boot. -- On the Arm FVP port, this function is used to initialize the Event Log - backend driver with the Event Log buffer information (base address and - size) received from BL1. It results in panic on error. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - -Function : bl2_plat_mboot_finish() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : void - Return : void - -When the MEASURED_BOOT flag is enabled: - -- This function is used to finalize the measured boot backend driver(s), - and also, set the information for the next bootloader component to extend - the measurement if needed. -- On the Arm FVP port, this function is used to pass the Event Log buffer - information (base address and size) to non-secure(BL33) and trusted OS(BL32) - via nt_fw and tos_fw config respectively. It results in panic on error. - -When the MEASURED_BOOT flag is disabled, this function doesn't do anything. - Boot Loader Stage 2 (BL2) at EL3 -------------------------------- @@ -2818,6 +2702,17 @@ for the higher power domain levels depending on the result of state coordination. The generic code expects the handler to succeed. +plat_psci_ops.pwr_domain_validate_suspend() [optional] +...................................................... + +This is an optional function that is only compiled into the build if the build +option ``PSCI_OS_INIT_MODE`` is enabled. + +If implemented, this function allows the platform to perform platform specific +validations based on hardware states. The generic code expects this function to +return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or +PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. + plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] ........................................................... @@ -2876,10 +2771,6 @@ data, for example in DRAM. The Distributor can then be powered down using an implementation-defined sequence. -If the build option ``PSCI_OS_INIT_MODE`` is enabled, the generic code expects -the platform to return PSCI_E_SUCCESS on success, or either PSCI_E_DENIED or -PSCI_E_INVALID_PARAMS as appropriate for any invalid requests. - plat_psci_ops.pwr_domain_pwr_down_wfi() ....................................... @@ -3400,10 +3291,10 @@ Argument : uint64_t Return : void -This function is invoked by the RAS framework for the platform to handle an -External Abort received at EL3. The intention of the function is to attempt to -resolve the cause of External Abort and return; if that's not possible, to -initiate orderly shutdown of the system. +This function is invoked by the runtime exception handling framework for the +platform to handle an External Abort received at EL3. The intention of the +function is to attempt to resolve the cause of External Abort and return; +if that's not possible then an orderly shutdown of the system is initiated. The first parameter (``int ea_reason``) indicates the reason for External Abort. Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. @@ -3418,13 +3309,8 @@ (``uint64_t flags``) indicates the preempted security state. These parameters are received from the top-level exception handler. -If ``RAS_FFH_SUPPORT`` is set to ``1``, the default implementation of this -function iterates through RAS handlers registered by the platform. If any of the -RAS handlers resolve the External Abort, no further action is taken. - -If ``RAS_FFH_SUPPORT`` is set to ``0``, or if none of the platform RAS handlers -could resolve the External Abort, the default implementation prints an error -message, and panics. +This function must be implemented if a platform expects Firmware First handling +of External Aborts. Function : plat_handle_uncontainable_ea ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -3565,6 +3451,15 @@ to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` are used, this flag will be set to ``no`` automatically. +- **ARM_ARCH_MAJOR and ARM_ARCH_MINOR** + By default, ARM_ARCH_MAJOR.ARM_ARCH_MINOR is set to 8.0 in ``defaults.mk``, + if the platform makefile/build defines or uses the correct ARM_ARCH_MAJOR and + ARM_ARCH_MINOR then mandatory Architectural features available for that Arch + version will be enabled by default and any optional Arch feature supported by + the Architecture and available in TF-A can be enabled from platform specific + makefile. Look up to ``arch_features.mk`` for details pertaining to mandatory + and optional Arch specific features. + Platform include paths ---------------------- @@ -3657,11 +3552,17 @@ dynamically allocating memory. This may also have the affect of limiting the amount of open resources per driver. +Measured Boot Platform Interface +-------------------------------- + +Enabling the MEASURED_BOOT flag adds extra platform requirements. Please refer +to :ref:`Measured Boot Design` for more details. + -------------- *Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* -.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html .. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html .. _FreeBSD: https://www.freebsd.org
diff --git a/docs/process/code-review-guidelines.rst b/docs/process/code-review-guidelines.rst index 67a211f..bd42811 100644 --- a/docs/process/code-review-guidelines.rst +++ b/docs/process/code-review-guidelines.rst
@@ -1,11 +1,6 @@ Code Review Guidelines ====================== -This document provides TF-A specific details about the project's code review -process. It should be read in conjunction with the `Project Maintenance -Process`_, which it supplements. - - Why do we do code reviews? -------------------------- @@ -23,8 +18,34 @@ unfairly criticizing or belittling the work of any contributor. -Good practices --------------- +Overview of the code review process +----------------------------------- + +All contributions to Trusted Firmware-A project are reviewed by the community to +ensure they meet the project's expectations before they get merged, according to +the `Project Maintenance Process`_ defined for all `Trusted Firmware` projects. + +Technical ownership of most parts of the codebase falls on the :ref:`code +owners`. All patches are ultimately merged by the :ref:`maintainers`. + +Approval of a patch is tracked using Gerrit `labels`. For a patch to be merged, +it must get all of the following votes: + +- At least one ``Code-Owner-Review+1`` up-vote, and no ``Code-Owner-Review-1`` + down-vote. + +- At least one ``Maintainer-Review+1`` up-vote, and no ``Maintainer-Review-1`` + down-vote. + +- ``Verified+1`` vote applied by the automated Continuous Integration (CI) + system. + +Note that, in some instances, the maintainers might give a waiver for some of +the CI failures and manually override the ``Verified+1`` score. + + +Good practices for all reviewers +-------------------------------- To ensure the code review gives the greatest possible benefit, participants in the project should: @@ -73,6 +94,14 @@ directory to have the freedom to change it in any way. This way, your changes benefit everyone and will be maintained over time. +- It is the patch-author's responsibility to respond to review comments within + 21 days. In the event that the patch-author does not respond within this + timeframe, the maintainer is entitled to abandon the patch(es). + Patch author(s) may be busy with other priorities, causing a delay in + responding to active review comments after posting patch(es). In such a + situation, if the author's patch(es) is/are abandoned, they can restore + their work for review by resolving comments, merge-conflicts, and revising + their original submissions. Guidelines for all reviewers ---------------------------- @@ -211,6 +240,6 @@ -------------- -*Copyright (c) 2020, Arm Limited. All rights reserved.* +*Copyright (c) 2020-2023, Arm Limited. All rights reserved.* .. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst index 13fb7cb..9730390 100644 --- a/docs/process/coding-guidelines.rst +++ b/docs/process/coding-guidelines.rst
@@ -449,17 +449,20 @@ portable, harder to understand, maintain and audit security wise. Also, static analysis tools generally don't analyze assembly code. -There are, however, legitimate uses of assembly language. These include: +If specific system-level instructions must be used (like cache maintenance +operations), please consider using inline assembly. The ``arch_helpers.h`` files +already define inline functions for a lot of these. - - Early boot code executed before the C runtime environment is setup. +There are, however, legitimate uses of assembly language. These are usually +early boot (eg. cpu reset sequences) and exception handling code before the C +runtime environment is set up. - - Exception handling code. - - - Low-level code where the exact sequence of instructions executed on the CPU - matters, such as CPU reset sequences. - - - Low-level code where specific system-level instructions must be used, such - as cache maintenance operations. +When writing assembly please note that a wide variety of common instruction +sequences have helper macros in ``asm_macros.S`` which are preferred over +writing them directly. This is especially important for debugging purposes as +debug symbols must manually be included. Please use the ``func_prologue`` and +``func_epilogue`` macros if you need to use the stack. Also, obeying the +Procedure Call Standard (PCS) is generally recommended. Do not use weak functions -------------------------
diff --git a/docs/process/faq.rst b/docs/process/faq.rst index daab198..0f33bc0 100644 --- a/docs/process/faq.rst +++ b/docs/process/faq.rst
@@ -67,9 +67,11 @@ What are these strange comments in my changes? ---------------------------------------------- -All the comments from ``ci-bot-user`` are associated with Continuous Integration -infrastructure. The links published on the comment are not currently accessible, -but would be after the CI has been transitioned to `trustedfirmware.org`_. +All the comments from ``TrustedFirmware Code Review`` user (email: +``ci@trustedfirmware.org``) are associated with Continuous Integration (CI) +infrastructure. The links published on the comments redirect to the CI web +interface at http://ci.trustedfirmware.org, where details of the tests failures, +if any, can be examined. -------------- @@ -77,4 +79,3 @@ .. _Gerrit Upload Patch Set documentation: https://review.trustedfirmware.org/Documentation/intro-user.html#upload-patch-set .. _Gerrit Replace Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html#push_replace -.. _trustedfirmware.org: https://www.trustedfirmware.org/
diff --git a/docs/process/index.rst b/docs/process/index.rst index 7914a4e..9b669c0 100644 --- a/docs/process/index.rst +++ b/docs/process/index.rst
@@ -13,4 +13,5 @@ contributing code-review-guidelines faq + maintenance security-hardening
diff --git a/docs/process/maintenance.rst b/docs/process/maintenance.rst new file mode 100644 index 0000000..45aada2 --- /dev/null +++ b/docs/process/maintenance.rst
@@ -0,0 +1,55 @@ +Project Maintenance Processes +============================= + +Trusted Firmware-A (TF-A) project follows the generic `trustedfirmware.org +Project Maintenance Process`_. The present document complements it by defining +TF-A project-specific decisions. + +How to become a maintainer? +--------------------------- + +Qualifying Criteria +~~~~~~~~~~~~~~~~~~~ + +To be elligible to become a maintainer for TF-A project, all criteria outlined +`here`_ must be fullfilled. These are: + +- Being an active member of the project for at least a couple of years. + +- Having contributed a substantial number of non-trivial and high-quality + patches. + +- Having reviewed a substantial number of non-trivial patches, preferably in the + generic layer, with high-quality constructive feedback. + +- Behaving in a professional and polite way, with the best interests of the + project at heart. + +- Showing a strong will to improve the project and to do the right thing, rather + than going for the quick and easy path. + +- Participating in design discussions on the development mailing list and during + TF-A tech forums calls. + +- Having appropriate bandwidth (minimum 2 hours per week) to deal with the workload. + +Election Process +~~~~~~~~~~~~~~~~ + +To put an individual's name up for election, + +#. Send an email to all existing TF-A maintainers, asking whether they have any + objections to this individual becoming a TF-A maintainer. + +#. Give existing maintainers one calendar week to participate in the discussion. + +#. If there are objections, the existing maintainers should try to resolve them + amongst themselves. If they cannot, this should be escalated to the + trustedfirmware.org Technical Steering Commitee (TSC). + +#. If there are no (more) objections, announce the news on the TF-A mailing list + and update the list of maintainers on the :ref:`Project + Maintenance<maintainers>` page. + +.. _trustedfirmware.org Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ +.. _here: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/#how-to-become-a-maintainer
diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst index f9618db..eace467 100644 --- a/docs/process/security-hardening.rst +++ b/docs/process/security-hardening.rst
@@ -135,6 +135,16 @@ it is recommended to develop against ``W=2`` (which will eventually become the default). +Additional guidelines are provided below for some security-related build +options: + +- The ``ENABLE_CONSOLE_GETC`` build flag should be set to 0 to disable the + `getc()` feature, which allows the firmware to read characters from the + console. Keeping this feature enabled is considered dangerous from a security + point of view because it potentially allows an attacker to inject arbitrary + data into the firmware. It should only be enabled on a need basis if there is + a use case for it, for example in a testing or factory environment. + .. rubric:: References - `Arm ARM`_
diff --git a/docs/resources/diagrams/Makefile b/docs/resources/diagrams/Makefile index c951754..faf9634 100644 --- a/docs/resources/diagrams/Makefile +++ b/docs/resources/diagrams/Makefile
@@ -79,7 +79,13 @@ FWU-update_struct_layers = "background" FWU-update_struct_opts = -all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG) $(RMM_PNG) $(RMM_EL3_MANIFEST_PNG) $(PSA_FWU_PNG) +MB_DESIGN_DIA = measured_boot_design.dia +MB_DESIGN_PNG = measured_boot_design.png + +measured_boot_design_layers = "background" +measured_boot_design_opts = + +all:$(RESET_PNGS) $(INT_PNGS) $(XLAT_PNG) $(RMM_PNG) $(RMM_EL3_MANIFEST_PNG) $(PSA_FWU_PNG) $(MB_DESIGN_PNG) $(RESET_PNGS):$(RESET_DIA) $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<) @@ -99,3 +105,6 @@ $(PSA_FWU_PNG):$(PSA_FWU_DIA) $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<) + +$(MB_DESIGN_PNG):$(MB_DESIGN_DIA) + $(call generate_image,$($(patsubst %.png,%_layers,$@)),$@,png,$($(patsubst %.png,%_opts,$@)),$<)
diff --git a/docs/resources/diagrams/bl31-exception-entry-error-synchronization.png b/docs/resources/diagrams/bl31-exception-entry-error-synchronization.png new file mode 100644 index 0000000..cdfdcb9 --- /dev/null +++ b/docs/resources/diagrams/bl31-exception-entry-error-synchronization.png Binary files differ
diff --git a/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png b/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png deleted file mode 100644 index 0619cf2..0000000 --- a/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png +++ /dev/null Binary files differ
diff --git a/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png b/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png deleted file mode 100644 index f110028..0000000 --- a/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png +++ /dev/null Binary files differ
diff --git a/docs/resources/diagrams/measured_boot_design.dia b/docs/resources/diagrams/measured_boot_design.dia new file mode 100644 index 0000000..fdae464 --- /dev/null +++ b/docs/resources/diagrams/measured_boot_design.dia Binary files differ
diff --git a/docs/resources/diagrams/measured_boot_design.png b/docs/resources/diagrams/measured_boot_design.png new file mode 100644 index 0000000..42469be --- /dev/null +++ b/docs/resources/diagrams/measured_boot_design.png Binary files differ
diff --git a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml index e513ed4..9b693c8 100644 --- a/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml +++ b/docs/resources/diagrams/plantuml/fconf_bl1_load_config.puml
@@ -21,7 +21,7 @@ fvp_bl1_setup -> arm_bl1_setup : arm_bl1_platform_setup() arm_bl1_setup -> arm_io_storage : plat_arm_io_setup() note over arm_io_storage : register and setup fip -arm_bl1_setup -> fconf : set_fw_config_info(fw_config_base, max_size) +arm_bl1_setup -> fconf : set_config_info(fw_config_base, max_size, FW_CONFIG_ID) note over fconf set fw_config information (address, size, image_id)
diff --git a/docs/resources/diagrams/plantuml/tfa_arm_cca_dfd.puml b/docs/resources/diagrams/plantuml/tfa_arm_cca_dfd.puml new file mode 100644 index 0000000..493f078 --- /dev/null +++ b/docs/resources/diagrams/plantuml/tfa_arm_cca_dfd.puml
@@ -0,0 +1,82 @@ +/' + ' Copyright (c) 2023, Arm Limited. All rights reserved. + ' + ' SPDX-License-Identifier: BSD-3-Clause + '/ + +/' +TF-A with Arm CCA Data Flow Diagram +'/ + +@startuml +digraph tfa_dfd { + + # Arrange nodes from left to right + rankdir="LR" + + # Allow arrows to end on cluster boundaries + compound=true + + # Default settings for edges and nodes + edge [minlen=2 color="#8c1b07"] + node [fillcolor="#ffb866" style=filled shape=box fixedsize=true width=1.6 height=0.7] + + # Nodes outside of the trust boundary + realm [label="Realm\nClients"] + nsec [label="Non-secure\nClients"] + sec [label="Secure\nClients"] + dbg [label="Debug & Trace"] + uart [label="UART"] + nvm [label="Non-volatile\nMemory"] + + # Trust boundary cluster + subgraph cluster_trusted{ + graph [style=dashed color="#f22430"] + + # HW IPs cluster + subgraph cluster_ip{ + label ="Hardware IPs"; + graph [style=filled color="#000000" fillcolor="#ffd29e"] + + rank="same" + gic [label="GIC" width=1.2 height=0.5] + mmu [label="MMU" width=1.2 height=0.5] + etc [label="..." shape=none style=none height=0.5] + } + + # TF-A cluster + subgraph cluster_tfa{ + label ="TF-A"; + graph [style=filled color="#000000" fillcolor="#faf9cd"] + + bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"]; + bl2 [label="Trusted Boot\nFirmware\n(BL2)" fillcolor="#ddffb3" height=1] + bl31 [label="TF-A Runtime\n(BL31)" fillcolor="#ddffb3"] + } + + # HES cluster + subgraph cluster_hes{ + label ="Arm CCA HES"; + graph [style=filled color="#000000" fillcolor="#ffd29e"] + + hes [label="Hardware\nEnforced Security"] + } + } + + # Interactions between nodes + + # -- The following lines are copied from tfa_dfd.puml and must not be + # changed, at the risk of invalidating DF* references. + nvm -> bl31 [lhead=cluster_tfa label="DF1"] + uart -> bl31 [dir="both" lhead=cluster_tfa label="DF2"] + dbg -> bl2 [dir="both" lhead=cluster_tfa label="DF3"] + sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"] + nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"] + bl2 -> mmu [dir="both" ltail=cluster_tfa lhead=cluster_ip label="DF6"] + + # -- The following lines are new for Arm CCA DFD. + bl2 -> hes [dir="both" ltail=cluster_tfa lhead=cluster_hes label="DF7"] + realm -> bl2 [dir="both" lhead=cluster_tfa label="DF8"] +} + +@enduml
diff --git a/docs/resources/diagrams/plantuml/tfa_dfd.puml b/docs/resources/diagrams/plantuml/tfa_dfd.puml index 0007911..9d3dcba 100644 --- a/docs/resources/diagrams/plantuml/tfa_dfd.puml +++ b/docs/resources/diagrams/plantuml/tfa_dfd.puml
@@ -25,7 +25,7 @@ nsec [label="Non-secure\nClients"] sec [label="Secure\nClients"] dbg [label="Debug & Trace"] - logs [label="Logs\n(UART)"] + uart [label="UART"] nvm [label="Non-volatile\nMemory"] # Trust boundary cluster @@ -56,7 +56,7 @@ # Interactions between nodes nvm -> bl31 [lhead=cluster_tfa label="DF1"] - logs -> bl31 [dir="back" lhead=cluster_tfa label="DF2"] + uart -> bl31 [dir="both" lhead=cluster_tfa label="DF2"] dbg -> bl2 [dir="both" lhead=cluster_tfa label="DF3"] sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"] nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
diff --git a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml b/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml index 23f5b17..a7e0ce5 100644 --- a/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml +++ b/docs/resources/diagrams/plantuml/tfa_rss_dfd.puml
@@ -25,7 +25,7 @@ nsec [label="Non-secure\nClients"] sec [label="Secure\nClients"] dbg [label="Debug & Trace"] - logs [label="Logs\n(UART)"] + uart [label="UART"] nvm [label="Non-volatile\nMemory"] @@ -65,7 +65,7 @@ # Interactions between nodes nvm -> bl31 [lhead=cluster_tfa label="DF1"] - logs -> bl31 [dir="back" lhead=cluster_tfa label="DF2"] + uart -> bl31 [dir="both" lhead=cluster_tfa label="DF2"] dbg -> bl2 [dir="both" lhead=cluster_tfa label="DF3"] sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"] nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
diff --git a/docs/resources/diagrams/psci-osi-mode.png b/docs/resources/diagrams/psci-osi-mode.png index d322953..09175e5 100644 --- a/docs/resources/diagrams/psci-osi-mode.png +++ b/docs/resources/diagrams/psci-osi-mode.png Binary files differ
diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst index d73e74b..762801d 100644 --- a/docs/security_advisories/security-advisory-tfv-9.rst +++ b/docs/security_advisories/security-advisory-tfv-9.rst
@@ -77,7 +77,7 @@ +----------------------+ | Cortex-A715 | +----------------------+ -| Cortex-Hunter | +| Cortex-A720 | +----------------------+ | Neoverse-N1 | +----------------------+
diff --git a/docs/threat_model/index.rst b/docs/threat_model/index.rst index b22fb18..e22378b 100644 --- a/docs/threat_model/index.rst +++ b/docs/threat_model/index.rst
@@ -31,10 +31,10 @@ :caption: Contents threat_model - threat_model_spm threat_model_el3_spm threat_model_fvp_r threat_model_rss_interface + threat_model_arm_cca --------------
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst index 71ec9b1..0da2558 100644 --- a/docs/threat_model/threat_model.rst +++ b/docs/threat_model/threat_model.rst
@@ -7,10 +7,7 @@ This document provides a generic threat model for TF-A firmware. -.. note:: - - This threat model doesn't consider Root and Realm worlds introduced by - :ref:`Realm Management Extension (RME)`. +.. _Target of Evaluation: ******************** Target of Evaluation @@ -36,33 +33,15 @@ - There is no Secure-EL2. We don't consider threats that may come with Secure-EL2 software. +- There are no Root and Realm worlds. These are introduced by :ref:`Realm + Management Extension (RME)`. + + The :ref:`Threat Model for TF-A with Arm CCA support` covers these types of + configurations. + - No experimental features are enabled. We do not consider threats that may come from them. -.. note:: - - In the current Measured Boot design, BL1, BL2, and BL31, as well as the - secure world components, form the |SRTM|. Measurement data is currently - considered an asset to be protected against attack, and this is achieved - by storing them in the Secure Memory. - Beyond the measurements stored inside the TCG-compliant Event Log buffer, - there are no other assets to protect or threats to defend against that - could compromise |TF-A| execution environment's security. - - There are general security assets and threats associated with remote/delegated - attestation. However, these are outside the |TF-A| security boundary and - should be dealt with by the appropriate agent in the platform/system. - Since current Measured Boot design does not use local attestation, there would - be no further assets to protect(like unsealed keys). - - A limitation of the current Measured Boot design is that it is dependent upon - Secure Boot as implementation of Measured Boot does not extend measurements - into a discrete |TPM|, where they would be securely stored and protected - against tampering. This implies that if Secure-Boot is compromised, Measured - Boot may also be compromised. - - Platforms must carefully evaluate the security of the default implementation - since the |SRTM| includes all secure world components. Data Flow Diagram ================= @@ -87,8 +66,10 @@ | | images include TF-A BL2 and BL31 images, as well as | | | other secure and non-secure images. | +-----------------+--------------------------------------------------------+ - | DF2 | | TF-A log system framework outputs debug messages | - | | over a UART interface. | + | DF2 | | TF-A log system framework outputs debug or | + | | informative messages over a UART interface. | + | | | + | | | Also, characters can be read from a UART interface. | +-----------------+--------------------------------------------------------+ | DF3 | | Debug and trace IP on a platform can allow access | | | to registers and memory of TF-A. | @@ -109,6 +90,8 @@ +-----------------+--------------------------------------------------------+ +.. _threat_analysis: + *************** Threat Analysis *************** @@ -286,201 +269,18 @@ Also, some mitigations require enabling specific features, which must be explicitly turned on via a build flag. -These are highlighted in the ``Mitigations implemented?`` box. +When such conditions must be met, these are highlighted in the ``Mitigations +implemented?`` box. -+------------------------+----------------------------------------------------+ -| ID | 01 | -+========================+====================================================+ -| Threat | | **An attacker can mangle firmware images to | -| | execute arbitrary code** | -| | | -| | | Some TF-A images are loaded from external | -| | storage. It is possible for an attacker to access| -| | the external flash memory and change its contents| -| | physically, through the Rich OS, or using the | -| | updating mechanism to modify the non-volatile | -| | images to execute arbitrary code. | -+------------------------+----------------------------------------------------+ -| Diagram Elements | DF1, DF4, DF5 | -+------------------------+----------------------------------------------------+ -| Affected TF-A | BL2, BL31 | -| Components | | -+------------------------+----------------------------------------------------+ -| Assets | Code Execution | -+------------------------+----------------------------------------------------+ -| Threat Agent | PhysicalAccess, NSCode, SecCode | -+------------------------+----------------------------------------------------+ -| Threat Type | Tampering, Elevation of Privilege | -+------------------------+------------------+-----------------+---------------+ -| Application | Server | IoT | Mobile | -+------------------------+------------------+-----------------+---------------+ -| Impact | Critical (5) | Critical (5) | Critical (5) | -+------------------------+------------------+-----------------+---------------+ -| Likelihood | Critical (5) | Critical (5) | Critical (5) | -+------------------------+------------------+-----------------+---------------+ -| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | -+------------------------+------------------+-----------------+---------------+ -| Mitigations | | 1) Implement the `Trusted Board Boot (TBB)`_ | -| | feature which prevents malicious firmware from | -| | running on the platform by authenticating all | -| | firmware images. | -| | | -| | | 2) Perform extra checks on unauthenticated data, | -| | such as FIP metadata, prior to use. | -+------------------------+----------------------------------------------------+ -| Mitigations | | 1) Yes, provided that the ``TRUSTED_BOARD_BOOT`` | -| implemented? | build option is set to 1. | -| | | -| | | 2) Yes. | -+------------------------+----------------------------------------------------+ +As our :ref:`Target of Evaluation` is made of several, distinct firmware images, +some threats are confined in specific images, while others apply to each of +them. To help developers implement mitigations in the right place, threats below +are categorized based on the firmware image that should mitigate them. -+------------------------+----------------------------------------------------+ -| ID | 02 | -+========================+====================================================+ -| Threat | | **An attacker may attempt to boot outdated, | -| | potentially vulnerable firmware image** | -| | | -| | | When updating firmware, an attacker may attempt | -| | to rollback to an older version that has unfixed | -| | vulnerabilities. | -+------------------------+----------------------------------------------------+ -| Diagram Elements | DF1, DF4, DF5 | -+------------------------+----------------------------------------------------+ -| Affected TF-A | BL2, BL31 | -| Components | | -+------------------------+----------------------------------------------------+ -| Assets | Code Execution | -+------------------------+----------------------------------------------------+ -| Threat Agent | PhysicalAccess, NSCode, SecCode | -+------------------------+----------------------------------------------------+ -| Threat Type | Tampering | -+------------------------+------------------+-----------------+---------------+ -| Application | Server | IoT | Mobile | -+------------------------+------------------+-----------------+---------------+ -| Impact | Critical (5) | Critical (5) | Critical (5) | -+------------------------+------------------+-----------------+---------------+ -| Likelihood | Critical (5) | Critical (5) | Critical (5) | -+------------------------+------------------+-----------------+---------------+ -| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | -+------------------------+------------------+-----------------+---------------+ -| Mitigations | Implement anti-rollback protection using | -| | non-volatile counters (NV counters) as required | -| | by `TBBR-Client specification`_. | -+------------------------+----------------------------------------------------+ -| Mitigations | | Yes / Platform specific. | -| implemented? | | -| | | After a firmware image is validated, the image | -| | revision number taken from a certificate | -| | extension field is compared with the | -| | corresponding NV counter stored in hardware to | -| | make sure the new counter value is larger than | -| | the current counter value. | -| | | -| | | **Platforms must implement this protection using | -| | platform specific hardware NV counters.** | -+------------------------+----------------------------------------------------+ +.. _General Threats: -+------------------------+-------------------------------------------------------+ -| ID | 03 | -+========================+=======================================================+ -| Threat | | **An attacker can use Time-of-Check-Time-of-Use | -| | (TOCTOU) attack to bypass image authentication | -| | during the boot process** | -| | | -| | | Time-of-Check-Time-of-Use (TOCTOU) threats occur | -| | when the security check is produced before the time | -| | the resource is accessed. If an attacker is sitting | -| | in the middle of the off-chip images, they could | -| | change the binary containing executable code right | -| | after the integrity and authentication check has | -| | been performed. | -+------------------------+-------------------------------------------------------+ -| Diagram Elements | DF1 | -+------------------------+-------------------------------------------------------+ -| Affected TF-A | BL1, BL2 | -| Components | | -+------------------------+-------------------------------------------------------+ -| Assets | Code Execution, Sensitive Data | -+------------------------+-------------------------------------------------------+ -| Threat Agent | PhysicalAccess | -+------------------------+-------------------------------------------------------+ -| Threat Type | Elevation of Privilege | -+------------------------+---------------------+-----------------+---------------+ -| Application | Server | IoT | Mobile | -+------------------------+---------------------+-----------------+---------------+ -| Impact | N/A | Critical (5) | Critical (5) | -+------------------------+---------------------+-----------------+---------------+ -| Likelihood | N/A | Medium (3) | Medium (3) | -+------------------------+---------------------+-----------------+---------------+ -| Total Risk Rating | N/A | High (15) | High (15) | -+------------------------+---------------------+-----------------+---------------+ -| Mitigations | Copy image to on-chip memory before authenticating | -| | it. | -+------------------------+-------------------------------------------------------+ -| Mitigations | | Platform specific. | -| implemented? | | -| | | The list of images to load and their location is | -| | platform specific. Platforms are responsible for | -| | arranging images to be loaded in on-chip memory. | -+------------------------+-------------------------------------------------------+ - -+------------------------+-------------------------------------------------------+ -| ID | 04 | -+========================+=======================================================+ -| Threat | | **An attacker with physical access can execute | -| | arbitrary image by bypassing the signature | -| | verification stage using glitching techniques** | -| | | -| | | Glitching (Fault injection) attacks attempt to put | -| | a hardware into a undefined state by manipulating an| -| | environmental variable such as power supply. | -| | | -| | | TF-A relies on a chain of trust that starts with the| -| | ROTPK, which is the key stored inside the chip and | -| | the root of all validation processes. If an attacker| -| | can break this chain of trust, they could execute | -| | arbitrary code on the device. This could be | -| | achieved with physical access to the device by | -| | attacking the normal execution flow of the | -| | process using glitching techniques that target | -| | points where the image is validated against the | -| | signature. | -+------------------------+-------------------------------------------------------+ -| Diagram Elements | DF1 | -+------------------------+-------------------------------------------------------+ -| Affected TF-A | BL1, BL2 | -| Components | | -+------------------------+-------------------------------------------------------+ -| Assets | Code Execution | -+------------------------+-------------------------------------------------------+ -| Threat Agent | PhysicalAccess | -+------------------------+-------------------------------------------------------+ -| Threat Type | Tampering, Elevation of Privilege | -+------------------------+---------------------+-----------------+---------------+ -| Application | Server | IoT | Mobile | -+------------------------+---------------------+-----------------+---------------+ -| Impact | N/A | Critical (5) | Critical (5) | -+------------------------+---------------------+-----------------+---------------+ -| Likelihood | N/A | Medium (3) | Medium (3) | -+------------------------+---------------------+-----------------+---------------+ -| Total Risk Rating | N/A | High (15) | High (15) | -+------------------------+---------------------+-----------------+---------------+ -| Mitigations | Mechanisms to detect clock glitch and power | -| | variations. | -+------------------------+-------------------------------------------------------+ -| Mitigations | | No. | -| implemented? | | -| | | The most effective mitigation is adding glitching | -| | detection and mitigation circuit at the hardware | -| | level. | -| | | -| | | However, software techniques, such as adding | -| | redundant checks when performing conditional | -| | branches that are security sensitive, can be used | -| | to harden TF-A against such attacks. | -| | **At the moment TF-A doesn't implement such | -| | mitigations.** | -+------------------------+-------------------------------------------------------+ +General Threats for All Firmware Images +--------------------------------------- +------------------------+---------------------------------------------------+ | ID | 05 | @@ -598,49 +398,6 @@ +------------------------+----------------------------------------------------+ +------------------------+------------------------------------------------------+ -| ID | 07 | -+========================+======================================================+ -| Threat | | **An attacker can perform a denial-of-service | -| | attack by using a broken SMC call that causes the | -| | system to reboot or enter into unknown state.** | -| | | -| | | Secure and non-secure clients access TF-A services | -| | through SMC calls. Malicious code can attempt to | -| | place the TF-A runtime into an inconsistent state | -| | by calling unimplemented SMC call or by passing | -| | invalid arguments. | -+------------------------+------------------------------------------------------+ -| Diagram Elements | DF4, DF5 | -+------------------------+------------------------------------------------------+ -| Affected TF-A | BL31 | -| Components | | -+------------------------+------------------------------------------------------+ -| Assets | Availability | -+------------------------+------------------------------------------------------+ -| Threat Agent | NSCode, SecCode | -+------------------------+------------------------------------------------------+ -| Threat Type | Denial of Service | -+------------------------+-------------------+----------------+-----------------+ -| Application | Server | IoT | Mobile | -+------------------------+-------------------+----------------+-----------------+ -| Impact | Medium (3) | Medium (3) | Medium (3) | -+------------------------+-------------------+----------------+-----------------+ -| Likelihood | High (4) | High (4) | High (4) | -+------------------------+-------------------+----------------+-----------------+ -| Total Risk Rating | High (12) | High (12) | High (12) | -+------------------------+-------------------+----------------+-----------------+ -| Mitigations | Validate SMC function ids and arguments before using | -| | them. | -+------------------------+------------------------------------------------------+ -| Mitigations | | Yes / Platform specific. | -| implemented? | | -| | | For standard services, all input is validated. | -| | | -| | | Platforms that implement SiP services must also | -| | validate SMC call arguments. | -+------------------------+------------------------------------------------------+ - -+------------------------+------------------------------------------------------+ | ID | 08 | +========================+======================================================+ | Threat | | **Memory corruption due to memory overflows and | @@ -712,6 +469,435 @@ | | platforms. | +------------------------+------------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 11 | ++========================+====================================================+ +| Threat | | **Misconfiguration of the Memory Management Unit | +| | (MMU) may allow a normal world software to | +| | access sensitive data, execute arbitrary | +| | code or access otherwise restricted HW | +| | interface** | +| | | +| | | A misconfiguration of the MMU could | +| | lead to an open door for software running in the | +| | normal world to access sensitive data or even | +| | execute code if the proper security mechanisms | +| | are not in place. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF5, DF6 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | BL1, BL2, BL31 | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | Sensitive Data, Code execution | ++------------------------+----------------------------------------------------+ +| Threat Agent | NSCode | ++------------------------+----------------------------------------------------+ +| Threat Type | Information Disclosure, Elevation of Privilege | ++------------------------+-----------------+-----------------+----------------+ +| Application | Server | IoT | Mobile | ++------------------------+-----------------+-----------------+----------------+ +| Impact | Critical (5) | Critical (5) | Critical (5) | ++------------------------+-----------------+-----------------+----------------+ +| Likelihood | High (4) | High (4) | High (4) | ++------------------------+-----------------+-----------------+----------------+ +| Total Risk Rating | Critical (20) | Critical (20) | Critical (20) | ++------------------------+-----------------+-----------------+----------------+ +| Mitigations | When configuring access permissions, the | +| | principle of least privilege ought to be | +| | enforced. This means we should not grant more | +| | privileges than strictly needed, e.g. code | +| | should be read-only executable, read-only data | +| | should be read-only execute-never, and so on. | ++------------------------+----------------------------------------------------+ +| Mitigations | | Platform specific. | +| implemented? | | +| | | MMU configuration is platform specific, | +| | therefore platforms need to make sure that the | +| | correct attributes are assigned to memory | +| | regions. | +| | | +| | | TF-A provides a library which abstracts the | +| | low-level details of MMU configuration. It | +| | provides well-defined and tested APIs. | +| | Platforms are encouraged to use it to limit the | +| | risk of misconfiguration. | ++------------------------+----------------------------------------------------+ + + ++------------------------+-----------------------------------------------------+ +| ID | 13 | ++========================+=====================================================+ +| Threat | | **Leaving sensitive information in the memory, | +| | can allow an attacker to retrieve them.** | +| | | +| | | Accidentally leaving not-needed sensitive data in | +| | internal buffers can leak them if an attacker | +| | gains access to memory due to a vulnerability. | ++------------------------+-----------------------------------------------------+ +| Diagram Elements | DF4, DF5 | ++------------------------+-----------------------------------------------------+ +| Affected TF-A | BL1, BL2, BL31 | +| Components | | ++------------------------+-----------------------------------------------------+ +| Assets | Sensitive Data | ++------------------------+-----------------------------------------------------+ +| Threat Agent | NSCode, SecCode | ++------------------------+-----------------------------------------------------+ +| Threat Type | Information Disclosure | ++------------------------+-------------------+----------------+----------------+ +| Application | Server | IoT | Mobile | ++------------------------+-------------------+----------------+----------------+ +| Impact | Critical (5) | Critical (5) | Critical (5) | ++------------------------+-------------------+----------------+----------------+ +| Likelihood | Medium (3) | Medium (3) | Medium (3) | ++------------------------+-------------------+----------------+----------------+ +| Total Risk Rating | High (15) | High (15) | High (15) | ++------------------------+-------------------+----------------+----------------+ +| Mitigations | Clear the sensitive data from internal buffers as | +| | soon as they are not needed anymore. | ++------------------------+-----------------------------------------------------+ +| Mitigations | | Yes / Platform specific | +| implemented? | | ++------------------------+-----------------------------------------------------+ + + ++------------------------+-----------------------------------------------------+ +| ID | 15 | ++========================+=====================================================+ +| Threat | | **Improper handling of input data received over | +| | a UART interface may allow an attacker to tamper | +| | with TF-A execution environment.** | +| | | +| | | The consequences of the attack depend on the | +| | the exact usage of input data received over UART. | +| | Examples are injection of arbitrary data, | +| | sensitive data tampering, influencing the | +| | execution path, denial of service (if using | +| | blocking I/O). This list may not be exhaustive. | ++------------------------+-----------------------------------------------------+ +| Diagram Elements | DF2, DF4, DF5 | ++------------------------+-----------------------------------------------------+ +| Affected TF-A | BL1, BL2, BL31 | +| Components | | ++------------------------+-----------------------------------------------------+ +| Assets | Sensitive Data, Code Execution, Availability | ++------------------------+-----------------------------------------------------+ +| Threat Agent | NSCode, SecCode | ++------------------------+-----------------------------------------------------+ +| Threat Type | Tampering, Information Disclosure, Denial of | +| | service, Elevation of privilege. | ++------------------------+-------------------+----------------+----------------+ +| Application | Server | IoT | Mobile | ++------------------------+-------------------+----------------+----------------+ +| Impact | Critical (5) | Critical (5) | Critical (5) | ++------------------------+-------------------+----------------+----------------+ +| Likelihood | Critical (5) | Critical (5) | Critical (5) | ++------------------------+-------------------+----------------+----------------+ +| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | ++------------------------+-------------------+----------------+----------------+ +| Mitigations | | By default, the code to read input data from UART | +| | interfaces is disabled (see `ENABLE_CONSOLE_GETC` | +| | build option). It should only be enabled on a | +| | need basis. | +| | | +| | | Data received over UART interfaces should be | +| | treated as untrusted data. As such, it should be | +| | properly sanitized and handled with caution. | ++------------------------+-----------------------------------------------------+ +| Mitigations | | Platform specific. | +| implemented? | | +| | | Generic code does not read any input data from | +| | UART interface(s). | ++------------------------+-----------------------------------------------------+ + + +.. _Boot Firmware Threats: + +Threats to be Mitigated by the Boot Firmware +-------------------------------------------- + +The boot firmware here refers to the boot ROM (BL1) and the trusted boot +firmware (BL2). Typically it does not stay resident in memory and it is +dismissed once execution has reached the runtime EL3 firmware (BL31). Thus, past +that point in time, the threats below can no longer be exploited. + +Note, however, that this is not necessarily true on all platforms. Platform +vendors should review these threats to make sure they cannot be exploited +nonetheless once execution has reached the runtime EL3 firmware. + ++------------------------+----------------------------------------------------+ +| ID | 01 | ++========================+====================================================+ +| Threat | | **An attacker can mangle firmware images to | +| | execute arbitrary code** | +| | | +| | | Some TF-A images are loaded from external | +| | storage. It is possible for an attacker to access| +| | the external flash memory and change its contents| +| | physically, through the Rich OS, or using the | +| | updating mechanism to modify the non-volatile | +| | images to execute arbitrary code. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF4, DF5 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | BL2, BL31 | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | Code Execution | ++------------------------+----------------------------------------------------+ +| Threat Agent | PhysicalAccess, NSCode, SecCode | ++------------------------+----------------------------------------------------+ +| Threat Type | Tampering, Elevation of Privilege | ++------------------------+------------------+-----------------+---------------+ +| Application | Server | IoT | Mobile | ++------------------------+------------------+-----------------+---------------+ +| Impact | Critical (5) | Critical (5) | Critical (5) | ++------------------------+------------------+-----------------+---------------+ +| Likelihood | Critical (5) | Critical (5) | Critical (5) | ++------------------------+------------------+-----------------+---------------+ +| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | ++------------------------+------------------+-----------------+---------------+ +| Mitigations | | 1) Implement the `Trusted Board Boot (TBB)`_ | +| | feature which prevents malicious firmware from | +| | running on the platform by authenticating all | +| | firmware images. | +| | | +| | | 2) Perform extra checks on unauthenticated data, | +| | such as FIP metadata, prior to use. | ++------------------------+----------------------------------------------------+ +| Mitigations | | 1) Yes, provided that the ``TRUSTED_BOARD_BOOT`` | +| implemented? | build option is set to 1. | +| | | +| | | 2) Yes. | ++------------------------+----------------------------------------------------+ + ++------------------------+----------------------------------------------------+ +| ID | 02 | ++========================+====================================================+ +| Threat | | **An attacker may attempt to boot outdated, | +| | potentially vulnerable firmware image** | +| | | +| | | When updating firmware, an attacker may attempt | +| | to rollback to an older version that has unfixed | +| | vulnerabilities. | ++------------------------+----------------------------------------------------+ +| Diagram Elements | DF1, DF4, DF5 | ++------------------------+----------------------------------------------------+ +| Affected TF-A | BL2, BL31 | +| Components | | ++------------------------+----------------------------------------------------+ +| Assets | Code Execution | ++------------------------+----------------------------------------------------+ +| Threat Agent | PhysicalAccess, NSCode, SecCode | ++------------------------+----------------------------------------------------+ +| Threat Type | Tampering | ++------------------------+------------------+-----------------+---------------+ +| Application | Server | IoT | Mobile | ++------------------------+------------------+-----------------+---------------+ +| Impact | Critical (5) | Critical (5) | Critical (5) | ++------------------------+------------------+-----------------+---------------+ +| Likelihood | Critical (5) | Critical (5) | Critical (5) | ++------------------------+------------------+-----------------+---------------+ +| Total Risk Rating | Critical (25) | Critical (25) | Critical (25) | ++------------------------+------------------+-----------------+---------------+ +| Mitigations | Implement anti-rollback protection using | +| | non-volatile counters (NV counters) as required | +| | by `TBBR-Client specification`_. | ++------------------------+----------------------------------------------------+ +| Mitigations | | Yes / Platform specific. | +| implemented? | | +| | | After a firmware image is validated, the image | +| | revision number taken from a certificate | +| | extension field is compared with the | +| | corresponding NV counter stored in hardware to | +| | make sure the new counter value is larger than | +| | the current counter value. | +| | | +| | | **Platforms must implement this protection using | +| | platform specific hardware NV counters.** | ++------------------------+----------------------------------------------------+ + + ++------------------------+-------------------------------------------------------+ +| ID | 03 | ++========================+=======================================================+ +| Threat | | **An attacker can use Time-of-Check-Time-of-Use | +| | (TOCTOU) attack to bypass image authentication | +| | during the boot process** | +| | | +| | | Time-of-Check-Time-of-Use (TOCTOU) threats occur | +| | when the security check is produced before the time | +| | the resource is accessed. If an attacker is sitting | +| | in the middle of the off-chip images, they could | +| | change the binary containing executable code right | +| | after the integrity and authentication check has | +| | been performed. | ++------------------------+-------------------------------------------------------+ +| Diagram Elements | DF1 | ++------------------------+-------------------------------------------------------+ +| Affected TF-A | BL1, BL2 | +| Components | | ++------------------------+-------------------------------------------------------+ +| Assets | Code Execution, Sensitive Data | ++------------------------+-------------------------------------------------------+ +| Threat Agent | PhysicalAccess | ++------------------------+-------------------------------------------------------+ +| Threat Type | Elevation of Privilege | ++------------------------+---------------------+-----------------+---------------+ +| Application | Server | IoT | Mobile | ++------------------------+---------------------+-----------------+---------------+ +| Impact | N/A | Critical (5) | Critical (5) | ++------------------------+---------------------+-----------------+---------------+ +| Likelihood | N/A | Medium (3) | Medium (3) | ++------------------------+---------------------+-----------------+---------------+ +| Total Risk Rating | N/A | High (15) | High (15) | ++------------------------+---------------------+-----------------+---------------+ +| Mitigations | Copy image to on-chip memory before authenticating | +| | it. | ++------------------------+-------------------------------------------------------+ +| Mitigations | | Platform specific. | +| implemented? | | +| | | The list of images to load and their location is | +| | platform specific. Platforms are responsible for | +| | arranging images to be loaded in on-chip memory. | ++------------------------+-------------------------------------------------------+ + + ++------------------------+-------------------------------------------------------+ +| ID | 04 | ++========================+=======================================================+ +| Threat | | **An attacker with physical access can execute | +| | arbitrary image by bypassing the signature | +| | verification stage using glitching techniques** | +| | | +| | | Glitching (Fault injection) attacks attempt to put | +| | a hardware into a undefined state by manipulating an| +| | environmental variable such as power supply. | +| | | +| | | TF-A relies on a chain of trust that starts with the| +| | ROTPK, which is the key stored inside the chip and | +| | the root of all validation processes. If an attacker| +| | can break this chain of trust, they could execute | +| | arbitrary code on the device. This could be | +| | achieved with physical access to the device by | +| | attacking the normal execution flow of the | +| | process using glitching techniques that target | +| | points where the image is validated against the | +| | signature. | ++------------------------+-------------------------------------------------------+ +| Diagram Elements | DF1 | ++------------------------+-------------------------------------------------------+ +| Affected TF-A | BL1, BL2 | +| Components | | ++------------------------+-------------------------------------------------------+ +| Assets | Code Execution | ++------------------------+-------------------------------------------------------+ +| Threat Agent | PhysicalAccess | ++------------------------+-------------------------------------------------------+ +| Threat Type | Tampering, Elevation of Privilege | ++------------------------+---------------------+-----------------+---------------+ +| Application | Server | IoT | Mobile | ++------------------------+---------------------+-----------------+---------------+ +| Impact | N/A | Critical (5) | Critical (5) | ++------------------------+---------------------+-----------------+---------------+ +| Likelihood | N/A | Medium (3) | Medium (3) | ++------------------------+---------------------+-----------------+---------------+ +| Total Risk Rating | N/A | High (15) | High (15) | ++------------------------+---------------------+-----------------+---------------+ +| Mitigations | Mechanisms to detect clock glitch and power | +| | variations. | ++------------------------+-------------------------------------------------------+ +| Mitigations | | No. | +| implemented? | | +| | | The most effective mitigation is adding glitching | +| | detection and mitigation circuit at the hardware | +| | level. | +| | | +| | | However, software techniques, such as adding | +| | redundant checks when performing conditional | +| | branches that are security sensitive, can be used | +| | to harden TF-A against such attacks. | +| | **At the moment TF-A doesn't implement such | +| | mitigations.** | ++------------------------+-------------------------------------------------------+ + +.. topic:: Measured Boot Threats (or lack of) + + In the current Measured Boot design, BL1, BL2, and BL31, as well as the + secure world components, form the |SRTM|. Measurement data is currently + considered an asset to be protected against attack, and this is achieved + by storing them in the Secure Memory. + Beyond the measurements stored inside the TCG-compliant Event Log buffer, + there are no other assets to protect or threats to defend against that + could compromise |TF-A| execution environment's security. + + There are general security assets and threats associated with remote/delegated + attestation. However, these are outside the |TF-A| security boundary and + should be dealt with by the appropriate agent in the platform/system. + Since current Measured Boot design does not use local attestation, there would + be no further assets to protect(like unsealed keys). + + A limitation of the current Measured Boot design is that it is dependent upon + Secure Boot as implementation of Measured Boot does not extend measurements + into a discrete |TPM|, where they would be securely stored and protected + against tampering. This implies that if Secure-Boot is compromised, Measured + Boot may also be compromised. + + Platforms must carefully evaluate the security of the default implementation + since the |SRTM| includes all secure world components. + + +.. _Runtime Firmware Threats: + +Threats to be Mitigated by the Runtime EL3 Firmware +--------------------------------------------------- + ++------------------------+------------------------------------------------------+ +| ID | 07 | ++========================+======================================================+ +| Threat | | **An attacker can perform a denial-of-service | +| | attack by using a broken SMC call that causes the | +| | system to reboot or enter into unknown state.** | +| | | +| | | Secure and non-secure clients access TF-A services | +| | through SMC calls. Malicious code can attempt to | +| | place the TF-A runtime into an inconsistent state | +| | by calling unimplemented SMC call or by passing | +| | invalid arguments. | ++------------------------+------------------------------------------------------+ +| Diagram Elements | DF4, DF5 | ++------------------------+------------------------------------------------------+ +| Affected TF-A | BL31 | +| Components | | ++------------------------+------------------------------------------------------+ +| Assets | Availability | ++------------------------+------------------------------------------------------+ +| Threat Agent | NSCode, SecCode | ++------------------------+------------------------------------------------------+ +| Threat Type | Denial of Service | ++------------------------+-------------------+----------------+-----------------+ +| Application | Server | IoT | Mobile | ++------------------------+-------------------+----------------+-----------------+ +| Impact | Medium (3) | Medium (3) | Medium (3) | ++------------------------+-------------------+----------------+-----------------+ +| Likelihood | High (4) | High (4) | High (4) | ++------------------------+-------------------+----------------+-----------------+ +| Total Risk Rating | High (12) | High (12) | High (12) | ++------------------------+-------------------+----------------+-----------------+ +| Mitigations | Validate SMC function ids and arguments before using | +| | them. | ++------------------------+------------------------------------------------------+ +| Mitigations | | Yes / Platform specific. | +| implemented? | | +| | | For standard services, all input is validated. | +| | | +| | | Platforms that implement SiP services must also | +| | validate SMC call arguments. | ++------------------------+------------------------------------------------------+ + + +------------------------+------------------------------------------------------+ | ID | 09 | +========================+======================================================+ @@ -795,60 +981,6 @@ | | attacks. | +------------------------+-----------------------------------------------------+ -+------------------------+----------------------------------------------------+ -| ID | 11 | -+========================+====================================================+ -| Threat | | **Misconfiguration of the Memory Management Unit | -| | (MMU) may allow a normal world software to | -| | access sensitive data, execute arbitrary | -| | code or access otherwise restricted HW | -| | interface** | -| | | -| | | A misconfiguration of the MMU could | -| | lead to an open door for software running in the | -| | normal world to access sensitive data or even | -| | execute code if the proper security mechanisms | -| | are not in place. | -+------------------------+----------------------------------------------------+ -| Diagram Elements | DF5, DF6 | -+------------------------+----------------------------------------------------+ -| Affected TF-A | BL1, BL2, BL31 | -| Components | | -+------------------------+----------------------------------------------------+ -| Assets | Sensitive Data, Code execution | -+------------------------+----------------------------------------------------+ -| Threat Agent | NSCode | -+------------------------+----------------------------------------------------+ -| Threat Type | Information Disclosure, Elevation of Privilege | -+------------------------+-----------------+-----------------+----------------+ -| Application | Server | IoT | Mobile | -+------------------------+-----------------+-----------------+----------------+ -| Impact | Critical (5) | Critical (5) | Critical (5) | -+------------------------+-----------------+-----------------+----------------+ -| Likelihood | High (4) | High (4) | High (4) | -+------------------------+-----------------+-----------------+----------------+ -| Total Risk Rating | Critical (20) | Critical (20) | Critical (20) | -+------------------------+-----------------+-----------------+----------------+ -| Mitigations | When configuring access permissions, the | -| | principle of least privilege ought to be | -| | enforced. This means we should not grant more | -| | privileges than strictly needed, e.g. code | -| | should be read-only executable, read-only data | -| | should be read-only execute-never, and so on. | -+------------------------+----------------------------------------------------+ -| Mitigations | | Platform specific. | -| implemented? | | -| | | MMU configuration is platform specific, | -| | therefore platforms need to make sure that the | -| | correct attributes are assigned to memory | -| | regions. | -| | | -| | | TF-A provides a library which abstracts the | -| | low-level details of MMU configuration. It | -| | provides well-defined and tested APIs. | -| | Platforms are encouraged to use it to limit the | -| | risk of misconfiguration. | -+------------------------+----------------------------------------------------+ +------------------------+-----------------------------------------------------+ | ID | 12 | @@ -905,40 +1037,9 @@ | | mitigated. | +------------------------+-----------------------------------------------------+ -+------------------------+-----------------------------------------------------+ -| ID | 13 | -+========================+=====================================================+ -| Threat | | **Leaving sensitive information in the memory, | -| | can allow an attacker to retrieve them.** | -| | | -| | | Accidentally leaving not-needed sensitive data in | -| | internal buffers can leak them if an attacker | -| | gains access to memory due to a vulnerability. | -+------------------------+-----------------------------------------------------+ -| Diagram Elements | DF4, DF5 | -+------------------------+-----------------------------------------------------+ -| Affected TF-A | BL1, BL2, BL31 | -| Components | | -+------------------------+-----------------------------------------------------+ -| Assets | Sensitive Data | -+------------------------+-----------------------------------------------------+ -| Threat Agent | NSCode, SecCode | -+------------------------+-----------------------------------------------------+ -| Threat Type | Information Disclosure | -+------------------------+-------------------+----------------+----------------+ -| Application | Server | IoT | Mobile | -+------------------------+-------------------+----------------+----------------+ -| Impact | Critical (5) | Critical (5) | Critical (5) | -+------------------------+-------------------+----------------+----------------+ -| Likelihood | Medium (3) | Medium (3) | Medium (3) | -+------------------------+-------------------+----------------+----------------+ -| Total Risk Rating | High (15) | High (15) | High (15) | -+------------------------+-------------------+----------------+----------------+ -| Mitigations | Clear the sensitive data from internal buffers as | -| | soon as they are not needed anymore. | -+------------------------+-----------------------------------------------------+ -| Mitigations | | Yes / Platform specific | -+------------------------+-----------------------------------------------------+ + +Threats to be Mitigated by an External Agent Outside of TF-A +------------------------------------------------------------ +------------------------+-----------------------------------------------------+ | ID | 14 |
diff --git a/docs/threat_model/threat_model_arm_cca.rst b/docs/threat_model/threat_model_arm_cca.rst new file mode 100644 index 0000000..fbf3327 --- /dev/null +++ b/docs/threat_model/threat_model_arm_cca.rst
@@ -0,0 +1,225 @@ +Threat Model for TF-A with Arm CCA support +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Introduction +************ + +This document provides a threat model of TF-A firmware for platforms with Arm +Realm Management Extension (RME) support which implement Arm Confidential +Compute Architecture (Arm CCA). + +Although it is a separate document, it references the :ref:`Generic Threat +Model` in a number of places, as some of the contents is commonly applicable to +TF-A with or without Arm CCA support. + +Target of Evaluation +******************** + +In this threat model, the target of evaluation is the Trusted Firmware for +A-class Processors (TF-A) with RME support and Arm CCA support. This includes +the boot ROM (BL1), the trusted boot firmware (BL2) and the runtime EL3 firmware +(BL31). + +Assumptions +=========== + +We make the following assumptions: + +- :ref:`Realm Management Extension (RME)` is enabled on the platform. + +- Arm CCA Hardware Enforced Security (HES) is available on the platform, as + recommended by `Arm CCA security model`_: + + *[R0004] Arm strongly recommends that all implementations of CCA utilize* + *hardware enforced security (CCA HES).* + +- All TF-A images run from on-chip memory. Data used by these images also live + in on-chip memory. This means TF-A is not vulnerable to an attacker that can + probe or tamper with off-chip memory. + + These are requirements of the `Arm CCA security model`_: + + *[R0147] Monitor code executes entirely from on-chip memory.* + + *[R0149] Any monitor data that may affect the CCA security guarantee, other* + *than GPT, is either held in on-chip memory, or in external memory but with* + *additional integrity protection.* + + Note that this threat model hardens *[R0149]* requirement by forbidding to + hold data in external memory, even if it is integrity-protected - except for + GPT data. + +- TF-A BL1 image is immutable and thus implicitly trusted. It runs from + read-only memory or write-protected memory. This could be on-chip ROM, on-chip + OTP, locked on-chip flash, or write-protected on-chip RAM for example. + + This is a requirement of the `Arm CCA security model`_: + + *[R0158] Arm recommends that all initial boot code is immutable on a* + *secured system.* + + *[R0050] If all or part of initial boot code is instantiated in on-chip* + *memory then other trusted subsystems or application PE cannot modify that* + *code before it has been executed.* + +- Trusted boot and measured boot are enabled. This means an attacker can't boot + arbitrary images that are not approved by platform providers. + + These are requirements of the `Arm CCA security model`_: + + *[R0048] A secured system can only load authorized CCA firmware.* + + *[R0079] All Monitor firmware loaded by PE initial boot is measured and* + *verified as outlined in Verified boot.* + +- No experimental features are enabled. These are typically incomplete features, + which need more time to stabilize. Thus, we do not consider threats that may + come from them. It is not recommended to use these features in production + builds. + +Data Flow Diagram +================= + +Figure 1 shows a high-level data flow diagram for TF-A. The diagram shows a +model of the different components of a TF-A-based system and their interactions +with TF-A. A description of each diagram element is given on Table 1. On the +diagram, the red broken lines indicate trust boundaries. Components outside of +the broken lines are considered untrusted by TF-A. + +.. uml:: ../resources/diagrams/plantuml/tfa_arm_cca_dfd.puml + :caption: Figure 1: Data Flow Diagram + +.. table:: Table 1: Data Flow Diagram Description + + +-----------------+--------------------------------------------------------+ + | Diagram Element | Description | + +=================+========================================================+ + | DF1 | | Refer to DF1 description in the | + | | :ref:`Generic Threat Model`. Additionally TF-A | + | | loads realm images. | + +-----------------+--------------------------------------------------------+ + | DF2-DF6 | | Refer to DF2-DF6 descriptions in the | + | | :ref:`Generic Threat Model`. | + +-----------------+--------------------------------------------------------+ + | DF7 | | Boot images interact with Arm CCA HES to record boot | + | | measurements and retrieve data used for AP images | + | | authentication. | + | | | + | | | The runtime firmware interacts with Arm CCA HES to | + | | obtain sensitive attestation data for the realm | + | | world. | + +-----------------+--------------------------------------------------------+ + | DF8 | | Realm world software (e.g. TF-RMM) interact with | + | | TF-A through SMC call interface and/or shared | + | | memory. | + +-----------------+--------------------------------------------------------+ + +Threat Analysis +*************** + +In this threat model, we use the same method to analyse threats as in the +:ref:`Generic Threat Model`. This section only points out differences where +applicable. + +- There is an additional threat agent: *RealmCode*. It takes the form of + malicious or faulty code running in the realm world, including R-EL2, R-EL1 + and R-EL0 levels. + +- At this time we only consider the ``Server`` target environment. New threats + identified in this threat model will only be given a risk rating for this + environment. Other environments may be added in a future revision + +Threat Assessment +================= + +General Threats for All Firmware Images +--------------------------------------- + +The following table analyses the :ref:`General Threats` in the context of this +threat model. Only deltas are pointed out. + + +----+-------------+-------------------------------------------------------+ + | ID | Applicable? | Comments | + +====+=============+=======================================================+ + | 05 | Yes | | + +----+-------------+-------------------------------------------------------+ + | 06 | Yes | | + +----+-------------+-------------------------------------------------------+ + | 08 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 11 | Yes | | Misconfiguration of the Memory Management Unit | + | | | (MMU) may allow a **normal/secure/realm** world | + | | | software to access sensitive data, execute arbitrary| + | | | code or access otherwise restricted HW interface. | + | | | | + | | | | **Note that on RME systems, MMU configuration also | + | | | includes Granule Protection Tables (GPT) setup.** | + | | | | + | | | | Additional diagram elements: DF4, DF7, DF8. | + | | | | + | | | | Additional threat agents: SecCode, RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 13 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 15 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + +Threats to be Mitigated by the Boot Firmware +-------------------------------------------- + +The following table analyses the :ref:`Boot Firmware Threats` in the context of +this threat model. Only deltas are pointed out. + + +----+-------------+-------------------------------------------------------+ + | ID | Applicable? | Comments | + +====+=============+=======================================================+ + | 01 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 02 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 03 | Yes | | + +----+-------------+-------------------------------------------------------+ + | 04 | Yes | | + +----+-------------+-------------------------------------------------------+ + +Threats to be Mitigated by the Runtime EL3 Firmware +--------------------------------------------------- + +The following table analyses the :ref:`Runtime Firmware Threats` in the context +of this threat model. Only deltas are pointed out. + + +----+-------------+-------------------------------------------------------+ + | ID | Applicable? | Comments | + +====+=============+=======================================================+ + | 07 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 09 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 10 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 12 | Yes | Additional diagram element: DF8. | + | | | | + | | | Additional threat agent: RealmCode. | + +----+-------------+-------------------------------------------------------+ + | 14 | Yes | | + +----+-------------+-------------------------------------------------------+ + +*Copyright (c) 2023, Arm Limited. All rights reserved.* + +.. _Arm CCA Security Model: https://developer.arm.com/documentation/DEN0096/A_a
diff --git a/docs/threat_model/threat_model_el3_spm.rst b/docs/threat_model/threat_model_el3_spm.rst index c3af7a2..8adf3dfd 100644 --- a/docs/threat_model/threat_model_el3_spm.rst +++ b/docs/threat_model/threat_model_el3_spm.rst
@@ -4,7 +4,7 @@ ************ Introduction ************ -This document provides a threat model for the TF-A `EL3 Secure Partition Manager`_ +This document provides a threat model for the TF-A :ref:`EL3 Secure Partition Manager` (EL3 SPM) implementation. The EL3 SPM implementation is based on the `Arm Firmware Framework for Arm A-profile`_ specification. @@ -13,7 +13,8 @@ ******************** In this threat model, the target of evaluation is the ``Secure Partition Manager Core`` component (SPMC) within the EL3 firmware. -The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_. +The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model +<threat_analysis>`. The scope for this threat model is: @@ -70,8 +71,8 @@ Threat Analysis *************** -This threat model follows a similar methodology to the `Generic TF-A threat model`_. -The following sections define: +This threat model follows a similar methodology to the :ref:`Generic TF-A threat model +<threat_analysis>`. The following sections define: - Trust boundaries - Assets @@ -115,7 +116,8 @@ Threat types ============ -The following threat categories as exposed in the `Generic TF-A threat model`_ +The following threat categories as exposed in the :ref:`Generic TF-A threat model +<threat_analysis>` are re-used: - Spoofing @@ -642,9 +644,7 @@ --------------- -*Copyright (c) 2022, Arm Limited. All rights reserved.* +*Copyright (c) 2022-2023, Arm Limited. All rights reserved.* .. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest -.. _EL3 Secure Partition Manager: ../components/el3-spmc.html -.. _Generic TF-A threat model: ./threat_model.html#threat-analysis .. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/docs/threat_model/threat_model_fvp_r.rst b/docs/threat_model/threat_model_fvp_r.rst index c1462bb..725eeed 100644 --- a/docs/threat_model/threat_model_fvp_r.rst +++ b/docs/threat_model/threat_model_fvp_r.rst
@@ -90,8 +90,10 @@ and since the MPU configuration is equivalent with that for the fvp platform and others, this is not expected to be a concern. + - ID 15: Improper handling of input data received over a UART interface may + allow an attacker to tamper with TF-A execution environment. -------------- -*Copyright (c) 2021, Arm Limited. All rights reserved.* +*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst deleted file mode 100644 index 9458a9f..0000000 --- a/docs/threat_model/threat_model_spm.rst +++ /dev/null
@@ -1,1339 +0,0 @@ -SPMC Threat Model -***************** - -************************ -Introduction -************************ -This document provides a threat model for the TF-A `Secure Partition Manager`_ -(SPM) implementation or more generally the S-EL2 reference firmware running on -systems implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2) architecture -extension. The SPM implementation is based on the `Arm Firmware Framework for -Arm A-profile`_ specification. - -In brief, the broad FF-A specification and S-EL2 firmware implementation -provide: - -- Isolation of mutually mistrusting SW components, or endpoints in the FF-A - terminology. -- Distinct sandboxes in the secure world called secure partitions. This permits - isolation of services from multiple vendors. -- A standard protocol for communication and memory sharing between FF-A - endpoints. -- Mutual isolation of the normal world and the secure world (e.g. a Trusted OS - is prevented to map an arbitrary NS physical memory region such as the kernel - or the Hypervisor). - -************************ -Target of Evaluation -************************ -In this threat model, the target of evaluation is the S-EL2 firmware or the -``Secure Partition Manager Core`` component (SPMC). -The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_. - -The scope for this threat model is: - -- The TF-A implementation for the S-EL2 SPMC based on the Hafnium hypervisor - running in the secure world of TrustZone (at S-EL2 exception level). - The threat model is not related to the normal world Hypervisor or VMs. - The S-EL1 and EL3 SPMC solutions are not covered. -- The implementation complies with the FF-A v1.0 specification, and a few - features of FF-A v1.1 specification. -- Secure partitions are statically provisioned at boot time. -- Focus on the run-time part of the life-cycle (no specific emphasis on boot - time, factory firmware provisioning, firmware udpate etc.) -- Not covering advanced or invasive physical attacks such as decapsulation, - FIB etc. -- Assumes secure boot or in particular TF-A trusted boot (TBBR or dual CoT) is - enabled. An attacker cannot boot arbitrary images that are not approved by the - SiP or platform providers. - -Data Flow Diagram -====================== -Figure 1 shows a high-level data flow diagram for the SPM split into an SPMD -component at EL3 and an SPMC component at S-EL2. The SPMD mostly acts as a -relayer/pass-through between the normal world and the secure world. It is -assumed to expose small attack surface. - -A description of each diagram element is given in Table 1. In the diagram, the -red broken lines indicate trust boundaries. - -Components outside of the broken lines are considered untrusted. - -.. uml:: ../resources/diagrams/plantuml/spm_dfd.puml - :caption: Figure 1: SPMC Data Flow Diagram - -.. table:: Table 1: SPMC Data Flow Diagram Description - - +---------------------+--------------------------------------------------------+ - | Diagram Element | Description | - +=====================+========================================================+ - | ``DF1`` | SP to SPMC communication. FF-A function invocation or | - | | implementation-defined Hypervisor call. | - +---------------------+--------------------------------------------------------+ - | ``DF2`` | SPMC to SPMD FF-A call. | - +---------------------+--------------------------------------------------------+ - | ``DF3`` | SPMD to NS forwarding. | - +---------------------+--------------------------------------------------------+ - | ``DF4`` | SP to SP FF-A direct message request/response. | - | | Note as a matter of simplifying the diagram | - | | the SP to SP communication happens through the SPMC | - | | (SP1 performs a direct message request to the | - | | SPMC targeting SP2 as destination. And similarly for | - | | the direct message response from SP2 to SP1). | - +---------------------+--------------------------------------------------------+ - | ``DF5`` | HW control. | - +---------------------+--------------------------------------------------------+ - | ``DF6`` | Bootloader image loading. | - +---------------------+--------------------------------------------------------+ - | ``DF7`` | External memory access. | - +---------------------+--------------------------------------------------------+ - -********************* -Threat Analysis -********************* - -This threat model follows a similar methodology to the `Generic TF-A threat model`_. -The following sections define: - -- Trust boundaries -- Assets -- Theat agents -- Threat types - -Trust boundaries -============================ - -- Normal world is untrusted. -- Secure world and normal world are separate trust boundaries. -- EL3 monitor, SPMD and SPMC are trusted. -- Bootloaders (in particular BL1/BL2 if using TF-A) and run-time BL31 are - implicitely trusted by the usage of secure boot. -- EL3 monitor, SPMD, SPMC do not trust SPs. - -.. figure:: ../resources/diagrams/spm-threat-model-trust-boundaries.png - - Figure 2: Trust boundaries - -Assets -============================ - -The following assets are identified: - -- SPMC state. -- SP state. -- Information exchange between endpoints (partition messages). -- SPMC secrets (e.g. pointer authentication key when enabled) -- SP secrets (e.g. application keys). -- Scheduling cycles. -- Shared memory. - -Threat Agents -============================ - -The following threat agents are identified: - -- NS-Endpoint identifies a non-secure endpoint: normal world client at NS-EL2 - (Hypervisor) or NS-EL1 (VM or OS kernel). -- S-Endpoint identifies a secure endpoint typically a secure partition. -- Hardware attacks (non-invasive) requiring a physical access to the device, - such as bus probing or DRAM stress. - -Threat types -============================ - -The following threat categories as exposed in the `Generic TF-A threat model`_ -are re-used: - -- Spoofing -- Tampering -- Repudiation -- Information disclosure -- Denial of service -- Elevation of privileges - -Similarly this threat model re-uses the same threat risk ratings. The risk -analysis is evaluated based on the environment being ``Server`` or ``Mobile``. - -Threat Assessment -============================ - -The following threats are identified by applying STRIDE analysis on each diagram -element of the data flow diagram. - -+------------------------+----------------------------------------------------+ -| ID | 01 | -+========================+====================================================+ -| ``Threat`` | **An endpoint impersonates the sender or receiver | -| | FF-A ID in a direct request/response invocation.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMD, SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Spoofing | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------++----------------+---------------+ -| ``Impact`` | Critical(5) | Critical(5) | | -+------------------------+------------------++----------------+---------------+ -| ``Likelihood`` | Critical(5) | Critical(5) | | -+------------------------+------------------++----------------+---------------+ -| ``Total Risk Rating`` | Critical(25) | Critical(25) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. | -| | The guidance below is left for a system integrator | -| | to implemented as necessary. | -| | The SPMC must enforce checks in the direct message | -| | request/response interfaces such an endpoint cannot| -| | spoof the origin and destination worlds (e.g. a NWd| -| | originated message directed to the SWd cannot use a| -| | SWd ID as the sender ID). | -| | Additionally a software component residing in the | -| | SPMC can be added for the purpose of direct | -| | request/response filtering. | -| | It can be configured with the list of known IDs | -| | and about which interaction can occur between one | -| | and another endpoint (e.g. which NWd endpoint ID | -| | sends a direct request to which SWd endpoint ID). | -| | This component checks the sender/receiver fields | -| | for a legitimate communication between endpoints. | -| | A similar component can exist in the OS kernel | -| | driver, or Hypervisor although it remains untrusted| -| | by the SPMD/SPMC. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 02 | -+========================+====================================================+ -| ``Threat`` | **Tampering with memory shared between an endpoint | -| | and the SPMC.** | -| | A malicious endpoint may attempt tampering with its| -| | RX/TX buffer contents while the SPMC is processing | -| | it (TOCTOU). | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF3, DF4, DF7 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | Shared memory, Information exchange | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | High (4) | High (4) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | High (4) | High (4) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | High (16) | High (16) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | In context of FF-A v1.0 and v1.1 this is the case | -| | of sharing the RX/TX buffer pair and usage in the | -| | PARTITION_INFO_GET or mem sharing primitives. | -| | The SPMC must copy the contents of the TX buffer | -| | to an internal temporary buffer before processing | -| | its contents. The SPMC must implement hardened | -| | input validation on data transmitted through the TX| -| | buffer by an untrusted endpoint. | -| | The TF-A SPMC mitigates this threat by enforcing | -| | checks on data transmitted through RX/TX buffers. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 03 | -+========================+====================================================+ -| ``Threat`` | **An endpoint may tamper with its own state or the | -| | state of another endpoint.** | -| | A malicious endpoint may attempt violating: | -| | - its own or another SP state by using an unusual | -| | combination (or out-of-order) FF-A function | -| | invocations. | -| | This can also be an endpoint emitting | -| | FF-A function invocations to another endpoint while| -| | the latter is not in a state to receive it (e.g. a | -| | SP sends a direct request to the normal world early| -| | while the normal world is not booted yet). | -| | - the SPMC state itself by employing unexpected | -| | transitions in FF-A memory sharing, direct requests| -| | and responses, or handling of interrupts. | -| | This can be led by random stimuli injection or | -| | fuzzing. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMD, SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP state, SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | High (4) | High (4) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | High (12) | High (12) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC provides mitigation against such | -| | threat by following the guidance for partition | -| | runtime models as described in FF-A v1.1 EAC0 spec.| -| | The SPMC performs numerous checks in runtime to | -| | prevent illegal state transitions by adhering to | -| | the partition runtime model. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 04 | -+========================+====================================================+ -| ``Threat`` | *An attacker may attempt injecting errors by the | -| | use of external DRAM stress techniques.** | -| | A malicious agent may attempt toggling an SP | -| | Stage-2 MMU descriptor bit within the page tables | -| | that the SPMC manages. This can happen in Rowhammer| -| | types of attack. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF7 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP or SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | Hardware attack | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering | -+------------------------+------------------+---------------+-----------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+---------------+-----------------+ -| ``Impact`` | High (4) | High (4) | | -+------------------------+------------------+---------------+-----------------+ -| ``Likelihood`` | Low (2) | Medium (3) | | -+------------------------+------------------+---------------+-----------------+ -| ``Total Risk Rating`` | Medium (8) | High (12) | | -+------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | The TF-A SPMC does not provide mitigations to this | -| | type of attack. It can be addressed by the use of | -| | dedicated HW circuity or hardening at the chipset | -| | or platform level left to the integrator. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 05 | -+========================+====================================================+ -| ``Threat`` | **Protection of the SPMC from a DMA capable device | -| | upstream to an SMMU.** | -| | A device may attempt to tamper with the internal | -| | SPMC code/data sections. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF5 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC or SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Elevation of privileges | -+------------------------+------------------+---------------+-----------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+---------------+-----------------+ -| ``Impact`` | High (4) | High (4) | | -+------------------------+------------------+---------------+-----------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+---------------+-----------------+ -| ``Total Risk Rating`` | High (12) | High (12) | | -+------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | A platform may prefer assigning boot time, | -| | statically alocated memory regions through the SMMU| -| | configuration and page tables. The FF-A v1.1 | -| | specification provisions this capability through | -| | static DMA isolation. | -| | The TF-A SPMC does not mitigate this threat. | -| | It will adopt the static DMA isolation approach in | -| | a future release. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 06 | -+========================+====================================================+ -| ``Threat`` | **Replay fragments of past communication between | -| | endpoints.** | -| | A malicious endpoint may replay a message exchange | -| | that occured between two legitimate endpoint as | -| | a matter of triggering a malfunction or extracting | -| | secrets from the receiving endpoint. In particular | -| | the memory sharing operation with fragmented | -| | messages between an endpoint and the SPMC may be | -| | replayed by a malicious agent as a matter of | -| | getting access or gaining permissions to a memory | -| | region which does not belong to this agent. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | Information exchange | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Repdudiation | -+------------------------+------------------+---------------+-----------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+---------------+-----------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+---------------+-----------------+ -| ``Likelihood`` | High (4) | High (4) | | -+------------------------+------------------+---------------+-----------------+ -| ``Total Risk Rating`` | High (12) | High (12) | | -+------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 07 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint may attempt to extract data | -| | or state information by the use of invalid or | -| | incorrect input arguments.** | -| | Lack of input parameter validation or side effects | -| | of maliciously forged input parameters might affect| -| | the SPMC. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMD, SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP secrets, SPMC secrets, SP state, SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Information discolure | -+------------------------+------------------+---------------+-----------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+---------------+-----------------+ -| ``Impact`` | High (4) | High (4) | | -+------------------------+------------------+---------------+-----------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+---------------+-----------------+ -| ``Total Risk Rating`` | High (12) | High (12) | | -+------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | Secure Partitions must follow security standards | -| | and best practises as a way to mitigate the risk | -| | of common vulnerabilities to be exploited. | -| | The use of software (canaries) or hardware | -| | hardening techniques (XN, WXN, BTI, pointer | -| | authentication, MTE) helps detecting and stopping | -| | an exploitation early. | -| | The TF-A SPMC mitigates this threat by implementing| -| | stack protector, pointer authentication, BTI, XN, | -| | WXN, security hardening techniques. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 08 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint may forge a direct message | -| | request such that it reveals the internal state of | -| | another endpoint through the direct message | -| | response.** | -| | The secure partition or SPMC replies to a partition| -| | message by a direct message response with | -| | information which may reveal its internal state | -| | (.e.g. partition message response outside of | -| | allowed bounds). | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC or SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Information discolure | -+------------------------+------------------+---------------+-----------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+---------------+-----------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+---------------+-----------------+ -| ``Likelihood`` | Low (2) | Low (2) | | -+------------------------+------------------+---------------+-----------------+ -| ``Total Risk Rating`` | Medium (6) | Medium (6) | | -+------------------------+------------------+---------------+-----------------+ -| ``Mitigations`` | For the specific case of direct requests targeting | -| | the SPMC, the latter is hardened to prevent | -| | its internal state or the state of an SP to be | -| | revealed through a direct message response. | -| | Further, SPMC performs numerous checks in runtime | -| | on the basis of the rules established by partition | -| | runtime models to stop any malicious attempts by | -| | an endpoint to extract internal state of another | -| | endpoint. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 09 | -+========================+====================================================+ -| ``Threat`` | **Probing the FF-A communication between | -| | endpoints.** | -| | SPMC and SPs are typically loaded to external | -| | memory (protected by a TrustZone memory | -| | controller). A malicious agent may use non invasive| -| | methods to probe the external memory bus and | -| | extract the traffic between an SP and the SPMC or | -| | among SPs when shared buffers are held in external | -| | memory. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF7 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP/SPMC state, SP/SPMC secrets | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | Hardware attack | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Information disclosure | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Low (2) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (6) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | It is expected the platform or chipset provides | -| | guarantees in protecting the DRAM contents. | -| | The TF-A SPMC does not mitigate this class of | -| | attack and this is left to the integrator. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 10 | -+========================+====================================================+ -| ``Threat`` | **A malicious agent may attempt revealing the SPMC | -| | state or secrets by the use of software-based cache| -| | side-channel attack techniques.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF7 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP or SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Information disclosure | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Low (2) | Low (2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (6) | Medium (6) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | From an integration perspective it is assumed | -| | platforms consuming the SPMC component at S-EL2 | -| | (hence implementing the Armv8.4 FEAT_SEL2 | -| | architecture extension) implement mitigations to | -| | Spectre, Meltdown or other cache timing | -| | side-channel type of attacks. | -| | The TF-A SPMC implements one mitigation (barrier | -| | preventing speculation past exeception returns). | -| | The SPMC may be hardened further with SW | -| | mitigations (e.g. speculation barriers) for the | -| | cases not covered in HW. Usage of hardened | -| | compilers and appropriate options, code inspection | -| | are recommended ways to mitigate Spectre types of | -| | attacks. For non-hardened cores, the usage of | -| | techniques such a kernel page table isolation can | -| | help mitigating Meltdown type of attacks. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 11 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint may attempt flooding the | -| | SPMC with requests targeting a service within an | -| | endpoint such that it denies another endpoint to | -| | access this service.** | -| | Similarly, the malicious endpoint may target a | -| | a service within an endpoint such that the latter | -| | is unable to request services from another | -| | endpoint. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. | -| | Bounding the time for operations to complete can | -| | be achieved by the usage of a trusted watchdog. | -| | Other quality of service monitoring can be achieved| -| | in the SPMC such as counting a number of operations| -| | in a limited timeframe. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 12 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint may attempt to allocate | -| | notifications bitmaps in the SPMC, through the | -| | FFA_NOTIFICATION_BITMAP_CREATE.** | -| | This might be an attempt to exhaust SPMC's memory, | -| | or to allocate a bitmap for a VM that was not | -| | intended to receive notifications from SPs. Thus | -| | creating the possibility for a channel that was not| -| | meant to exist. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of service, Spoofing | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium(3) | Medium(3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium(3) | Medium(3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium(9) | Medium(9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this threat by defining a | -| | a fixed size pool for bitmap allocation. | -| | It also limits the designated FF-A calls to be used| -| | from NWd endpoints. | -| | In the NWd the hypervisor is supposed to limit the | -| | access to the designated FF-A call. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 13 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint may attempt to destroy the | -| | notifications bitmaps in the SPMC, through the | -| | FFA_NOTIFICATION_BITMAP_DESTROY.** | -| | This might be an attempt to tamper with the SPMC | -| | state such that a partition isn't able to receive | -| | notifications. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Low(4) | Low(4) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this issue by limiting the | -| | designated FF-A call to be issued by the NWd. | -| | Also, the notifications bitmap can't be destroyed | -| | if there are pending notifications. | -| | In the NWd, the hypervisor must restrict the | -| | NS-endpoints that can issue the designated call. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 14 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint might attempt to give | -| | permissions to an unintended sender to set | -| | notifications targeting another receiver using the | -| | FF-A call FFA_NOTIFICATION_BIND.** | -| | This might be an attempt to tamper with the SPMC | -| | state such that an unintended, and possibly | -| | malicious, communication channel is established. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Spoofing | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium(3) | Medium(3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium(6) | Medium(6) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this by restricting | -| | designated FFA_NOTIFICATION_BIND call to be issued | -| | by the receiver only. The receiver is responsible | -| | for allocating the notifications IDs to one | -| | specific partition. | -| | Also, receivers that are not meant to receive | -| | notifications, must have notifications receipt | -| | disabled in the respective partition's manifest. | -| | As for calls coming from NWd, if the NWd VM has had| -| | its bitmap allocated at initialization, the TF-A | -| | SPMC can't guarantee this threat won't happen. | -| | The Hypervisor must mitigate in the NWd, similarly | -| | to SPMC for calls in SWd. Though, if the Hypervisor| -| | has been compromised, the SPMC won't be able to | -| | mitigate it for calls forwarded from NWd. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 15 | -+========================+====================================================+ -| ``Threat`` | **A malicious partition endpoint might attempt to | -| | set notifications that are not bound to it.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Spoofing | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Low(4) | Low(4) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this by checking the | -| | sender's ID provided in the input to the call | -| | FFA_NOTIFICATION_SET. The SPMC keeps track of which| -| | notifications are bound to which sender, for a | -| | given receiver. If the sender is an SP, the | -| | provided sender ID must match the ID of the | -| | currently running partition. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 16 | -+========================+====================================================+ -| ``Threat`` | **A malicious partition endpoint might attempt to | -| | get notifications that are not targeted to it.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Spoofing | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Informational(1) | Informational(1)| | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this by checking the | -| | receiver's ID provided in the input to the call | -| | FFA_NOTIFICATION_GET. The SPMC keeps track of which| -| | notifications are pending for each receiver. | -| | The provided receiver ID must match the ID of the | -| | currently running partition, if it is an SP. | -| | For calls forwarded from NWd, the SPMC will return | -| | the pending notifications if the receiver had its | -| | bitmap created, and has pending notifications. | -| | If Hypervisor or OS kernel are compromised, the | -| | SPMC won't be able to mitigate calls from rogue NWd| -| | endpoints. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 17 | -+========================+====================================================+ -| ``Threat`` | **A malicious partition endpoint might attempt to | -| | get the information about pending notifications, | -| | through the FFA_NOTIFICATION_INFO_GET call.** | -| | This call is meant to be used by the NWd FF-A | -| | driver. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Information disclosure | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium(3) | Medium(3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium(6) | Medium(6) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this by returning error to | -| | calls made by SPs to FFA_NOTIFICATION_INFO_GET. | -| | If Hypervisor or OS kernel are compromised, the | -| | SPMC won't be able mitigate calls from rogue NWd | -| | endpoints. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 18 | -+========================+====================================================+ -| ``Threat`` | **A malicious partition endpoint might attempt to | -| | flood another partition endpoint with notifications| -| | hindering its operation.** | -| | The intent of the malicious endpoint could be to | -| | interfere with both the receiver's and/or primary | -| | endpoint execution, as they can both be preempted | -| | by the NPI and SRI, respectively. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state, CPU cycles | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | DoS | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Low(2) | Low(2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium(3) | Medium(3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium(6) | Medium(6) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. | -| | However, the impact is limited due to the | -| | architecture: | -| | - Notifications are not queued, one that has been | -| | signaled needs to be retrieved by the receiver, | -| | until it can be sent again. | -| | - Both SRI and NPI can't be pended until handled | -| | which limits the amount of spurious interrupts. | -| | - A given receiver could only bind a maximum number| -| | of notifications to a given sender, within a given | -| | execution context. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 19 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint may abuse FFA_RUN call to | -| | resume or turn on other endpoint execution | -| | contexts, attempting to alter the internal state of| -| | SPMC and SPs, potentially leading to illegal state | -| | transitions and deadlocks.** | -| | An endpoint can call into another endpoint | -| | execution context using FFA_MSG_SEND_DIRECT_REQ | -| | ABI to create a call chain. A malicious endpoint | -| | could abuse this to form loops in a call chain that| -| | could lead to potential deadlocks. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF4 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, SPMD | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state, Scheduling cycles | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC provides mitigation against such | -| | threats by following the guidance for partition | -| | runtime models as described in FF-A v1.1 EAC0 spec.| -| | The SPMC performs numerous checks in runtime to | -| | prevent illegal state transitions by adhering to | -| | the partition runtime model. Further, if the | -| | receiver endpoint is a predecessor of current | -| | endpoint in the present call chain, the SPMC denies| -| | any attempts to form loops by returning FFA_DENIED | -| | error code. Only the primary scheduler is allowed | -| | to turn on execution contexts of other partitions | -| | though SPMC does not have the ability to | -| | scrutinize its identity. Secure partitions have | -| | limited ability to resume execution contexts of | -| | other partitions based on the runtime model. Such | -| | attempts cannot compromise the integrity of the | -| | SPMC. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 20 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint can perform a | -| | denial-of-service attack by using FFA_INTERRUPT | -| | call that could attempt to cause the system to | -| | crash or enter into an unknown state as no physical| -| | interrupt could be pending for it to be handled in | -| | the SPMC.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF5 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, SPMD | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state, Scheduling cycles | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC provides mitigation against such | -| | attack by detecting invocations from partitions | -| | and simply returning FFA_ERROR status interface. | -| | SPMC only allows SPMD to use FFA_INTERRUPT ABI to | -| | communicate a pending secure interrupt triggered | -| | while execution was in normal world. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 21 | -+========================+====================================================+ -| ``Threat`` | **A malicious secure endpoint might deactivate a | -| | (virtual) secure interrupt that was not originally | -| | signaled by SPMC, thereby attempting to alter the | -| | state of the SPMC and potentially lead to system | -| | crash.** | -| | SPMC maps the virtual interrupt ids to the physical| -| | interrupt ids to keep the implementation of virtual| -| | interrupt driver simple. | -| | Similarly, a malicious secure endpoint might invoke| -| | the deactivation ABI more than once for a secure | -| | interrupt. Moreover, a malicious secure endpoint | -| | might attempt to deactivate a (virtual) secure | -| | interrupt that was signaled to another endpoint | -| | execution context by the SPMC even before secure | -| | interrupt was handled. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF5 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | At initialization, the TF-A SPMC parses the | -| | partition manifests to find the target execution | -| | context responsible for handling the various | -| | secure physical interrupts. The TF-A SPMC provides | -| | mitigation against above mentioned threats by: | -| | | -| | - Keeping track of each pending virtual interrupt | -| | signaled to an execution context of a secure | -| | secure partition. | -| | - Denying any deactivation call from SP if there is| -| | no pending physical interrupt mapped to the | -| | given virtual interrupt. | -| | - Denying any deactivation call from SP if the | -| | virtual interrupt has not been signaled to the | -| | current execution context. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 22 | -+========================+====================================================+ -| ``Threat`` | **A malicious secure endpoint might not deactivate | -| | a virtual interrupt signaled to it by the SPMC but | -| | perform secure interrupt signal completion. This | -| | attempt to corrupt the internal state of the SPMC | -| | could lead to an unknown state and further lead to | -| | system crash.** | -| | Similarly, a malicious secure endpoint could | -| | deliberately not perform either interrupt | -| | deactivation or interrupt completion signal. Since,| -| | the SPMC can only process one secure interrupt at a| -| | time, this could choke the system where all | -| | interrupts are indefinitely masked which could | -| | potentially lead to system crash or reboot. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF5 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state, Scheduling cycles | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Tampering, Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC does not provide mitigation against | -| | such threat. This is a limitation of the current | -| | SPMC implementation and needs to be handled in the | -| | future releases. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 23 | -+========================+====================================================+ -| ``Threat`` | **A malicious endpoint could leverage non-secure | -| | interrupts to preempt a secure endpoint, thereby | -| | attempting to render it unable to handle a secure | -| | virtual interrupt targetted for it. This could lead| -| | to priority inversion as secure virtual interrupts | -| | are kept pending while non-secure interrupts are | -| | handled by normal world VMs.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF5 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, SPMD | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state, Scheduling cycles | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC alone does not provide mitigation | -| | against such threats. System integrators must take | -| | necessary high level design decisions that takes | -| | care of interrupt prioritization. The SPMC performs| -| | its role of enabling SPs to specify appropriate | -| | action towards non-secure interrupt with the help | -| | of partition manifest based on the guidance in the | -| | FF-A v1.1 EAC0 specification. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 24 | -+========================+====================================================+ -| ``Threat`` | **A secure endpoint depends on primary scheduler | -| | for CPU cycles. A malicious endpoint could delay | -| | the secure endpoint from being scheduled. Secure | -| | interrupts, if not handled timely, could compromise| -| | the state of SP and SPMC, thereby rendering the | -| | system unresponsive.** | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2, DF3, DF5 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, SPMD | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state, SP state, Scheduling cycles | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (9) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC does not provide full mitigation | -| | against such threats. However, based on the | -| | guidance provided in the FF-A v1.1 EAC0 spec, SPMC | -| | provisions CPU cycles to run a secure endpoint | -| | execution context in SPMC schedule mode which | -| | cannot be preempted by a non-secure interrupt. | -| | This reduces the dependency on primary scheduler | -| | for cycle allocation. Moreover, all further | -| | interrupts are masked until pending secure virtual | -| | interrupt on current CPU is handled. This allows SP| -| | execution context to make progress even upon being | -| | interrupted. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 25 | -+========================+====================================================+ -| ``Threat`` | **A rogue FF-A endpoint can use memory sharing | -| | calls to exhaust SPMC resources.** | -| | For each on-going operation that involves an SP, | -| | the SPMC allocates resources to track its state. | -| | If the operation is never concluded, the resources | -| | are never freed. | -| | In the worst scenario, multiple operations that | -| | never conclude may exhaust the SPMC resources to a | -| | point in which renders memory sharing operations | -| | impossible. This could affect other, non-harmful | -| | FF-A endpoints, from legitimately using memory | -| | share functionality. The intent might even be | -| | to cause the SPMC to consume excessive CPU cycles, | -| | attempting to make it deny its service to the NWd. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, SPMD | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SPMC state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | High (4) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | High (4) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | High (16) | Medium (9) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC uses a statically allocated pool of | -| | memory to keep track of on-going memory sharing | -| | operations. After a possible attack, this could | -| | fail due to insufficient memory, and return an | -| | error to the caller. At this point, any other | -| | endpoint that requires use of memory sharing for | -| | its operation could get itself in an unusable | -| | state. | -| | Regarding CPU cycles starving threat, the SPMC | -| | doesn't provide any mitigation for this, as any | -| | FF-A endpoint, at the virtual FF-A instance is | -| | allowed to invoke memory share/lend/donate. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 26 | -+========================+====================================================+ -| ``Threat`` | **A borrower may interfere with lender's | -| | operation, if it terminates due to a fatal error | -| | condition without releasing the memory | -| | shared/lent.** | -| | Such scenario may render the lender inoperable. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of Service | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | High (4) | Low (2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | High (12) | Medium(6) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC does not provide mitigation for such | -| | scenario. The FF-A endpoints must attempt to | -| | relinquish memory shared/lent themselves in | -| | case of failure. The memory used to track the | -| | operation in the SPMC will also remain usuable. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 27 | -+========================+====================================================+ -| ``Threat`` | **A rogue FF-A endpoint may attempt to tamper with | -| | the content of the memory shared/lent, whilst | -| | being accessed by other FF-A endpoints.** | -| | It might attempt to do so: using one of the clear | -| | flags, when either retrieving or relinquishing | -| | access to the memory via the respective FF-A | -| | calls; or directly accessing memory without | -| | respecting the synchronization protocol between | -| | all involved endpoints. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, FF-A endpoint | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of Service, Tampering | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | Low (2) | Low (2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Medium (3) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | Medium (6) | Medium(6) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The first case defined in the threat, the TF-A | -| | SPMC mitigates it, by ensuring a memory is cleared | -| | only when all borrowers have relinquished access | -| | to the memory, in a scenario involving multiple | -| | borrowers. Also, if the receiver is granted RO, | -| | permissions, the SPMC will reject any request | -| | to clear memory on behalf of the borrower, by | -| | returning an error to the respective FF-A call. | -| | The second case defined in the threat can't be | -| | mitigated by the SPMC. It is up to the NS/S FF-A | -| | endpoints to establish a robust protocol for using | -| | the shared memory. | -+------------------------+----------------------------------------------------+ - -+------------------------+----------------------------------------------------+ -| ID | 28 | -+========================+====================================================+ -| ``Threat`` | **A rogue FF-A endpoint may attempt to share | -| | memory that is not in its translation regime, or | -| | attempt to specify attributes more permissive than | -| | those it possesses at a given time.** | -| | Both ways could be an attempt for escalating its | -| | privileges. | -+------------------------+----------------------------------------------------+ -| ``Diagram Elements`` | DF1, DF2 | -+------------------------+----------------------------------------------------+ -| ``Affected TF-A | SPMC, FF-A endpoint | -| Components`` | | -+------------------------+----------------------------------------------------+ -| ``Assets`` | SP state | -+------------------------+----------------------------------------------------+ -| ``Threat Agent`` | NS-Endpoint, S-Endpoint | -+------------------------+----------------------------------------------------+ -| ``Threat Type`` | Denial of Service, Tampering | -+------------------------+------------------+-----------------+---------------+ -| ``Application`` | ``Server`` | ``Mobile`` | | -+------------------------+------------------+-----------------+---------------+ -| ``Impact`` | High (4) | Low (2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Likelihood`` | Medium (3) | Low (2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Total Risk Rating`` | High (12) | Low (2) | | -+------------------------+------------------+-----------------+---------------+ -| ``Mitigations`` | The TF-A SPMC mitigates this threat by performing | -| | sanity checks to the provided memory region | -| | descriptor. | -| | For operations at the virtual FF-A instance, and | -| | once the full memory descriptor is provided, | -| | the SPMC validates that the memory is part of the | -| | caller's translation regime. The SPMC also checks | -| | that the memory attributes provided are within | -| | those the owner possesses, in terms of | -| | permissiveness. If more permissive attributes are | -| | specified, the SPMC returns an error | -| | FFA_INVALID_PARAMETERS. The permissiveness rules | -| | are enforced in any call to share/lend or donate | -| | the memory, and in retrieve requests. | -+------------------------+----------------------------------------------------+ - --------------- - -*Copyright (c) 2021-2023, Arm Limited. All rights reserved.* - -.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest -.. _Secure Partition Manager: ../components/secure-partition-manager.html -.. _Generic TF-A threat model: ./threat_model.html#threat-analysis -.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases -
diff --git a/docs/tools/index.rst b/docs/tools/index.rst new file mode 100644 index 0000000..2dee2c0 --- /dev/null +++ b/docs/tools/index.rst
@@ -0,0 +1,12 @@ +Tools +===== + +.. toctree:: + :maxdepth: 1 + :caption: Contents + + memory-layout-tool + +-------------- + +*Copyright (c) 2023, Arm Limited. All rights reserved.*
diff --git a/docs/tools/memory-layout-tool.rst b/docs/tools/memory-layout-tool.rst new file mode 100644 index 0000000..8874bd7 --- /dev/null +++ b/docs/tools/memory-layout-tool.rst
@@ -0,0 +1,236 @@ +TF-A Memory Layout Tool +======================= + +TF-A's memory layout tool is a Python script for analyzing the virtual +memory layout of TF-A builds. + +Prerequisites +~~~~~~~~~~~~~ + +#. Python (3.8 or later) +#. `Poetry`_ Python package manager + +Getting Started +~~~~~~~~~~~~~~~ + +#. Install Poetry + + .. code:: shell + + curl -sSL https://install.python-poetry.org | python3 - + +#. Install the required packages + + .. code:: shell + + poetry install --with memory + +#. Verify that the tool runs in the installed virtual environment + + .. code:: shell + + poetry run memory --help + +Symbol Virtual Map +~~~~~~~~~~~~~~~~~~ + +The tool can be used to generate a visualisation of the symbol table. By +default, it prints the symbols representing the start and end address of the +main memory regions in an ELF file (i.e. text, bss, rodata) but can be modified +to print any set of symbols. + +.. code:: shell + + $ poetry run memory -s + build-path: build/fvp/release + Virtual Address Map: + +------------__BL1_RAM_END__------------+---------------------------------------+ + +---------__COHERENT_RAM_END__----------+ | + +--------__COHERENT_RAM_START__---------+ | + 0x0403b000 +----------__XLAT_TABLE_END__-----------+ | + 0x04036000 +---------__XLAT_TABLE_START__----------+ | + +--------__BASE_XLAT_TABLE_END__--------+ | + 0x04035600 +--------------__BSS_END__--------------+ | + +-------__BASE_XLAT_TABLE_START__-------+ | + +-----__PMF_PERCPU_TIMESTAMP_END__------+ | + +---------__PMF_TIMESTAMP_END__---------+ | + 0x04035400 +--------__PMF_TIMESTAMP_START__--------+ | + +-------------__BSS_START__-------------+ | + 0x04034a00 +------------__STACKS_END__-------------+ | + 0x04034500 +-----------__STACKS_START__------------+ | + 0x040344c5 +-----------__DATA_RAM_END__------------+ | + +-----------__BL1_RAM_START__-----------+ | + 0x04034000 +----------__DATA_RAM_START__-----------+ | + | +---------__COHERENT_RAM_END__----------+ + | +--------__COHERENT_RAM_START__---------+ + 0x0402e000 | +----------__XLAT_TABLE_END__-----------+ + 0x04029000 | +---------__XLAT_TABLE_START__----------+ + | +--------__BASE_XLAT_TABLE_END__--------+ + 0x04028800 | +--------------__BSS_END__--------------+ + | +-------__BASE_XLAT_TABLE_START__-------+ + | +-----__PMF_PERCPU_TIMESTAMP_END__------+ + | +---------__PMF_TIMESTAMP_END__---------+ + 0x04028580 | +--------__PMF_TIMESTAMP_START__--------+ + 0x04028000 | +-------------__BSS_START__-------------+ + 0x04027e40 | +------------__STACKS_END__-------------+ + 0x04027840 | +-----------__STACKS_START__------------+ + 0x04027000 | +------------__RODATA_END__-------------+ + | +------------__CPU_OPS_END__------------+ + | +-----------__CPU_OPS_START__-----------+ + | +--------__FCONF_POPULATOR_END__--------+ + | +--------------__GOT_END__--------------+ + | +-------------__GOT_START__-------------+ + | +---------__PMF_SVC_DESCS_END__---------+ + 0x04026c10 | +--------__PMF_SVC_DESCS_START__--------+ + 0x04026bf8 | +-------__FCONF_POPULATOR_START__-------+ + | +-----------__RODATA_START__------------+ + 0x04026000 | +-------------__TEXT_END__--------------+ + 0x04021000 | +------------__TEXT_START__-------------+ + 0x000062b5 +------------__BL1_ROM_END__------------+ | + 0x00005df0 +----------__DATA_ROM_START__-----------+ | + +------------__CPU_OPS_END__------------+ | + +--------------__GOT_END__--------------+ | + +-------------__GOT_START__-------------+ | + 0x00005de8 +------------__RODATA_END__-------------+ | + +-----------__CPU_OPS_START__-----------+ | + +--------__FCONF_POPULATOR_END__--------+ | + +---------__PMF_SVC_DESCS_END__---------+ | + 0x00005c98 +--------__PMF_SVC_DESCS_START__--------+ | + 0x00005c80 +-------__FCONF_POPULATOR_START__-------+ | + +-----------__RODATA_START__------------+ | + 0x00005000 +-------------__TEXT_END__--------------+ | + 0x00000000 +------------__TEXT_START__-------------+---------------------------------------+ + +Addresses are displayed in hexadecimal by default but can be printed in decimal +instead with the ``-d`` option. + +Because of the length of many of the symbols, the tool defaults to a text width +of 120 chars. This can be increased if needed with the ``-w`` option. + +For more detailed help instructions, run: + +.. code:: shell + + poetry run memory --help + +Memory Footprint +~~~~~~~~~~~~~~~~ + +The tool enables users to view static memory consumption. When the options +``-f``, or ``--footprint`` are provided, the script analyses the ELF binaries in +the build path to generate a table (per memory type), showing memory allocation +and usage. This is the default output generated by the tool. + +.. code:: shell + + $ poetry run memory -f + build-path: build/fvp/release + +----------------------------------------------------------------------------+ + | Memory Usage (bytes) [RAM] | + +-----------+------------+------------+------------+------------+------------+ + | Component | Start | Limit | Size | Free | Total | + +-----------+------------+------------+------------+------------+------------+ + | BL1 | 4034000 | 4040000 | 7000 | 5000 | c000 | + | BL2 | 4021000 | 4034000 | d000 | 6000 | 13000 | + | BL2U | 4021000 | 4034000 | a000 | 9000 | 13000 | + | BL31 | 4003000 | 4040000 | 1e000 | 1f000 | 3d000 | + +-----------+------------+------------+------------+------------+------------+ + + +----------------------------------------------------------------------------+ + | Memory Usage (bytes) [ROM] | + +-----------+------------+------------+------------+------------+------------+ + | Component | Start | Limit | Size | Free | Total | + +-----------+------------+------------+------------+------------+------------+ + | BL1 | 0 | 4000000 | 5df0 | 3ffa210 | 4000000 | + +-----------+------------+------------+------------+------------+------------+ + +The script relies on symbols in the symbol table to determine the start, end, +and limit addresses of each bootloader stage. + +Memory Tree +~~~~~~~~~~~ + +A hierarchical view of the memory layout can be produced by passing the option +``-t`` or ``--tree`` to the tool. This gives the start, end, and size of each +module, their ELF segments as well as sections. + +.. code:: shell + + $ poetry run memory -t + build-path: build/fvp/release + name start end size + bl1 0 400c000 400c000 + ├── 00 0 5de0 5de0 + │ ├── .text 0 5000 5000 + │ └── .rodata 5000 5de0 de0 + ├── 01 4034000 40344c5 4c5 + │ └── .data 4034000 40344c5 4c5 + ├── 02 4034500 4034a00 500 + │ └── .stacks 4034500 4034a00 500 + ├── 04 4034a00 4035600 c00 + │ └── .bss 4034a00 4035600 c00 + └── 03 4036000 403b000 5000 + └── .xlat_table 4036000 403b000 5000 + bl2 4021000 4034000 13000 + ├── 00 4021000 4027000 6000 + │ ├── .text 4021000 4026000 5000 + │ └── .rodata 4026000 4027000 1000 + └── 01 4027000 402e000 7000 + ├── .data 4027000 4027809 809 + ├── .stacks 4027840 4027e40 600 + ├── .bss 4028000 4028800 800 + └── .xlat_table 4029000 402e000 5000 + bl2u 4021000 4034000 13000 + ├── 00 4021000 4025000 4000 + │ ├── .text 4021000 4024000 3000 + │ └── .rodata 4024000 4025000 1000 + └── 01 4025000 402b000 6000 + ├── .data 4025000 4025065 65 + ├── .stacks 4025080 4025480 400 + ├── .bss 4025600 4025c00 600 + └── .xlat_table 4026000 402b000 5000 + bl31 4003000 4040000 3d000 + ├── 02 ffe00000 ffe03000 3000 + │ └── .el3_tzc_dram ffe00000 ffe03000 3000 + ├── 00 4003000 4010000 d000 + │ └── .text 4003000 4010000 d000 + └── 01 4010000 4021000 11000 + ├── .rodata 4010000 4012000 2000 + ├── .data 4012000 401219d 19d + ├── .stacks 40121c0 40161c0 4000 + ├── .bss 4016200 4018c00 2a00 + ├── .xlat_table 4019000 4020000 7000 + └── .coherent_ram 4020000 4021000 1000 + + +The granularity of this view can be modified with the ``--depth`` option. For +instance, if you only require the tree up to the level showing segment data, +you can specify the depth with: + +.. code:: + + $ poetry run memory -t --depth 2 + build-path: build/fvp/release + name start end size + bl1 0 400c000 400c000 + ├── 00 0 5df0 5df0 + ├── 01 4034000 40344c5 4c5 + ├── 02 4034500 4034a00 500 + ├── 04 4034a00 4035600 c00 + └── 03 4036000 403b000 5000 + bl2 4021000 4034000 13000 + ├── 00 4021000 4027000 6000 + └── 01 4027000 402e000 7000 + bl2u 4021000 4034000 13000 + ├── 00 4021000 4025000 4000 + └── 01 4025000 402b000 6000 + bl31 4003000 4040000 3d000 + ├── 02 ffe00000 ffe03000 3000 + ├── 00 4003000 4010000 d000 + └── 01 4010000 4021000 11000 + +-------------- + +*Copyright (c) 2023, Arm Limited. All rights reserved.* + +.. _Poetry: https://python-poetry.org/docs/
diff --git a/drivers/amlogic/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S index 6d0a2d6..d955d83 100644 --- a/drivers/amlogic/console/aarch64/meson_console.S +++ b/drivers/amlogic/console/aarch64/meson_console.S
@@ -69,7 +69,7 @@ mov x0, x6 mov x30, x7 - finish_console_register meson putc=1, getc=1, flush=1 + finish_console_register meson putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/drivers/arm/dcc/dcc_console.c b/drivers/arm/dcc/dcc_console.c index 0b7e541..19c3450 100644 --- a/drivers/arm/dcc/dcc_console.c +++ b/drivers/arm/dcc/dcc_console.c
@@ -53,6 +53,7 @@ return read_mdccsr_el0(); } +#if ENABLE_CONSOLE_GETC static inline char __dcc_getchar(void) { char c; @@ -61,6 +62,7 @@ return c; } +#endif static inline void __dcc_putchar(char c) { @@ -102,6 +104,7 @@ return ch; } +#if ENABLE_CONSOLE_GETC static int32_t dcc_console_getc(struct console *console) { unsigned int status; @@ -113,12 +116,7 @@ return __dcc_getchar(); } - -int32_t dcc_console_init(unsigned long base_addr, uint32_t uart_clk, - uint32_t baud_rate) -{ - return 0; /* No init needed */ -} +#endif /** * dcc_console_flush() - Function to force a write of all buffered data @@ -139,9 +137,12 @@ static struct dcc_console dcc_console = { .console = { .flags = CONSOLE_FLAG_BOOT | - CONSOLE_FLAG_RUNTIME, + CONSOLE_FLAG_RUNTIME | + CONSOLE_FLAG_CRASH, .putc = dcc_console_putc, +#if ENABLE_CONSOLE_GETC .getc = dcc_console_getc, +#endif .flush = dcc_console_flush, }, }; @@ -150,3 +151,9 @@ { return console_register(&dcc_console.console); } + +void console_dcc_unregister(void) +{ + dcc_console_flush(&dcc_console.console); + (void)console_unregister(&dcc_console.console); +}
diff --git a/drivers/arm/ethosn/ethosn_big_fw.c b/drivers/arm/ethosn/ethosn_big_fw.c index 628f5d9..2aad5da 100644 --- a/drivers/arm/ethosn/ethosn_big_fw.c +++ b/drivers/arm/ethosn/ethosn_big_fw.c
@@ -12,7 +12,7 @@ #define ETHOSN_BIG_FW_MAGIC ('E' | ('N' << 8) | ('F' << 16) | ('W' << 24)) /* Supported big firmware version */ -#define ETHOSN_BIG_FW_VERSION_MAJOR 11 +#define ETHOSN_BIG_FW_VERSION_MAJOR 15 #define ETHOSN_ARCH_VER_MAJOR_MASK U(0xF000) #define ETHOSN_ARCH_VER_MAJOR_SHIFT U(0xC)
diff --git a/drivers/arm/ethosn/ethosn_npu.mk b/drivers/arm/ethosn/ethosn_npu.mk new file mode 100644 index 0000000..4a31b59 --- /dev/null +++ b/drivers/arm/ethosn/ethosn_npu.mk
@@ -0,0 +1,49 @@ +# +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# Arm(R) Ethos(TM)-N NPU SiP service +ETHOSN_NPU_DRIVER := 0 + +$(eval $(call assert_boolean,ETHOSN_NPU_DRIVER)) +$(eval $(call add_define,ETHOSN_NPU_DRIVER)) + +#Ethos-N NPU TZMP1 +ETHOSN_NPU_TZMP1 := 0 +$(eval $(call assert_boolean,ETHOSN_NPU_TZMP1)) +$(eval $(call add_define,ETHOSN_NPU_TZMP1)) +ifeq (${ETHOSN_NPU_TZMP1},1) + ifeq (${ETHOSN_NPU_DRIVER},0) + $(error "ETHOSN_NPU_TZMP1 is only available if ETHOSN_NPU_DRIVER=1) + endif + ifeq (${PLAT},juno) + $(eval $(call add_define,JUNO_ETHOSN_TZMP1)) + else + $(error "ETHOSN_NPU_TZMP1 only supported on Juno platform, not ", ${PLAT}) + endif + + ifeq (${TRUSTED_BOARD_BOOT},0) + # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being + # tampered with, which is required to protect the confidentiality of protected + # inference data. + $(error "ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled) + endif + + # We need the FW certificate and key certificate + $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert)) + $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert)) + # We need the firmware to be built into the FIP + $(eval $(call TOOL_ADD_IMG,ETHOSN_NPU_FW,--npu-fw)) + + # Needed for our OIDs to be available in tbbr_cot_bl2.c + $(eval $(call add_define, PLAT_DEF_OID)) + + # Needed so that UUIDs from the FIP are available in BL2 + $(eval $(call add_define,PLAT_DEF_FIP_UUID)) + + PLAT_INCLUDES += -I${PLAT_DIR}certificate/include + PLAT_INCLUDES += -Iinclude/drivers/arm/ + PLAT_INCLUDES += -I${PLAT_DIR}fip +endif
diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c index 85a12c5..9aa7e23 100644 --- a/drivers/arm/ethosn/ethosn_smc.c +++ b/drivers/arm/ethosn/ethosn_smc.c
@@ -17,9 +17,9 @@ #include <platform_def.h> -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 #include "ethosn_big_fw.h" -#endif +#endif /* ETHOSN_NPU_TZMP1 */ /* * Number of Arm(R) Ethos(TM)-N NPU (NPU) devices available @@ -46,16 +46,16 @@ #define ETHOSN_AUX_FEAT_STASHING U(0x2) #define SEC_AUXCTLR_REG U(0x0024) -#define SEC_AUXCTLR_VAL U(0x80) +#define SEC_AUXCTLR_VAL U(0x000ce080) #define SEC_AUXCTLR_LEVEL_IRQ_VAL U(0x04) #define SEC_AUXCTLR_STASHING_VAL U(0xA5000000) #define SEC_DEL_REG U(0x0004) -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 #define SEC_DEL_VAL U(0x808) #else #define SEC_DEL_VAL U(0x80C) -#endif +#endif /* ETHOSN_NPU_TZMP1 */ #define SEC_DEL_EXCC_MASK U(0x20) #define SEC_SECCTLR_REG U(0x0010) @@ -69,11 +69,11 @@ #define SEC_SYSCTRL0_CPU_WAIT U(1) #define SEC_SYSCTRL0_SLEEPING U(1U << 4) #define SEC_SYSCTRL0_INITVTOR_MASK U(0x1FFFFF80) -#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29) +#define SEC_SYSCTRL0_SOFT_RESET U(1U << 29) #define SEC_SYSCTRL0_HARD_RESET U(1U << 31) #define SEC_SYSCTRL1_REG U(0x001C) -#define SEC_SYSCTRL1_VAL U(0x180110) +#define SEC_SYSCTRL1_VAL U(0xe0180110) #define SEC_NSAID_REG_BASE U(0x3004) #define SEC_NSAID_OFFSET U(0x1000) @@ -104,8 +104,8 @@ #define TO_EXTEND_ADDR(addr) \ ((addr >> SEC_ADDR_EXT_SHIFT) & SEC_ADDR_EXT_MASK) -#if ARM_ETHOSN_NPU_TZMP1 -CASSERT(ARM_ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base); +#if ETHOSN_NPU_TZMP1 +CASSERT(ETHOSN_NPU_FW_IMAGE_BASE > 0U, assert_ethosn_invalid_fw_image_base); static const struct ethosn_big_fw *big_fw; #define FW_INITVTOR_ADDR(big_fw) \ @@ -115,7 +115,7 @@ #define SYSCTRL0_INITVTOR_ADDR(value) \ (value & SEC_SYSCTRL0_INITVTOR_MASK) -#endif +#endif /* ETHOSN_NPU_TZMP1 */ static bool ethosn_get_device_and_core(uintptr_t core_addr, const struct ethosn_device_t **dev_match, @@ -142,7 +142,7 @@ return false; } -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 static uint32_t ethosn_core_read_arch_version(uintptr_t core_addr) { uint32_t npu_id = mmio_read_32(ETHOSN_CORE_SEC_REG(core_addr, @@ -155,23 +155,23 @@ bool is_protected) { size_t i; - uint32_t streams[9] = {[0 ... 8] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID}; + uint32_t streams[9] = {[0 ... 8] = ETHOSN_NPU_NS_RO_DATA_NSAID}; - streams[FIRMWARE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID; - streams[PLE_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_FW_NSAID; + streams[FIRMWARE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID; + streams[PLE_STREAM_INDEX] = ETHOSN_NPU_PROT_FW_NSAID; - streams[WORKING_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID; + streams[WORKING_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID; if (is_protected) { - streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID; + streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RO_DATA_NSAID; streams[INTERMEDIATE_STREAM_INDEX] = - ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID; - streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID; + ETHOSN_NPU_PROT_RW_DATA_NSAID; + streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_PROT_RW_DATA_NSAID; } else { - streams[INPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RO_DATA_NSAID; + streams[INPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RO_DATA_NSAID; streams[INTERMEDIATE_STREAM_INDEX] = - ARM_ETHOSN_NPU_NS_RW_DATA_NSAID; - streams[OUTPUT_STREAM_INDEX] = ARM_ETHOSN_NPU_NS_RW_DATA_NSAID; + ETHOSN_NPU_NS_RW_DATA_NSAID; + streams[OUTPUT_STREAM_INDEX] = ETHOSN_NPU_NS_RW_DATA_NSAID; } for (i = 0U; i < ARRAY_SIZE(streams); ++i) { @@ -188,7 +188,7 @@ FW_INITVTOR_ADDR(big_fw)); } -#endif +#endif /* ETHOSN_NPU_TZMP1 */ static void ethosn_configure_events(uintptr_t core_addr) { @@ -343,7 +343,7 @@ static int ethosn_core_boot_fw(uintptr_t core_addr) { -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 const uintptr_t sysctrl0_reg = ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG); const uint32_t sysctrl0_val = mmio_read_32(sysctrl0_reg); const bool waiting = (sysctrl0_val & SEC_SYSCTRL0_CPU_WAIT); @@ -363,7 +363,7 @@ return ETHOSN_SUCCESS; #else return ETHOSN_NOT_SUPPORTED; -#endif +#endif /* ETHOSN_NPU_TZMP1 */ } static int ethosn_core_full_reset(const struct ethosn_device_t *device, @@ -392,17 +392,17 @@ if (!device->has_reserved_memory) { ethosn_configure_smmu_streams(device, core, asset_alloc_idx); -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 ethosn_configure_stream_nsaid(core, is_protected); -#endif +#endif /* ETHOSN_NPU_TZMP1 */ } ethosn_configure_stream_addr_extends(device, core->addr); ethosn_configure_stream_attr_ctlr(core->addr); -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 ethosn_configure_vector_table(core->addr); -#endif +#endif /* ETHOSN_NPU_TZMP1 */ ethosn_delegate_to_ns(core->addr); @@ -481,7 +481,7 @@ static uintptr_t ethosn_smc_fw_prop_handler(u_register_t fw_property, void *handle) { -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 switch (fw_property) { case ETHOSN_FW_PROP_VERSION: SMC_RET4(handle, ETHOSN_SUCCESS, @@ -507,7 +507,7 @@ } #else SMC_RET1(handle, ETHOSN_NOT_SUPPORTED); -#endif +#endif /* ETHOSN_NPU_TZMP1 */ } uintptr_t ethosn_smc_handler(uint32_t smc_fid, @@ -554,17 +554,17 @@ int ethosn_smc_setup(void) { -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 struct ethosn_device_t *dev; uint32_t arch_ver; -#endif +#endif /* ETHOSN_NPU_TZMP1 */ if (ETHOSN_NUM_DEVICES == 0U) { ERROR("ETHOSN: No NPU found\n"); return ETHOSN_FAILURE; } -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 /* Only one NPU core is supported in the TZMP1 setup */ if ((ETHOSN_NUM_DEVICES != 1U) || @@ -580,7 +580,7 @@ } arch_ver = ethosn_core_read_arch_version(dev->cores[0U].addr); - big_fw = (struct ethosn_big_fw *)ARM_ETHOSN_NPU_FW_IMAGE_BASE; + big_fw = (struct ethosn_big_fw *)ETHOSN_NPU_FW_IMAGE_BASE; if (!ethosn_big_fw_verify_header(big_fw, arch_ver)) { return ETHOSN_FAILURE; @@ -591,7 +591,7 @@ big_fw->fw_ver_patch); #else NOTICE("ETHOSN: Setup succeeded\n"); -#endif +#endif /* ETHOSN_NPU_TZMP1 */ return 0; }
diff --git a/drivers/arm/fvp/fvp_pwrc.c b/drivers/arm/fvp/fvp_pwrc.c index 75a2b66..fb77f77 100644 --- a/drivers/arm/fvp/fvp_pwrc.c +++ b/drivers/arm/fvp/fvp_pwrc.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,22 +10,39 @@ #include <plat/arm/common/plat_arm.h> #include <platform_def.h> +#define FVP_PWRC_ID_MASK U(0x00FFFFFF) + /* * TODO: Someday there will be a generic power controller api. At the moment * each platform has its own pwrc so just exporting functions is fine. */ ARM_INSTANTIATE_LOCK; +/* + * Core ID field is 24 bits wide and extracted from MPIDR. + * Bits[23:16] represent Affinity Level 2 + * Bits[15:8] represent Affinity Level 1 + * Bits[7:0] represent Affinity Level 0 + */ +static unsigned int fvp_pwrc_core_id(u_register_t mpidr) +{ + return (unsigned int)(mpidr & FVP_PWRC_ID_MASK); +} + unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr) { - return PSYSR_WK(fvp_pwrc_read_psysr(mpidr)); + unsigned int id = fvp_pwrc_core_id(mpidr); + + return PSYSR_WK(fvp_pwrc_read_psysr(id)); } unsigned int fvp_pwrc_read_psysr(u_register_t mpidr) { unsigned int rc; + unsigned int id = fvp_pwrc_core_id(mpidr); + arm_lock_get(); - mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); + mmio_write_32(PWRC_BASE + PSYSR_OFF, id); rc = mmio_read_32(PWRC_BASE + PSYSR_OFF); arm_lock_release(); return rc; @@ -33,38 +50,47 @@ void fvp_pwrc_write_pponr(u_register_t mpidr) { + unsigned int id = fvp_pwrc_core_id(mpidr); + arm_lock_get(); - mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr); + mmio_write_32(PWRC_BASE + PPONR_OFF, id); arm_lock_release(); } void fvp_pwrc_write_ppoffr(u_register_t mpidr) { + unsigned int id = fvp_pwrc_core_id(mpidr); + arm_lock_get(); - mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr); + mmio_write_32(PWRC_BASE + PPOFFR_OFF, id); arm_lock_release(); } void fvp_pwrc_set_wen(u_register_t mpidr) { + unsigned int id = fvp_pwrc_core_id(mpidr); + arm_lock_get(); mmio_write_32(PWRC_BASE + PWKUPR_OFF, - (unsigned int) (PWKUPR_WEN | mpidr)); + (unsigned int) (PWKUPR_WEN | id)); arm_lock_release(); } void fvp_pwrc_clr_wen(u_register_t mpidr) { + unsigned int id = fvp_pwrc_core_id(mpidr); + arm_lock_get(); - mmio_write_32(PWRC_BASE + PWKUPR_OFF, - (unsigned int) mpidr); + mmio_write_32(PWRC_BASE + PWKUPR_OFF, id); arm_lock_release(); } void fvp_pwrc_write_pcoffr(u_register_t mpidr) { + unsigned int id = fvp_pwrc_core_id(mpidr); + arm_lock_get(); - mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr); + mmio_write_32(PWRC_BASE + PCOFFR_OFF, id); arm_lock_release(); }
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index ca2a038..696bede 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -390,7 +390,7 @@ * This function assigns group for the interrupt identified by id. The group can * be any of GICV2_INTR_GROUP* ******************************************************************************/ -void gicv2_set_interrupt_type(unsigned int id, unsigned int type) +void gicv2_set_interrupt_group(unsigned int id, unsigned int group) { assert(driver_data != NULL); assert(driver_data->gicd_base != 0U); @@ -398,7 +398,7 @@ /* Serialize read-modify-write to Distributor registers */ spin_lock(&gic_lock); - switch (type) { + switch (group) { case GICV2_INTR_GROUP1: gicd_set_igroupr(driver_data->gicd_base, id); break;
diff --git a/drivers/arm/gic/v3/gic600_multichip.c b/drivers/arm/gic/v3/gic600_multichip.c index 7f0735d..a4786bb 100644 --- a/drivers/arm/gic/v3/gic600_multichip.c +++ b/drivers/arm/gic/v3/gic600_multichip.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * Copyright (c) 2022-2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -217,7 +217,7 @@ /* SPI IDs range check */ if (!(spi_id_min >= GIC600_SPI_ID_MIN) || - !(spi_id_max < GIC600_SPI_ID_MAX) || + !(spi_id_max <= GIC600_SPI_ID_MAX) || !(spi_id_min <= spi_id_max) || !((spi_id_max - spi_id_min + 1) % 32 == 0)) { ERROR("Invalid SPI IDs {%u, %u} passed for "
diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h index f6028ad..fd1cb57 100644 --- a/drivers/arm/gic/v3/gic600_multichip_private.h +++ b/drivers/arm/gic/v3/gic600_multichip_private.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,7 +39,7 @@ /* SPI interrupt id minimum and maximum range */ #define GIC600_SPI_ID_MIN 32 -#define GIC600_SPI_ID_MAX 960 +#define GIC600_SPI_ID_MAX 991 #define GIC700_SPI_ID_MIN 32 #define GIC700_SPI_ID_MAX 991
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c index 00bd7a1..b27debf 100644 --- a/drivers/arm/gic/v3/gicv3_helpers.c +++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -223,13 +223,16 @@ current_prop = &interrupt_props[i]; unsigned int intr_num = current_prop->intr_num; - uintptr_t multichip_gicd_base = gicv3_get_multichip_base(intr_num, gicd_base); + uintptr_t multichip_gicd_base; /* Skip SGI, (E)PPI and LPI interrupts */ if (!IS_SPI(intr_num)) { continue; } + multichip_gicd_base = + gicv3_get_multichip_base(intr_num, gicd_base); + /* Configure this interrupt as a secure interrupt */ gicd_clr_igroupr(multichip_gicd_base, intr_num);
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c index 2c74800..3c99517 100644 --- a/drivers/arm/gic/v3/gicv3_main.c +++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -421,16 +421,15 @@ } /******************************************************************************* - * This function returns the type of the interrupt id depending upon the group - * this interrupt has been configured under by the interrupt controller i.e. - * group0 or group1 Secure / Non Secure. The return value can be one of the - * following : + * This function returns the group that has been configured under by the + * interrupt controller for the given interrupt id i.e. either group0 or group1 + * Secure / Non Secure. The return value can be one of the following : * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure * interrupt. ******************************************************************************/ -unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) +unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num) { unsigned int igroup, grpmodr; uintptr_t gicr_base; @@ -1059,8 +1058,8 @@ * is used if the interrupt is SGI or (E)PPI, and programs the corresponding * Redistributor interface. The group can be any of GICV3_INTR_GROUP* ******************************************************************************/ -void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, - unsigned int type) +void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num, + unsigned int group) { bool igroup = false, grpmod = false; uintptr_t gicr_base; @@ -1071,7 +1070,7 @@ assert(proc_num < gicv3_driver_data->rdistif_num); assert(gicv3_driver_data->rdistif_base_addrs != NULL); - switch (type) { + switch (group) { case INTR_GROUP1S: igroup = false; grpmod = true;
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S index 9caeb0c..b7d1747 100644 --- a/drivers/arm/pl011/aarch32/pl011_console.S +++ b/drivers/arm/pl011/aarch32/pl011_console.S
@@ -116,7 +116,7 @@ mov r0, r4 pop {r4, lr} - finish_console_register pl011 putc=1, getc=1, flush=1 + finish_console_register pl011 putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: pop {r4, pc}
diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S index 861d2ed..8cb0122 100644 --- a/drivers/arm/pl011/aarch64/pl011_console.S +++ b/drivers/arm/pl011/aarch64/pl011_console.S
@@ -103,7 +103,7 @@ mov x0, x6 mov x30, x7 - finish_console_register pl011 putc=1, getc=1, flush=1 + finish_console_register pl011 putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c index 7a9cca8..608866c 100644 --- a/drivers/auth/auth_mod.c +++ b/drivers/auth/auth_mod.c
@@ -20,16 +20,11 @@ #include <lib/fconf/fconf_tbbr_getter.h> #include <plat/common/platform.h> +#include <tools_share/zero_oid.h> + /* ASN.1 tags */ #define ASN1_INTEGER 0x02 -#define return_if_error(rc) \ - do { \ - if (rc != 0) { \ - return rc; \ - } \ - } while (0) - #pragma weak plat_set_nv_ctr2 static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a, @@ -97,24 +92,37 @@ { void *data_ptr, *hash_der_ptr; unsigned int data_len, hash_der_len; - int rc = 0; + int rc; /* Get the hash from the parent image. This hash will be DER encoded * and contain the hash algorithm */ rc = auth_get_param(param->hash, img_desc->parent, &hash_der_ptr, &hash_der_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Get the data to be hashed from the current image */ rc = img_parser_get_auth_param(img_desc->img_type, param->data, img, img_len, &data_ptr, &data_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Ask the crypto module to verify this hash */ rc = crypto_mod_verify_hash(data_ptr, data_len, hash_der_ptr, hash_der_len); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } - return rc; + return 0; } /* @@ -148,25 +156,37 @@ const auth_img_desc_t *img_desc, void *img, unsigned int img_len) { - void *data_ptr, *pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr; - unsigned int data_len, pk_len, pk_plat_len, sig_len, sig_alg_len; + void *data_ptr, *pk_ptr, *cnv_pk_ptr, *pk_plat_ptr, *sig_ptr, *sig_alg_ptr, *pk_oid; + unsigned int data_len, pk_len, cnv_pk_len, pk_plat_len, sig_len, sig_alg_len; unsigned int flags = 0; - int rc = 0; + int rc; /* Get the data to be signed from current image */ rc = img_parser_get_auth_param(img_desc->img_type, param->data, img, img_len, &data_ptr, &data_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Get the signature from current image */ rc = img_parser_get_auth_param(img_desc->img_type, param->sig, img, img_len, &sig_ptr, &sig_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Get the signature algorithm from current image */ rc = img_parser_get_auth_param(img_desc->img_type, param->alg, img, img_len, &sig_alg_ptr, &sig_alg_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Get the public key from the parent. If there is no parent (NULL), * the certificate has been signed with the ROTPK, so we have to get @@ -174,7 +194,11 @@ if (img_desc->parent != NULL) { rc = auth_get_param(param->pk, img_desc->parent, &pk_ptr, &pk_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } } else { /* * Root certificates are signed with the ROTPK, so we have to @@ -182,7 +206,11 @@ */ rc = plat_get_rotpk_info(param->pk->cookie, &pk_plat_ptr, &pk_plat_len, &flags); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } assert(is_rotpk_flags_valid(flags)); @@ -190,7 +218,11 @@ rc = img_parser_get_auth_param(img_desc->img_type, param->pk, img, img_len, &pk_ptr, &pk_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* * Validate the certificate's key against the platform ROTPK. @@ -208,16 +240,24 @@ * platform may store the hash of a prefixed, * suffixed or modified pk */ - rc = crypto_mod_convert_pk(pk_ptr, pk_len, &pk_ptr, &pk_len); - return_if_error(rc); + rc = crypto_mod_convert_pk(pk_ptr, pk_len, &cnv_pk_ptr, &cnv_pk_len); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* * The hash of the certificate's public key must match * the hash of the ROTPK. */ - rc = crypto_mod_verify_hash(pk_ptr, pk_len, + rc = crypto_mod_verify_hash(cnv_pk_ptr, cnv_pk_len, pk_plat_ptr, pk_plat_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } } else { /* Platform supports full ROTPK */ if ((pk_len != pk_plat_len) || @@ -226,6 +266,26 @@ return -1; } } + + /* + * Set Zero-OID for ROTPK(subject key) as a the certificate + * does not hold Key-OID information for ROTPK. + */ + if (param->pk->cookie != NULL) { + pk_oid = param->pk->cookie; + } else { + pk_oid = ZERO_OID; + } + + /* + * Public key is verified at this stage, notify platform + * to measure and publish it. + */ + rc = plat_mboot_measure_key(pk_oid, pk_ptr, pk_len); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + } } /* Ask the crypto module to verify the signature */ @@ -233,8 +293,13 @@ sig_ptr, sig_len, sig_alg_ptr, sig_alg_len, pk_ptr, pk_len); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } - return rc; + return 0; } /* @@ -262,14 +327,18 @@ void *data_ptr = NULL; unsigned int data_len, len, i; unsigned int plat_nv_ctr; - int rc = 0; + int rc; bool is_trial_run = false; /* Get the counter value from current image. The AM expects the IPM * to return the counter value as a DER encoded integer */ rc = img_parser_get_auth_param(img_desc->img_type, param->cert_nv_ctr, img, img_len, &data_ptr, &data_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Parse the DER encoded integer */ assert(data_ptr); @@ -308,7 +377,11 @@ /* Get the counter from the platform */ rc = plat_get_nv_ctr(param->plat_nv_ctr->cookie, &plat_nv_ctr); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } if (*cert_nv_ctr < plat_nv_ctr) { /* Invalid NV-counter */ @@ -381,6 +454,7 @@ unsigned int img_len) { const auth_img_desc_t *img_desc = NULL; + const auth_param_type_desc_t *type_desc = NULL; const auth_method_desc_t *auth_method = NULL; void *param_ptr; unsigned int param_len; @@ -395,7 +469,11 @@ /* Ask the parser to check the image integrity */ rc = img_parser_check_integrity(img_desc->img_type, img_ptr, img_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Authenticate the image using the methods indicated in the image * descriptor. */ @@ -427,7 +505,11 @@ rc = 1; break; } - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } } /* @@ -437,7 +519,11 @@ if (need_nv_ctr_upgrade && sig_auth_done) { rc = plat_set_nv_ctr2(nv_ctr_param->plat_nv_ctr->cookie, img_desc, cert_nv_ctr); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } } /* Extract the parameters indicated in the image descriptor to @@ -452,7 +538,11 @@ rc = img_parser_get_auth_param(img_desc->img_type, img_desc->authenticated_data[i].type_desc, img_ptr, img_len, ¶m_ptr, ¶m_len); - return_if_error(rc); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + return rc; + } /* Check parameter size */ if (param_len > img_desc->authenticated_data[i].data.len) { @@ -462,6 +552,21 @@ /* Copy the parameter for later use */ memcpy((void *)img_desc->authenticated_data[i].data.ptr, (void *)param_ptr, param_len); + + /* + * If this is a public key then measure and publicise + * it. + */ + type_desc = img_desc->authenticated_data[i].type_desc; + if (type_desc->type == AUTH_PARAM_PUB_KEY) { + rc = plat_mboot_measure_key(type_desc->cookie, + param_ptr, + param_len); + if (rc != 0) { + VERBOSE("[TBB] %s():%d failed with error code %d.\n", + __func__, __LINE__, rc); + } + } } }
diff --git a/drivers/auth/cca/cot.c b/drivers/auth/cca/cot.c index e8f4d9c..2a03604 100644 --- a/drivers/auth/cca/cot.c +++ b/drivers/auth/cca/cot.c
@@ -42,8 +42,8 @@ /* * Parameter type descriptors. */ -static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( - AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID); +static auth_param_type_desc_t cca_nv_ctr = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_NV_CTR, CCA_FW_NVCOUNTER_OID); static auth_param_type_desc_t subject_pk = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_PUB_KEY, 0); static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC( @@ -69,6 +69,8 @@ AUTH_PARAM_HASH, RMM_HASH_OID); #ifdef IMAGE_BL2 +static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID); static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID); @@ -127,8 +129,8 @@ [1] = { .type = AUTH_METHOD_NV_CTR, .param.nv_ctr = { - .cert_nv_ctr = &trusted_nv_ctr, - .plat_nv_ctr = &trusted_nv_ctr + .cert_nv_ctr = &cca_nv_ctr, + .plat_nv_ctr = &cca_nv_ctr } } },
diff --git a/drivers/auth/cryptocell/712/cryptocell_crypto.c b/drivers/auth/cryptocell/712/cryptocell_crypto.c deleted file mode 100644 index bba13f8..0000000 --- a/drivers/auth/cryptocell/712/cryptocell_crypto.c +++ /dev/null
@@ -1,334 +0,0 @@ -/* - * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <stddef.h> -#include <string.h> - -#include <mbedtls/oid.h> -#include <mbedtls/x509.h> - -#include <arch_helpers.h> -#include <common/debug.h> -#include <drivers/arm/cryptocell/712/crypto_driver.h> -#include <drivers/arm/cryptocell/712/rsa.h> -#include <drivers/arm/cryptocell/712/sbrom_bsv_api.h> -#include <drivers/arm/cryptocell/712/secureboot_base_func.h> -#include <drivers/arm/cryptocell/712/secureboot_gen_defs.h> -#include <drivers/arm/cryptocell/712/util.h> -#include <drivers/auth/crypto_mod.h> -#include <drivers/auth/mbedtls/mbedtls_common.h> -#include <lib/utils.h> - -#include <platform_def.h> - -#define LIB_NAME "CryptoCell 712 SBROM" -#define RSA_SALT_LEN 32 -#define RSA_EXPONENT 65537 - -/* - * AlgorithmIdentifier ::= SEQUENCE { - * algorithm OBJECT IDENTIFIER, - * parameters ANY DEFINED BY algorithm OPTIONAL - * } - * - * SubjectPublicKeyInfo ::= SEQUENCE { - * algorithm AlgorithmIdentifier, - * subjectPublicKey BIT STRING - * } - * - * DigestInfo ::= SEQUENCE { - * digestAlgorithm AlgorithmIdentifier, - * digest OCTET STRING - * } - * - * RSASSA-PSS-params ::= SEQUENCE { - * hashAlgorithm [0] HashAlgorithm, - * maskGenAlgorithm [1] MaskGenAlgorithm, - * saltLength [2] INTEGER, - * trailerField [3] TrailerField DEFAULT trailerFieldBC - * } - */ - -/* - * Initialize the library and export the descriptor - */ -static void init(void) -{ - CCError_t ret; - uint32_t lcs; - - /* Initialize CC SBROM */ - ret = CC_BsvSbromInit((uintptr_t)PLAT_CRYPTOCELL_BASE); - if (ret != CC_OK) { - ERROR("CryptoCell CC_BsvSbromInit() error %x\n", ret); - panic(); - } - - /* Initialize lifecycle state */ - ret = CC_BsvLcsGetAndInit((uintptr_t)PLAT_CRYPTOCELL_BASE, &lcs); - if (ret != CC_OK) { - ERROR("CryptoCell CC_BsvLcsGetAndInit() error %x\n", ret); - panic(); - } - - /* If the lifecyclestate is `SD`, then stop further execution */ - if (lcs == CC_BSV_SECURITY_DISABLED_LCS) { - ERROR("CryptoCell LCS is security-disabled\n"); - panic(); - } -} - -/* - * Verify a signature. - * - * Parameters are passed using the DER encoding format following the ASN.1 - * structures detailed above. - */ -static int verify_signature(void *data_ptr, unsigned int data_len, - void *sig_ptr, unsigned int sig_len, - void *sig_alg, unsigned int sig_alg_len, - void *pk_ptr, unsigned int pk_len) -{ - CCError_t error; - CCSbNParams_t pk; - CCSbSignature_t signature; - int rc, exp, expected_salt_len; - mbedtls_asn1_buf sig_oid, alg_oid, params; - mbedtls_md_type_t md_alg, mgf1_hash_id; - mbedtls_pk_type_t pk_alg; - size_t len; - uint8_t *p, *end; - /* Temp buf to store the public key modulo (N) in LE format */ - uint32_t RevN[SB_RSA_MOD_SIZE_IN_WORDS]; - - /* Verify the signature algorithm */ - /* Get pointers to signature OID and parameters */ - p = sig_alg; - end = p + sig_alg_len; - rc = mbedtls_asn1_get_alg(&p, end, &sig_oid, ¶ms); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Get the actual signature algorithm (MD + PK) */ - rc = mbedtls_oid_get_sig_alg(&sig_oid, &md_alg, &pk_alg); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - /* The CryptoCell only supports RSASSA-PSS signature */ - if ((pk_alg != MBEDTLS_PK_RSASSA_PSS) || (md_alg != MBEDTLS_MD_NONE)) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Verify the RSASSA-PSS params */ - /* The trailer field is verified to be 0xBC internally by this API */ - rc = mbedtls_x509_get_rsassa_pss_params(¶ms, &md_alg, - &mgf1_hash_id, - &expected_salt_len); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - /* The CryptoCell only supports SHA256 as hash algorithm */ - if ((md_alg != MBEDTLS_MD_SHA256) || (mgf1_hash_id != MBEDTLS_MD_SHA256)) { - return CRYPTO_ERR_SIGNATURE; - } - - if (expected_salt_len != RSA_SALT_LEN) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Parse the public key */ - p = pk_ptr; - end = p + pk_len; - rc = mbedtls_asn1_get_tag(&p, end, &len, - MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - end = p + len; - rc = mbedtls_asn1_get_alg_null(&p, end, &alg_oid); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (mbedtls_oid_get_pk_alg(&alg_oid, &pk_alg) != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (pk_alg != MBEDTLS_PK_RSA) { - return CRYPTO_ERR_SIGNATURE; - } - - rc = mbedtls_asn1_get_bitstring_null(&p, end, &len); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - rc = mbedtls_asn1_get_tag(&p, end, &len, - MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_INTEGER); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (*p == 0) { - p++; len--; - } - - if (len != RSA_MOD_SIZE_IN_BYTES || ((p + len) > end)) { - return CRYPTO_ERR_SIGNATURE; - } - - /* - * The CCSbVerifySignature() API expects N and Np in BE format and - * the signature in LE format. Copy N from certificate. - */ - memcpy(pk.N, p, RSA_MOD_SIZE_IN_BYTES); - - /* Verify the RSA exponent */ - p += len; - rc = mbedtls_asn1_get_int(&p, end, &exp); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (exp != RSA_EXPONENT) { - return CRYPTO_ERR_SIGNATURE; - } - - /* - * Calculate the Np (Barrett n' value). The RSA_CalcNp() API expects - * N in LE format. Hence reverse N into a temporary buffer `RevN`. - */ - UTIL_ReverseMemCopy((uint8_t *)RevN, (uint8_t *)pk.N, sizeof(RevN)); - - RSA_CalcNp((uintptr_t)PLAT_CRYPTOCELL_BASE, RevN, pk.Np); - - /* Np is in LE format. Reverse it to BE */ - UTIL_ReverseBuff((uint8_t *)pk.Np, sizeof(pk.Np)); - - /* Get the signature (bitstring) */ - p = sig_ptr; - end = p + sig_len; - rc = mbedtls_asn1_get_bitstring_null(&p, end, &len); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (len != RSA_MOD_SIZE_IN_BYTES || ((p + len) > end)) { - return CRYPTO_ERR_SIGNATURE; - } - - /* - * The signature is BE format. Convert it to LE before calling - * CCSbVerifySignature(). - */ - UTIL_ReverseMemCopy((uint8_t *)signature.sig, p, RSA_MOD_SIZE_IN_BYTES); - - /* - * CryptoCell utilises DMA internally to transfer data. Flush the data - * from caches. - */ - flush_dcache_range((uintptr_t)data_ptr, data_len); - - /* Verify the signature */ - error = CCSbVerifySignature((uintptr_t)PLAT_CRYPTOCELL_BASE, - (uint32_t *)data_ptr, &pk, &signature, - data_len, RSA_PSS); - if (error != CC_OK) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Signature verification success */ - return CRYPTO_SUCCESS; -} - -/* - * Match a hash - * - * Digest info is passed in DER format following the ASN.1 structure detailed - * above. - */ -static int verify_hash(void *data_ptr, unsigned int data_len, - void *digest_info_ptr, unsigned int digest_info_len) -{ - mbedtls_asn1_buf hash_oid, params; - mbedtls_md_type_t md_alg; - uint8_t *p, *end, *hash; - CCHashResult_t pubKeyHash; - size_t len; - int rc; - CCError_t error; - - /* Digest info should be an MBEDTLS_ASN1_SEQUENCE */ - p = digest_info_ptr; - end = p + digest_info_len; - rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | - MBEDTLS_ASN1_SEQUENCE); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - /* Get the hash algorithm */ - rc = mbedtls_asn1_get_alg(&p, end, &hash_oid, ¶ms); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - rc = mbedtls_oid_get_md_alg(&hash_oid, &md_alg); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - /* Verify that hash algorithm is SHA256 */ - if (md_alg != MBEDTLS_MD_SHA256) { - return CRYPTO_ERR_HASH; - } - - /* Hash should be octet string type */ - rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OCTET_STRING); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - /* Length of hash must match the algorithm's size */ - if (len != HASH_RESULT_SIZE_IN_BYTES) { - return CRYPTO_ERR_HASH; - } - - /* - * CryptoCell utilises DMA internally to transfer data. Flush the data - * from caches. - */ - flush_dcache_range((uintptr_t)data_ptr, data_len); - - hash = p; - error = SBROM_CryptoHash((uintptr_t)PLAT_CRYPTOCELL_BASE, - (uintptr_t)data_ptr, data_len, pubKeyHash); - if (error != CC_OK) { - return CRYPTO_ERR_HASH; - } - - rc = memcmp(pubKeyHash, hash, HASH_RESULT_SIZE_IN_BYTES); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - return CRYPTO_SUCCESS; -} - -/* - * Register crypto library descriptor - */ -REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, NULL, NULL); -
diff --git a/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c b/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c deleted file mode 100644 index 53d77db..0000000 --- a/drivers/auth/cryptocell/712/cryptocell_plat_helpers.c +++ /dev/null
@@ -1,113 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <stddef.h> -#include <string.h> - -#include <platform_def.h> - -#include <plat/common/platform.h> -#include <tools_share/tbbr_oid.h> - -#include <common/debug.h> -#include <drivers/arm/cryptocell/712/sbrom_bsv_api.h> -#include <drivers/arm/cryptocell/712/nvm.h> -#include <drivers/arm/cryptocell/712/nvm_otp.h> - -/* - * Return the ROTPK hash - * - * dst: buffer into which the ROTPK hash will be copied into - * len: length of the provided buffer, which must be at least enough for a - * SHA256 hash - * flags: a pointer to integer that will be set to indicate the ROTPK status - * - * Return: 0 = success, Otherwise = error - */ -int cc_get_rotpk_hash(unsigned char *dst, unsigned int len, unsigned int *flags) -{ - CCError_t error; - uint32_t lcs; - - assert(dst != NULL); - assert(len >= HASH_RESULT_SIZE_IN_WORDS); - assert(flags != NULL); - - error = NVM_GetLCS(PLAT_CRYPTOCELL_BASE, &lcs); - if (error != CC_OK) - return 1; - - /* If the lifecycle state is `SD`, return failure */ - if (lcs == CC_BSV_SECURITY_DISABLED_LCS) - return 1; - - /* - * If the lifecycle state is `CM` or `DM`, ROTPK shouldn't be verified. - * Return success after setting ROTPK_NOT_DEPLOYED flag - */ - if ((lcs == CC_BSV_CHIP_MANUFACTURE_LCS) || - (lcs == CC_BSV_DEVICE_MANUFACTURE_LCS)) { - *flags = ROTPK_NOT_DEPLOYED; - return 0; - } - - /* Copy the DER header */ - error = NVM_ReadHASHPubKey(PLAT_CRYPTOCELL_BASE, - CC_SB_HASH_BOOT_KEY_256B, - (uint32_t *)dst, HASH_RESULT_SIZE_IN_WORDS); - if (error != CC_OK) - return 1; - - *flags = ROTPK_IS_HASH; - return 0; -} - -/* - * Return the non-volatile counter value stored in the platform. The cookie - * specifies the OID of the counter in the certificate. - * - * Return: 0 = success, Otherwise = error - */ -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - CCError_t error = CC_FAIL; - - if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = NVM_GetSwVersion(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_COUNTER1, nv_ctr); - } else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = NVM_GetSwVersion(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_COUNTER2, nv_ctr); - } - - return (error != CC_OK); -} - -/* - * Store a new non-volatile counter value in the counter specified by the OID - * in the cookie. This function is not expected to be called if the Lifecycle - * state is RMA as the values in the certificate are expected to always match - * the nvcounter values. But if called when the LCS is RMA, the underlying - * helper functions will return success but without updating the counter. - * - * Return: 0 = success, Otherwise = error - */ -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - CCError_t error = CC_FAIL; - - if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = NVM_SetSwVersion(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_COUNTER1, nv_ctr); - } else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = NVM_SetSwVersion(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_COUNTER2, nv_ctr); - } - - return (error != CC_OK); -} -
diff --git a/drivers/auth/cryptocell/713/cryptocell_crypto.c b/drivers/auth/cryptocell/713/cryptocell_crypto.c deleted file mode 100644 index 6601b3a..0000000 --- a/drivers/auth/cryptocell/713/cryptocell_crypto.c +++ /dev/null
@@ -1,305 +0,0 @@ -/* - * Copyright (c) 2017-2023 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <stddef.h> -#include <string.h> - -#include <mbedtls/oid.h> -#include <mbedtls/x509.h> - -#include <drivers/arm/cryptocell/713/bsv_api.h> -#include <drivers/arm/cryptocell/713/bsv_crypto_asym_api.h> -#include <drivers/auth/crypto_mod.h> - -#include <platform_def.h> - -#define LIB_NAME "CryptoCell 713 SBROM" -#define RSA_SALT_LEN 32 -#define RSA_EXPONENT 65537 - -/* - * AlgorithmIdentifier ::= SEQUENCE { - * algorithm OBJECT IDENTIFIER, - * parameters ANY DEFINED BY algorithm OPTIONAL - * } - * - * SubjectPublicKeyInfo ::= SEQUENCE { - * algorithm AlgorithmIdentifier, - * subjectPublicKey BIT STRING - * } - * - * DigestInfo ::= SEQUENCE { - * digestAlgorithm AlgorithmIdentifier, - * digest OCTET STRING - * } - * - * RSASSA-PSS-params ::= SEQUENCE { - * hashAlgorithm [0] HashAlgorithm, - * maskGenAlgorithm [1] MaskGenAlgorithm, - * saltLength [2] INTEGER, - * trailerField [3] TrailerField DEFAULT trailerFieldBC - * } - */ - -/* - * Initialize the library and export the descriptor - */ -static void init(void) -{ - CCError_t ret; - uint32_t lcs; - - /* Initialize CC SBROM */ - ret = CC_BsvInit((uintptr_t)PLAT_CRYPTOCELL_BASE); - if (ret != CC_OK) { - ERROR("CryptoCell CC_BsvInit() error %x\n", ret); - panic(); - } - - /* Initialize lifecycle state */ - ret = CC_BsvGetAndInitLcs((uintptr_t)PLAT_CRYPTOCELL_BASE, &lcs); - if (ret != CC_OK) { - ERROR("CryptoCell CC_BsvGetAndInitLcs() error %x\n", ret); - panic(); - } -} - -/* - * Verify a signature. - * - * Parameters are passed using the DER encoding format following the ASN.1 - * structures detailed above. - */ -static int verify_signature(void *data_ptr, unsigned int data_len, - void *sig_ptr, unsigned int sig_len, - void *sig_alg, unsigned int sig_alg_len, - void *pk_ptr, unsigned int pk_len) -{ - CCError_t error; - CCBsvNBuff_t NBuff; - CCBsvSignature_t signature; - int rc, exp, expected_salt_len; - mbedtls_asn1_buf sig_oid, alg_oid, params; - mbedtls_md_type_t md_alg, mgf1_hash_id; - mbedtls_pk_type_t pk_alg; - - size_t len; - uint8_t *p, *end; - CCHashResult_t digest; - CCBool_t is_verified; - /* This is a rather large array, we don't want it on stack */ - static uint32_t workspace[BSV_RSA_WORKSPACE_MIN_SIZE]; - - /* Verify the signature algorithm */ - /* Get pointers to signature OID and parameters */ - p = sig_alg; - end = p + sig_alg_len; - rc = mbedtls_asn1_get_alg(&p, end, &sig_oid, ¶ms); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Get the actual signature algorithm (MD + PK) */ - rc = mbedtls_oid_get_sig_alg(&sig_oid, &md_alg, &pk_alg); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - /* The CryptoCell only supports RSASSA-PSS signature */ - if (pk_alg != MBEDTLS_PK_RSASSA_PSS || md_alg != MBEDTLS_MD_NONE) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Verify the RSASSA-PSS params */ - /* The trailer field is verified to be 0xBC internally by this API */ - rc = mbedtls_x509_get_rsassa_pss_params(¶ms, &md_alg, - &mgf1_hash_id, - &expected_salt_len); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - /* The CryptoCell only supports SHA256 as hash algorithm */ - if (md_alg != MBEDTLS_MD_SHA256 || - mgf1_hash_id != MBEDTLS_MD_SHA256) { - return CRYPTO_ERR_SIGNATURE; - } - - if (expected_salt_len != RSA_SALT_LEN) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Parse the public key */ - p = pk_ptr; - end = p + pk_len; - rc = mbedtls_asn1_get_tag(&p, end, &len, - MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - end = p + len; - rc = mbedtls_asn1_get_alg_null(&p, end, &alg_oid); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (mbedtls_oid_get_pk_alg(&alg_oid, &pk_alg) != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (pk_alg != MBEDTLS_PK_RSA) { - return CRYPTO_ERR_SIGNATURE; - } - - rc = mbedtls_asn1_get_bitstring_null(&p, end, &len); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - rc = mbedtls_asn1_get_tag(&p, end, &len, - MBEDTLS_ASN1_CONSTRUCTED | - MBEDTLS_ASN1_SEQUENCE); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_INTEGER); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (*p == 0) { - p++; len--; - } - if (len != BSV_CERT_RSA_KEY_SIZE_IN_BYTES || ((p + len) > end)) { - return CRYPTO_ERR_SIGNATURE; - } - - /* - * Copy N from certificate. - */ - memcpy(NBuff, p, BSV_CERT_RSA_KEY_SIZE_IN_BYTES); - - /* Verify the RSA exponent */ - p += len; - rc = mbedtls_asn1_get_int(&p, end, &exp); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (exp != RSA_EXPONENT) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Get the signature (bitstring) */ - p = sig_ptr; - end = p + sig_len; - rc = mbedtls_asn1_get_bitstring_null(&p, end, &len); - if (rc != 0) { - return CRYPTO_ERR_SIGNATURE; - } - - if (len != BSV_CERT_RSA_KEY_SIZE_IN_BYTES || ((p + len) > end)) { - return CRYPTO_ERR_SIGNATURE; - } - - /* - * Copy the signature (in BE format) - */ - memcpy((uint8_t *)signature, p, BSV_CERT_RSA_KEY_SIZE_IN_BYTES); - - error = CC_BsvSha256((uintptr_t)PLAT_CRYPTOCELL_BASE, - data_ptr, data_len, digest); - if (error != CC_OK) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Verify the signature */ - error = CC_BsvRsaPssVerify((uintptr_t)PLAT_CRYPTOCELL_BASE, NBuff, - NULL, signature, digest, workspace, - BSV_RSA_WORKSPACE_MIN_SIZE, &is_verified); - if ((error != CC_OK) || (is_verified != CC_TRUE)) { - return CRYPTO_ERR_SIGNATURE; - } - - /* Signature verification success */ - return CRYPTO_SUCCESS; -} - -/* - * Match a hash - * - * Digest info is passed in DER format following the ASN.1 structure detailed - * above. - */ -static int verify_hash(void *data_ptr, unsigned int data_len, - void *digest_info_ptr, unsigned int digest_info_len) -{ - mbedtls_asn1_buf hash_oid, params; - mbedtls_md_type_t md_alg; - uint8_t *p, *end, *hash; - CCHashResult_t pubKeyHash; - size_t len; - int rc; - CCError_t error; - - /* Digest info should be an MBEDTLS_ASN1_SEQUENCE */ - p = digest_info_ptr; - end = p + digest_info_len; - rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | - MBEDTLS_ASN1_SEQUENCE); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - /* Get the hash algorithm */ - rc = mbedtls_asn1_get_alg(&p, end, &hash_oid, ¶ms); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - rc = mbedtls_oid_get_md_alg(&hash_oid, &md_alg); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - /* Verify that hash algorithm is SHA256 */ - if (md_alg != MBEDTLS_MD_SHA256) { - return CRYPTO_ERR_HASH; - } - - /* Hash should be octet string type */ - rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OCTET_STRING); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - /* Length of hash must match the algorithm's size */ - if (len != HASH_RESULT_SIZE_IN_BYTES) { - return CRYPTO_ERR_HASH; - } - - hash = p; - error = CC_BsvSha256((uintptr_t)PLAT_CRYPTOCELL_BASE, data_ptr, - data_len, pubKeyHash); - if (error != CC_OK) { - return CRYPTO_ERR_HASH; - } - - rc = memcmp(pubKeyHash, hash, HASH_RESULT_SIZE_IN_BYTES); - if (rc != 0) { - return CRYPTO_ERR_HASH; - } - - return CRYPTO_SUCCESS; -} - -/* - * Register crypto library descriptor - */ -REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, NULL, NULL);
diff --git a/drivers/auth/cryptocell/713/cryptocell_plat_helpers.c b/drivers/auth/cryptocell/713/cryptocell_plat_helpers.c deleted file mode 100644 index 17e1280..0000000 --- a/drivers/auth/cryptocell/713/cryptocell_plat_helpers.c +++ /dev/null
@@ -1,109 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <stddef.h> -#include <string.h> - -#include <plat/common/platform.h> -#include <tools_share/tbbr_oid.h> - -#include <lib/libc/endian.h> -#include <drivers/arm/cryptocell/713/bsv_api.h> -#include <drivers/arm/cryptocell/713/bsv_error.h> - -/* - * Return the ROTPK hash - * - * Return: 0 = success, Otherwise = error - */ -int cc_get_rotpk_hash(unsigned char *dst, unsigned int len, unsigned int *flags) -{ - CCError_t error; - uint32_t lcs; - int i; - uint32_t *key = (uint32_t *)dst; - - assert(dst != NULL); - assert(len >= HASH_RESULT_SIZE_IN_WORDS); - assert(flags != NULL); - - error = CC_BsvLcsGet(PLAT_CRYPTOCELL_BASE, &lcs); - if (error != CC_OK) - return 1; - - if ((lcs == CC_BSV_CHIP_MANUFACTURE_LCS) || (lcs == CC_BSV_RMA_LCS)) { - *flags = ROTPK_NOT_DEPLOYED; - return 0; - } - - error = CC_BsvPubKeyHashGet(PLAT_CRYPTOCELL_BASE, - CC_SB_HASH_BOOT_KEY_256B, - key, HASH_RESULT_SIZE_IN_WORDS); - - if (error == CC_BSV_HASH_NOT_PROGRAMMED_ERR) { - *flags = ROTPK_NOT_DEPLOYED; - return 0; - } - - if (error == CC_OK) { - - /* Keys are stored in OTP in little-endian format */ - for (i = 0; i < HASH_RESULT_SIZE_IN_WORDS; i++) - key[i] = le32toh(key[i]); - - *flags = ROTPK_IS_HASH; - return 0; - } - - return 1; -} - -/* - * Return the non-volatile counter value stored in the platform. The cookie - * specifies the OID of the counter in the certificate. - * - * Return: 0 = success, Otherwise = error - */ -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - CCError_t error = CC_FAIL; - - if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = CC_BsvSwVersionGet(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_TRUSTED, nv_ctr); - } else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = CC_BsvSwVersionGet(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_NON_TRUSTED, nv_ctr); - } - - return (error != CC_OK); -} - -/* - * Store a new non-volatile counter value in the counter specified by the OID - * in the cookie. This function is not expected to be called if the Lifecycle - * state is RMA as the values in the certificate are expected to always match - * the nvcounter values. But if called when the LCS is RMA, the underlying - * helper functions will return success but without updating the counter. - * - * Return: 0 = success, Otherwise = error - */ -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - CCError_t error = CC_FAIL; - - if (strcmp(cookie, TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = CC_BsvSwVersionSet(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_TRUSTED, nv_ctr); - } else if (strcmp(cookie, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - error = CC_BsvSwVersionSet(PLAT_CRYPTOCELL_BASE, - CC_SW_VERSION_NON_TRUSTED, nv_ctr); - } - - return (error != CC_OK); -} -
diff --git a/drivers/auth/cryptocell/cryptocell_crypto.mk b/drivers/auth/cryptocell/cryptocell_crypto.mk deleted file mode 100644 index db39047..0000000 --- a/drivers/auth/cryptocell/cryptocell_crypto.mk +++ /dev/null
@@ -1,40 +0,0 @@ -# -# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. -# -# SPDX-License-Identifier: BSD-3-Clause -# - -include drivers/auth/mbedtls/mbedtls_common.mk - -# The algorithm is RSA when using Cryptocell crypto driver -TF_MBEDTLS_KEY_ALG_ID := TF_MBEDTLS_RSA - -# Needs to be set to drive mbed TLS configuration correctly -$(eval $(call add_define,TF_MBEDTLS_KEY_ALG_ID)) - -$(eval $(call add_define,KEY_SIZE)) - -# CCSBROM_LIB_PATH must be set to the Cryptocell SBROM library path -ifeq (${CCSBROM_LIB_PATH},) - $(error Error: CCSBROM_LIB_PATH not set) -endif - -CRYPTOCELL_VERSION ?= 712 -ifeq (${CRYPTOCELL_VERSION},712) - CCSBROM_LIB_FILENAME := cc_712sbromx509 -else ifeq (${CRYPTOCELL_VERSION},713) - CCSBROM_LIB_FILENAME := cc_713bsv -else - $(error Error: CRYPTOCELL_VERSION set to invalid version) -endif - -CRYPTOCELL_SRC_DIR := drivers/auth/cryptocell/${CRYPTOCELL_VERSION}/ - -CRYPTOCELL_SOURCES := ${CRYPTOCELL_SRC_DIR}/cryptocell_crypto.c \ - ${CRYPTOCELL_SRC_DIR}/cryptocell_plat_helpers.c - -TF_LDFLAGS += -L$(CCSBROM_LIB_PATH) -LDLIBS += -l$(CCSBROM_LIB_FILENAME) - -BL1_SOURCES += ${CRYPTOCELL_SOURCES} -BL2_SOURCES += ${CRYPTOCELL_SOURCES}
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk index 79c4512..a2c6430 100644 --- a/drivers/auth/mbedtls/mbedtls_common.mk +++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -21,9 +21,14 @@ # Specify mbed TLS configuration file ifeq (${MBEDTLS_MAJOR}, 2) - MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/mbedtls_config-2.h>" + $(info Deprecation Notice: Please migrate to Mbedtls version 3.x (refer to TF-A documentation for the exact version number)) + MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/mbedtls_config-2.h>" else ifeq (${MBEDTLS_MAJOR}, 3) - MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/mbedtls_config-3.h>" + ifeq (${PSA_CRYPTO},1) + MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/psa_mbedtls_config.h>" + else + MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/mbedtls_config-3.h>" + endif endif $(eval $(call add_define,MBEDTLS_CONFIG_FILE)) @@ -77,6 +82,18 @@ LIBMBEDTLS_CFLAGS += -Wno-error=redundant-decls endif +ifeq (${PSA_CRYPTO},1) +LIBMBEDTLS_SRCS += $(addprefix ${MBEDTLS_DIR}/library/, \ + psa_crypto.c \ + psa_crypto_client.c \ + psa_crypto_driver_wrappers.c \ + psa_crypto_hash.c \ + psa_crypto_rsa.c \ + psa_crypto_ecp.c \ + psa_crypto_slot_management.c \ + ) +endif + # The platform may define the variable 'TF_MBEDTLS_KEY_ALG' to select the key # algorithm to use. If the variable is not defined, select it based on # algorithm used for key generation `KEY_ALG`. If `KEY_ALG` is not defined, @@ -91,11 +108,21 @@ ifeq (${TF_MBEDTLS_KEY_SIZE},) ifneq ($(findstring rsa,${TF_MBEDTLS_KEY_ALG}),) - ifeq (${KEY_SIZE},) + ifeq (${KEY_SIZE},) TF_MBEDTLS_KEY_SIZE := 2048 - else + else ifneq ($(filter $(KEY_SIZE), 1024 2048 3072 4096),) TF_MBEDTLS_KEY_SIZE := ${KEY_SIZE} - endif + else + $(error "Invalid value for KEY_SIZE: ${KEY_SIZE}") + endif + else ifneq ($(findstring ecdsa,${TF_MBEDTLS_KEY_ALG}),) + ifeq (${KEY_SIZE},) + TF_MBEDTLS_KEY_SIZE := 256 + else ifneq ($(filter $(KEY_SIZE), 256 384),) + TF_MBEDTLS_KEY_SIZE := ${KEY_SIZE} + else + $(error "Invalid value for KEY_SIZE: ${KEY_SIZE}") + endif endif endif
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c index 6d6364f..230cec9 100644 --- a/drivers/auth/mbedtls/mbedtls_crypto.c +++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -172,17 +172,20 @@ int rc; /* - * Digest info should be an MBEDTLS_ASN1_SEQUENCE - * and consume all bytes. + * Digest info should be an MBEDTLS_ASN1_SEQUENCE, but padding after + * it is allowed. This is necessary to support multiple hash + * algorithms. */ p = (unsigned char *)digest_info_ptr; end = p + digest_info_len; rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE); - if (rc != 0 || ((size_t)(end - p) != len)) { + if (rc != 0) { return CRYPTO_ERR_HASH; } + end = p + len; + /* Get the hash algorithm */ rc = mbedtls_asn1_get_alg(&p, end, &hash_oid, ¶ms); if (rc != 0) {
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.mk b/drivers/auth/mbedtls/mbedtls_crypto.mk index 2a9fbbf..bd36730 100644 --- a/drivers/auth/mbedtls/mbedtls_crypto.mk +++ b/drivers/auth/mbedtls/mbedtls_crypto.mk
@@ -1,11 +1,16 @@ # -# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # include drivers/auth/mbedtls/mbedtls_common.mk -MBEDTLS_SOURCES += drivers/auth/mbedtls/mbedtls_crypto.c - - +ifeq (${PSA_CRYPTO},1) + # Some of the PSA functions are declared in multiple header files + # that triggers this warning. + TF_CFLAGS += -Wno-error=redundant-decls + MBEDTLS_SOURCES += drivers/auth/mbedtls/mbedtls_psa_crypto.c +else + MBEDTLS_SOURCES += drivers/auth/mbedtls/mbedtls_crypto.c +endif
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c new file mode 100644 index 0000000..5891acf --- /dev/null +++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -0,0 +1,696 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stddef.h> +#include <string.h> + +/* mbed TLS headers */ +#include <mbedtls/gcm.h> +#include <mbedtls/md.h> +#include <mbedtls/memory_buffer_alloc.h> +#include <mbedtls/oid.h> +#include <mbedtls/platform.h> +#include <mbedtls/version.h> +#include <mbedtls/x509.h> +#include <psa/crypto.h> +#include <psa/crypto_platform.h> +#include <psa/crypto_types.h> +#include <psa/crypto_values.h> + +#include <common/debug.h> +#include <drivers/auth/crypto_mod.h> +#include <drivers/auth/mbedtls/mbedtls_common.h> +#include <plat/common/platform.h> + +#define LIB_NAME "mbed TLS PSA" + +/* Maximum length of R_S pair in the ECDSA signature in bytes */ +#define MAX_ECDSA_R_S_PAIR_LEN 64U + +/* Size of ASN.1 length and tag in bytes*/ +#define SIZE_OF_ASN1_LEN 1U +#define SIZE_OF_ASN1_TAG 1U + +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC +/* + * CRYPTO_MD_MAX_SIZE value is as per current stronger algorithm available + * so make sure that mbed TLS MD maximum size must be lesser than this. + */ +CASSERT(CRYPTO_MD_MAX_SIZE >= MBEDTLS_MD_MAX_SIZE, + assert_mbedtls_md_size_overflow); + +#endif /* + * CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + * CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC + */ + +static inline psa_algorithm_t mbedtls_md_psa_alg_from_type( + mbedtls_md_type_t md_type) +{ + assert((md_type == MBEDTLS_MD_SHA256) || + (md_type == MBEDTLS_MD_SHA384) || + (md_type == MBEDTLS_MD_SHA512)); + + return PSA_ALG_CATEGORY_HASH | (psa_algorithm_t) (md_type + 0x5); +} + +/* + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ + +/* + * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * mbedTLS config option) so we need to provide an implementation of + * mbedtls_psa_external_get_random(). Provide a fake one, since we do not + * actually have any external RNG and TF-A itself doesn't engage in + * cryptographic operations that demands randomness. + */ +psa_status_t mbedtls_psa_external_get_random( + mbedtls_psa_external_random_context_t *context, + uint8_t *output, size_t output_size, + size_t *output_length) +{ + return PSA_ERROR_INSUFFICIENT_ENTROPY; +} + +/* + * Initialize the library and export the descriptor + */ +static void init(void) +{ + /* Initialize mbed TLS */ + mbedtls_init(); + + /* Initialise PSA mbedTLS */ + psa_status_t status = psa_crypto_init(); + + if (status != PSA_SUCCESS) { + ERROR("Failed to initialize %s crypto (%d).\n", LIB_NAME, status); + panic(); + } + + INFO("PSA crypto initialized successfully!\n"); +} + +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC + +static void construct_psa_key_alg_and_type(mbedtls_pk_type_t pk_alg, + mbedtls_md_type_t md_alg, + psa_ecc_family_t psa_ecc_family, + psa_algorithm_t *psa_alg, + psa_key_type_t *psa_key_type) +{ + psa_algorithm_t psa_md_alg = mbedtls_md_psa_alg_from_type(md_alg); + + switch (pk_alg) { + case MBEDTLS_PK_RSASSA_PSS: + *psa_alg = PSA_ALG_RSA_PSS(psa_md_alg); + *psa_key_type = PSA_KEY_TYPE_RSA_PUBLIC_KEY; + break; + case MBEDTLS_PK_ECDSA: + *psa_alg = PSA_ALG_ECDSA(psa_md_alg); + *psa_key_type = PSA_KEY_TYPE_ECC_PUBLIC_KEY(psa_ecc_family); + break; + default: + *psa_alg = PSA_ALG_NONE; + *psa_key_type = PSA_KEY_TYPE_NONE; + break; + } +} + + +#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \ +TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA + +/* + * This is a helper function to detect padding byte (if the MSB bit of the + * first data byte is set to 1, for example 0x80) and on detection, ignore the + * padded byte(0x00) and increase the buffer pointer beyond padded byte and + * decrease the length of the buffer by 1. + * + * On Success returns 0, error otherwise. + **/ +static inline int ignore_asn1_int_padding_byte(unsigned char **buf_start, + size_t *buf_len) +{ + unsigned char *local_buf = *buf_start; + + /* Check for negative number */ + if ((local_buf[0] & 0x80U) != 0U) { + return -1; + } + + if ((local_buf[0] == 0U) && (local_buf[1] > 0x7FU) && + (*buf_len > 1U)) { + *buf_start = &local_buf[1]; + (*buf_len)--; + } + + return 0; +} + +/* + * This is a helper function that gets a pointer to the encoded ECDSA publicKey + * and its length (as per RFC5280) and returns corresponding decoded publicKey + * and its length. As well, it retrieves the family of ECC key in the PSA + * format. + * + * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure, + * otherwise success(0). + **/ +static int get_ecdsa_pkinfo_from_asn1(unsigned char **pk_start, + unsigned int *pk_len, + psa_ecc_family_t *psa_ecc_family) +{ + mbedtls_asn1_buf alg_oid, alg_params; + mbedtls_ecp_group_id grp_id; + int rc; + unsigned char *pk_end; + size_t len; + size_t curve_bits; + unsigned char *pk_ptr = *pk_start; + + pk_end = pk_ptr + *pk_len; + rc = mbedtls_asn1_get_tag(&pk_ptr, pk_end, &len, + MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + pk_end = pk_ptr + len; + rc = mbedtls_asn1_get_alg(&pk_ptr, pk_end, &alg_oid, &alg_params); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + if (alg_params.tag == MBEDTLS_ASN1_OID) { + if (mbedtls_oid_get_ec_grp(&alg_params, &grp_id) != 0) { + return CRYPTO_ERR_SIGNATURE; + } + *psa_ecc_family = mbedtls_ecc_group_to_psa(grp_id, + &curve_bits); + } else { + return CRYPTO_ERR_SIGNATURE; + } + + pk_end = pk_ptr + len - (alg_oid.len + alg_params.len + + 2 * (SIZE_OF_ASN1_LEN + SIZE_OF_ASN1_TAG)); + rc = mbedtls_asn1_get_bitstring_null(&pk_ptr, pk_end, &len); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + *pk_start = pk_ptr; + *pk_len = len; + + return rc; +} + +/* + * Ecdsa-Sig-Value ::= SEQUENCE { + * r INTEGER, + * s INTEGER + * } + * + * This helper function that gets a pointer to the encoded ECDSA signature and + * its length (as per RFC5280) and returns corresponding decoded signature + * (R_S pair) and its size. + * + * This function returns error(CRYPTO_ERR_SIGNATURE) on ASN.1 parsing failure, + * otherwise success(0). + **/ +static int get_ecdsa_signature_from_asn1(unsigned char *sig_ptr, + size_t *sig_len, + unsigned char *r_s_pair) +{ + int rc; + unsigned char *sig_end; + size_t len, r_len, s_len; + + sig_end = sig_ptr + *sig_len; + rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &len, + MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + sig_end = sig_ptr + len; + rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &r_len, + MBEDTLS_ASN1_INTEGER); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + if (ignore_asn1_int_padding_byte(&sig_ptr, &r_len) != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + (void)memcpy((void *)&r_s_pair[0], (const void *)sig_ptr, r_len); + + sig_ptr = sig_ptr + r_len; + sig_end = sig_ptr + len - (r_len + (SIZE_OF_ASN1_LEN + + SIZE_OF_ASN1_TAG)); + rc = mbedtls_asn1_get_tag(&sig_ptr, sig_end, &s_len, + MBEDTLS_ASN1_INTEGER); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + if (ignore_asn1_int_padding_byte(&sig_ptr, &s_len) != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + (void)memcpy((void *)&r_s_pair[r_len], (const void *)sig_ptr, s_len); + + *sig_len = s_len + r_len; + + return 0; +} +#endif /* + * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \ + * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA + **/ + +/* + * Verify a signature. + * + * Parameters are passed using the DER encoding format following the ASN.1 + * structures detailed above. + */ +static int verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len) +{ + mbedtls_asn1_buf sig_oid, sig_params; + mbedtls_asn1_buf signature; + mbedtls_md_type_t md_alg; + mbedtls_pk_type_t pk_alg; + int rc; + void *sig_opts = NULL; + unsigned char *p, *end; + unsigned char *local_sig_ptr; + size_t local_sig_len; + psa_ecc_family_t psa_ecc_family = 0U; + __unused unsigned char reformatted_sig[MAX_ECDSA_R_S_PAIR_LEN] = {0}; + + /* construct PSA key algo and type */ + psa_status_t status = PSA_SUCCESS; + psa_key_attributes_t psa_key_attr = PSA_KEY_ATTRIBUTES_INIT; + psa_key_id_t psa_key_id = PSA_KEY_ID_NULL; + psa_key_type_t psa_key_type; + psa_algorithm_t psa_alg; + + /* Get pointers to signature OID and parameters */ + p = (unsigned char *)sig_alg; + end = (unsigned char *)(p + sig_alg_len); + rc = mbedtls_asn1_get_alg(&p, end, &sig_oid, &sig_params); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the actual signature algorithm (MD + PK) */ + rc = mbedtls_x509_get_sig_alg(&sig_oid, &sig_params, &md_alg, &pk_alg, &sig_opts); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the signature (bitstring) */ + p = (unsigned char *)sig_ptr; + end = (unsigned char *)(p + sig_len); + signature.tag = *p; + rc = mbedtls_asn1_get_bitstring_null(&p, end, &signature.len); + if ((rc != 0) || ((size_t)(end - p) != signature.len)) { + rc = CRYPTO_ERR_SIGNATURE; + goto end2; + } + + local_sig_ptr = p; + local_sig_len = signature.len; + +#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \ +TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA + if (pk_alg == MBEDTLS_PK_ECDSA) { + rc = get_ecdsa_signature_from_asn1(local_sig_ptr, + &local_sig_len, + reformatted_sig); + if (rc != 0) { + goto end2; + } + + local_sig_ptr = reformatted_sig; + + rc = get_ecdsa_pkinfo_from_asn1((unsigned char **)&pk_ptr, + &pk_len, + &psa_ecc_family); + if (rc != 0) { + goto end2; + } + } +#endif /* + * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA || \ + * TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA + **/ + + /* Convert this pk_alg and md_alg to PSA key type and key algorithm */ + construct_psa_key_alg_and_type(pk_alg, md_alg, psa_ecc_family, + &psa_alg, &psa_key_type); + + + if ((psa_alg == PSA_ALG_NONE) || (psa_key_type == PSA_KEY_TYPE_NONE)) { + rc = CRYPTO_ERR_SIGNATURE; + goto end2; + } + + /* filled-in key_attributes */ + psa_set_key_algorithm(&psa_key_attr, psa_alg); + psa_set_key_type(&psa_key_attr, psa_key_type); + psa_set_key_usage_flags(&psa_key_attr, PSA_KEY_USAGE_VERIFY_MESSAGE); + + /* Get the key_id using import API */ + status = psa_import_key(&psa_key_attr, + pk_ptr, + (size_t)pk_len, + &psa_key_id); + + if (status != PSA_SUCCESS) { + rc = CRYPTO_ERR_SIGNATURE; + goto end2; + } + + /* + * Hash calculation and Signature verification of the given data payload + * is wrapped under the psa_verify_message function. + */ + status = psa_verify_message(psa_key_id, psa_alg, + data_ptr, data_len, + local_sig_ptr, local_sig_len); + + if (status != PSA_SUCCESS) { + rc = CRYPTO_ERR_SIGNATURE; + goto end1; + } + + /* Signature verification success */ + rc = CRYPTO_SUCCESS; + +end1: + /* + * Destroy the key if it is created successfully + */ + psa_destroy_key(psa_key_id); +end2: + mbedtls_free(sig_opts); + return rc; +} + +/* + * Match a hash + * + * Digest info is passed in DER format following the ASN.1 structure detailed + * above. + */ +static int verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len) +{ + mbedtls_asn1_buf hash_oid, params; + mbedtls_md_type_t md_alg; + unsigned char *p, *end, *hash; + size_t len; + int rc; + psa_status_t status; + psa_algorithm_t psa_md_alg; + + /* + * Digest info should be an MBEDTLS_ASN1_SEQUENCE, but padding after + * it is allowed. This is necessary to support multiple hash + * algorithms. + */ + p = (unsigned char *)digest_info_ptr; + end = p + digest_info_len; + rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + end = p + len; + + /* Get the hash algorithm */ + rc = mbedtls_asn1_get_alg(&p, end, &hash_oid, ¶ms); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Hash should be octet string type and consume all bytes */ + rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OCTET_STRING); + if ((rc != 0) || ((size_t)(end - p) != len)) { + return CRYPTO_ERR_HASH; + } + hash = p; + + rc = mbedtls_oid_get_md_alg(&hash_oid, &md_alg); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* convert the md_alg to psa_algo */ + psa_md_alg = mbedtls_md_psa_alg_from_type(md_alg); + + /* Length of hash must match the algorithm's size */ + if (len != PSA_HASH_LENGTH(psa_md_alg)) { + return CRYPTO_ERR_HASH; + } + + /* + * Calculate Hash and compare it against the retrieved hash from + * the certificate (one shot API). + */ + status = psa_hash_compare(psa_md_alg, + data_ptr, (size_t)data_len, + (const uint8_t *)hash, len); + + if (status != PSA_SUCCESS) { + return CRYPTO_ERR_HASH; + } + + return CRYPTO_SUCCESS; +} +#endif /* + * CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY || \ + * CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC + */ + +#if CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ +CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC +/* + * Map a generic crypto message digest algorithm to the corresponding macro used + * by Mbed TLS. + */ +static inline mbedtls_md_type_t md_type(enum crypto_md_algo algo) +{ + switch (algo) { + case CRYPTO_MD_SHA512: + return MBEDTLS_MD_SHA512; + case CRYPTO_MD_SHA384: + return MBEDTLS_MD_SHA384; + case CRYPTO_MD_SHA256: + return MBEDTLS_MD_SHA256; + default: + /* Invalid hash algorithm. */ + return MBEDTLS_MD_NONE; + } +} + +/* + * Calculate a hash + * + * output points to the computed hash + */ +static int calc_hash(enum crypto_md_algo md_algo, void *data_ptr, + unsigned int data_len, + unsigned char output[CRYPTO_MD_MAX_SIZE]) +{ + size_t hash_length; + psa_status_t status; + psa_algorithm_t psa_md_alg; + + /* convert the md_alg to psa_algo */ + psa_md_alg = mbedtls_md_psa_alg_from_type(md_type(md_algo)); + + /* + * Calculate the hash of the data, it is safe to pass the + * 'output' hash buffer pointer considering its size is always + * bigger than or equal to MBEDTLS_MD_MAX_SIZE. + */ + status = psa_hash_compute(psa_md_alg, data_ptr, (size_t)data_len, + (uint8_t *)output, CRYPTO_MD_MAX_SIZE, + &hash_length); + if (status != PSA_SUCCESS) { + return CRYPTO_ERR_HASH; + } + + return CRYPTO_SUCCESS; +} +#endif /* + * CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY || \ + * CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC + */ + +#if TF_MBEDTLS_USE_AES_GCM +/* + * Stack based buffer allocation for decryption operation. It could + * be configured to balance stack usage vs execution speed. + */ +#define DEC_OP_BUF_SIZE 128 + +static int aes_gcm_decrypt(void *data_ptr, size_t len, const void *key, + unsigned int key_len, const void *iv, + unsigned int iv_len, const void *tag, + unsigned int tag_len) +{ + mbedtls_gcm_context ctx; + mbedtls_cipher_id_t cipher = MBEDTLS_CIPHER_ID_AES; + unsigned char buf[DEC_OP_BUF_SIZE]; + unsigned char tag_buf[CRYPTO_MAX_TAG_SIZE]; + unsigned char *pt = data_ptr; + size_t dec_len; + int diff, i, rc; + size_t output_length __unused; + + mbedtls_gcm_init(&ctx); + + rc = mbedtls_gcm_setkey(&ctx, cipher, key, key_len * 8); + if (rc != 0) { + rc = CRYPTO_ERR_DECRYPTION; + goto exit_gcm; + } + +#if (MBEDTLS_VERSION_MAJOR < 3) + rc = mbedtls_gcm_starts(&ctx, MBEDTLS_GCM_DECRYPT, iv, iv_len, NULL, 0); +#else + rc = mbedtls_gcm_starts(&ctx, MBEDTLS_GCM_DECRYPT, iv, iv_len); +#endif + if (rc != 0) { + rc = CRYPTO_ERR_DECRYPTION; + goto exit_gcm; + } + + while (len > 0) { + dec_len = MIN(sizeof(buf), len); + +#if (MBEDTLS_VERSION_MAJOR < 3) + rc = mbedtls_gcm_update(&ctx, dec_len, pt, buf); +#else + rc = mbedtls_gcm_update(&ctx, pt, dec_len, buf, sizeof(buf), &output_length); +#endif + + if (rc != 0) { + rc = CRYPTO_ERR_DECRYPTION; + goto exit_gcm; + } + + memcpy(pt, buf, dec_len); + pt += dec_len; + len -= dec_len; + } + +#if (MBEDTLS_VERSION_MAJOR < 3) + rc = mbedtls_gcm_finish(&ctx, tag_buf, sizeof(tag_buf)); +#else + rc = mbedtls_gcm_finish(&ctx, NULL, 0, &output_length, tag_buf, sizeof(tag_buf)); +#endif + + if (rc != 0) { + rc = CRYPTO_ERR_DECRYPTION; + goto exit_gcm; + } + + /* Check tag in "constant-time" */ + for (diff = 0, i = 0; i < tag_len; i++) + diff |= ((const unsigned char *)tag)[i] ^ tag_buf[i]; + + if (diff != 0) { + rc = CRYPTO_ERR_DECRYPTION; + goto exit_gcm; + } + + /* GCM decryption success */ + rc = CRYPTO_SUCCESS; + +exit_gcm: + mbedtls_gcm_free(&ctx); + return rc; +} + +/* + * Authenticated decryption of an image + */ +static int auth_decrypt(enum crypto_dec_algo dec_algo, void *data_ptr, + size_t len, const void *key, unsigned int key_len, + unsigned int key_flags, const void *iv, + unsigned int iv_len, const void *tag, + unsigned int tag_len) +{ + int rc; + + assert((key_flags & ENC_KEY_IS_IDENTIFIER) == 0); + + switch (dec_algo) { + case CRYPTO_GCM_DECRYPT: + rc = aes_gcm_decrypt(data_ptr, len, key, key_len, iv, iv_len, + tag, tag_len); + if (rc != 0) + return rc; + break; + default: + return CRYPTO_ERR_DECRYPTION; + } + + return CRYPTO_SUCCESS; +} +#endif /* TF_MBEDTLS_USE_AES_GCM */ + +/* + * Register crypto library descriptor + */ +#if CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC +#if TF_MBEDTLS_USE_AES_GCM +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, + auth_decrypt, NULL); +#else +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash, + NULL, NULL); +#endif +#elif CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_ONLY +#if TF_MBEDTLS_USE_AES_GCM +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, + auth_decrypt, NULL); +#else +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL, + NULL, NULL); +#endif +#elif CRYPTO_SUPPORT == CRYPTO_HASH_CALC_ONLY +REGISTER_CRYPTO_LIB(LIB_NAME, init, NULL, NULL, calc_hash, NULL, NULL); +#endif /* CRYPTO_SUPPORT == CRYPTO_AUTH_VERIFY_AND_HASH_CALC */
diff --git a/drivers/auth/mbedtls/mbedtls_x509_parser.c b/drivers/auth/mbedtls/mbedtls_x509_parser.c index fb5b036..8bde5bb 100644 --- a/drivers/auth/mbedtls/mbedtls_x509_parser.c +++ b/drivers/auth/mbedtls/mbedtls_x509_parser.c
@@ -135,8 +135,38 @@ if ((oid != NULL) && ((size_t)oid_len == strlen(oid_str)) && (strcmp(oid, oid_str) == 0)) { + /* Extension must be ASN.1 DER */ + if (len < 2) { + /* too short */ + return IMG_PARSER_ERR_FORMAT; + } + + if ((p[0] & 0x1F) == 0x1F) { + /* multi-byte ASN.1 DER tag, not allowed */ + return IMG_PARSER_ERR_FORMAT; + } + + if ((p[0] & 0xDF) == 0) { + /* UNIVERSAL 0 tag, not allowed */ + return IMG_PARSER_ERR_FORMAT; + } + *ext = (void *)p; *ext_len = (unsigned int)len; + + /* Advance past the tag byte */ + p++; + + if (mbedtls_asn1_get_len(&p, end_ext_data, &len)) { + /* not valid DER */ + return IMG_PARSER_ERR_FORMAT; + } + + if (p + len != end_ext_data) { + /* junk after ASN.1 object */ + return IMG_PARSER_ERR_FORMAT; + } + return IMG_PARSER_OK; }
diff --git a/drivers/cadence/combo_phy/cdns_combo_phy.c b/drivers/cadence/combo_phy/cdns_combo_phy.c new file mode 100644 index 0000000..f00d0c1 --- /dev/null +++ b/drivers/cadence/combo_phy/cdns_combo_phy.c
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_combo_phy.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, + uint32_t phy_reg_data, uint32_t phy_reg_data_value) +{ + uint32_t data = 0U; + uint32_t value = 0U; + + /* Get PHY register address, write HRS04*/ + value = mmio_read_32(phy_reg_addr); + value &= ~PHY_REG_ADDR_MASK; + value |= phy_reg_addr_value; + mmio_write_32(phy_reg_addr, value); + data = mmio_read_32(phy_reg_addr); + if ((data & PHY_REG_ADDR_MASK) != phy_reg_addr_value) { + ERROR("PHY_REG_ADDR is not set properly\n"); + return -ENXIO; + } + + /* Get PHY register data, write HRS05 */ + value &= ~PHY_REG_DATA_MASK; + value |= phy_reg_data_value; + mmio_write_32(phy_reg_data, value); + data = mmio_read_32(phy_reg_data); + if (data != phy_reg_data_value) { + ERROR("PHY_REG_DATA is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_sd_card_detect(void) +{ + uint32_t value = 0; + + /* Card detection */ + do { + value = mmio_read_32(SDMMC_CDN(SRS09)); + /* Wait for card insertion. SRS09.CI = 1 */ + } while ((value & (1 << SDMMC_CDN_CI)) == 0); + + if ((value & (1 << SDMMC_CDN_CI)) == 0) { + ERROR("Card does not detect\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_emmc_card_reset(void) +{ + uint32_t _status = 0; + + /* Reset embedded card */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); + mdelay(68680); /* ~68680us */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); + udelay(340); /* ~340us */ + + /* Turn on supply voltage */ + /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ + mmio_write_32(SDMMC_CDN(SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP) | _status); + + return 0; +}
diff --git a/drivers/cadence/emmc/cdns_sdmmc.c b/drivers/cadence/emmc/cdns_sdmmc.c new file mode 100644 index 0000000..d2cd4d6 --- /dev/null +++ b/drivers/cadence/emmc/cdns_sdmmc.c
@@ -0,0 +1,824 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <stddef.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/delay_timer.h> +#include <drivers/mmc.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +/* Card busy and present */ +#define CARD_BUSY 1 +#define CARD_NOT_BUSY 0 + +/* 500 ms delay to read the RINST register */ +#define DELAY_MS_SRS_READ 500 +#define DELAY_RES 10 + +/* SRS12 error mask */ +#define SRS12_ERR_MASK 0xFFFF8000 + +/* Check DV dfi_init val=0 */ +#define IO_MASK_END_DATA 0x0 + +/* Check DV dfi_init val=2; DDR Mode */ +#define IO_MASK_END_DATA_DDR 0x2 +#define IO_MASK_START_DATA 0x0 +#define DATA_SELECT_OE_END_DATA 0x1 + +#define TIMEOUT 100000 + +/* General define */ +#define SDHC_REG_MASK UINT_MAX +#define SD_HOST_BLOCK_SIZE 0x200 +#define DTCVVAL_DEFAULT_VAL 0xE +#define CDMMC_DMA_MAX_BUFFER_SIZE 64*1024 +#define CDNSMMC_ADDRESS_MASK U(0x0f) +#define CONFIG_CDNS_DESC_COUNT 8 + +void cdns_init(void); +int cdns_send_cmd(struct mmc_cmd *cmd); +int cdns_set_ios(unsigned int clk, unsigned int width); +int cdns_prepare(int lba, uintptr_t buf, size_t size); +int cdns_read(int lba, uintptr_t buf, size_t size); +int cdns_write(int lba, uintptr_t buf, size_t size); + +const struct mmc_ops cdns_sdmmc_ops = { + .init = cdns_init, + .send_cmd = cdns_send_cmd, + .set_ios = cdns_set_ios, + .prepare = cdns_prepare, + .read = cdns_read, + .write = cdns_write, +}; + +struct cdns_sdmmc_params cdns_params; +struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg; +struct cdns_sdmmc_sdhc sdmmc_sdhc_reg; +#ifdef CONFIG_DMA_ADDR_T_64BIT +struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT]; +#else +struct cdns_idmac_desc cdns_desc[CONFIG_CDNS_DESC_COUNT] __aligned(32); +#endif + +bool data_cmd; + +int cdns_wait_ics(uint16_t timeout, uint32_t cdn_srs_res) +{ + /* Clock for sdmclk and sdclk */ + uint32_t count = 0; + uint32_t data = 0; + + /* Wait status command response ready */ + do { + data = mmio_read_32(cdn_srs_res); + count++; + if (count >= timeout) { + return -ETIMEDOUT; + } + } while ((data & (1 << SDMMC_CDN_ICS)) == 0); + + return 0; +} + +int cdns_busy(void) +{ + unsigned int data; + + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS09); + return (data & STATUS_DATA_BUSY) ? CARD_BUSY : CARD_NOT_BUSY; +} + +int cdns_vol_reset(void) +{ + /* Reset embedded card */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + udelay(250); + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (0 << SDMMC_CDN_BP)); + udelay(500); + + /* Turn on supply voltage */ + /* BVS = 7, BP = 1, BP2 only in UHS2 mode */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), (7 << SDMMC_CDN_BVS) | (1 << SDMMC_CDN_BP)); + udelay(250); + return 0; +} + +void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + /* Values are taken by the reference of cadence IP documents */ + combo_phy_reg->cp_clk_wr_delay = 0; + combo_phy_reg->cp_clk_wrdqs_delay = 0; + combo_phy_reg->cp_data_select_oe_end = 0; + combo_phy_reg->cp_dll_bypass_mode = 1; + combo_phy_reg->cp_dll_locked_mode = 0; + combo_phy_reg->cp_dll_start_point = 0; + combo_phy_reg->cp_gate_cfg_always_on = 1; + combo_phy_reg->cp_io_mask_always_on = 0; + combo_phy_reg->cp_io_mask_end = 0; + combo_phy_reg->cp_io_mask_start = 0; + combo_phy_reg->cp_rd_del_sel = 52; + combo_phy_reg->cp_read_dqs_cmd_delay = 0; + combo_phy_reg->cp_read_dqs_delay = 0; + combo_phy_reg->cp_sw_half_cycle_shift = 0; + combo_phy_reg->cp_sync_method = 1; + combo_phy_reg->cp_underrun_suppress = 1; + combo_phy_reg->cp_use_ext_lpbk_dqs = 1; + combo_phy_reg->cp_use_lpbk_dqs = 1; + combo_phy_reg->cp_use_phony_dqs = 1; + combo_phy_reg->cp_use_phony_dqs_cmd = 1; + + sdhc_reg->sdhc_extended_rd_mode = 1; + sdhc_reg->sdhc_extended_wr_mode = 1; + sdhc_reg->sdhc_hcsdclkadj = 0; + sdhc_reg->sdhc_idelay_val = 0; + sdhc_reg->sdhc_rdcmd_en = 1; + sdhc_reg->sdhc_rddata_en = 1; + sdhc_reg->sdhc_rw_compensate = 9; + sdhc_reg->sdhc_sdcfsh = 0; + sdhc_reg->sdhc_sdcfsl = 1; + sdhc_reg->sdhc_wrcmd0_dly = 1; + sdhc_reg->sdhc_wrcmd0_sdclk_dly = 0; + sdhc_reg->sdhc_wrcmd1_dly = 0; + sdhc_reg->sdhc_wrcmd1_sdclk_dly = 0; + sdhc_reg->sdhc_wrdata0_dly = 1; + sdhc_reg->sdhc_wrdata0_sdclk_dly = 0; + sdhc_reg->sdhc_wrdata1_dly = 0; + sdhc_reg->sdhc_wrdata1_sdclk_dly = 0; +} + +static int cdns_program_phy_reg(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + uint32_t value = 0; + int ret = 0; + + /* program PHY_DQS_TIMING_REG */ + value = (CP_USE_EXT_LPBK_DQS(combo_phy_reg->cp_use_ext_lpbk_dqs)) | + (CP_USE_LPBK_DQS(combo_phy_reg->cp_use_lpbk_dqs)) | + (CP_USE_PHONY_DQS(combo_phy_reg->cp_use_phony_dqs)) | + (CP_USE_PHONY_DQS_CMD(combo_phy_reg->cp_use_phony_dqs_cmd)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DQS_TIMING_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_GATE_LPBK_CTRL_REG */ + value = (CP_SYNC_METHOD(combo_phy_reg->cp_sync_method)) | + (CP_SW_HALF_CYCLE_SHIFT(combo_phy_reg->cp_sw_half_cycle_shift)) | + (CP_RD_DEL_SEL(combo_phy_reg->cp_rd_del_sel)) | + (CP_UNDERRUN_SUPPRESS(combo_phy_reg->cp_underrun_suppress)) | + (CP_GATE_CFG_ALWAYS_ON(combo_phy_reg->cp_gate_cfg_always_on)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_GATE_LPBK_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_DLL_MASTER_CTRL_REG */ + value = (CP_DLL_BYPASS_MODE(combo_phy_reg->cp_dll_bypass_mode)) + | (CP_DLL_START_POINT(combo_phy_reg->cp_dll_start_point)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DLL_MASTER_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_DLL_SLAVE_CTRL_REG */ + value = (CP_READ_DQS_CMD_DELAY(combo_phy_reg->cp_read_dqs_cmd_delay)) + | (CP_CLK_WRDQS_DELAY(combo_phy_reg->cp_clk_wrdqs_delay)) + | (CP_CLK_WR_DELAY(combo_phy_reg->cp_clk_wr_delay)) + | (CP_READ_DQS_DELAY(combo_phy_reg->cp_read_dqs_delay)); + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DLL_SLAVE_CTRL_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + + /* program PHY_CTRL_REG */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS04, COMBO_PHY_REG + + PHY_CTRL_REG); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS05); + + /* phony_dqs_timing=0 */ + value &= ~(CP_PHONY_DQS_TIMING_MASK << CP_PHONY_DQS_TIMING_SHIFT); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS05, value); + + /* switch off DLL_RESET */ + do { + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + value |= SDHC_PHY_SW_RESET; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + /* polling PHY_INIT_COMPLETE */ + } while ((value & SDHC_PHY_INIT_COMPLETE) != SDHC_PHY_INIT_COMPLETE); + + /* program PHY_DQ_TIMING_REG */ + combo_phy_reg->cp_io_mask_end = 0U; + value = (CP_IO_MASK_ALWAYS_ON(combo_phy_reg->cp_io_mask_always_on)) + | (CP_IO_MASK_END(combo_phy_reg->cp_io_mask_end)) + | (CP_IO_MASK_START(combo_phy_reg->cp_io_mask_start)) + | (CP_DATA_SELECT_OE_END(combo_phy_reg->cp_data_select_oe_end)); + + ret = cdns_sdmmc_write_phy_reg(MMC_REG_BASE + SDHC_CDNS_HRS04, + COMBO_PHY_REG + PHY_DQ_TIMING_REG, MMC_REG_BASE + + SDHC_CDNS_HRS05, value); + if (ret != 0) { + return ret; + } + return 0; +} + +int cdns_read(int lba, uintptr_t buf, size_t size) +{ + inv_dcache_range(buf, size); + + return 0; +} + +void cdns_init(void) +{ + /* Dummy function pointer for cdns_init. */ +} + +int cdns_prepare(int dma_start_addr, uintptr_t dma_buff, size_t size) +{ + data_cmd = true; + struct cdns_idmac_desc *desc; + uint32_t desc_cnt, i; + uint64_t desc_base; + + assert(((dma_buff & CDNSMMC_ADDRESS_MASK) == 0) && + (cdns_params.desc_size > 0) && + ((MMC_REG_BASE & MMC_BLOCK_MASK) == 0) && + ((cdns_params.desc_base & MMC_BLOCK_MASK) == 0) && + ((cdns_params.desc_size & MMC_BLOCK_MASK) == 0)); + + flush_dcache_range(dma_buff, size); + + desc_cnt = (size + (CDMMC_DMA_MAX_BUFFER_SIZE) - 1) / (CDMMC_DMA_MAX_BUFFER_SIZE); + assert(desc_cnt * sizeof(struct cdns_idmac_desc) < cdns_params.desc_size); + + if (desc_cnt > CONFIG_CDNS_DESC_COUNT) { + ERROR("Requested data transfer length %ld is greater than configured length %d", + size, (CONFIG_CDNS_DESC_COUNT * CDMMC_DMA_MAX_BUFFER_SIZE)); + return -EINVAL; + } + + desc = (struct cdns_idmac_desc *)cdns_params.desc_base; + desc_base = (uint64_t)desc; + i = 0; + + while ((i + 1) < desc_cnt) { + desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + desc->reserved = 0; + desc->len = MAX_64KB_PAGE; + desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i); +#if CONFIG_DMA_ADDR_T_64BIT == 1 + desc->addr_hi = (dma_buff >> 32) & 0xffffffff; +#endif + size -= CDMMC_DMA_MAX_BUFFER_SIZE; + desc++; + i++; + } + + desc->attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA | + ADMA_DESC_ATTR_END; + desc->reserved = 0; + desc->len = size; +#if CONFIG_DMA_ADDR_T_64BIT == 1 + desc->addr_lo = (dma_buff & UINT_MAX) + (CDMMC_DMA_MAX_BUFFER_SIZE * i); + desc->addr_hi = (dma_buff >> 32) & UINT_MAX; +#else + desc->addr_lo = (dma_buff & UINT_MAX); +#endif + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS22, (uint32_t)desc_base); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS23, (uint32_t)(desc_base >> 32)); + flush_dcache_range(cdns_params.desc_base, + desc_cnt * CDMMC_DMA_MAX_BUFFER_SIZE); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS01, + ((512 << BLOCK_SIZE) | ((size/512) << BLK_COUNT_CT) | SDMA_BUF)); + return 0; +} + +static void cdns_host_set_clk(int clk) +{ + uint32_t ret = 0; + uint32_t sdclkfsval = 0; + uint32_t dtcvval = DTCVVAL_DEFAULT_VAL; + + sdclkfsval = (cdns_params.clk_rate / 2000) / clk; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE)); + + ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11); + if (ret != 0U) { + ERROR("Waiting SDMMC_CDN_ICS timeout"); + } + + /* Enable DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & + ~SDHC_DLL_RESET_MASK); + /* Set extended_wr_mode */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) + & SDHC_EXTENDED_WR_MODE_MASK) | (1 << EXTENDED_WR_MODE)); + /* Release DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | 1); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | (3 << RDCMD_EN)); + + do { + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE)); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX); +} + +int cdns_set_ios(unsigned int clk, unsigned int width) +{ + + switch (width) { + case MMC_BUS_WIDTH_1: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), LEDC_OFF); + break; + case MMC_BUS_WIDTH_4: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), DTW_4BIT); + break; + case MMC_BUS_WIDTH_8: + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_SRS10), EDTW_8BIT); + break; + default: + assert(0); + break; + } + cdns_host_set_clk(clk); + + return 0; +} + +int cdns_sdmmc_write_sd_host_reg(uint32_t addr, uint32_t data) +{ + uint32_t value = 0; + + value = mmio_read_32(addr); + value &= ~SDHC_REG_MASK; + value |= data; + mmio_write_32(addr, value); + value = mmio_read_32(addr); + if (value != data) { + ERROR("SD host address is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int cdns_write(int lba, uintptr_t buf, size_t size) +{ + return 0; +} + +static int cdns_init_hrs_io(struct cdns_sdmmc_combo_phy *combo_phy_reg, + struct cdns_sdmmc_sdhc *sdhc_reg) +{ + uint32_t value = 0; + int ret = 0; + + /* program HRS09, register 42 */ + value = (SDHC_RDDATA_EN(sdhc_reg->sdhc_rddata_en)) + | (SDHC_RDCMD_EN(sdhc_reg->sdhc_rdcmd_en)) + | (SDHC_EXTENDED_WR_MODE(sdhc_reg->sdhc_extended_wr_mode)) + | (SDHC_EXTENDED_RD_MODE(sdhc_reg->sdhc_extended_rd_mode)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + if (ret != 0) { + ERROR("Program HRS09 failed"); + return ret; + } + + /* program HRS10, register 43 */ + value = (SDHC_HCSDCLKADJ(sdhc_reg->sdhc_hcsdclkadj)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS10, value); + if (ret != 0) { + ERROR("Program HRS10 failed"); + return ret; + } + + /* program HRS16, register 48 */ + value = (SDHC_WRDATA1_SDCLK_DLY(sdhc_reg->sdhc_wrdata1_sdclk_dly)) + | (SDHC_WRDATA0_SDCLK_DLY(sdhc_reg->sdhc_wrdata0_sdclk_dly)) + | (SDHC_WRCMD1_SDCLK_DLY(sdhc_reg->sdhc_wrcmd1_sdclk_dly)) + | (SDHC_WRCMD0_SDCLK_DLY(sdhc_reg->sdhc_wrcmd0_sdclk_dly)) + | (SDHC_WRDATA1_DLY(sdhc_reg->sdhc_wrdata1_dly)) + | (SDHC_WRDATA0_DLY(sdhc_reg->sdhc_wrdata0_dly)) + | (SDHC_WRCMD1_DLY(sdhc_reg->sdhc_wrcmd1_dly)) + | (SDHC_WRCMD0_DLY(sdhc_reg->sdhc_wrcmd0_dly)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS16, value); + if (ret != 0) { + ERROR("Program HRS16 failed"); + return ret; + } + + /* program HRS07, register 40 */ + value = (SDHC_RW_COMPENSATE(sdhc_reg->sdhc_rw_compensate)) + | (SDHC_IDELAY_VAL(sdhc_reg->sdhc_idelay_val)); + ret = cdns_sdmmc_write_sd_host_reg(MMC_REG_BASE + SDHC_CDNS_HRS07, value); + if (ret != 0) { + ERROR("Program HRS07 failed"); + return ret; + } + + return ret; +} + +static int cdns_hc_set_clk(struct cdns_sdmmc_params *cdn_sdmmc_dev_mode_params) +{ + uint32_t ret = 0; + uint32_t dtcvval, sdclkfsval; + + dtcvval = DTC_VAL; + sdclkfsval = 0; + + if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_DS) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR12) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR_BC)) { + sdclkfsval = 4; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_HS) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR25) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_DDR50) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_SDR)) { + sdclkfsval = 2; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR50) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_DDR) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS400es)) { + sdclkfsval = 1; + } else if ((cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == SD_UHS_SDR104) || + (cdn_sdmmc_dev_mode_params->cdn_sdmmc_dev_mode == EMMC_HS200)) { + sdclkfsval = 0; + } + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, 0); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE)); + ret = cdns_wait_ics(5000, MMC_REG_BASE + SDHC_CDNS_SRS11); + if (ret != 0U) { + ERROR("Waiting SDMMC_CDN_ICS timeout"); + return ret; + } + + /* Enable DLL reset */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) & ~SDHC_DLL_RESET_MASK); + /* Set extended_wr_mode */ + mmio_write_32((MMC_REG_BASE + SDHC_CDNS_HRS09), + (mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & SDHC_EXTENDED_WR_MODE_MASK) | + (1 << EXTENDED_WR_MODE)); + /* Release DLL reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | 1); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, mmio_read_32(MMC_REG_BASE + + SDHC_CDNS_HRS09) | (3 << RDCMD_EN)); + do { + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + } while (~mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09) & (1 << 1)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (dtcvval << SDMMC_CDN_DTCV) | + (sdclkfsval << SDMMC_CDN_SDCLKFS) | (1 << SDMMC_CDN_ICE) | (1 << SDMMC_CDN_SDCE)); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS13, UINT_MAX); + return 0; +} + +int cdns_reset(void) +{ + uint32_t data = 0; + uint32_t count = 0; + uint32_t value = 0; + + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11); + value &= ~(0xFFFF); + value |= 0x0; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, value); + udelay(500); + + /* Software reset */ + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS00, 1); + /* Wait status command response ready */ + do { + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS00); + count++; + if (count >= 5000) { + return -ETIMEDOUT; + } + /* Wait for HRS00.SWR */ + } while ((data & 1) == 1); + + /* Step 1, switch on DLL_RESET */ + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_HRS09); + value &= ~SDHC_PHY_SW_RESET; + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_HRS09, value); + + return 0; +} + +int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, +struct cdns_sdmmc_sdhc *mmc_sdhc_reg) +{ + int ret = 0; + + ret = cdns_reset(); + if (ret != 0) { + ERROR("Program phy reg init failed"); + return ret; + } + + ret = cdns_program_phy_reg(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (ret != 0) { + ERROR("Program phy reg init failed"); + return ret; + } + + ret = cdns_init_hrs_io(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (ret != 0) { + ERROR("Program init for HRS reg is failed"); + return ret; + } + + ret = cdns_sd_card_detect(); + if (ret != 0) { + ERROR("SD card does not detect"); + return ret; + } + + ret = cdns_vol_reset(); + if (ret != 0) { + ERROR("eMMC card reset failed"); + return ret; + } + + ret = cdns_hc_set_clk(&cdns_params); + if (ret != 0) { + ERROR("hc set clk failed"); + return ret; + } + + return 0; +} + +void cdns_srs10_value_toggle(uint8_t write_val, uint8_t prev_val) +{ + uint32_t data_op = 0U; + + data_op = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, (data_op & (prev_val << 0))); + mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS10); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS10, data_op | (write_val << 0)); +} + +void cdns_srs11_srs15_config(uint32_t srs11_val, uint32_t srs15_val) +{ + uint32_t data = 0U; + + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS11); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS11, (data | srs11_val)); + data = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS15); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS15, (data | srs15_val)); +} + +int cdns_send_cmd(struct mmc_cmd *cmd) +{ + uint32_t op = 0, ret = 0; + uint8_t write_value = 0, prev_val = 0; + uint32_t value; + int32_t timeout; + uint32_t cmd_indx; + uint32_t status = 0, srs15_val = 0, srs11_val = 0; + uint32_t status_check = 0; + + assert(cmd); + cmd_indx = (cmd->cmd_idx) << COM_IDX; + + if (data_cmd) { + switch (cmd->cmd_idx) { + case SD_SWITCH: + op = DATA_PRESENT; + write_value = ADMA2_32 | DT_WIDTH; + prev_val = ADMA2_32 | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + srs15_val = BIT_AD_64 | HV4E | V18SE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_WRITE_SINGLE_BLOCK: + case SD_READ_SINGLE_BLOCK: + op = DATA_PRESENT; + write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC; + prev_val = ADMA2_32 | HS_EN | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR); + break; + + case SD_WRITE_MULTIPLE_BLOCK: + case SD_READ_MULTIPLE_BLOCK: + op = DATA_PRESENT | AUTO_CMD_EN | MULTI_BLK_READ; + write_value = ADMA2_32 | HS_EN | DT_WIDTH | LEDC; + prev_val = ADMA2_32 | HS_EN | DT_WIDTH; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = PVE | BIT_AD_64 | HV4E | SDR104_MODE | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS00, SAAR); + break; + + case SD_APP_SEND_SCR: + op = DATA_PRESENT; + write_value = ADMA2_32 | LEDC; + prev_val = LEDC; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = BIT_AD_64 | HV4E | V18SE; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_SEND_IF_COND: + op = DATA_PRESENT | CMD_IDX_CHK_ENABLE; + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + default: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + op = 0; + break; + } + } else { + switch (cmd->cmd_idx) { + case SD_GO_IDLE_STATE: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_ALL_SEND_CID: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E | V18SE; + srs11_val = SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_SEND_IF_COND: + op = CMD_IDX_CHK_ENABLE; + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + srs15_val = HV4E; + srs11_val = READ_CLK | SDMMC_CDN_ICE | SDMMC_CDN_ICS | SDMMC_CDN_SDCE; + cdns_srs11_srs15_config(srs11_val, srs15_val); + break; + + case SD_STOP_TRANSMISSION: + op = CMD_STOP_ABORT_CMD; + break; + + case SD_SEND_STATUS: + break; + + case 1: + cmd->cmd_arg = 0; + break; + + case SD_SELECT_CARD: + op = MULTI_BLK_READ; + break; + + case SD_APP_CMD: + default: + write_value = LEDC; + prev_val = 0x0; + cdns_srs10_value_toggle(write_value, prev_val); + op = 0; + break; + } + } + + switch (cmd->resp_type) { + case MMC_RESPONSE_NONE: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN; + break; + + case MMC_RESPONSE_R2: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN | + RES_TYPE_SEL_136 | CMD_CHECK_RESP_CRC; + break; + + case MMC_RESPONSE_R3: + op |= CMD_READ | MULTI_BLK_READ | DMA_ENABLED | BLK_CNT_EN | + RES_TYPE_SEL_48; + break; + + case MMC_RESPONSE_R1: + if ((cmd->cmd_idx == SD_WRITE_SINGLE_BLOCK) || (cmd->cmd_idx + == SD_WRITE_MULTIPLE_BLOCK)) { + op |= DMA_ENABLED | BLK_CNT_EN | RES_TYPE_SEL_48 + | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + } else { + op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | RES_TYPE_SEL_48 + | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + } + break; + + default: + op |= DMA_ENABLED | BLK_CNT_EN | CMD_READ | MULTI_BLK_READ | + RES_TYPE_SEL_48 | CMD_CHECK_RESP_CRC | CMD_IDX_CHK_ENABLE; + break; + } + + timeout = TIMEOUT; + do { + udelay(100); + ret = cdns_busy(); + if (--timeout <= 0) { + udelay(50); + panic(); + } + } while (ret); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS12, UINT_MAX); + + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS02, cmd->cmd_arg); + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS14, 0x00000000); + if (cmd_indx == 1) + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, SDHC_CDNS_SRS03_VALUE); + else + mmio_write_32(MMC_REG_BASE + SDHC_CDNS_SRS03, op | cmd_indx); + + timeout = TIMEOUT; + do { + udelay(500); + value = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS12); + } while (((value & (INT_CMD_DONE | ERROR_INT)) == 0) && (timeout-- > 0)); + + timeout = TIMEOUT; + + if (data_cmd) { + data_cmd = false; + do { + udelay(250); + } while (((value & TRAN_COMP) == 0) && (timeout-- > 0)); + } + + status_check = value & SRS12_ERR_MASK; + if (status_check != 0U) { + ERROR("SD host controller send command failed, SRS12 = %x", status); + return -1; + } + + if ((op & RES_TYPE_SEL_48) || (op & RES_TYPE_SEL_136)) { + cmd->resp_data[0] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS04); + if (op & RES_TYPE_SEL_136) { + cmd->resp_data[1] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS05); + cmd->resp_data[2] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS06); + cmd->resp_data[3] = mmio_read_32(MMC_REG_BASE + SDHC_CDNS_SRS07); + } + } + + return 0; +}
diff --git a/drivers/cadence/nand/cdns_nand.c b/drivers/cadence/nand/cdns_nand.c new file mode 100644 index 0000000..5a66262 --- /dev/null +++ b/drivers/cadence/nand/cdns_nand.c
@@ -0,0 +1,435 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_nand.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> +#include <platform_def.h> + +/* NAND flash device information struct */ +static cnf_dev_info_t dev_info; + +/* Scratch buffers for read and write operations */ +static uint8_t scratch_buff[PLATFORM_MTD_MAX_PAGE_SIZE]; + +/* Wait for controller to be in idle state */ +static inline void cdns_nand_wait_idle(void) +{ + uint32_t reg = 0U; + + do { + udelay(CNF_DEF_DELAY_US); + reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); + } while (CNF_GET_CTRL_BUSY(reg) != 0U); +} + +/* Wait for given thread to be in ready state */ +static inline void cdns_nand_wait_thread_ready(uint8_t thread_id) +{ + uint32_t reg = 0U; + + do { + udelay(CNF_DEF_DELAY_US); + reg = mmio_read_32(CNF_CMDREG(TRD_STATUS)); + reg &= (1U << (uint32_t)thread_id); + } while (reg != 0U); +} + +/* Check if the last operation/command in selected thread is completed */ +static int cdns_nand_last_opr_status(uint8_t thread_id) +{ + uint8_t nthreads = 0U; + uint32_t reg = 0U; + + /* Get number of threads */ + reg = mmio_read_32(CNF_CTRLPARAM(FEATURE)); + nthreads = CNF_GET_NTHREADS(reg); + + if (thread_id > nthreads) { + ERROR("%s: Invalid thread ID\n", __func__); + return -EINVAL; + } + + /* Select thread */ + mmio_write_32(CNF_CMDREG(CMD_STAT_PTR), (uint32_t)thread_id); + + uint32_t err_mask = CNF_ECMD | CNF_EECC | CNF_EDEV | CNF_EDQS | CNF_EFAIL | + CNF_EBUS | CNF_EDI | CNF_EPAR | CNF_ECTX | CNF_EPRO; + + do { + udelay(CNF_DEF_DELAY_US * 2); + reg = mmio_read_32(CNF_CMDREG(CMD_STAT)); + } while ((reg & CNF_CMPLT) == 0U); + + /* last operation is completed, make sure no other error bits are set */ + if ((reg & err_mask) == 1U) { + ERROR("%s, CMD_STATUS:0x%x\n", __func__, reg); + return -EIO; + } + + return 0; +} + +/* Set feature command */ +int cdns_nand_set_feature(uint8_t feat_addr, uint8_t feat_val, uint8_t thread_id) +{ + /* Wait for thread to be ready */ + cdns_nand_wait_thread_ready(thread_id); + + /* Set feature address */ + mmio_write_32(CNF_CMDREG(CMD_REG1), (uint32_t)feat_addr); + /* Set feature volume */ + mmio_write_32(CNF_CMDREG(CMD_REG2), (uint32_t)feat_val); + + /* Set feature command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (thread_id << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_SET_FEATURE << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + return cdns_nand_last_opr_status(thread_id); +} + +/* Reset command to the selected device */ +int cdns_nand_reset(uint8_t thread_id) +{ + /* Operation is executed in selected thread */ + cdns_nand_wait_thread_ready(thread_id); + + /* Select memory */ + mmio_write_32(CNF_CMDREG(CMD_REG4), (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Issue reset command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (thread_id << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_RESET_ASYNC << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + return cdns_nand_last_opr_status(thread_id); +} + +/* Set operation work mode */ +static void cdns_nand_set_opr_mode(uint8_t opr_mode) +{ + /* Wait for controller to be in idle state */ + cdns_nand_wait_idle(); + + /* Reset DLL PHY */ + uint32_t reg = mmio_read_32(CNF_MINICTRL(DLL_PHY_CTRL)); + + reg &= ~(1 << CNF_DLL_PHY_RST_N); + mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg); + + if (opr_mode == CNF_OPR_WORK_MODE_SDR) { + /* Combo PHY Control Timing Block register settings */ + mmio_write_32(CP_CTB(CTRL_REG), CP_CTRL_REG_SDR); + mmio_write_32(CP_CTB(TSEL_REG), CP_TSEL_REG_SDR); + + /* Combo PHY DLL register settings */ + mmio_write_32(CP_DLL(DQ_TIMING_REG), CP_DQ_TIMING_REG_SDR); + mmio_write_32(CP_DLL(DQS_TIMING_REG), CP_DQS_TIMING_REG_SDR); + mmio_write_32(CP_DLL(GATE_LPBK_CTRL_REG), CP_GATE_LPBK_CTRL_REG_SDR); + mmio_write_32(CP_DLL(MASTER_CTRL_REG), CP_DLL_MASTER_CTRL_REG_SDR); + + /* Async mode timing settings */ + mmio_write_32(CNF_MINICTRL(ASYNC_TOGGLE_TIMINGS), + (2 << CNF_ASYNC_TIMINGS_TRH) | + (4 << CNF_ASYNC_TIMINGS_TRP) | + (2 << CNF_ASYNC_TIMINGS_TWH) | + (4 << CNF_ASYNC_TIMINGS_TWP)); + + /* Set extended read and write mode */ + reg |= (1 << CNF_DLL_PHY_EXT_RD_MODE); + reg |= (1 << CNF_DLL_PHY_EXT_WR_MODE); + + /* Set operation work mode in common settings */ + uint32_t data = mmio_read_32(CNF_MINICTRL(CMN_SETTINGS)); + + data |= (CNF_OPR_WORK_MODE_SDR << CNF_CMN_SETTINGS_OPR); + mmio_write_32(CNF_MINICTRL(CMN_SETTINGS), data); + + } else if (opr_mode == CNF_OPR_WORK_MODE_NVDDR) { + ; /* ToDo: add DDR mode settings also once available on SIMICS */ + } else { + ; + } + + reg |= (1 << CNF_DLL_PHY_RST_N); + mmio_write_32(CNF_MINICTRL(DLL_PHY_CTRL), reg); +} + +/* Data transfer configuration */ +static void cdns_nand_transfer_config(void) +{ + /* Wait for controller to be in idle state */ + cdns_nand_wait_idle(); + + /* Configure data transfer parameters */ + mmio_write_32(CNF_CTRLCFG(TRANS_CFG0), 1); + + /* ECC is disabled */ + mmio_write_32(CNF_CTRLCFG(ECC_CFG0), 0); + + /* DMA burst select */ + mmio_write_32(CNF_CTRLCFG(DMA_SETTINGS), + (CNF_DMA_BURST_SIZE_MAX << CNF_DMA_SETTINGS_BURST) | + (1 << CNF_DMA_SETTINGS_OTE)); + + /* Enable pre-fetching for 1K */ + mmio_write_32(CNF_CTRLCFG(FIFO_TLEVEL), + (CNF_DMA_PREFETCH_SIZE << CNF_FIFO_TLEVEL_POS) | + (CNF_DMA_PREFETCH_SIZE << CNF_FIFO_TLEVEL_DMA_SIZE)); + + /* Select access type */ + mmio_write_32(CNF_CTRLCFG(MULTIPLANE_CFG), 0); + mmio_write_32(CNF_CTRLCFG(CACHE_CFG), 0); +} + +/* Update the nand flash device info */ +static int cdns_nand_update_dev_info(void) +{ + uint32_t reg = 0U; + + /* Read the device type and number of LUNs */ + reg = mmio_read_32(CNF_CTRLPARAM(DEV_PARAMS0)); + dev_info.type = CNF_GET_DEV_TYPE(reg); + if (dev_info.type == CNF_DT_UNKNOWN) { + ERROR("%s: device type unknown\n", __func__); + return -ENXIO; + } + dev_info.nluns = CNF_GET_NLUNS(reg); + + /* Pages per block */ + reg = mmio_read_32(CNF_CTRLCFG(DEV_LAYOUT)); + dev_info.npages_per_block = CNF_GET_NPAGES_PER_BLOCK(reg); + + /* Sector size and last sector size */ + reg = mmio_read_32(CNF_CTRLCFG(TRANS_CFG1)); + dev_info.sector_size = CNF_GET_SCTR_SIZE(reg); + dev_info.last_sector_size = CNF_GET_LAST_SCTR_SIZE(reg); + + /* Page size and spare size */ + reg = mmio_read_32(CNF_CTRLPARAM(DEV_AREA)); + dev_info.page_size = CNF_GET_PAGE_SIZE(reg); + dev_info.spare_size = CNF_GET_SPARE_SIZE(reg); + + /* Device blocks per LUN */ + dev_info.nblocks_per_lun = mmio_read_32(CNF_CTRLPARAM(DEV_BLOCKS_PLUN)); + + /* Calculate block size and total device size */ + dev_info.block_size = (dev_info.npages_per_block * dev_info.page_size); + dev_info.total_size = (dev_info.block_size * dev_info.nblocks_per_lun * + dev_info.nluns); + + VERBOSE("CNF params: page %d, spare %d, block %d, total %lld\n", + dev_info.page_size, dev_info.spare_size, + dev_info.block_size, dev_info.total_size); + + return 0; +} + +/* NAND Flash Controller/Host initialization */ +int cdns_nand_host_init(void) +{ + uint32_t reg = 0U; + int ret = 0; + + do { + /* Read controller status register for init complete */ + reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); + } while (CNF_GET_INIT_COMP(reg) == 0); + + ret = cdns_nand_update_dev_info(); + if (ret != 0) { + return ret; + } + + INFO("CNF: device discovery process completed and device type %d\n", + dev_info.type); + + /* Enable data integrity, enable CRC and parity */ + reg = mmio_read_32(CNF_DI(CONTROL)); + reg |= (1 << CNF_DI_PAR_EN); + reg |= (1 << CNF_DI_CRC_EN); + mmio_write_32(CNF_DI(CONTROL), reg); + + /* Status polling mode, device control and status register */ + cdns_nand_wait_idle(); + reg = mmio_read_32(CNF_CTRLCFG(DEV_STAT)); + reg = reg & ~1; + mmio_write_32(CNF_CTRLCFG(DEV_STAT), reg); + + /* Set operation work mode */ + cdns_nand_set_opr_mode(CNF_OPR_WORK_MODE_SDR); + + /* Set data transfer configuration parameters */ + cdns_nand_transfer_config(); + + return 0; +} + +/* erase: Block erase command */ +int cdns_nand_erase(uint32_t offset, uint32_t size) +{ + /* Determine the starting block offset i.e row address */ + uint32_t row_address = dev_info.npages_per_block * offset; + + /* Wait for thread to be in ready state */ + cdns_nand_wait_thread_ready(CNF_DEF_TRD); + + /*Set row address */ + mmio_write_32(CNF_CMDREG(CMD_REG1), row_address); + + /* Operation bank number */ + mmio_write_32(CNF_CMDREG(CMD_REG4), (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Block erase command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_CT_ERASE << CNF_CMDREG0_CMD); + reg |= (((size-1) & 0xFF) << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + /* Wait for erase operation to complete */ + return cdns_nand_last_opr_status(CNF_DEF_TRD); +} + +/* io mtd functions */ +int cdns_nand_init_mtd(unsigned long long *size, unsigned int *erase_size) +{ + *size = dev_info.total_size; + *erase_size = dev_info.block_size; + + return 0; +} + +/* NAND Flash page read */ +static int cdns_nand_read_page(uint32_t block, uint32_t page, uintptr_t buffer) +{ + /* Wait for thread to be ready */ + cdns_nand_wait_thread_ready(CNF_DEF_TRD); + + /* Select device */ + mmio_write_32(CNF_CMDREG(CMD_REG4), + (CNF_DEF_DEVICE << CNF_CMDREG4_MEM)); + + /* Set host memory address for DMA transfers */ + mmio_write_32(CNF_CMDREG(CMD_REG2), (buffer & 0xFFFF)); + mmio_write_32(CNF_CMDREG(CMD_REG3), ((buffer >> 32) & 0xFFFF)); + + /* Set row address */ + uint32_t row_address = 0U; + + row_address |= ((page & 0x3F) | (block << 6)); + mmio_write_32(CNF_CMDREG(CMD_REG1), row_address); + + /* Page read command */ + uint32_t reg = (CNF_WORK_MODE_PIO << CNF_CMDREG0_CT); + + reg |= (CNF_DEF_TRD << CNF_CMDREG0_TRD); + reg |= (CNF_DEF_VOL_ID << CNF_CMDREG0_VOL); + reg |= (CNF_INT_DIS << CNF_CMDREG0_INTR); + reg |= (CNF_DMA_MASTER_SEL << CNF_CMDREG0_DMA); + reg |= (CNF_CT_PAGE_READ << CNF_CMDREG0_CMD); + reg |= (((CNF_READ_SINGLE_PAGE-1) & 0xFF) << CNF_CMDREG0_CMD); + mmio_write_32(CNF_CMDREG(CMD_REG0), reg); + + /* Wait for read operation to complete */ + if (cdns_nand_last_opr_status(CNF_DEF_TRD)) { + ERROR("%s: Page read failed\n", __func__); + return -EIO; + } + + return 0; +} + +int cdns_nand_read(unsigned int offset, uintptr_t buffer, size_t length, + size_t *out_length) +{ + uint32_t block = offset / dev_info.block_size; + uint32_t end_block = (offset + length - 1U) / dev_info.block_size; + uint32_t page_start = (offset % dev_info.block_size) / dev_info.page_size; + uint32_t start_offset = offset % dev_info.page_size; + uint32_t nb_pages = dev_info.block_size / dev_info.page_size; + uint32_t bytes_read = 0U; + uint32_t page = 0U; + int result = 0; + + VERBOSE("CNF: block %u-%u, page_start %u, len %zu, offset %u\n", + block, end_block, page_start, length, offset); + + if ((offset >= dev_info.total_size) || + (offset + length-1 >= dev_info.total_size) || + (length == 0U)) { + ERROR("CNF: Invalid read parameters\n"); + return -EINVAL; + } + + *out_length = 0UL; + + while (block <= end_block) { + for (page = page_start; page < nb_pages; page++) { + if ((start_offset != 0U) || (length < dev_info.page_size)) { + /* Partial page read */ + result = cdns_nand_read_page(block, page, + (uintptr_t)scratch_buff); + if (result != 0) { + return result; + } + + bytes_read = MIN((size_t)(dev_info.page_size - start_offset), + length); + + memcpy((uint8_t *)buffer, scratch_buff + start_offset, + bytes_read); + start_offset = 0U; + } else { + /* Full page read */ + result = cdns_nand_read_page(block, page, + (uintptr_t)scratch_buff); + if (result != 0) { + return result; + } + + bytes_read = dev_info.page_size; + memcpy((uint8_t *)buffer, scratch_buff, bytes_read); + } + + length -= bytes_read; + buffer += bytes_read; + *out_length += bytes_read; + + /* All the bytes have read */ + if (length == 0U) { + break; + } + + udelay(CNF_READ_INT_DELAY_US); + } /* for */ + + page_start = 0U; + block++; + } /* while */ + + return 0; +}
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S index 4c1a80e..d2dd0a8 100644 --- a/drivers/cadence/uart/aarch64/cdns_console.S +++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -79,7 +79,7 @@ mov x0, x6 mov x30, x7 - finish_console_register cdns putc=1, getc=1, flush=1 + finish_console_register cdns putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7 @@ -197,7 +197,14 @@ cmp x0, #0 ASM_ASSERT(ne) #endif /* ENABLE_ASSERTIONS */ - /* Placeholder */ + /* Loop until the transmit FIFO is empty */ +check_txfifo_empty: + ldr w2, [x0, #R_UART_SR] + tbz w2, #UART_SR_INTR_TEMPTY_BIT, check_txfifo_empty + /* Wait until the Transmit is Inactive */ +check_tx_inactive_state: + ldr w2, [x0, #R_UART_SR] + tbnz w2, #UART_SR_INTR_TACTIVE_BIT, check_tx_inactive_state ret endfunc console_cdns_core_flush
diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S index a9e13ec..05a5985 100644 --- a/drivers/console/aarch32/skeleton_console.S +++ b/drivers/console/aarch32/skeleton_console.S
@@ -63,7 +63,7 @@ * If any of the argument is unspecified, then the corresponding * entry in console_t is set to 0. */ - finish_console_register xxx putc=1, getc=1, flush=1 + finish_console_register xxx putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 /* Jump here if hardware init fails or parameters are invalid. */ register_fail:
diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S index 7ea2eec..3310d28 100644 --- a/drivers/console/aarch64/skeleton_console.S +++ b/drivers/console/aarch64/skeleton_console.S
@@ -63,7 +63,7 @@ * If any of the argument is unspecified, then the corresponding * entry in console_t is set to 0. */ - finish_console_register xxx putc=1, getc=1, flush=1 + finish_console_register xxx putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 /* Jump here if hardware init fails or parameters are invalid. */ register_fail:
diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c index 93c38d8..e962fff 100644 --- a/drivers/console/multi_console.c +++ b/drivers/console/multi_console.c
@@ -108,6 +108,7 @@ return EOF; } +#if ENABLE_CONSOLE_GETC int console_getc(void) { int err = ERROR_NO_VALID_CONSOLE; @@ -127,6 +128,7 @@ return err; } +#endif void console_flush(void) {
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S index c7eb165..a1eacbc 100644 --- a/drivers/marvell/uart/a3700_console.S +++ b/drivers/marvell/uart/a3700_console.S
@@ -140,7 +140,7 @@ mov x0, x6 mov x30, x7 - finish_console_register a3700, putc=1, getc=1, flush=1 + finish_console_register a3700, putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/drivers/measured_boot/rss/rss_measured_boot.c b/drivers/measured_boot/rss/rss_measured_boot.c index cf545a7..258aa8d 100644 --- a/drivers/measured_boot/rss/rss_measured_boot.c +++ b/drivers/measured_boot/rss/rss_measured_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,39 +32,42 @@ # error Invalid Measured Boot algorithm. #endif /* MBOOT_ALG_ID */ -/* Pointer to struct rss_mboot_metadata */ -static struct rss_mboot_metadata *plat_metadata_ptr; +#if ENABLE_ASSERTIONS +static bool null_arr(const uint8_t *signer_id, size_t signer_id_size) +{ + for (size_t i = 0U; i < signer_id_size; i++) { + if (signer_id[i] != 0U) { + return false; + } + } + + return true; +} +#endif /* ENABLE_ASSERTIONS */ /* Functions' declarations */ -void rss_measured_boot_init(void) +void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr) { - /* At this point it is expected that communication channel over MHU - * is already initialised by platform init. - */ - struct rss_mboot_metadata *metadata_ptr; - - /* Get pointer to platform's struct rss_mboot_metadata structure */ - plat_metadata_ptr = plat_rss_mboot_get_metadata(); - assert(plat_metadata_ptr != NULL); - - /* Use a local variable to preserve the value of the global pointer */ - metadata_ptr = plat_metadata_ptr; + assert(metadata_ptr != NULL); /* Init the non-const members of the metadata structure */ while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) { + assert(null_arr(metadata_ptr->signer_id, MBOOT_DIGEST_SIZE)); metadata_ptr->sw_type_size = strlen((const char *)&metadata_ptr->sw_type) + 1; metadata_ptr++; } } -int rss_mboot_measure_and_record(uintptr_t data_base, uint32_t data_size, +int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr, + uintptr_t data_base, uint32_t data_size, uint32_t data_id) { unsigned char hash_data[CRYPTO_MD_MAX_SIZE]; int rc; psa_status_t ret; - const struct rss_mboot_metadata *metadata_ptr = plat_metadata_ptr; + + assert(metadata_ptr != NULL); /* Get the metadata associated with this image. */ while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) && @@ -103,35 +106,54 @@ return 0; } -int rss_mboot_set_signer_id(unsigned int img_id, +int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr, + const void *pk_oid, const void *pk_ptr, size_t pk_len) { unsigned char hash_data[CRYPTO_MD_MAX_SIZE]; - struct rss_mboot_metadata *metadata_ptr = plat_metadata_ptr; int rc; + bool hash_calc_done = false; - /* Get the metadata associated with this image. */ - while ((metadata_ptr->id != RSS_MBOOT_INVALID_ID) && - (metadata_ptr->id != img_id)) { + assert(metadata_ptr != NULL); + + /* + * Do an exhaustive search over the platform metadata to find + * all images whose key OID matches the one passed in argument. + * + * Note that it is not an error if do not get any matches. + * The platform may decide not to measure all of the images + * in the system. + */ + while (metadata_ptr->id != RSS_MBOOT_INVALID_ID) { + /* Get the metadata associated with this key-oid */ + if (metadata_ptr->pk_oid == pk_oid) { + if (!hash_calc_done) { + /* Calculate public key hash */ + rc = crypto_mod_calc_hash(CRYPTO_MD_ID, + (void *)pk_ptr, + pk_len, hash_data); + if (rc != 0) { + return rc; + } + + hash_calc_done = true; + } + + /* + * Fill the signer-ID field with the newly/already + * computed hash of the public key and update its + * signer ID size field with compile-time decided + * digest size. + */ + (void)memcpy(metadata_ptr->signer_id, + hash_data, + MBOOT_DIGEST_SIZE); + metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE; + } + metadata_ptr++; } - /* If image is not present in metadata array then skip */ - if (metadata_ptr->id == RSS_MBOOT_INVALID_ID) { - return 0; - } - - /* Calculate public key hash */ - rc = crypto_mod_calc_hash(CRYPTO_MD_ID, (void *)pk_ptr, - pk_len, hash_data); - if (rc != 0) { - return rc; - } - - /* Update metadata struct with the received signer_id */ - (void)memcpy(metadata_ptr->signer_id, hash_data, MBOOT_DIGEST_SIZE); - metadata_ptr->signer_id_size = MBOOT_DIGEST_SIZE; - return 0; }
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 57f4748..b51e744 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c
@@ -83,7 +83,7 @@ static int mmc_device_state(void) { int retries = MMC_DEFAULT_MAX_RETRIES; - unsigned int resp_data[4]; + unsigned int resp_data[4] = {0}; do { int ret;
diff --git a/drivers/mtd/nand/raw_nand.c b/drivers/mtd/nand/raw_nand.c index 021e30b..3595c21 100644 --- a/drivers/mtd/nand/raw_nand.c +++ b/drivers/mtd/nand/raw_nand.c
@@ -218,6 +218,18 @@ return -ETIMEDOUT; } +static int nand_reset(void) +{ + int ret; + + ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX); + if (ret != 0) { + return ret; + } + + return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U); +} + #if NAND_ONFI_DETECT static uint16_t nand_check_crc(uint16_t crc, uint8_t *data_in, unsigned int data_len) @@ -265,18 +277,6 @@ return nand_read_data(id, size, true); } -static int nand_reset(void) -{ - int ret; - - ret = nand_send_cmd(NAND_CMD_RESET, NAND_TWB_MAX); - if (ret != 0) { - return ret; - } - - return nand_send_wait(PSEC_TO_MSEC(NAND_TRST_MAX), 0U); -} - static int nand_read_param_page(void) { struct nand_param_page page; @@ -346,11 +346,6 @@ int ret; char id[4]; - ret = nand_reset(); - if (ret != 0) { - return ret; - } - ret = nand_read_id(ONFI_SIGNATURE_ADDR, (uint8_t *)id, sizeof(id)); if (ret != 0) { return ret; @@ -406,6 +401,8 @@ int nand_raw_init(unsigned long long *size, unsigned int *erase_size) { + int ret; + rawnand_dev.nand_dev = get_nand_device(); if (rawnand_dev.nand_dev == NULL) { return -EINVAL; @@ -420,6 +417,11 @@ return -ENODEV; } + ret = nand_reset(); + if (ret != 0) { + return ret; + } + #if NAND_ONFI_DETECT if (detect_onfi() != 0) { WARN("Detect ONFI failed\n");
diff --git a/drivers/mtd/nand/spi_nand.c b/drivers/mtd/nand/spi_nand.c index 542b614..744383a 100644 --- a/drivers/mtd/nand/spi_nand.c +++ b/drivers/mtd/nand/spi_nand.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #define SPI_NAND_MAX_ID_LEN 4U #define DELAY_US_400MS 400000U -#define MACRONIX_ID 0xC2U static struct spinand_device spinand_dev; @@ -91,7 +90,7 @@ { bool enable = false; - if (manufacturer_id != MACRONIX_ID) { + if ((spinand_dev.flags & SPI_NAND_HAS_QE_BIT) == 0U) { return 0; }
diff --git a/drivers/nxp/console/16550_console.S b/drivers/nxp/console/16550_console.S index 044d3d0..b5617a3 100644 --- a/drivers/nxp/console/16550_console.S +++ b/drivers/nxp/console/16550_console.S
@@ -167,7 +167,7 @@ register_16550: mov x0, x6 mov x30, x7 - finish_console_register 16550 putc=1, getc=1, flush=1 + finish_console_register 16550 putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/drivers/nxp/trdc/imx_trdc.c b/drivers/nxp/trdc/imx_trdc.c new file mode 100644 index 0000000..ab66585 --- /dev/null +++ b/drivers/nxp/trdc/imx_trdc.c
@@ -0,0 +1,365 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> + +#include <common/bl_common.h> +#include <common/debug.h> +#include <drivers/nxp/trdc/imx_trdc.h> +#include <lib/mmio.h> + + +int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst, + uint32_t mda_reg, uint8_t sa, uint8_t dids, + uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid) +{ + uint32_t val = mmio_read_32(trdc_base + MDAC_W_X(mda_inst, mda_reg)); + /* invalid: config non-cpu master with cpu config format. */ + if ((val & MDA_DFMT) != 0U) { + return -EINVAL; + } + + val = MDA_VLD | MDA_DFMT0_DID(pid) | MDA_DFMT0_PIDM(pidm) | MDA_DFMT0_PE(pe) | + MDA_DFMT0_SA(sa) | MDA_DFMT0_DIDS(dids) | MDA_DFMT0_DID(did); + + mmio_write_32(trdc_base + MDAC_W_X(mda_inst, mda_reg), val); + + return 0; +} + +int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst, + bool did_bypass, uint8_t sa, uint8_t pa, + uint8_t did) +{ + uint32_t val = mmio_read_32(trdc_base + MDAC_W_X(mda_inst, 0)); + + /* invalid: config cpu master with non-cpu config format. */ + if ((val & MDA_DFMT) == 0U) { + return -EINVAL; + } + + val = MDA_VLD | MDA_DFMT1_SA(sa) | MDA_DFMT1_PA(pa) | MDA_DFMT1_DID(did) | + MDA_DFMT1_DIDB(did_bypass ? 1U : 0U); + + mmio_write_32(trdc_base + MDAC_W_X(mda_inst, 0), val); + + return 0; +} + +static uintptr_t trdc_get_mbc_base(uintptr_t trdc_reg, uint32_t mbc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + uint32_t mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + + if (mbc_x >= mbc_num) { + return 0U; + } + + return trdc_reg + 0x10000 + 0x2000 * mbc_x; +} + +static uintptr_t trdc_get_mrc_base(uintptr_t trdc_reg, uint32_t mrc_x) +{ + struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg; + uint32_t mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0); + uint32_t mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0); + + if (mrc_x >= mrc_num) { + return 0U; + } + + return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x; +} + +uint32_t trdc_mbc_blk_num(uintptr_t trdc_reg, uint32_t mbc_x, uint32_t mem_x) +{ + uint32_t glbcfg; + struct mbc_mem_dom *mbc_dom; + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + + if (mbc_base == NULL) { + return 0; + } + + /* only first dom has the glbcfg */ + mbc_dom = &mbc_base->mem_dom[0]; + glbcfg = mmio_read_32((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]); + + return MBC_BLK_NUM(glbcfg); +} + +uint32_t trdc_mrc_rgn_num(uintptr_t trdc_reg, uint32_t mrc_x) +{ + uint32_t glbcfg; + struct mrc_rgn_dom *mrc_dom; + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + + if (mrc_base == NULL) { + return 0; + } + + /* only first dom has the glbcfg */ + mrc_dom = &mrc_base->mrc_dom[0]; + glbcfg = mmio_read_32((uintptr_t)&mrc_dom->mrc_glbcfg[0]); + + return MBC_BLK_NUM(glbcfg); +} + +int trdc_mbc_set_control(uintptr_t trdc_reg, uint32_t mbc_x, + uint32_t glbac_id, uint32_t glbac_val) +{ + struct mbc_mem_dom *mbc_dom; + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + + if (mbc_base == NULL || glbac_id >= GLBAC_NUM) { + return -EINVAL; + } + + /* only first dom has the glbac */ + mbc_dom = &mbc_base->mem_dom[0]; + + mmio_write_32((uintptr_t)&mbc_dom->memn_glbac[glbac_id], glbac_val); + + return 0; +} + +int trdc_mbc_blk_config(uintptr_t trdc_reg, uint32_t mbc_x, + uint32_t dom_x, uint32_t mem_x, uint32_t blk_x, + bool sec_access, uint32_t glbac_id) +{ + uint32_t *cfg_w; + uint32_t index, offset, val; + struct mbc_mem_dom *mbc_dom; + struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x); + + if (mbc_base == NULL || glbac_id >= GLBAC_NUM) { + return -EINVAL; + } + + mbc_dom = &mbc_base->mem_dom[dom_x]; + + switch (mem_x) { + case 0: + cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; + break; + case 1: + cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; + break; + case 2: + cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; + break; + case 3: + cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; + break; + default: + return -EINVAL; + }; + + index = blk_x % 8; + offset = index * 4; + + val = mmio_read_32((uintptr_t)cfg_w); + val &= ~(0xF << offset); + + /* + * MBC0-3 + * Global 0, 0x7777 secure pri/user read/write/execute, + * S400 has already set it. So select MBC0_MEMN_GLBAC0 + */ + if (sec_access) { + val |= ((0x0 | (glbac_id & 0x7)) << offset); + mmio_write_32((uintptr_t)cfg_w, val); + } else { + /* nse bit set */ + val |= ((0x8 | (glbac_id & 0x7)) << offset); + mmio_write_32((uintptr_t)cfg_w, val); + } + + return 0; +} + +int trdc_mrc_set_control(uintptr_t trdc_reg, uint32_t mrc_x, + uint32_t glbac_id, uint32_t glbac_val) +{ + struct mrc_rgn_dom *mrc_dom; + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + + if (mrc_base == NULL || glbac_id >= GLBAC_NUM) { + return -EINVAL; + } + + /* only first dom has the glbac */ + mrc_dom = &mrc_base->mrc_dom[0]; + + mmio_write_32((uintptr_t)&mrc_dom->memn_glbac[glbac_id], glbac_val); + + return 0; +} + +int trdc_mrc_rgn_config(uintptr_t trdc_reg, uint32_t mrc_x, + uint32_t dom_x, uint32_t rgn_id, + uint32_t addr_start, uint32_t addr_size, + bool sec_access, uint32_t glbac_id) +{ + uint32_t *desc_w; + uint32_t addr_end; + struct mrc_rgn_dom *mrc_dom; + struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x); + + if (mrc_base == NULL || glbac_id >= GLBAC_NUM || rgn_id >= MRC_REG_ALL) { + return -EINVAL; + } + + mrc_dom = &mrc_base->mrc_dom[dom_x]; + + addr_end = addr_start + addr_size - 1; + addr_start &= ~0x3fff; + addr_end &= ~0x3fff; + + desc_w = &mrc_dom->rgn_desc_words[rgn_id][0]; + + if (sec_access) { + mmio_write_32((uintptr_t)desc_w, addr_start | (glbac_id & 0x7)); + mmio_write_32((uintptr_t)(desc_w + 1), addr_end | 0x1); + } else { + mmio_write_32((uintptr_t)desc_w, addr_start | (glbac_id & 0x7)); + mmio_write_32((uintptr_t)(desc_w + 1), (addr_end | 0x1 | 0x10)); + } + + return 0; +} + +bool trdc_mrc_enabled(uintptr_t mrc_base) +{ + return (mmio_read_32(mrc_base) & BIT(15)); +} + +bool trdc_mbc_enabled(uintptr_t mbc_base) +{ + return (mmio_read_32(mbc_base) & BIT(14)); +} + +static bool is_trdc_mgr_slot(uintptr_t trdc_base, uint8_t mbc_id, + uint8_t mem_id, uint16_t blk_id) +{ + unsigned int i; + + for (i = 0U; i < trdc_mgr_num; i++) { + if (trdc_mgr_blks[i].trdc_base == trdc_base) { + if (mbc_id == trdc_mgr_blks[i].mbc_id && + mem_id == trdc_mgr_blks[i].mbc_mem_id && + (blk_id == trdc_mgr_blks[i].blk_mgr || + blk_id == trdc_mgr_blks[i].blk_mc)) { + return true; + } + } + } + + return false; +} + +/* + * config the TRDC MGR & MC's access policy. only the secure privilege + * mode SW can access it. + */ +void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr) +{ + unsigned int i; + + /* + * If the MBC is global enabled, need to cconfigure the MBCs of + * TRDC MGR & MC correctly. + */ + if (trdc_mbc_enabled(mgr->trdc_base)) { + /* ONLY secure privilige can access */ + trdc_mbc_set_control(mgr->trdc_base, mgr->mbc_id, 7, 0x6000); + for (i = 0U; i < 16U; i++) { + trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, i, + mgr->mbc_mem_id, mgr->blk_mgr, true, 7); + + trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, i, + mgr->mbc_mem_id, mgr->blk_mc, true, 7); + } + } +} + +/* + * Set up the TRDC access policy for all the resources under + * the TRDC control. + */ +void trdc_setup(struct trdc_config_info *cfg) +{ + unsigned int i, j, num; + bool is_mgr; + + /* config the MRCs */ + if (trdc_mrc_enabled(cfg->trdc_base)) { + /* set global access policy */ + for (i = 0U; i < cfg->num_mrc_glbac; i++) { + trdc_mrc_set_control(cfg->trdc_base, + cfg->mrc_glbac[i].mbc_mrc_id, + cfg->mrc_glbac[i].glbac_id, + cfg->mrc_glbac[i].glbac_val); + } + + /* set each MRC region access policy */ + for (i = 0U; i < cfg->num_mrc_cfg; i++) { + trdc_mrc_rgn_config(cfg->trdc_base, cfg->mrc_cfg[i].mrc_id, + cfg->mrc_cfg[i].dom_id, + cfg->mrc_cfg[i].region_id, + cfg->mrc_cfg[i].region_start, + cfg->mrc_cfg[i].region_size, + cfg->mrc_cfg[i].secure, + cfg->mrc_cfg[i].glbac_id); + } + } + + /* config the MBCs */ + if (trdc_mbc_enabled(cfg->trdc_base)) { + /* set MBC global access policy */ + for (i = 0U; i < cfg->num_mbc_glbac; i++) { + trdc_mbc_set_control(cfg->trdc_base, + cfg->mbc_glbac[i].mbc_mrc_id, + cfg->mbc_glbac[i].glbac_id, + cfg->mbc_glbac[i].glbac_val); + } + + for (i = 0U; i < cfg->num_mbc_cfg; i++) { + if (cfg->mbc_cfg[i].blk_id == MBC_BLK_ALL) { + num = trdc_mbc_blk_num(cfg->trdc_base, + cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].mem_id); + + for (j = 0U; j < num; j++) { + /* Skip mgr and mc */ + is_mgr = is_trdc_mgr_slot(cfg->trdc_base, + cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].mem_id, j); + if (is_mgr) { + continue; + } + + trdc_mbc_blk_config(cfg->trdc_base, + cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].dom_id, + cfg->mbc_cfg[i].mem_id, j, + cfg->mbc_cfg[i].secure, + cfg->mbc_cfg[i].glbac_id); + } + } else { + trdc_mbc_blk_config(cfg->trdc_base, + cfg->mbc_cfg[i].mbc_id, + cfg->mbc_cfg[i].dom_id, + cfg->mbc_cfg[i].mem_id, + cfg->mbc_cfg[i].blk_id, + cfg->mbc_cfg[i].secure, + cfg->mbc_cfg[i].glbac_id); + } + } + } +}
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c index 1881c91..c60820d 100644 --- a/drivers/partition/partition.c +++ b/drivers/partition/partition.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,30 +49,43 @@ static int load_mbr_header(uintptr_t image_handle, mbr_entry_t *mbr_entry) { size_t bytes_read; - uintptr_t offset; int result; + mbr_entry_t *tmp; assert(mbr_entry != NULL); /* MBR partition table is in LBA0. */ result = io_seek(image_handle, IO_SEEK_SET, MBR_OFFSET); if (result != 0) { - WARN("Failed to seek (%i)\n", result); + VERBOSE("Failed to seek (%i)\n", result); return result; } result = io_read(image_handle, (uintptr_t)&mbr_sector, PLAT_PARTITION_BLOCK_SIZE, &bytes_read); - if (result != 0) { - WARN("Failed to read data (%i)\n", result); + if ((result != 0) || (bytes_read != PLAT_PARTITION_BLOCK_SIZE)) { + VERBOSE("Failed to read data (%i)\n", result); return result; } /* Check MBR boot signature. */ if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { + VERBOSE("MBR boot signature failure\n"); return -ENOENT; } - offset = (uintptr_t)&mbr_sector + MBR_PRIMARY_ENTRY_OFFSET; - memcpy(mbr_entry, (void *)offset, sizeof(mbr_entry_t)); + + tmp = (mbr_entry_t *)(&mbr_sector[MBR_PRIMARY_ENTRY_OFFSET]); + + if (tmp->first_lba != 1) { + VERBOSE("MBR header may have an invalid first LBA\n"); + return -EINVAL; + } + + if ((tmp->sector_nums == 0) || (tmp->sector_nums == UINT32_MAX)) { + VERBOSE("MBR header entry has an invalid number of sectors\n"); + return -EINVAL; + } + + memcpy(mbr_entry, tmp, sizeof(mbr_entry_t)); return 0; } @@ -80,24 +93,31 @@ * Load GPT header and check the GPT signature and header CRC. * If partition numbers could be found, check & update it. */ -static int load_gpt_header(uintptr_t image_handle) +static int load_gpt_header(uintptr_t image_handle, size_t header_offset, + unsigned long long *part_lba) { gpt_header_t header; size_t bytes_read; int result; uint32_t header_crc, calc_crc; - result = io_seek(image_handle, IO_SEEK_SET, GPT_HEADER_OFFSET); + result = io_seek(image_handle, IO_SEEK_SET, header_offset); if (result != 0) { + VERBOSE("Failed to seek into the GPT image at offset (%zu)\n", + header_offset); return result; } result = io_read(image_handle, (uintptr_t)&header, sizeof(gpt_header_t), &bytes_read); if ((result != 0) || (sizeof(gpt_header_t) != bytes_read)) { + VERBOSE("GPT header read error(%i) or read mismatch occurred," + "expected(%zu) and actual(%zu)\n", result, + sizeof(gpt_header_t), bytes_read); return result; } if (memcmp(header.signature, GPT_SIGNATURE, - sizeof(header.signature)) != 0) { + sizeof(header.signature)) != 0) { + VERBOSE("GPT header signature failure\n"); return -EINVAL; } @@ -109,7 +129,7 @@ header_crc = header.header_crc; header.header_crc = 0U; - calc_crc = tf_crc32(0U, (uint8_t *)&header, DEFAULT_GPT_HEADER_SIZE); + calc_crc = tf_crc32(0U, (uint8_t *)&header, sizeof(gpt_header_t)); if (header_crc != calc_crc) { ERROR("Invalid GPT Header CRC: Expected 0x%x but got 0x%x.\n", header_crc, calc_crc); @@ -123,11 +143,16 @@ if (list.entry_count > PLAT_PARTITION_MAX_ENTRIES) { list.entry_count = PLAT_PARTITION_MAX_ENTRIES; } + + *part_lba = header.part_lba; return 0; } +/* + * Load a single MBR entry based on details from MBR header. + */ static int load_mbr_entry(uintptr_t image_handle, mbr_entry_t *mbr_entry, - int part_number) + int part_number) { size_t bytes_read; uintptr_t offset; @@ -137,19 +162,20 @@ /* MBR partition table is in LBA0. */ result = io_seek(image_handle, IO_SEEK_SET, MBR_OFFSET); if (result != 0) { - WARN("Failed to seek (%i)\n", result); + VERBOSE("Failed to seek (%i)\n", result); return result; } result = io_read(image_handle, (uintptr_t)&mbr_sector, PLAT_PARTITION_BLOCK_SIZE, &bytes_read); if (result != 0) { - WARN("Failed to read data (%i)\n", result); + VERBOSE("Failed to read data (%i)\n", result); return result; } /* Check MBR boot signature. */ if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) || (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) { + VERBOSE("MBR Entry boot signature failure\n"); return -ENOENT; } offset = (uintptr_t)&mbr_sector + @@ -160,6 +186,9 @@ return 0; } +/* + * Load MBR entries based on max number of partition entries. + */ static int load_mbr_entries(uintptr_t image_handle) { mbr_entry_t mbr_entry; @@ -177,33 +206,60 @@ return 0; } +/* + * Try to read and load a single GPT entry. + */ static int load_gpt_entry(uintptr_t image_handle, gpt_entry_t *entry) { - size_t bytes_read; + size_t bytes_read = 0U; int result; assert(entry != NULL); result = io_read(image_handle, (uintptr_t)entry, sizeof(gpt_entry_t), - &bytes_read); - if (sizeof(gpt_entry_t) != bytes_read) + &bytes_read); + if ((result != 0) || (sizeof(gpt_entry_t) != bytes_read)) { + VERBOSE("GPT Entry read error(%i) or read mismatch occurred," + "expected(%zu) and actual(%zu)\n", result, + sizeof(gpt_entry_t), bytes_read); return -EINVAL; + } + return result; } -static int verify_partition_gpt(uintptr_t image_handle) +/* + * Retrieve each entry in the partition table, parse the data from each + * entry and store them in the list of partition table entries. + */ +static int load_partition_gpt(uintptr_t image_handle, + unsigned long long part_lba) { + const signed long long gpt_entry_offset = LBA(part_lba); gpt_entry_t entry; int result, i; + result = io_seek(image_handle, IO_SEEK_SET, gpt_entry_offset); + if (result != 0) { + VERBOSE("Failed to seek (%i), Failed loading GPT partition" + "table entries\n", result); + return result; + } + for (i = 0; i < list.entry_count; i++) { result = load_gpt_entry(image_handle, &entry); - assert(result == 0); + if (result != 0) { + VERBOSE("Failed to load gpt entry data(%i) error is (%i)\n", + i, result); + return result; + } + result = parse_gpt_entry(&entry, &list.list[i]); if (result != 0) { break; } } if (i == 0) { + VERBOSE("No Valid GPT Entries found\n"); return -EINVAL; } /* @@ -216,6 +272,94 @@ return 0; } +/* + * Try retrieving and parsing the backup-GPT header and backup GPT entries. + * Last 33 blocks contains the backup-GPT entries and header. + */ +static int load_backup_gpt(unsigned int image_id, unsigned int sector_nums) +{ + int result; + unsigned long long part_lba = 0; + size_t gpt_header_offset; + uintptr_t dev_handle, image_spec, image_handle; + io_block_spec_t *block_spec; + int part_num_entries; + + result = plat_get_image_source(image_id, &dev_handle, &image_spec); + if (result != 0) { + VERBOSE("Failed to obtain reference to image id=%u (%i)\n", + image_id, result); + return result; + } + + block_spec = (io_block_spec_t *)image_spec; + /* + * We need to read 32 blocks of GPT entries and one block of GPT header + * try mapping only last 33 last blocks from the image to read the + * Backup-GPT header and its entries. + */ + part_num_entries = (PLAT_PARTITION_MAX_ENTRIES / 4); + /* Move the offset base to LBA-33 */ + block_spec->offset += LBA(sector_nums - part_num_entries); + /* + * Set length as LBA-33, 32 blocks of backup-GPT entries and one + * block of backup-GPT header. + */ + block_spec->length = LBA(part_num_entries + 1); + + result = io_open(dev_handle, image_spec, &image_handle); + if (result != 0) { + VERBOSE("Failed to access image id (%i)\n", result); + return result; + } + + INFO("Trying to retrieve back-up GPT header\n"); + /* Last block is backup-GPT header, after the end of GPT entries */ + gpt_header_offset = LBA(part_num_entries); + result = load_gpt_header(image_handle, gpt_header_offset, &part_lba); + if ((result != 0) || (part_lba == 0)) { + ERROR("Failed to retrieve Backup GPT header," + "Partition maybe corrupted\n"); + goto out; + } + + /* + * Note we mapped last 33 blocks(LBA-33), first block here starts with + * entries while last block was header. + */ + result = load_partition_gpt(image_handle, 0); + +out: + io_close(image_handle); + return result; +} + +/* + * Load a GPT partition, Try retrieving and parsing the primary GPT header, + * if its corrupted try loading backup GPT header and then retrieve list + * of partition table entries found from the GPT. + */ +static int load_primary_gpt(uintptr_t image_handle, unsigned int first_lba) +{ + int result; + unsigned long long part_lba; + size_t gpt_header_offset; + + /* Try to load Primary GPT header from LBA1 */ + gpt_header_offset = LBA(first_lba); + result = load_gpt_header(image_handle, gpt_header_offset, &part_lba); + if ((result != 0) || (part_lba == 0)) { + VERBOSE("Failed to retrieve Primary GPT header," + "trying to retrieve back-up GPT header\n"); + return result; + } + + return load_partition_gpt(image_handle, part_lba); +} + +/* + * Load the partition table info based on the image id provided. + */ int load_partition_table(unsigned int image_id) { uintptr_t dev_handle, image_handle, image_spec = 0; @@ -224,36 +368,41 @@ result = plat_get_image_source(image_id, &dev_handle, &image_spec); if (result != 0) { - WARN("Failed to obtain reference to image id=%u (%i)\n", + VERBOSE("Failed to obtain reference to image id=%u (%i)\n", image_id, result); return result; } result = io_open(dev_handle, image_spec, &image_handle); if (result != 0) { - WARN("Failed to access image id=%u (%i)\n", image_id, result); + VERBOSE("Failed to access image id=%u (%i)\n", image_id, result); return result; } result = load_mbr_header(image_handle, &mbr_entry); if (result != 0) { - WARN("Failed to access image id=%u (%i)\n", image_id, result); - return result; + VERBOSE("Failed to access image id=%u (%i)\n", image_id, result); + goto out; } if (mbr_entry.type == PARTITION_TYPE_GPT) { - result = load_gpt_header(image_handle); - assert(result == 0); - result = io_seek(image_handle, IO_SEEK_SET, GPT_ENTRY_OFFSET); - assert(result == 0); - result = verify_partition_gpt(image_handle); + result = load_primary_gpt(image_handle, mbr_entry.first_lba); + if (result != 0) { + io_close(image_handle); + return load_backup_gpt(BKUP_GPT_IMAGE_ID, + mbr_entry.sector_nums); + } } else { result = load_mbr_entries(image_handle); } +out: io_close(image_handle); return result; } +/* + * Try retrieving a partition table entry based on the name of the partition. + */ const partition_entry_t *get_partition_entry(const char *name) { int i; @@ -266,6 +415,9 @@ return NULL; } +/* + * Try retrieving a partition table entry based on the GUID. + */ const partition_entry_t *get_partition_entry_by_type(const uuid_t *type_uuid) { int i; @@ -279,6 +431,9 @@ return NULL; } +/* + * Try retrieving a partition table entry based on the UUID. + */ const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid) { int i; @@ -292,12 +447,32 @@ return NULL; } +/* + * Return entry to the list of partition table entries. + */ const partition_entry_list_t *get_partition_entry_list(void) { return &list; } +/* + * Try loading partition table info for the given image ID. + */ void partition_init(unsigned int image_id) { - load_partition_table(image_id); + int ret; + + ret = load_partition_table(image_id); + if (ret != 0) { + ERROR("Failed to parse partition with image id = %u\n", + image_id); + } +} + +/* + * Load a GPT based image. + */ +int gpt_partition_init(void) +{ + return load_partition_table(GPT_IMAGE_ID); }
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c index 8d002de..3f6a948 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1180,6 +1180,11 @@ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_TOP_PLL_CTRL )); + if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_LOW_FREQ_SEL), + _cnf_DDR_PHY_ADR_G_REGSET[0x7f & ddr_regdef_adr( + _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)]); + } } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), @@ -2856,6 +2861,16 @@ timeout = wait_freqchgreq(1); + if ((!((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))) && (on)) { + if (((1600U * ddr_mbpsdiv) < ddr_mbps) || (prr_product == PRR_PRODUCT_M3)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x01421142U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000142U); + } else { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x03421342U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000342U); + } + } + if (timeout) { return 1; }
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h index 3cb1975..328adbf 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
@@ -1,11 +1,11 @@ /* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#define RCAR_DDR_VERSION "rev.0.41" +#define RCAR_DDR_VERSION "rev.0.42" #define DRAM_CH_CNT 0x04 #define SLICE_CNT 0x04 #define CS_CNT 0x02
diff --git a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h index e5258af..5a662ec 100644 --- a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h +++ b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -230,8 +230,8 @@ /*0693*/ 0x00000000, /*0694*/ 0x00000000, /*0695*/ 0x00005064, - /*0696*/ 0x01421142, - /*0697*/ 0x00000142, + /*0696*/ 0x05421542, + /*0697*/ 0x00000542, /*0698*/ 0x00000000, /*0699*/ 0x000f1100, /*069a*/ 0x0f110f11, @@ -240,12 +240,12 @@ /*069d*/ 0x0002c000, /*069e*/ 0x02c002c0, /*069f*/ 0x000002c0, - /*06a0*/ 0x03421342, - /*06a1*/ 0x00000342, + /*06a0*/ 0x05421542, + /*06a1*/ 0x00000542, /*06a2*/ 0x00000000, /*06a3*/ 0x00000000, /*06a4*/ 0x05020000, - /*06a5*/ 0x14000000, + /*06a5*/ 0x14000001, /*06a6*/ 0x027f6e00, /*06a7*/ 0x047f027f, /*06a8*/ 0x00027f6e,
diff --git a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h index b491f0e..482a2a5 100644 --- a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h +++ b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -210,8 +210,8 @@ /*0b8b*/ 0x01010100, /*0b8c*/ 0x00000600, /*0b8d*/ 0x50640000, - /*0b8e*/ 0x01421142, - /*0b8f*/ 0x00000142, + /*0b8e*/ 0x03421342, + /*0b8f*/ 0x00000342, /*0b90*/ 0x00000000, /*0b91*/ 0x000f1600, /*0b92*/ 0x0f160f16,
diff --git a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h index fb3032d..436c1a0 100644 --- a/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h +++ b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -230,8 +230,8 @@ /*0b93*/ 0x00000000, /*0b94*/ 0x00000000, /*0b95*/ 0x00005064, - /*0b96*/ 0x01421142, - /*0b97*/ 0x00000142, + /*0b96*/ 0x05421542, + /*0b97*/ 0x00000542, /*0b98*/ 0x00000000, /*0b99*/ 0x000f1600, /*0b9a*/ 0x0f160f16, @@ -241,12 +241,12 @@ /*0b9e*/ 0x02c002c0, /*0b9f*/ 0x000002c0, /*0ba0*/ 0x08040201, - /*0ba1*/ 0x03421342, - /*0ba2*/ 0x00000342, + /*0ba1*/ 0x05421542, + /*0ba2*/ 0x00000542, /*0ba3*/ 0x00000000, /*0ba4*/ 0x00000000, /*0ba5*/ 0x05030000, - /*0ba6*/ 0x00010700, + /*0ba6*/ 0x00010701, /*0ba7*/ 0x00000014, /*0ba8*/ 0x00027f6e, /*0ba9*/ 0x047f027f,
diff --git a/drivers/renesas/rcar/board/board.h b/drivers/renesas/rcar/board/board.h index 51a8e30..2346911 100644 --- a/drivers/renesas/rcar/board/board.h +++ b/drivers/renesas/rcar/board/board.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights + * Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights * reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -11,13 +11,13 @@ #define BOARD_SALVATOR_X (0x00) #define BOARD_KRIEK (0x01) #define BOARD_STARTER_KIT (0x02) +#define BOARD_EAGLE (0x03) #define BOARD_SALVATOR_XS (0x04) +#define BOARD_DRAAK (0x07) #define BOARD_EBISU (0x08) #define BOARD_STARTER_KIT_PRE (0x0B) -#define BOARD_EBISU_4D (0x0DU) -#define BOARD_DRAAK (0x0EU) -#define BOARD_EAGLE (0x0FU) -#define BOARD_UNKNOWN (BOARD_EAGLE + 1U) +#define BOARD_EBISU_4D (0x0D) +#define BOARD_UNKNOWN (BOARD_EBISU_4D + 1U) #define BOARD_REV_UNKNOWN (0xFF)
diff --git a/drivers/scmi-msg/clock.c b/drivers/scmi-msg/clock.c index 98fdc6a..5aaf68c 100644 --- a/drivers/scmi-msg/clock.c +++ b/drivers/scmi-msg/clock.c
@@ -37,7 +37,8 @@ int32_t plat_scmi_clock_rates_array(unsigned int agent_id __unused, unsigned int scmi_id __unused, unsigned long *rates __unused, - size_t *nb_elts __unused) + size_t *nb_elts __unused, + uint32_t start_idx __unused) { return SCMI_NOT_SUPPORTED; } @@ -298,7 +299,7 @@ /* Platform may support array rate description */ status = plat_scmi_clock_rates_array(msg->agent_id, clock_id, NULL, - &nb_rates); + &nb_rates, 0); if (status == SCMI_SUCCESS) { /* Currently 12 cells mex, so it's affordable for the stack */ unsigned long plat_rates[RATES_ARRAY_SIZE_MAX / RATE_DESC_SIZE]; @@ -307,7 +308,8 @@ size_t rem_nb = nb_rates - in_args->rate_index - ret_nb; status = plat_scmi_clock_rates_array(msg->agent_id, clock_id, - plat_rates, &ret_nb); + plat_rates, &ret_nb, + in_args->rate_index); if (status == SCMI_SUCCESS) { write_rate_desc_array_in_buffer(msg->out + sizeof(p2a), plat_rates, ret_nb);
diff --git a/drivers/st/clk/clk-stm32mp13.c b/drivers/st/clk/clk-stm32mp13.c index db427ad..01d1764 100644 --- a/drivers/st/clk/clk-stm32mp13.c +++ b/drivers/st/clk/clk-stm32mp13.c
@@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -1216,7 +1216,7 @@ * => deactivate CKPER only after switching clock */ if (ckper_disabled) { - ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED & CMD_MASK); + ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED); if (ret != 0) { return ret; }
diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c index 01d1420..379547f 100644 --- a/drivers/st/clk/stm32mp_clkfunc.c +++ b/drivers/st/clk/stm32mp_clkfunc.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -248,6 +248,7 @@ return cuint; } +#if defined(IMAGE_BL32) /* * Get the secure state for rcc node in device tree. * @return: true if rcc is configured for secure world access, false if not. @@ -266,6 +267,7 @@ return true; } +#endif /* * Get the clock ID of the given node in device tree. @@ -320,6 +322,19 @@ } /******************************************************************************* + * This function sets the STGEN counter value. + ******************************************************************************/ +static void stgen_set_counter(unsigned long long counter) +{ +#ifdef __aarch64__ + mmio_write_64(STGEN_BASE + CNTCV_OFF, counter); +#else + mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); + mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); +#endif +} + +/******************************************************************************* * This function configures and restores the STGEN counter depending on the * connected clock. ******************************************************************************/ @@ -337,8 +352,7 @@ mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); counter = stm32mp_stgen_get_counter() * rate / cntfid0; - mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); - mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); + stgen_set_counter(counter); mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); @@ -353,8 +367,12 @@ ******************************************************************************/ unsigned long long stm32mp_stgen_get_counter(void) { +#ifdef __aarch64__ + return mmio_read_64(STGEN_BASE + CNTCV_OFF); +#else return (((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | mmio_read_32(STGEN_BASE + CNTCVL_OFF)); +#endif } /******************************************************************************* @@ -371,7 +389,6 @@ mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U); mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); - mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); - mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); + stgen_set_counter(cnt); mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); }
diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c index 1e7c42c..3054577 100644 --- a/drivers/st/crypto/stm32_pka.c +++ b/drivers/st/crypto/stm32_pka.c
@@ -33,10 +33,10 @@ #define UINT8_LEN 8U #define UINT64_LEN (UINT8_LEN * sizeof(uint64_t)) -#define WORD_SIZE (sizeof(uint64_t)) +#define PKA_WORD_SIZE (sizeof(uint64_t)) #define OP_NBW_FROM_LEN(len) (DIV_ROUND_UP_2EVAL((len), UINT64_LEN) + 1) #define OP_NBW_FROM_SIZE(s) OP_NBW_FROM_LEN((s) * UINT8_LEN) -#define OP_SIZE_FROM_SIZE(s) (OP_NBW_FROM_SIZE(s) * WORD_SIZE) +#define OP_SIZE_FROM_SIZE(s) (OP_NBW_FROM_SIZE(s) * PKA_WORD_SIZE) #define DT_PKA_COMPAT "st,stm32-pka64" @@ -56,7 +56,7 @@ #define _PKA_IPIDR 0x1FF8U /* PKA control register fields */ -#define _PKA_CR_MODE_MASK GENMASK(13, 8) +#define _PKA_CR_MODE_MASK GENMASK_32(13, 8) #define _PKA_CR_MODE_SHIFT 8U #define _PKA_CR_MODE_ADD 0x9U #define _PKA_CR_MODE_ECDSA_VERIF 0x26U @@ -69,7 +69,7 @@ #define _PKA_SR_INITOK BIT(0) /* PKA it flag fields (used in CR, SR and CLRFR) */ -#define _PKA_IT_MASK (GENMASK(21, 19) | BIT(17)) +#define _PKA_IT_MASK (GENMASK_32(21, 19) | BIT(17)) #define _PKA_IT_SHIFT 17U #define _PKA_IT_OPERR BIT(21) #define _PKA_IT_ADDRERR BIT(20) @@ -77,9 +77,9 @@ #define _PKA_IT_PROCEND BIT(17) /* PKA version register fields */ -#define _PKA_VERR_MAJREV_MASK GENMASK(7, 4) +#define _PKA_VERR_MAJREV_MASK GENMASK_32(7, 4) #define _PKA_VERR_MAJREV_SHIFT 4U -#define _PKA_VERR_MINREV_MASK GENMASK(3, 0) +#define _PKA_VERR_MINREV_MASK GENMASK_32(3, 0) #define _PKA_VERR_MINREV_SHIFT 0U /* RAM magic offset */
diff --git a/drivers/st/crypto/stm32_rng.c b/drivers/st/crypto/stm32_rng.c index a9dc43f..1342fd4 100644 --- a/drivers/st/crypto/stm32_rng.c +++ b/drivers/st/crypto/stm32_rng.c
@@ -187,6 +187,10 @@ count = 4U; while (len != 0U) { + if ((mmio_read_32(stm32_rng.base + RNG_SR) & RNG_SR_DRDY) == 0U) { + break; + } + data32 = mmio_read_32(stm32_rng.base + RNG_DR); count--;
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index b510c8f..c96fa04 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c
@@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -56,7 +56,8 @@ int ret; struct stm32mp_ddr_config config; int node; - uint32_t uret; + uintptr_t uret; + size_t retsize; void *fdt; const struct stm32mp_ddr_param param[] = { @@ -106,26 +107,28 @@ } uret = stm32mp_ddr_test_data_bus(); - if (uret != 0U) { - ERROR("DDR data bus test: can't access memory @ 0x%x\n", + if (uret != 0UL) { + ERROR("DDR data bus test: can't access memory @ 0x%lx\n", uret); panic(); } uret = stm32mp_ddr_test_addr_bus(config.info.size); - if (uret != 0U) { - ERROR("DDR addr bus test: can't access memory @ 0x%x\n", + if (uret != 0UL) { + ERROR("DDR addr bus test: can't access memory @ 0x%lx\n", uret); panic(); } - uret = stm32mp_ddr_check_size(); - if (uret < config.info.size) { - ERROR("DDR size: 0x%x does not match DT config: 0x%x\n", - uret, config.info.size); + retsize = stm32mp_ddr_check_size(); + if (retsize < config.info.size) { + ERROR("DDR size: 0x%zx does not match DT config: 0x%zx\n", + retsize, config.info.size); panic(); } + INFO("Memory size = 0x%zx (%zu MB)\n", retsize, retsize / (1024U * 1024U)); + if (stm32mp_unmap_ddr() != 0) { panic(); }
diff --git a/drivers/st/ddr/stm32mp_ddr_test.c b/drivers/st/ddr/stm32mp_ddr_test.c index 6733cc6..0f6aff1 100644 --- a/drivers/st/ddr/stm32mp_ddr_test.c +++ b/drivers/st/ddr/stm32mp_ddr_test.c
@@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,19 +18,19 @@ * Note that the previous content is restored after test. * Returns 0 if success, and address value else. ******************************************************************************/ -uint32_t stm32mp_ddr_test_rw_access(void) +uintptr_t stm32mp_ddr_test_rw_access(void) { uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE); mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { - return (uint32_t)STM32MP_DDR_BASE; + return STM32MP_DDR_BASE; } mmio_write_32(STM32MP_DDR_BASE, saved_value); - return 0U; + return 0UL; } /******************************************************************************* @@ -41,7 +41,7 @@ * File: memtest.c - This source code belongs to Public Domain. * Returns 0 if success, and address value else. ******************************************************************************/ -uint32_t stm32mp_ddr_test_data_bus(void) +uintptr_t stm32mp_ddr_test_data_bus(void) { uint32_t pattern; @@ -49,11 +49,11 @@ mmio_write_32(STM32MP_DDR_BASE, pattern); if (mmio_read_32(STM32MP_DDR_BASE) != pattern) { - return (uint32_t)STM32MP_DDR_BASE; + return STM32MP_DDR_BASE; } } - return 0; + return 0UL; } /******************************************************************************* @@ -65,38 +65,34 @@ * size: size in bytes of the DDR memory device. * Returns 0 if success, and address value else. ******************************************************************************/ -uint32_t stm32mp_ddr_test_addr_bus(uint64_t size) +uintptr_t stm32mp_ddr_test_addr_bus(size_t size) { - uint64_t addressmask = size - 1U; - uint64_t offset; - uint64_t testoffset = 0U; + size_t addressmask = size - 1U; + size_t offset; + size_t testoffset = 0U; /* Write the default pattern at each of the power-of-two offsets. */ for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1U) { - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset, - DDR_PATTERN); + mmio_write_32(STM32MP_DDR_BASE + offset, DDR_PATTERN); } /* Check for address bits stuck high. */ - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, - DDR_ANTIPATTERN); + mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN); for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1U) { - if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != - DDR_PATTERN) { - return (uint32_t)(STM32MP_DDR_BASE + offset); + if (mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) { + return STM32MP_DDR_BASE + offset; } } - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); + mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN); /* Check for address bits stuck low or shorted. */ for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; testoffset <<= 1U) { - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, - DDR_ANTIPATTERN); + mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN); if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { return STM32MP_DDR_BASE; @@ -104,18 +100,16 @@ for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { - if ((mmio_read_32(STM32MP_DDR_BASE + - (uint32_t)offset) != DDR_PATTERN) && + if ((mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) && (offset != testoffset)) { - return (uint32_t)(STM32MP_DDR_BASE + offset); + return STM32MP_DDR_BASE + offset; } } - mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, - DDR_PATTERN); + mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN); } - return 0U; + return 0UL; } /******************************************************************************* @@ -125,9 +119,9 @@ * restore its content. * Returns DDR computed size. ******************************************************************************/ -uint32_t stm32mp_ddr_check_size(void) +size_t stm32mp_ddr_check_size(void) { - uint32_t offset = sizeof(uint32_t); + size_t offset = sizeof(uint32_t); mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); @@ -142,7 +136,5 @@ offset <<= 1U; } - INFO("Memory size = 0x%x (%u MB)\n", offset, offset / (1024U * 1024U)); - return offset; }
diff --git a/drivers/st/ddr/stm32mp_ram.c b/drivers/st/ddr/stm32mp_ram.c index 0804568..28dc17d 100644 --- a/drivers/st/ddr/stm32mp_ram.c +++ b/drivers/st/ddr/stm32mp_ram.c
@@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,8 +23,8 @@ VERBOSE("%s: no st,mem-speed\n", __func__); return -EINVAL; } - ret = fdt_read_uint32(fdt, node, "st,mem-size", &info->size); - if (ret < 0) { + info->size = dt_get_ddr_size(); + if (info->size == 0U) { VERBOSE("%s: no st,mem-size\n", __func__); return -EINVAL; }
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c index 1ee3580..be722f3 100644 --- a/drivers/st/mmc/stm32_sdmmc2.c +++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2018-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -131,6 +131,12 @@ #define SDMMC_FIFO_SIZE 64U +#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ +#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ +#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ +#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ +#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ + static void stm32_sdmmc2_init(void); static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
diff --git a/drivers/st/regulator/regulator_fixed.c b/drivers/st/regulator/regulator_fixed.c index f1c224e..6c9d3b1 100644 --- a/drivers/st/regulator/regulator_fixed.c +++ b/drivers/st/regulator/regulator_fixed.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,8 +13,8 @@ #include <drivers/st/regulator_fixed.h> #include <libfdt.h> -#ifndef PLAT_NB_FIXED_REGS -#error "Missing PLAT_NB_FIXED_REGS" +#ifndef PLAT_NB_FIXED_REGUS +#error "Missing PLAT_NB_FIXED_REGUS" #endif #define FIXED_NAME_LEN 32 @@ -25,7 +25,7 @@ struct regul_description desc; }; -static struct fixed_data data[PLAT_NB_FIXED_REGS]; +static struct fixed_data data[PLAT_NB_FIXED_REGUS]; static int fixed_set_state(const struct regul_description *desc, bool state) { @@ -79,7 +79,7 @@ } count++; - assert(count <= PLAT_NB_FIXED_REGS); + assert(count <= PLAT_NB_FIXED_REGUS); }
diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S index e3e0e67..e063941 100644 --- a/drivers/st/uart/aarch32/stm32_console.S +++ b/drivers/st/uart/aarch32/stm32_console.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -234,11 +234,16 @@ cmp r0, #0 ASM_ASSERT(ne) #endif /* ENABLE_ASSERTIONS */ + /* Skip flush if UART is not enabled */ + ldr r1, [r0, #USART_CR1] + tst r1, #USART_CR1_UE + beq 1f /* Check Transmit Data Register Empty */ txe_loop_3: ldr r1, [r0, #USART_ISR] tst r1, #USART_ISR_TXE beq txe_loop_3 +1: bx lr endfunc console_stm32_core_flush
diff --git a/drivers/st/uart/aarch64/stm32_console.S b/drivers/st/uart/aarch64/stm32_console.S new file mode 100644 index 0000000..312b35d --- /dev/null +++ b/drivers/st/uart/aarch64/stm32_console.S
@@ -0,0 +1,255 @@ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <console_macros.S> +#include <drivers/st/stm32_console.h> +#include <drivers/st/stm32_uart_regs.h> + +#define USART_TIMEOUT 0x1000 + + /* + * "core" functions are low-level implementations that don't require + * writeable memory and are thus safe to call in BL1 crash context. + */ + .globl console_stm32_core_init + .globl console_stm32_core_putc + .globl console_stm32_core_getc + .globl console_stm32_core_flush + + .globl console_stm32_putc + .globl console_stm32_flush + + + + /* ----------------------------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, + * unsigned int baud_rate) + * + * Function to initialize the console without a C Runtime to print + * debug information. This function will be accessed by console_init + * and crash reporting. + * + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2, x3, x4 + * ----------------------------------------------- + */ +func console_stm32_core_init + /* Check the input base address */ + cbz x0, core_init_fail +#if !defined(IMAGE_BL2) +#if STM32MP_RECONFIGURE_CONSOLE + /* UART clock rate is set to 0 in BL32, skip init in that case */ + cbz x1, 1f +#else /* STM32MP_RECONFIGURE_CONSOLE */ + /* Skip UART initialization if it is already enabled */ + ldr w3, [x0, #USART_CR1] + tst w3, #USART_CR1_UE + b.ne 1f +#endif /* STM32MP_RECONFIGURE_CONSOLE */ +#endif /* IMAGE_BL2 */ + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + /* Disable UART */ + ldr w3, [x0, #USART_CR1] + mov w4, #USART_CR1_UE + bic w3, w3, w4 + str w3, [x0, #USART_CR1] + /* Configure UART */ + mov w4, #(USART_CR1_TE) + orr w4, w4, #(USART_CR1_FIFOEN) + orr w3, w3, w4 + str w3, [x0, #USART_CR1] + ldr w3, [x0, #USART_CR2] + mov w4, #USART_CR2_STOP + bic w3, w3, w4 + str w3, [x0, #USART_CR2] + /* Divisor = (Uart clock + (baudrate / 2)) / baudrate */ + lsr w3, w2, #1 + add w3, w1, w3 + udiv w3, w3, w2 + cmp w3, #16 + b.hi 2f + /* Oversampling 8 */ + /* Divisor = (2 * Uart clock + (baudrate / 2)) / baudrate */ + lsr w3, w2, #1 + add w3, w3, w1, lsl #1 + udiv w3, w3, w2 + and w1, w3, #USART_BRR_DIV_FRACTION + lsr w1, w1, #1 + bic w3, w3, #USART_BRR_DIV_FRACTION + orr w3, w3, w1 + ldr w1, [x0, #USART_CR1] + orr w1, w1, #USART_CR1_OVER8 + str w1, [x0, #USART_CR1] +2: + str w3, [x0, #USART_BRR] + /* Enable UART */ + ldr w3, [x0, #USART_CR1] + mov w4, #USART_CR1_UE + orr w3, w3, w4 + str w3, [x0, #USART_CR1] + /* Check TEACK bit */ + mov w2, #USART_TIMEOUT +teack_loop: + subs w2, w2, #1 + beq core_init_fail + ldr w3, [x0, #USART_ISR] + tst w3, #USART_ISR_TEACK + beq teack_loop +1: + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_stm32_core_init + + .globl console_stm32_register + + /* ------------------------------------------------------- + * int console_stm32_register(uintptr_t baseaddr, + * uint32_t clock, uint32_t baud, + * console_t *console); + * Function to initialize and register a new STM32 + * console. Storage passed in for the console struct + * *must* be persistent (i.e. not from the stack). + * In: x0 - UART register base address + * w1 - UART clock in Hz + * w2 - Baud rate + * x3 - pointer to empty console_t struct + * Out: return 1 on success, 0 on error + * Clobber list : x0, x1, x2, x6, x7, x14 + * ------------------------------------------------------- + */ +func console_stm32_register + mov x7, x30 + mov x6, x3 + cbz x6, register_fail + str x0, [x6, #CONSOLE_T_BASE] + + bl console_stm32_core_init + cbz x0, register_fail + + mov x0, x6 + mov x30, x7 + finish_console_register stm32 putc=1, getc=0, flush=1 + +register_fail: + ret x7 +endfunc console_stm32_register + + /* -------------------------------------------------------- + * int console_stm32_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_stm32_core_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + + /* Check Transmit Data Register Empty */ +txe_loop: + ldr w2, [x1, #USART_ISR] + tst w2, #USART_ISR_TXE + beq txe_loop + str w0, [x1, #USART_TDR] + /* Check transmit complete flag */ +tc_loop: + ldr w2, [x1, #USART_ISR] + tst w2, #USART_ISR_TC + beq tc_loop + ret +endfunc console_stm32_core_putc + + /* -------------------------------------------------------- + * int console_stm32_putc(int c, console_t *console) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - pointer to console_t structure + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_stm32_putc +#if ENABLE_ASSERTIONS + cmp x1, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x1, [x1, #CONSOLE_T_BASE] + b console_stm32_core_putc +endfunc console_stm32_putc + + /* --------------------------------------------- + * int console_stm32_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 if no character is available. + * In : x0 - console base address + * Out: w0 - character if available, else -1 + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_stm32_core_getc + /* Not supported */ + mov w0, #-1 + ret +endfunc console_stm32_core_getc + + /* --------------------------------------------- + * int console_stm32_core_flush(uintptr_t base_addr) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - console base address + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_stm32_core_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + /* Check Transmit Data Register Empty */ +txe_loop_3: + ldr w1, [x0, #USART_ISR] + tst w1, #USART_ISR_TXE + beq txe_loop_3 + mov w0, #0 + ret +endfunc console_stm32_core_flush + + /* --------------------------------------------- + * int console_stm32_flush(console_t *console) + * Function to force a write of all buffered + * data that hasn't been output. + * In : x0 - pointer to console_t structure + * Out : return -1 on error else return 0. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_stm32_flush +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ + ldr x0, [x0, #CONSOLE_T_BASE] + b console_stm32_core_flush +endfunc console_stm32_flush
diff --git a/drivers/ti/uart/aarch32/16550_console.S b/drivers/ti/uart/aarch32/16550_console.S index 0429f87..898a68d 100644 --- a/drivers/ti/uart/aarch32/16550_console.S +++ b/drivers/ti/uart/aarch32/16550_console.S
@@ -124,7 +124,7 @@ register_16550: mov r0, r4 pop {r4, lr} - finish_console_register 16550 putc=1, getc=1, flush=1 + finish_console_register 16550 putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: pop {r4, pc}
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index cb215125..2b1b5a9 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S
@@ -118,7 +118,7 @@ register_16550: mov x0, x6 mov x30, x7 - finish_console_register 16550 putc=1, getc=1, flush=1 + finish_console_register 16550 putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c index b8137c2..19f894f 100644 --- a/drivers/ufs/ufs.c +++ b/drivers/ufs/ufs.c
@@ -540,6 +540,7 @@ query_upiu->trans_type = QUERY_REQUEST_UPIU; query_upiu->task_tag = utrd->task_tag; + query_upiu->data_segment_len = htobe16(length); query_upiu->ts.desc.opcode = op; query_upiu->ts.desc.idn = idn; query_upiu->ts.desc.index = index; @@ -608,7 +609,7 @@ UTRIACR_IATOVAL(0xFF); mmio_write_32(ufs_params.reg_base + UTRIACR, data); /* send request */ - mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot); + mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1U << slot); } static int ufs_check_resp(utp_utrd_t *utrd, int trans_type, unsigned int timeout_ms)
diff --git a/fdts/juno.dts b/fdts/juno.dts index 56fe167..8e373e7 100644 --- a/fdts/juno.dts +++ b/fdts/juno.dts
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,6 +10,6 @@ }; -#if ARM_ETHOSN_NPU_DRIVER +#if ETHOSN_NPU_DRIVER #include "juno-ethosn.dtsi" #endif
diff --git a/fdts/morello-coresight.dtsi b/fdts/morello-coresight.dtsi new file mode 100644 index 0000000..ed3e9e5 --- /dev/null +++ b/fdts/morello-coresight.dtsi
@@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + /* + * Morello TRMs specify the size for these coresight components as 64K. + * The actual size is just 4K though 64K is reserved. Access to the + * unmapped reserved region results in a DECERR response. + */ + cpu_debug0: cpu-debug@402010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + cpu = <&cpu0>; + reg = <0x4 0x02010000 0x0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + etm0: etm@402040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + cpu = <&cpu0>; + reg = <0x4 0x02040000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster0_etm0_out_port: endpoint { + remote-endpoint = <&cluster0_static_funnel_in_port0>; + }; + }; + }; + }; + + cpu_debug1: cpu-debug@402110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + cpu = <&cpu1>; + reg = <0x4 0x02110000 0x0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + etm1: etm@402140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + cpu = <&cpu1>; + reg = <0x4 0x02140000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster0_etm1_out_port: endpoint { + remote-endpoint = <&cluster0_static_funnel_in_port1>; + }; + }; + }; + }; + + cpu_debug2: cpu-debug@403010000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + cpu = <&cpu2>; + reg = <0x4 0x03010000 0x0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + etm2: etm@403040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + cpu = <&cpu2>; + reg = <0x4 0x03040000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster1_etm0_out_port: endpoint { + remote-endpoint = <&cluster1_static_funnel_in_port0>; + }; + }; + }; + }; + + cpu_debug3: cpu-debug@403110000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + cpu = <&cpu3>; + reg = <0x4 0x03110000 0x0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + etm3: etm@403140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + cpu = <&cpu3>; + reg = <0x4 0x03140000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster1_etm1_out_port: endpoint { + remote-endpoint = <&cluster1_static_funnel_in_port1>; + }; + }; + }; + }; + + sfunnel0: funnel@0 { /* cluster0 funnel */ + compatible = "arm,coresight-static-funnel"; + out-ports { + port { + cluster0_static_funnel_out_port: endpoint { + remote-endpoint = <&etf0_in_port>; + }; + }; + }; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + cluster0_static_funnel_in_port0: endpoint { + remote-endpoint = <&cluster0_etm0_out_port>; + }; + }; + port@1 { + reg = <1>; + cluster0_static_funnel_in_port1: endpoint { + remote-endpoint = <&cluster0_etm1_out_port>; + }; + }; + }; + }; + + sfunnel1: funnel@1 { /* cluster1 funnel */ + compatible = "arm,coresight-static-funnel"; + out-ports { + port { + cluster1_static_funnel_out_port: endpoint { + remote-endpoint = <&etf1_in_port>; + }; + }; + }; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + cluster1_static_funnel_in_port0: endpoint { + remote-endpoint = <&cluster1_etm0_out_port>; + }; + }; + port@1 { + reg = <1>; + cluster1_static_funnel_in_port1: endpoint { + remote-endpoint = <&cluster1_etm1_out_port>; + }; + }; + }; + }; + + tpiu@400130000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x4 0x00130000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + }; + + main_funnel: funnel@4000a0000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x4 0x000a0000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + main_funnel_out_port: endpoint { + remote-endpoint = <&replicator_in_port>; + }; + }; + }; + main_funnel_in_ports: in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + main_funnel_in_port0: endpoint { + remote-endpoint = <&cluster_funnel_out_port>; + }; + }; + port@5 { + reg = <5>; + main_funnel_in_port5: endpoint { + remote-endpoint = <&etf2_out_port>; + }; + }; + }; + }; + + etr@400120000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x4 0x00120000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + arm,scatter-gather; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "etrbufint"; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + }; + + replicator@400110000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x4 0x00110000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + #address-cells = <1>; + #size-cells = <0>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + in-ports { + port { + replicator_in_port: endpoint { + remote-endpoint = <&main_funnel_out_port>; + }; + }; + }; + }; + + cluster_funnel: funnel@4000b0000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x4 0x000b0000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster_funnel_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port0>; + }; + }; + }; + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + cluster_funnel_in_port0: endpoint { + remote-endpoint = <&etf0_out_port>; + }; + }; + port@1 { + reg = <1>; + cluster_funnel_in_port1: endpoint { + remote-endpoint = <&etf1_out_port>; + }; + }; + }; + }; + + etf0: etf@400410000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x4 0x00410000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + in-ports { + port { + etf0_in_port: endpoint { + remote-endpoint = <&cluster0_static_funnel_out_port>; + }; + }; + }; + out-ports { + port { + etf0_out_port: endpoint { + remote-endpoint = <&cluster_funnel_in_port0>; + }; + }; + }; + }; + + etf1: etf@400420000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x4 0x00420000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + in-ports { + port { + etf1_in_port: endpoint { + remote-endpoint = <&cluster1_static_funnel_out_port>; + }; + }; + }; + out-ports { + port { + etf1_out_port: endpoint { + remote-endpoint = <&cluster_funnel_in_port1>; + }; + }; + }; + }; + + stm_etf: etf@400010000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x4 0x00010000 0 0x1000>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + in-ports { + port { + etf2_in_port: endpoint { + remote-endpoint = <&stm_out_port>; + }; + }; + }; + out-ports { + port { + etf2_out_port: endpoint { + remote-endpoint = <&main_funnel_in_port5>; + }; + }; + }; + }; + + stm@400800000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <4 0x00800000 0 0x1000>, + <0 0x4d000000 0 0x1000000>; + reg-names = "stm-base", "stm-stimulus-base"; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&etf2_in_port>; + }; + }; + }; + }; +};
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts index dc3df41..fda0f55 100644 --- a/fdts/morello-fvp.dts +++ b/fdts/morello-fvp.dts
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +25,32 @@ }; }; + /* + * The timings below are just to demonstrate working cpuidle. + * These values may be inaccurate. + */ + idle-states { + entry-method = "psci"; + + cluster_sleep: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000022>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000002>; + local-timer-stop; + entry-latency-us = <150>; + exit-latency-us = <300>; + min-residency-us = <200>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -53,6 +79,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; CPU1: cpu1@100 { compatible = "arm,armv8"; @@ -60,6 +87,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; CPU2: cpu2@10000 { compatible = "arm,armv8"; @@ -67,6 +95,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 1>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; CPU3: cpu3@10100 { compatible = "arm,armv8"; @@ -74,6 +103,7 @@ device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 1>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; };
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts index e87b617..fba904b 100644 --- a/fdts/morello-soc.dts +++ b/fdts/morello-soc.dts
@@ -6,6 +6,7 @@ /dts-v1/; #include "morello.dtsi" +#include "morello-coresight.dtsi" / { model = "Arm Morello System Development Platform"; @@ -25,36 +26,102 @@ }; }; + /* + * The timings below are just to demonstrate working cpuidle. + * These values may be inaccurate. + */ + idle-states { + entry-method = "psci"; + + cluster_sleep: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000022>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000002>; + local-timer-stop; + entry-latency-us = <150>; + exit-latency-us = <300>; + min-residency-us = <200>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; - cpu0@0 { + cpu0: cpu0@0 { compatible = "arm,armv8"; reg = <0x0 0x0>; device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 0>; + operating-points = < + /* kHz uV */ + 2600000 925000 + 2400000 875000 + 2200000 825000 + 2000000 775000 + 1800000 750000 + >; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; - cpu1@100 { + cpu1: cpu1@100 { compatible = "arm,armv8"; reg = <0x0 0x100>; device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 0>; + operating-points = < + /* kHz uV */ + 2600000 925000 + 2400000 875000 + 2200000 825000 + 2000000 775000 + 1800000 750000 + >; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; - cpu2@10000 { + cpu2: cpu2@10000 { compatible = "arm,armv8"; reg = <0x0 0x10000>; device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 1>; + operating-points = < + /* kHz uV */ + 2600000 925000 + 2400000 875000 + 2200000 825000 + 2000000 775000 + 1800000 750000 + >; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; - cpu3@10100 { + cpu3: cpu3@10100 { compatible = "arm,armv8"; reg = <0x0 0x10100>; device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_dvfs 1>; + operating-points = < + /* kHz uV */ + 2600000 925000 + 2400000 875000 + 2200000 825000 + 2000000 775000 + 1800000 750000 + >; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; }; }; @@ -193,10 +260,12 @@ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&dpu_aclk>; - hdmi-transmitter@70 { + hdmi_tx: hdmi-transmitter@70 { compatible = "nxp,tda998x"; reg = <0x70>; video-ports = <0x234501>; + #sound-dai-cells = <0>; + audio-ports = <2 0x03>; port { tda998x_0_input: endpoint { remote-endpoint = <&dp_pl0_out0>; @@ -252,8 +321,140 @@ reg = <0x14>; #clock-cells = <1>; }; + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; }; }; + + thermal-zones { + clus0-thermal { + polling-delay-passive = <200>; /* ms */ + polling-delay = <1000>; /* ms */ + + thermal-sensors = <&scmi_sensor 0>; + + trips { + clus0_alarm: clus0-alarm { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "passive"; + }; + clus0_shutdown: clus0-shutdown { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&clus0_alarm>; + cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; + }; + }; + }; + clus1-thermal { + polling-delay-passive = <200>; /* ms */ + polling-delay = <1000>; /* ms */ + + thermal-sensors = <&scmi_sensor 1>; + trips { + clus1_alarm: clus1-alarm { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "passive"; + }; + clus1_shutdown: clus1-shutdown { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&clus1_alarm>; + cooling-device = <&cpu2 4 4>, <&cpu3 4 4>; + }; + }; + }; + sys-thermal { + polling-delay-passive = <200>; /* ms */ + polling-delay = <1000>; /* ms */ + + thermal-sensors = <&scmi_sensor 2>; + trips { + sys_alarm: sys-alarm { + temperature = <85000>; /* millicelsius */ + hysteresis = <1000>; /* millicelsius */ + type = "passive"; + }; + sys_shutdown: sys-shutdown { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&sys_alarm>; + cooling-device = <&cpu0 4 4>, + <&cpu1 4 4>, + <&cpu2 4 4>, + <&cpu3 4 4>; + }; + }; + }; + }; + + iofpga_i2s: xlnx-i2s@1c150000 { + #sound-dai-cells = <0>; + compatible = "xlnx,i2s-transmitter-1.0"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1c150000 0x0 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; + + audio_formatter: audio-formatter@1c100000 { + compatible = "xlnx,audio-formatter-1.0"; + reg = <0x0 0x1c000000 0x0 0x10000>; + #sound-dai-cells = <0>; + interrupt-names = "irq_mm2s"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk"; + clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&audio_master>; + simple-audio-card,frame-master = <&audio_master>; + audio_master: simple-audio-card,cpu { + sound-dai = <&iofpga_i2s>; + clocks = <&i2s_audclk>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi_tx>; + }; + + simple-audio-card,plat { + sound-dai = <&audio_formatter>; + }; + }; + + i2s_audclk: i2s_audclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "iofpga:i2s_audclk"; + }; }; &gic {
diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi index 20640c5..7f39d75 100644 --- a/fdts/morello.dtsi +++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -88,6 +88,13 @@ clock-output-names = "apb_pclk"; }; + soc_refclk85mhz: refclk85mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <85000000>; + clock-output-names = "iofpga:aclk"; + }; + soc_uartclk: uartclk { compatible = "fixed-clock"; #clock-cells = <0>;
diff --git a/fdts/stm32mp13-pinctrl.dtsi b/fdts/stm32mp13-pinctrl.dtsi index 0129372..6de9bb0 100644 --- a/fdts/stm32mp13-pinctrl.dtsi +++ b/fdts/stm32mp13-pinctrl.dtsi
@@ -6,7 +6,8 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { - /omit-if-no-ref/ i2c4_pins_a: i2c4-0 { + /omit-if-no-ref/ + i2c4_pins_a: i2c4-0 { pins { pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */ <STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */ @@ -16,7 +17,8 @@ }; }; - /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { + /omit-if-no-ref/ + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ @@ -29,7 +31,8 @@ }; }; - /omit-if-no-ref/ sdmmc1_clk_pins_a: sdmmc1-clk-0 { + /omit-if-no-ref/ + sdmmc1_clk_pins_a: sdmmc1-clk-0 { pins { pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ slew-rate = <1>; @@ -38,7 +41,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ @@ -51,7 +55,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_clk_pins_a: sdmmc2-clk-0 { + /omit-if-no-ref/ + sdmmc2_clk_pins_a: sdmmc2-clk-0 { pins { pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ slew-rate = <1>; @@ -60,7 +65,8 @@ }; }; - /omit-if-no-ref/ uart4_pins_a: uart4-0 { + /omit-if-no-ref/ + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ bias-disable; @@ -73,7 +79,8 @@ }; }; - /omit-if-no-ref/ usart1_pins_a: usart1-0 { + /omit-if-no-ref/ + usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ @@ -88,7 +95,8 @@ }; }; - /omit-if-no-ref/ uart8_pins_a: uart8-0 { + /omit-if-no-ref/ + uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ bias-disable;
diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi index 543afa5..8bcf363 100644 --- a/fdts/stm32mp131.dtsi +++ b/fdts/stm32mp131.dtsi
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ #include <dt-bindings/clock/stm32mp13-clks.h> @@ -276,23 +276,20 @@ }; fmc: memory-controller@58002000 { - #address-cells = <2>; - #size-cells = <1>; compatible = "st,stm32mp1-fmc2-ebi"; reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; nand-controller@4,0 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32mp1-fmc2-nfc"; reg = <4 0x00000000 0x1000>, <4 0x08010000 0x1000>, @@ -300,6 +297,8 @@ <4 0x01000000 0x1000>, <4 0x09010000 0x1000>, <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -341,7 +340,7 @@ status = "disabled"; }; - usbh_ohci: usbh-ohci@5800c000 { + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; clocks = <&rcc USBH>; @@ -350,7 +349,7 @@ status = "disabled"; }; - usbh_ehci: usbh-ehci@5800d000 { + usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc USBH>; @@ -416,7 +415,7 @@ }; bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; + compatible = "st,stm32mp13-bsec"; reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; @@ -424,7 +423,7 @@ cfg0_otp: cfg0_otp@0 { reg = <0x0 0x2>; }; - part_number_otp: part_number_otp@4 { + part_number_otp: part-number-otp@4 { reg = <0x4 0x2>; }; monotonic_otp: monotonic_otp@10 { @@ -470,7 +469,6 @@ ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller;
diff --git a/fdts/stm32mp135f-dk.dts b/fdts/stm32mp135f-dk.dts index 0f06b67..1204692 100644 --- a/fdts/stm32mp135f-dk.dts +++ b/fdts/stm32mp135f-dk.dts
@@ -223,20 +223,20 @@ }; pll2_vco_1066Mhz: pll2-vco-1066Mhz { - src = < CLK_PLL12_HSE >; - divmn = < 2 65 >; - frac = < 0x1400 >; + src = <CLK_PLL12_HSE>; + divmn = <2 65>; + frac = <0x1400>; }; - pll3_vco_417_8Mhz: pll3-vco-417_8Mhz { - src = < CLK_PLL3_HSE >; - divmn = < 1 33 >; - frac = < 0x1a04 >; + pll3_vco_417Mhz: pll3-vco-417Mhz { + src = <CLK_PLL3_HSE>; + divmn = <1 33>; + frac = <0x1a04>; }; pll4_vco_600Mhz: pll4-vco-600Mhz { - src = < CLK_PLL4_HSE >; - divmn = < 1 49 >; + src = <CLK_PLL4_HSE>; + divmn = <1 49>; }; }; @@ -258,11 +258,11 @@ compatible = "st,stm32mp1-pll"; reg = <1>; - st,pll = < &pll2_cfg1 >; + st,pll = <&pll2_cfg1>; pll2_cfg1: pll2_cfg1 { - st,pll_vco = < &pll2_vco_1066Mhz >; - st,pll_div_pqr = < 1 1 0 >; + st,pll_vco = <&pll2_vco_1066Mhz>; + st,pll_div_pqr = <1 1 0>; }; }; @@ -271,11 +271,11 @@ compatible = "st,stm32mp1-pll"; reg = <2>; - st,pll = < &pll3_cfg1 >; + st,pll = <&pll3_cfg1>; pll3_cfg1: pll3_cfg1 { - st,pll_vco = < &pll3_vco_417_8Mhz >; - st,pll_div_pqr = < 1 16 1 >; + st,pll_vco = <&pll3_vco_417Mhz>; + st,pll_div_pqr = <1 16 1>; }; }; @@ -284,11 +284,11 @@ compatible = "st,stm32mp1-pll"; reg = <3>; - st,pll = < &pll4_cfg1 >; + st,pll = <&pll4_cfg1>; pll4_cfg1: pll4_cfg1 { - st,pll_vco = < &pll4_vco_600Mhz >; - st,pll_div_pqr = < 11 59 5 >; + st,pll_vco = <&pll4_vco_600Mhz>; + st,pll_div_pqr = <11 59 5>; }; }; };
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi index 8dc00fe..70d1db1 100644 --- a/fdts/stm32mp15-pinctrl.dtsi +++ b/fdts/stm32mp15-pinctrl.dtsi
@@ -6,7 +6,8 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { - /omit-if-no-ref/ fmc_pins_a: fmc-0 { + /omit-if-no-ref/ + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ @@ -31,7 +32,8 @@ }; }; - /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { + /omit-if-no-ref/ + i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ @@ -41,7 +43,8 @@ }; }; - /omit-if-no-ref/ qspi_clk_pins_a: qspi-clk-0 { + /omit-if-no-ref/ + qspi_clk_pins_a: qspi-clk-0 { pins { pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ bias-disable; @@ -50,8 +53,9 @@ }; }; - /omit-if-no-ref/ qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { + /omit-if-no-ref/ + qspi_bk1_pins_a: qspi-bk1-0 { + pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ @@ -60,16 +64,11 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { - pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; }; - /omit-if-no-ref/ qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { + /omit-if-no-ref/ + qspi_bk2_pins_a: qspi-bk2-0 { + pins { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ @@ -78,7 +77,21 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { + }; + + /omit-if-no-ref/ + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + qspi_cs2_pins_a: qspi-cs2-0 { + pins { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; @@ -86,7 +99,8 @@ }; }; - /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { + /omit-if-no-ref/ + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ @@ -105,7 +119,8 @@ }; }; - /omit-if-no-ref/ sdmmc1_dir_pins_a: sdmmc1-dir-0 { + /omit-if-no-ref/ + sdmmc1_dir_pins_a: sdmmc1-dir-0 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ @@ -120,7 +135,8 @@ }; }; - /omit-if-no-ref/ sdmmc1_dir_pins_b: sdmmc1-dir-1 { + /omit-if-no-ref/ + sdmmc1_dir_pins_b: sdmmc1-dir-1 { pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ @@ -129,13 +145,14 @@ drive-push-pull; bias-pull-up; }; - pins2{ + pins2 { pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ bias-pull-up; }; }; - /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ @@ -154,7 +171,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_b4_pins_b: sdmmc2-b4-1 { + /omit-if-no-ref/ + sdmmc2_b4_pins_b: sdmmc2-b4-1 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ @@ -173,7 +191,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ @@ -185,7 +204,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_d47_pins_b: sdmmc2-d47-1 { + /omit-if-no-ref/ + sdmmc2_d47_pins_b: sdmmc2-d47-1 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ @@ -197,7 +217,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_d47_pins_c: sdmmc2-d47-2 { + /omit-if-no-ref/ + sdmmc2_d47_pins_c: sdmmc2-d47-2 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ @@ -209,7 +230,8 @@ }; }; - /omit-if-no-ref/ sdmmc2_d47_pins_d: sdmmc2-d47-3 { + /omit-if-no-ref/ + sdmmc2_d47_pins_d: sdmmc2-d47-3 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ @@ -218,7 +240,8 @@ }; }; - /omit-if-no-ref/ uart4_pins_a: uart4-0 { + /omit-if-no-ref/ + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ bias-disable; @@ -231,7 +254,8 @@ }; }; - /omit-if-no-ref/ uart4_pins_b: uart4-1 { + /omit-if-no-ref/ + uart4_pins_b: uart4-1 { pins1 { pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ bias-disable; @@ -244,7 +268,8 @@ }; }; - /omit-if-no-ref/ uart7_pins_a: uart7-0 { + /omit-if-no-ref/ + uart7_pins_a: uart7-0 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ bias-disable; @@ -259,7 +284,8 @@ }; }; - /omit-if-no-ref/ uart7_pins_b: uart7-1 { + /omit-if-no-ref/ + uart7_pins_b: uart7-1 { pins1 { pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ bias-disable; @@ -272,7 +298,8 @@ }; }; - /omit-if-no-ref/ uart7_pins_c: uart7-2 { + /omit-if-no-ref/ + uart7_pins_c: uart7-2 { pins1 { pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ bias-disable; @@ -281,11 +308,12 @@ }; pins2 { pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ - bias-disable; + bias-pull-up; }; }; - /omit-if-no-ref/ uart8_pins_a: uart8-0 { + /omit-if-no-ref/ + uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ bias-disable; @@ -298,7 +326,8 @@ }; }; - /omit-if-no-ref/ usart2_pins_a: usart2-0 { + /omit-if-no-ref/ + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ @@ -313,7 +342,8 @@ }; }; - /omit-if-no-ref/ usart2_pins_b: usart2-1 { + /omit-if-no-ref/ + usart2_pins_b: usart2-1 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ @@ -328,13 +358,14 @@ }; }; - /omit-if-no-ref/ usart2_pins_c: usart2-2 { + /omit-if-no-ref/ + usart2_pins_c: usart2-2 { pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins2 { pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ @@ -343,7 +374,8 @@ }; }; - /omit-if-no-ref/ usart3_pins_a: usart3-0 { + /omit-if-no-ref/ + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ bias-disable; @@ -356,7 +388,8 @@ }; }; - /omit-if-no-ref/ usart3_pins_b: usart3-1 { + /omit-if-no-ref/ + usart3_pins_b: usart3-1 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ @@ -371,7 +404,8 @@ }; }; - /omit-if-no-ref/ usart3_pins_c: usart3-2 { + /omit-if-no-ref/ + usart3_pins_c: usart3-2 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ @@ -386,13 +420,15 @@ }; }; - /omit-if-no-ref/ usbotg_hs_pins_a: usbotg-hs-0 { + /omit-if-no-ref/ + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ }; }; - /omit-if-no-ref/ usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { + /omit-if-no-ref/ + usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { pins { pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ @@ -401,7 +437,8 @@ }; &pinctrl_z { - /omit-if-no-ref/ i2c4_pins_a: i2c4-0 { + /omit-if-no-ref/ + i2c4_pins_a: i2c4-0 { pins { pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi index 869b912..7a22a1c 100644 --- a/fdts/stm32mp151.dtsi +++ b/fdts/stm32mp151.dtsi
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -324,9 +324,8 @@ sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + reg = <0x58005000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -339,9 +338,8 @@ sdmmc2: mmc@58007000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; @@ -463,7 +461,7 @@ cfg0_otp: cfg0_otp@0 { reg = <0x0 0x1>; }; - part_number_otp: part_number_otp@4 { + part_number_otp: part-number-otp@4 { reg = <0x4 0x1>; }; monotonic_otp: monotonic_otp@10 { @@ -523,7 +521,7 @@ }; tamp: tamp@5c00a000 { - compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd"; + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; reg = <0x5c00a000 0x400>; secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc RTCAPB>; @@ -540,7 +538,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; @@ -669,7 +666,6 @@ #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; - pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>;
diff --git a/fdts/stm32mp151a-prtt1a.dts b/fdts/stm32mp151a-prtt1a.dts index be9bdae..3634620 100644 --- a/fdts/stm32mp151a-prtt1a.dts +++ b/fdts/stm32mp151a-prtt1a.dts
@@ -39,7 +39,9 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; @@ -56,7 +58,7 @@ }; &qspi_bk1_pins_a { - pins1 { + pins { bias-pull-up; drive-push-pull; slew-rate = <1>;
diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts index a73bef8..b4d5d20 100644 --- a/fdts/stm32mp157a-dk1.dts +++ b/fdts/stm32mp157a-dk1.dts
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ @@ -15,12 +15,6 @@ model = "STMicroelectronics STM32MP157A-DK1 Discovery Board"; compatible = "st,stm32mp157a-dk1", "st,stm32mp157"; - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; - }; - chosen { stdout-path = "serial0:115200n8"; };
diff --git a/fdts/stm32mp157c-dk2.dts b/fdts/stm32mp157c-dk2.dts index be8300e..f6f3782 100644 --- a/fdts/stm32mp157c-dk2.dts +++ b/fdts/stm32mp157c-dk2.dts
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + * Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics. */ @@ -17,9 +17,6 @@ compatible = "st,stm32mp157c-dk2", "st,stm32mp157"; aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; serial3 = &usart2; };
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 63753bd..949c929 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ /dts-v1/; @@ -16,6 +16,10 @@ model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + aliases { + serial0 = &uart4; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -24,10 +28,6 @@ device_type = "memory"; reg = <0xC0000000 0x40000000>; }; - - aliases { - serial0 = &uart4; - }; }; &bsec {
diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts index 02840a2..e274645 100644 --- a/fdts/stm32mp157c-ev1.dts +++ b/fdts/stm32mp157c-ev1.dts
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. */ /dts-v1/; @@ -11,13 +11,13 @@ model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial1 = &usart3; }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &fmc { @@ -39,13 +39,15 @@ &qspi { pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>;
diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi index c9f21b0..7737a44 100644 --- a/fdts/stm32mp15xx-dhcom-som.dtsi +++ b/fdts/stm32mp15xx-dhcom-som.dtsi
@@ -2,6 +2,7 @@ /* * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de> * Copyright (C) 2022 DH electronics GmbH + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved */ #include "stm32mp15-pinctrl.dtsi" @@ -169,7 +170,9 @@ &qspi { pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>;
diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi index c241efc..8d829a4 100644 --- a/fdts/stm32mp15xx-dhcor-som.dtsi +++ b/fdts/stm32mp15xx-dhcor-som.dtsi
@@ -4,6 +4,7 @@ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> * Copyright (C) 2020 Marek Vasut <marex@denx.de> * Copyright (C) 2022 DH electronics GmbH + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved */ #include "stm32mp15-pinctrl.dtsi" @@ -164,7 +165,9 @@ &qspi { pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells = <1>; #size-cells = <0>;
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi index 52d4170..f8baa9d 100644 --- a/fdts/stm32mp15xx-dkx.dtsi +++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -8,6 +8,12 @@ #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>;
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi new file mode 100644 index 0000000..438a58c --- /dev/null +++ b/fdts/stm32mp25-bl2.dtsi
@@ -0,0 +1,4 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */
diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi new file mode 100644 index 0000000..05876a3 --- /dev/null +++ b/fdts/stm32mp25-pinctrl.dtsi
@@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + /omit-if-no-ref/ + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; +};
diff --git a/fdts/stm32mp251.dtsi b/fdts/stm32mp251.dtsi new file mode 100644 index 0000000..f55a3b9 --- /dev/null +++ b/fdts/stm32mp251.dtsi
@@ -0,0 +1,289 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +#include <dt-bindings/clock/stm32mp25-clks.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/stm32mp25-resets.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_msi: clk-msi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc@42080000 { + compatible = "st,stm32mp25-rifsc"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + clocks = <&rcc CK_KER_USART2>; + resets = <&rcc USART2_R>; + status = "disabled"; + }; + }; + + rcc: rcc@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pwr: pwr@44210000 { + compatible = "st,stm32mp25-pwr"; + reg = <0x44210000 0x400>; + + vddio1: vddio1 { + regulator-name = "vddio1"; + }; + + vddio2: vddio2 { + regulator-name = "vddio2"; + }; + + vddio3: vddio3 { + regulator-name = "vddio3"; + }; + + vddio4: vddio4 { + regulator-name = "vddio4"; + }; + + vddio: vddio { + regulator-name = "vddio"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc CK_BUS_GPIOA>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&rcc CK_BUS_GPIOB>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&rcc CK_BUS_GPIOC>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&rcc CK_BUS_GPIOD>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&rcc CK_BUS_GPIOE>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&rcc CK_BUS_GPIOF>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&rcc CK_BUS_GPIOG>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&rcc CK_BUS_GPIOH>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&rcc CK_BUS_GPIOI>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&rcc CK_BUS_GPIOJ>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&rcc CK_BUS_GPIOK>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&rcc CK_BUS_GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +};
diff --git a/fdts/stm32mp253.dtsi b/fdts/stm32mp253.dtsi new file mode 100644 index 0000000..cc7dad5 --- /dev/null +++ b/fdts/stm32mp253.dtsi
@@ -0,0 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp251.dtsi"
diff --git a/fdts/stm32mp255.dtsi b/fdts/stm32mp255.dtsi new file mode 100644 index 0000000..14164ce --- /dev/null +++ b/fdts/stm32mp255.dtsi
@@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +};
diff --git a/fdts/stm32mp257.dtsi b/fdts/stm32mp257.dtsi new file mode 100644 index 0000000..a8c9f51 --- /dev/null +++ b/fdts/stm32mp257.dtsi
@@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +};
diff --git a/fdts/stm32mp257f-ev1.dts b/fdts/stm32mp257f-ev1.dts new file mode 100644 index 0000000..b7e92e4 --- /dev/null +++ b/fdts/stm32mp257f-ev1.dts
@@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; +}; + +&usart2 { + pinctrl-names = "default"; + pinctrl-0 = <&usart2_pins_a>; + status = "okay"; +};
diff --git a/fdts/stm32mp25xc.dtsi b/fdts/stm32mp25xc.dtsi new file mode 100644 index 0000000..8afb685 --- /dev/null +++ b/fdts/stm32mp25xc.dtsi
@@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +};
diff --git a/fdts/stm32mp25xf.dtsi b/fdts/stm32mp25xf.dtsi new file mode 100644 index 0000000..8afb685 --- /dev/null +++ b/fdts/stm32mp25xf.dtsi
@@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { +};
diff --git a/fdts/stm32mp25xxai-pinctrl.dtsi b/fdts/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 0000000..d6e47f5 --- /dev/null +++ b/fdts/stm32mp25xxai-pinctrl.dtsi
@@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +};
diff --git a/fdts/stm32mp25xxak-pinctrl.dtsi b/fdts/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 0000000..0ae46e9 --- /dev/null +++ b/fdts/stm32mp25xxak-pinctrl.dtsi
@@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +};
diff --git a/fdts/stm32mp25xxal-pinctrl.dtsi b/fdts/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 0000000..0ae46e9 --- /dev/null +++ b/fdts/stm32mp25xxal-pinctrl.dtsi
@@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +&pinctrl { + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +};
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 227f058..a711753 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -104,7 +104,11 @@ /* CSSELR definitions */ #define LEVEL_SHIFT U(1) -/* ID_DFR0_EL1 definitions */ +/* ID_DFR0 definitions */ +#define ID_DFR0_PERFMON_SHIFT U(24) +#define ID_DFR0_PERFMON_MASK U(0xf) +#define ID_DFR0_PERFMON_PMUV3 U(3) +#define ID_DFR0_PERFMON_PMUV3P5 U(6) #define ID_DFR0_COPTRC_SHIFT U(12) #define ID_DFR0_COPTRC_MASK U(0xf) #define ID_DFR0_COPTRC_SUPPORTED U(1) @@ -118,6 +122,11 @@ #define ID_DFR1_MTPMU_SHIFT U(0) #define ID_DFR1_MTPMU_MASK U(0xf) #define ID_DFR1_MTPMU_SUPPORTED U(1) +#define ID_DFR1_MTPMU_DISABLED U(15) + +/* ID_MMFR3 definitions */ +#define ID_MMFR3_PAN_SHIFT U(16) +#define ID_MMFR3_PAN_MASK U(0xf) /* ID_MMFR4 definitions */ #define ID_MMFR4_CNP_SHIFT U(12) @@ -188,11 +197,11 @@ #define SDCR_SPD_LEGACY U(0x0) #define SDCR_SPD_DISABLE U(0x2) #define SDCR_SPD_ENABLE U(0x3) -#define SDCR_SCCD_BIT (U(1) << 23) -#define SDCR_TTRF_BIT (U(1) << 19) #define SDCR_SPME_BIT (U(1) << 17) -#define SDCR_RESET_VAL U(0x0) +#define SDCR_TTRF_BIT (U(1) << 19) +#define SDCR_SCCD_BIT (U(1) << 23) #define SDCR_MTPME_BIT (U(1) << 28) +#define SDCR_RESET_VAL U(0x0) /* HSCTLR definitions */ #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ @@ -460,6 +469,10 @@ #define PMCR_LP_BIT (U(1) << 7) #define PMCR_LC_BIT (U(1) << 6) #define PMCR_DP_BIT (U(1) << 5) +#define PMCR_X_BIT (U(1) << 4) +#define PMCR_C_BIT (U(1) << 2) +#define PMCR_P_BIT (U(1) << 1) +#define PMCR_E_BIT (U(1) << 0) #define PMCR_RESET_VAL U(0x0) /******************************************************************************* @@ -533,6 +546,7 @@ #define DCISW p15, 0, c7, c6, 2 #define CTR p15, 0, c0, c0, 1 #define CNTFRQ p15, 0, c14, c0, 0 +#define ID_MMFR3 p15, 0, c0, c1, 7 #define ID_MMFR4 p15, 0, c0, c2, 6 #define ID_DFR0 p15, 0, c0, c1, 2 #define ID_DFR1 p15, 0, c0, c3, 5 @@ -782,5 +796,6 @@ #define DSU_CLUSTER_PWR_OFF 0 #define DSU_CLUSTER_PWR_ON 1 #define DSU_CLUSTER_PWR_MASK U(1) +#define DSU_CLUSTER_MEM_RET BIT(1) #endif /* ARCH_H */
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h index 62a512b..f19c4c2 100644 --- a/include/arch/aarch32/arch_features.h +++ b/include/arch/aarch32/arch_features.h
@@ -110,10 +110,81 @@ return read_feat_dit_id_field() != 0U; } -static inline bool is_feat_spe_supported(void) +static inline unsigned int read_feat_pan_id_field(void) { - /* FEAT_SPE is AArch64 only */ - return false; + return ISOLATE_FIELD(read_id_mmfr3(), ID_MMFR3_PAN); +} + +static inline bool is_feat_pan_supported(void) +{ + if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) { + return false; + } + + if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) { + return true; + } + + return read_feat_pan_id_field() != 0U; +} + +/* + * TWED, ECV, CSV2, RAS are only used by the AArch64 EL2 context switch + * code. In fact, EL2 context switching is only needed for AArch64 (since + * there is no secure AArch32 EL2), so just disable these features here. + */ +static inline bool is_feat_twed_supported(void) { return false; } +static inline bool is_feat_ecv_supported(void) { return false; } +static inline bool is_feat_ecv_v2_supported(void) { return false; } +static inline bool is_feat_csv2_2_supported(void) { return false; } +static inline bool is_feat_ras_supported(void) { return false; } + +/* The following features are supported in AArch64 only. */ +static inline bool is_feat_vhe_supported(void) { return false; } +static inline bool is_feat_sel2_supported(void) { return false; } +static inline bool is_feat_fgt_supported(void) { return false; } +static inline bool is_feat_tcr2_supported(void) { return false; } +static inline bool is_feat_spe_supported(void) { return false; } +static inline bool is_feat_rng_supported(void) { return false; } +static inline bool is_feat_gcs_supported(void) { return false; } +static inline bool is_feat_mpam_supported(void) { return false; } +static inline bool is_feat_hcx_supported(void) { return false; } +static inline bool is_feat_sve_supported(void) { return false; } +static inline bool is_feat_brbe_supported(void) { return false; } +static inline bool is_feat_trbe_supported(void) { return false; } +static inline bool is_feat_nv2_supported(void) { return false; } +static inline bool is_feat_sme_supported(void) { return false; } +static inline bool is_feat_sme2_supported(void) { return false; } +static inline bool is_feat_s2poe_supported(void) { return false; } +static inline bool is_feat_s1poe_supported(void) { return false; } +static inline bool is_feat_sxpoe_supported(void) { return false; } +static inline bool is_feat_s2pie_supported(void) { return false; } +static inline bool is_feat_s1pie_supported(void) { return false; } +static inline bool is_feat_sxpie_supported(void) { return false; } + +static inline unsigned int read_feat_pmuv3_id_field(void) +{ + return ISOLATE_FIELD(read_id_dfr0(), ID_DFR0_PERFMON); +} + +static inline unsigned int read_feat_mtpmu_id_field(void) +{ + return ISOLATE_FIELD(read_id_dfr1(), ID_DFR1_MTPMU); +} + +static inline bool is_feat_mtpmu_supported(void) +{ + if (DISABLE_MTPMU == FEAT_STATE_DISABLED) { + return false; + } + + if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) { + return true; + } + + unsigned int mtpmu = read_feat_mtpmu_id_field(); + + return mtpmu != 0U && mtpmu != ID_DFR1_MTPMU_DISABLED; } #endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h index 95d056f..3a7c768 100644 --- a/include/arch/aarch32/arch_helpers.h +++ b/include/arch/aarch32/arch_helpers.h
@@ -8,6 +8,7 @@ #ifndef ARCH_HELPERS_H #define ARCH_HELPERS_H +#include <assert.h> #include <cdefs.h> #include <stdbool.h> #include <stdint.h> @@ -217,8 +218,10 @@ ******************************************************************************/ DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) DEFINE_COPROCR_READ_FUNC(midr, MIDR) +DEFINE_COPROCR_READ_FUNC(id_mmfr3, ID_MMFR3) DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4) DEFINE_COPROCR_READ_FUNC(id_dfr0, ID_DFR0) +DEFINE_COPROCR_READ_FUNC(id_dfr1, ID_DFR1) DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0) DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1) DEFINE_COPROCR_READ_FUNC(isr, ISR) @@ -288,7 +291,7 @@ DEFINE_COPROCR_RW_FUNCS(sdcr, SDCR) DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR) DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL) -DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) +DEFINE_COPROCR_RW_FUNCS(pmcr, PMCR) /* * Address translation @@ -351,6 +354,17 @@ */ DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN) +/* + * RNDR is AArch64 only, so just provide a placeholder here to make the + * linker happy. + */ +static inline u_register_t read_rndr(void) +{ + assert(1); + + return 0; +} + /* Previously defined accessor functions with incomplete register names */ #define dsb() dsbsy() #define dmb() dmbsy()
diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 483f9fe..3ba86e9 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include <arch.h> #include <common/asm_macros_common.S> +#include <lib/cpus/cpu_ops.h> #include <lib/spinlock.h> /* @@ -24,8 +25,6 @@ stcopr _reg, _coproc #endif -#define WORD_SIZE 4 - /* * Co processor register accessors */ @@ -49,14 +48,14 @@ .macro dcache_line_size reg, tmp ldcopr \tmp, CTR ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH - mov \reg, #WORD_SIZE + mov \reg, #CPU_WORD_SIZE lsl \reg, \reg, \tmp .endm .macro icache_line_size reg, tmp ldcopr \tmp, CTR and \tmp, \tmp, #CTR_IMINLINE_MASK - mov \reg, #WORD_SIZE + mov \reg, #CPU_WORD_SIZE lsl \reg, \reg, \tmp .endm @@ -121,6 +120,14 @@ .endm #endif + /* Macro for error synchronization */ + .macro synchronize_errors + /* Complete any stores that may return an abort */ + dsb sy + /* Synchronise the CPU context with the completion of the dsb */ + isb + .endm + #if (ARM_ARCH_MAJOR == 7) /* ARMv7 does not support stl instruction */ .macro stl _reg, _write_lock
diff --git a/include/arch/aarch32/console_macros.S b/include/arch/aarch32/console_macros.S index 996cb32..726b281 100644 --- a/include/arch/aarch32/console_macros.S +++ b/include/arch/aarch32/console_macros.S
@@ -29,12 +29,20 @@ .endif str r1, [r0, #CONSOLE_T_PUTC] + /* + * If ENABLE_CONSOLE_GETC support is disabled, but a getc callback is + * specified nonetheless, the assembler will abort on encountering the + * CONSOLE_T_GETC macro, which is undefined. + */ .ifne \getc ldr r1, =console_\_driver\()_getc + str r1, [r0, #CONSOLE_T_GETC] .else +#if ENABLE_CONSOLE_GETC mov r1, #0 + str r1, [r0, #CONSOLE_T_GETC] +#endif .endif - str r1, [r0, #CONSOLE_T_GETC] .ifne \flush ldr r1, =console_\_driver\()_flush
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 585a9ae..697eb82 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S
@@ -277,10 +277,6 @@ cps #MODE32_mon isb -#if DISABLE_MTPMU - bl mtpmu_disable -#endif - .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets.
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 0038893..e9d22b6 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h
@@ -157,6 +157,8 @@ #define DCCSW U(0x2) #endif +#define ID_REG_FIELD_MASK ULL(0xf) + /* ID_AA64PFR0_EL1 definitions */ #define ID_AA64PFR0_EL0_SHIFT U(0) #define ID_AA64PFR0_EL1_SHIFT U(4) @@ -221,6 +223,12 @@ #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) +#define ID_AA64DFR0_PMUVER_LENGTH U(4) +#define ID_AA64DFR0_PMUVER_SHIFT U(8) +#define ID_AA64DFR0_PMUVER_MASK U(0xf) +#define ID_AA64DFR0_PMUVER_PMUV3 U(1) +#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) +#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ #define ID_AA64DFR0_PMS_SHIFT U(32) @@ -237,6 +245,7 @@ #define ID_AA64DFR0_MTPMU_SHIFT U(48) #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) +#define ID_AA64DFR0_MTPMU_DISABLED ULL(15) /* ID_AA64DFR0_EL1.BRBE definitions */ #define ID_AA64DFR0_BRBE_SHIFT U(52) @@ -268,6 +277,9 @@ /* ID_AA64ISAR2_EL1 definitions */ #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 +/* ID_AA64PFR2_EL1 definitions */ +#define ID_AA64PFR2_EL1 S3_0_C0_C4_2 + #define ID_AA64ISAR2_GPA3_SHIFT U(8) #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) @@ -300,6 +312,7 @@ #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) @@ -311,6 +324,7 @@ #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) +#define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) /* ID_AA64MMFR1_EL1 definitions */ #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) @@ -393,6 +407,16 @@ #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) +/* ID_AA64PFR2_EL1 definitions */ +#define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) +#define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) + +#define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) +#define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) + +#define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) +#define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) + #define VDISR_EL2 S3_4_C12_C1_1 #define VSESR_EL2 S3_4_C5_C2_3 @@ -413,6 +437,7 @@ #define ID_AA64PFR1_EL1_SME_SHIFT U(24) #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) +#define ID_AA64PFR1_EL1_SME_WIDTH U(4) #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) @@ -574,7 +599,7 @@ #define MDCR_SBRBE_MASK ULL(0x3) #define MDCR_NSTB(x) ((x) << 24) #define MDCR_NSTB_EL1 ULL(0x3) -#define MDCR_NSTBE (ULL(1) << 26) +#define MDCR_NSTBE_BIT (ULL(1) << 26) #define MDCR_MTPME_BIT (ULL(1) << 28) #define MDCR_TDCC_BIT (ULL(1) << 27) #define MDCR_SCCD_BIT (ULL(1) << 23) @@ -590,19 +615,20 @@ #define MDCR_SPD32_ENABLE ULL(0x3) #define MDCR_NSPB(x) ((x) << 12) #define MDCR_NSPB_EL1 ULL(0x3) +#define MDCR_NSPBE_BIT (ULL(1) << 11) #define MDCR_TDOSA_BIT (ULL(1) << 10) #define MDCR_TDA_BIT (ULL(1) << 9) #define MDCR_TPM_BIT (ULL(1) << 6) -#define MDCR_EL3_RESET_VAL ULL(0x0) +#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT /* MDCR_EL2 definitions */ #define MDCR_EL2_MTPME (U(1) << 28) -#define MDCR_EL2_HLP (U(1) << 26) +#define MDCR_EL2_HLP_BIT (U(1) << 26) #define MDCR_EL2_E2TB(x) ((x) << 24) #define MDCR_EL2_E2TB_EL1 U(0x3) -#define MDCR_EL2_HCCD (U(1) << 23) +#define MDCR_EL2_HCCD_BIT (U(1) << 23) #define MDCR_EL2_TTRF (U(1) << 19) -#define MDCR_EL2_HPMD (U(1) << 17) +#define MDCR_EL2_HPMD_BIT (U(1) << 17) #define MDCR_EL2_TPMS (U(1) << 14) #define MDCR_EL2_E2PB(x) ((x) << 12) #define MDCR_EL2_E2PB_EL1 U(0x3) @@ -613,6 +639,7 @@ #define MDCR_EL2_HPME_BIT (U(1) << 7) #define MDCR_EL2_TPM_BIT (U(1) << 6) #define MDCR_EL2_TPMCR_BIT (U(1) << 5) +#define MDCR_EL2_HPMN_MASK U(0x1f) #define MDCR_EL2_RESET_VAL U(0x0) /* HSTR_EL2 definitions */ @@ -935,6 +962,7 @@ #define EC_AARCH64_HVC U(0x16) #define EC_AARCH64_SMC U(0x17) #define EC_AARCH64_SYS U(0x18) +#define EC_IMP_DEF_EL3 U(0x1f) #define EC_IABORT_LOWER_EL U(0x20) #define EC_IABORT_CUR_EL U(0x21) #define EC_PC_ALIGN U(0x22) @@ -1204,7 +1232,9 @@ /* MPAM register definitions */ #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) +#define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) +#define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) @@ -1352,6 +1382,13 @@ #define HCRX_EL2_INIT_VAL ULL(0x0) /******************************************************************************* + * FEAT_FGT - Definitions for Fine-Grained Trap registers + ******************************************************************************/ +#define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) +#define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) +#define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) + +/******************************************************************************* * FEAT_TCR2 - Extended Translation Control Register ******************************************************************************/ #define TCR2_EL2 S3_4_C2_C0_3 @@ -1380,6 +1417,7 @@ #define DSU_CLUSTER_PWR_OFF 0 #define DSU_CLUSTER_PWR_ON 1 #define DSU_CLUSTER_PWR_MASK U(1) +#define DSU_CLUSTER_MEM_RET BIT(1) /******************************************************************************* * Definitions for CPU Power/Performance Management registers
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index d6f12f3..cf8da5e 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h
@@ -13,7 +13,26 @@ #include <common/feat_detect.h> #define ISOLATE_FIELD(reg, feat) \ - ((unsigned int)(((reg) >> (feat ## _SHIFT)) & (feat ## _MASK))) + ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK)) + +#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \ +static inline bool is_ ## name ## _supported(void) \ +{ \ + if ((guard) == FEAT_STATE_DISABLED) { \ + return false; \ + } \ + if ((guard) == FEAT_STATE_ALWAYS) { \ + return true; \ + } \ + return read_func() >= (idvalue); \ +} + +#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \ +static unsigned int read_ ## name ## _id_field(void) \ +{ \ + return ISOLATE_FIELD(read_ ## idreg(), idfield); \ +} \ +CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard) static inline bool is_armv7_gentimer_present(void) { @@ -21,41 +40,10 @@ return true; } -static inline unsigned int read_feat_pan_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN); -} - -static inline bool is_feat_pan_supported(void) -{ - if (ENABLE_FEAT_PAN == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_PAN == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_pan_id_field() != 0U; -} - -static inline unsigned int read_feat_vhe_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE); -} - -static inline bool is_feat_vhe_supported(void) -{ - if (ENABLE_FEAT_VHE == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_VHE == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_vhe_id_field() != 0U; -} +CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT, + ENABLE_FEAT_PAN) +CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT, + ENABLE_FEAT_VHE) static inline bool is_armv8_2_ttcnp_present(void) { @@ -107,260 +95,51 @@ ID_AA64PFR1_EL1_MTE_MASK); } -static inline unsigned int read_feat_sel2_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2); -} +CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT, + ENABLE_FEAT_SEL2) +CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT, + ENABLE_FEAT_TWED) +CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT, + ENABLE_FEAT_FGT) +CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1, + ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM) +CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT, + ENABLE_FEAT_ECV) +CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field, + ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV) -static inline bool is_feat_sel2_supported(void) -{ - if (ENABLE_FEAT_SEL2 == FEAT_STATE_DISABLED) { - return false; - } +CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT, + ENABLE_FEAT_RNG) +CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT, + ENABLE_FEAT_TCR2) - if (ENABLE_FEAT_SEL2 == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_sel2_id_field() != 0U; -} - -static inline unsigned int read_feat_twed_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED); -} - -static inline bool is_feat_twed_supported(void) -{ - if (ENABLE_FEAT_TWED == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_TWED == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_twed_id_field() != 0U; -} - -static unsigned int read_feat_fgt_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT); -} - -static inline bool is_feat_fgt_supported(void) -{ - if (ENABLE_FEAT_FGT == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_FGT == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_fgt_id_field() != 0U; -} - -static unsigned int read_feat_ecv_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV); -} - -static inline bool is_feat_ecv_supported(void) -{ - if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_ecv_id_field() != 0U; -} - -static inline bool is_feat_ecv_v2_supported(void) -{ - if (ENABLE_FEAT_ECV == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_ECV == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_ecv_id_field() >= ID_AA64MMFR0_EL1_ECV_SELF_SYNCH; -} - -static unsigned int read_feat_rng_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR); -} - -static inline bool is_feat_rng_supported(void) -{ - if (ENABLE_FEAT_RNG == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_RNG == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_rng_id_field() != 0U; -} - -static unsigned int read_feat_tcrx_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX); -} - -static inline bool is_feat_tcr2_supported(void) -{ - if (ENABLE_FEAT_TCR2 == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_TCR2 == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_tcrx_id_field() != 0U; -} - -static unsigned int read_feat_s2poe_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE); -} - -static inline bool is_feat_s2poe_supported(void) -{ - if (ENABLE_FEAT_S2POE == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_S2POE == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_s2poe_id_field() != 0U; -} - -static unsigned int read_feat_s1poe_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE); -} - -static inline bool is_feat_s1poe_supported(void) -{ - if (ENABLE_FEAT_S1POE == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_S1POE == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_s1poe_id_field() != 0U; -} - +CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT, + ENABLE_FEAT_S2POE) +CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT, + ENABLE_FEAT_S1POE) static inline bool is_feat_sxpoe_supported(void) { return is_feat_s1poe_supported() || is_feat_s2poe_supported(); } -static unsigned int read_feat_s2pie_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE); -} - -static inline bool is_feat_s2pie_supported(void) -{ - if (ENABLE_FEAT_S2PIE == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_S2PIE == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_s2pie_id_field() != 0U; -} - -static unsigned int read_feat_s1pie_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE); -} - -static inline bool is_feat_s1pie_supported(void) -{ - if (ENABLE_FEAT_S1PIE == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_S1PIE == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_s1pie_id_field() != 0U; -} - +CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT, + ENABLE_FEAT_S2PIE) +CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT, + ENABLE_FEAT_S1PIE) static inline bool is_feat_sxpie_supported(void) { return is_feat_s1pie_supported() || is_feat_s2pie_supported(); } -static unsigned int read_feat_gcs_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS); -} +/* FEAT_GCS: Guarded Control Stack */ +CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT, + ENABLE_FEAT_GCS) -static inline bool is_feat_gcs_supported(void) -{ - if (ENABLE_FEAT_GCS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_GCS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_gcs_id_field() != 0U; -} - -/******************************************************************************* - * Functions to identify the presence of the Activity Monitors Extension - ******************************************************************************/ -static unsigned int read_feat_amu_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU); -} - -static inline bool is_feat_amu_supported(void) -{ - if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1; -} - -static inline bool is_feat_amuv1p1_supported(void) -{ - if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_AMUv1p1 == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_amu_id_field() >= ID_AA64PFR0_AMU_V1P1; -} +/* FEAT_AMU: Activity Monitors Extension */ +CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT, + ENABLE_FEAT_AMU) +CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field, + ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1) /* * Return MPAM version: @@ -379,36 +158,12 @@ ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); } -static inline bool is_feat_mpam_supported(void) -{ - if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_DISABLED) { - return false; - } +CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U, + ENABLE_FEAT_MPAM) - if (ENABLE_MPAM_FOR_LOWER_ELS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_mpam_version() != 0U; -} - -static inline unsigned int read_feat_hcx_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX); -} - -static inline bool is_feat_hcx_supported(void) -{ - if (ENABLE_FEAT_HCX == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_HCX == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_hcx_id_field() != 0U; -} +/* FEAT_HCX: Extended Hypervisor Configuration Register */ +CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT, + ENABLE_FEAT_HCX) static inline bool is_feat_rng_trap_present(void) { @@ -433,249 +188,106 @@ ********************************************************************************/ static inline unsigned int read_feat_sb_id_field(void) { - return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB); + return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT); } -/********************************************************************************* - * Function to identify the presence of FEAT_CSV2_2 (Cache Speculation Variant 2) - ********************************************************************************/ -static inline unsigned int read_feat_csv2_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2); -} +/* FEAT_CSV2_2: Cache Speculation Variant 2 */ +CREATE_FEATURE_FUNCS(feat_csv2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 0) +CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field, + ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2) -static inline bool is_feat_csv2_2_supported(void) -{ - if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_DISABLED) { - return false; - } +/* FEAT_SPE: Statistical Profiling Extension */ +CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT, + ENABLE_SPE_FOR_NS) - if (ENABLE_FEAT_CSV2_2 == FEAT_STATE_ALWAYS) { - return true; - } +/* FEAT_SVE: Scalable Vector Extension */ +CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT, + ENABLE_SVE_FOR_NS) - return read_feat_csv2_id_field() >= ID_AA64PFR0_CSV2_2_SUPPORTED; -} +/* FEAT_RAS: Reliability, Accessibility, Serviceability */ +CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1, + ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS) -/********************************************************************************** - * Function to identify the presence of FEAT_SPE (Statistical Profiling Extension) - *********************************************************************************/ -static inline unsigned int read_feat_spe_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS); -} +/* FEAT_DIT: Data Independent Timing instructions */ +CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1, + ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT) -static inline bool is_feat_spe_supported(void) -{ - if (ENABLE_SPE_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } +CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1, + ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS) - if (ENABLE_SPE_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } +/* FEAT_TRF: TraceFilter */ +CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT, + ENABLE_TRF_FOR_NS) - return read_feat_spe_id_field() != 0U; -} +/* FEAT_NV2: Enhanced Nested Virtualization */ +CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0) +CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field, + ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS) -/******************************************************************************* - * Function to identify the presence of FEAT_SVE (Scalable Vector Extension) - ******************************************************************************/ -static inline unsigned int read_feat_sve_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE); -} +/* FEAT_BRBE: Branch Record Buffer Extension */ +CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT, + ENABLE_BRBE_FOR_NS) -static inline bool is_feat_sve_supported(void) -{ - if (ENABLE_SVE_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } +/* FEAT_TRBE: Trace Buffer Extension */ +CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT, + ENABLE_TRBE_FOR_NS) - if (ENABLE_SVE_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_sve_id_field() >= ID_AA64PFR0_SVE_SUPPORTED; -} - -static unsigned int read_feat_ras_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS); -} - -static inline bool is_feat_ras_supported(void) -{ - if (ENABLE_FEAT_RAS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_RAS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_ras_id_field() != 0U; -} - -static unsigned int read_feat_dit_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT); -} - -static inline bool is_feat_dit_supported(void) -{ - if (ENABLE_FEAT_DIT == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_FEAT_DIT == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_dit_id_field() != 0U; -} - -static inline unsigned int read_feat_tracever_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEVER); -} - -static inline bool is_feat_sys_reg_trace_supported(void) -{ - if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_SYS_REG_TRACE_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_tracever_id_field() != 0U; -} - -/************************************************************************* - * Function to identify the presence of FEAT_TRF (TraceLift) - ************************************************************************/ -static inline unsigned int read_feat_trf_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT); -} - -static inline bool is_feat_trf_supported(void) -{ - if (ENABLE_TRF_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_TRF_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_trf_id_field() != 0U; -} - -/******************************************************************************** - * Function to identify the presence of FEAT_NV2 (Enhanced Nested Virtualization - * Support) - *******************************************************************************/ -static inline unsigned int read_feat_nv_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV); -} - -static inline bool is_feat_nv2_supported(void) -{ - if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_DISABLED) { - return false; - } - - if (CTX_INCLUDE_NEVE_REGS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_nv_id_field() >= ID_AA64MMFR2_EL1_NV2_SUPPORTED; -} - -/******************************************************************************* - * Function to identify the presence of FEAT_BRBE (Branch Record Buffer - * Extension) - ******************************************************************************/ -static inline unsigned int read_feat_brbe_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE); -} - -static inline bool is_feat_brbe_supported(void) -{ - if (ENABLE_BRBE_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_BRBE_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_brbe_id_field() != 0U; -} - -/******************************************************************************* - * Function to identify the presence of FEAT_TRBE (Trace Buffer Extension) - ******************************************************************************/ -static inline unsigned int read_feat_trbe_id_field(void) -{ - return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER); -} - -static inline bool is_feat_trbe_supported(void) -{ - if (ENABLE_TRBE_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_TRBE_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_trbe_id_field() != 0U; - -} -/******************************************************************************* - * Function to identify the presence of FEAT_SMEx (Scalar Matrix Extension) - ******************************************************************************/ static inline unsigned int read_feat_sme_fa64_id_field(void) { - return ISOLATE_FIELD(read_id_aa64smfr0_el1(), ID_AA64SMFR0_EL1_SME_FA64); + return ISOLATE_FIELD(read_id_aa64smfr0_el1(), + ID_AA64SMFR0_EL1_SME_FA64_SHIFT); +} +/* FEAT_SMEx: Scalar Matrix Extension */ +CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT, + ENABLE_SME_FOR_NS) +CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field, + ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS) + +/******************************************************************************* + * Function to get hardware granularity support + ******************************************************************************/ + +static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void) +{ + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), + ID_AA64MMFR0_EL1_TGRAN4_SHIFT); } -static inline unsigned int read_feat_sme_id_field(void) +static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void) { - return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME); + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), + ID_AA64MMFR0_EL1_TGRAN16_SHIFT); } -static inline bool is_feat_sme_supported(void) +static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void) { - if (ENABLE_SME_FOR_NS == FEAT_STATE_DISABLED) { + return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), + ID_AA64MMFR0_EL1_TGRAN64_SHIFT); +} + +static inline unsigned int read_feat_pmuv3_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT); +} + +static inline unsigned int read_feat_mtpmu_id_field(void) +{ + return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT); +} + +static inline bool is_feat_mtpmu_supported(void) +{ + if (DISABLE_MTPMU == FEAT_STATE_DISABLED) { return false; } - if (ENABLE_SME_FOR_NS == FEAT_STATE_ALWAYS) { + if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) { return true; } - return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME_SUPPORTED; -} + unsigned int mtpmu = read_feat_mtpmu_id_field(); -static inline bool is_feat_sme2_supported(void) -{ - if (ENABLE_SME2_FOR_NS == FEAT_STATE_DISABLED) { - return false; - } - - if (ENABLE_SME2_FOR_NS == FEAT_STATE_ALWAYS) { - return true; - } - - return read_feat_sme_id_field() >= ID_AA64PFR1_EL1_SME2_SUPPORTED; + return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED); } #endif /* ARCH_FEATURES_H */
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 5b3d4c2..6fdc7e8 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -269,6 +269,7 @@ DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1) DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1) +DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1) DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1) DEFINE_IDREG_READ_FUNC(id_afr0_el1) DEFINE_SYSREG_READ_FUNC(CurrentEl) @@ -486,6 +487,13 @@ DEFINE_SYSREG_RW_FUNCS(vpidr_el2) DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) +DEFINE_SYSREG_RW_FUNCS(hacr_el2) +DEFINE_SYSREG_RW_FUNCS(hpfar_el2) +DEFINE_SYSREG_RW_FUNCS(tpidr_el2) +DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2) +DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2) + DEFINE_SYSREG_READ_FUNC(isr_el1) DEFINE_SYSREG_RW_FUNCS(mdcr_el2) @@ -584,6 +592,7 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2) /* Armv8.5 FEAT_RNG Registers */ DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S index 7d1407a..d09ad0f 100644 --- a/include/arch/aarch64/asm_macros.S +++ b/include/arch/aarch64/asm_macros.S
@@ -25,12 +25,50 @@ #endif - .macro func_prologue + /* + * Create a stack frame at the start of an assembly function. Will also + * add all necessary call frame information (cfi) directives for a + * pretty stack trace. This is necessary as there is quite a bit of + * flexibility within a stack frame and the stack pointer can move + * around throughout the function. If the debugger isn't told where to + * find things, it gets lost, gives up and displays nothing. So inform + * the debugger of what's where. Anchor the Canonical Frame Address + * (CFA; the thing used to track what's where) to the frame pointer as + * that's not expected to change in the function body and no extra + * bookkeeping will be necessary, allowing free movement of the sp + * + * _frame_size: requested space for caller to use. Must be a mutliple + * of 16 for stack pointer alignment + */ + .macro func_prologue _frame_size=0 + .if \_frame_size & 0xf + .error "frame_size must have stack pointer alignment (multiple of 16)" + .endif + + /* put frame record at top of frame */ stp x29, x30, [sp, #-0x10]! mov x29,sp + .if \_frame_size + sub sp, sp, #\_frame_size + .endif + + /* point CFA to start of frame record, i.e. x29 + 0x10 */ + .cfi_def_cfa x29, 0x10 + /* inform it about x29, x30 locations */ + .cfi_offset x30, -0x8 + .cfi_offset x29, -0x10 .endm - .macro func_epilogue + /* + * Clear stack frame at the end of an assembly function. + * + * _frame_size: the value passed to func_prologue + */ + .macro func_epilogue _frame_size=0 + /* remove requested space */ + .if \_frame_size + add sp, sp, #\_frame_size + .endif ldp x29, x30, [sp], #0x10 .endm @@ -254,4 +292,29 @@ #endif .endm + /* + * Macro to unmask External Aborts by changing PSTATE.A bit. + * Put explicit synchronization event to ensure newly unmasked interrupt + * is taken immediately. + */ + .macro unmask_async_ea + msr daifclr, #DAIF_ABT_BIT + isb + .endm + + /* Macro for error synchronization on exception boundries. + * With FEAT_RAS enabled, it is assumed that FEAT_IESB is also present + * and enabled. + * FEAT_IESB provides an implicit error synchronization event at exception + * entry and exception return, so there is no need for any explicit instruction. + */ + .macro synchronize_errors +#if !ENABLE_FEAT_RAS + /* Complete any stores that may return an abort */ + dsb sy + /* Synchronise the CPU context with the completion of the dsb */ + isb +#endif + .endm + #endif /* ASM_MACROS_S */
diff --git a/include/arch/aarch64/console_macros.S b/include/arch/aarch64/console_macros.S index 3285d85..8adb9cd 100644 --- a/include/arch/aarch64/console_macros.S +++ b/include/arch/aarch64/console_macros.S
@@ -30,12 +30,19 @@ str xzr, [x0, #CONSOLE_T_PUTC] .endif + /* + * If ENABLE_CONSOLE_GETC support is disabled, but a getc callback is + * specified nonetheless, the assembler will abort on encountering the + * CONSOLE_T_GETC macro, which is undefined. + */ .ifne \getc adrp x1, console_\_driver\()_getc add x1, x1, :lo12:console_\_driver\()_getc str x1, [x0, #CONSOLE_T_GETC] .else +#if ENABLE_CONSOLE_GETC str xzr, [x0, #CONSOLE_T_GETC] +#endif .endif .ifne \flush
diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S index dcaea3d..9609c0d 100644 --- a/include/arch/aarch64/el2_common_macros.S +++ b/include/arch/aarch64/el2_common_macros.S
@@ -103,7 +103,7 @@ */ mov_imm x0, ((MDCR_EL2_RESET_VAL | \ MDCR_SPD32(MDCR_SPD32_DISABLE)) \ - & ~(MDCR_EL2_HPMD | MDCR_TDOSA_BIT | \ + & ~(MDCR_EL2_HPMD_BIT | MDCR_TDOSA_BIT | \ MDCR_TDA_BIT | MDCR_TPM_BIT)) msr mdcr_el2, x0 @@ -244,10 +244,6 @@ isb .endif /* _init_sctlr */ -#if DISABLE_MTPMU - bl mtpmu_disable -#endif - .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets.
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 2dee07d..a78837f 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S
@@ -59,43 +59,14 @@ * zero here but are updated ahead of transitioning to a lower EL in the * function cm_init_context_common(). * - * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at - * EL2, EL1 and EL0 are not trapped to EL3. - * - * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at - * EL2, EL1 and EL0 are not trapped to EL3. - * * SCR_EL3.SIF: Set to one to disable instruction fetches from * Non-secure memory. * - * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from - * both Security states and both Execution states. - * * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts * to EL3 when executing at any EL. - * - * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature, - * disable traps to EL3 when accessing key registers or using pointer - * authentication instructions from lower ELs. * --------------------------------------------------------------------- */ - mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \ - & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) -#if CTX_INCLUDE_PAUTH_REGS - /* - * If the pointer authentication registers are saved during world - * switches, enable pointer authentication everywhere, as it is safe to - * do so. - */ - orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT) -#endif -#if ENABLE_RME - /* - * TODO: Settting the EEL2 bit to allow EL3 access to secure only registers - * in context management. This will need to be refactored. - */ - orr x0, x0, #SCR_EEL2_BIT -#endif + mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) msr scr_el3, x0 /* --------------------------------------------------------------------- @@ -115,83 +86,14 @@ * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the * debug registers, other than those registers that are controlled by * MDCR_EL3.TDOSA. - * - * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register - * accesses to all Performance Monitors registers do not trap to EL3. - * - * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is - * prohibited in Secure state. This bit is RES0 in versions of the - * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 - * doesn't have any effect on them. - * - * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is - * prohibited in EL3. This bit is RES0 in versions of the - * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 - * doesn't have any effect on them. - * - * MDCR_EL3.SPME: Set to zero so that event counting by the programmable - * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 - * Debug is not implemented this bit does not have any effect on the - * counters unless there is support for the implementation defined - * authentication interface ExternalSecureNoninvasiveDebugEnabled(). - * - * MDCR_EL3.NSTB, MDCR_EL3.NSTBE: Set to zero so that Trace Buffer - * owning security state is Secure state. If FEAT_TRBE is implemented, - * accesses to Trace Buffer control registers at EL2 and EL1 in any - * security state generates trap exceptions to EL3. - * If FEAT_TRBE is not implemented, these bits are RES0. - * - * MDCR_EL3.TTRF: Set to one so that access to trace filter control - * registers in non-monitor mode generate EL3 trap exception, - * unless the access generates a higher priority exception when trace - * filter control(FEAT_TRF) is implemented. - * When FEAT_TRF is not implemented, this bit is RES0. - * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ - MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ - MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ - MDCR_TDA_BIT | MDCR_TPM_BIT | MDCR_NSTB(MDCR_NSTB_EL1) | \ - MDCR_NSTBE | MDCR_TTRF_BIT)) + MDCR_SPD32(MDCR_SPD32_DISABLE)) & \ + ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT)) - mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #ID_AA64DFR0_TRACEFILT_SHIFT, #ID_AA64DFR0_TRACEFILT_LENGTH - cbz x1, 1f - orr x0, x0, #MDCR_TTRF_BIT -1: msr mdcr_el3, x0 /* --------------------------------------------------------------------- - * Initialise PMCR_EL0 setting all fields rather than relying - * on hw. Some fields are architecturally UNKNOWN on reset. - * - * PMCR_EL0.LP: Set to one so that event counter overflow, that - * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment - * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU - * is implemented. This bit is RES0 in versions of the architecture - * earlier than ARMv8.5, setting it to 1 doesn't have any effect - * on them. - * - * PMCR_EL0.LC: Set to one so that cycle counter overflow, that - * is recorded in PMOVSCLR_EL0[31], occurs on the increment - * that changes PMCCNTR_EL0[63] from 1 to 0. - * - * PMCR_EL0.DP: Set to one so that the cycle counter, - * PMCCNTR_EL0 does not count when event counting is prohibited. - * - * PMCR_EL0.X: Set to zero to disable export of events. - * - * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 - * counts on every clock cycle. - * --------------------------------------------------------------------- - */ - mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ - PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ - ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) - - msr pmcr_el0, x0 - - /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. * --------------------------------------------------------------------- @@ -201,39 +103,9 @@ /* --------------------------------------------------------------------- * Initialise CPTR_EL3, setting all fields rather than relying on hw. * All fields are architecturally UNKNOWN on reset. - * - * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1, - * CPTR_EL2, CPACR, or HCPTR do not trap to EL3. - * - * CPTR_EL3.TTA: Set to one so that accesses to the trace system - * registers trap to EL3 from all exception levels and security - * states when system register trace is implemented. - * When system register trace is not implemented, this bit is RES0 and - * hence set to zero. - * - * CPTR_EL3.TTA: Set to zero so that System register accesses to the - * trace registers do not trap to EL3. - * - * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers - * by Advanced SIMD, floating-point or SVE instructions (if implemented) - * do not trap to EL3. - * - * CPTR_EL3.TAM: Set to one so that Activity Monitor access is - * trapped to EL3 by default. - * - * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped - * to EL3 by default. - * - * CPTR_EL3.ESM: Set to zero so that all SME functionality is trapped - * to EL3 by default. + * --------------------------------------------------------------------- */ - - mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT)) - mrs x1, id_aa64dfr0_el1 - ubfx x1, x1, #ID_AA64DFR0_TRACEVER_SHIFT, #ID_AA64DFR0_TRACEVER_LENGTH - cbz x1, 1f - orr x0, x0, #TTA_BIT -1: + mov_imm x0, CPTR_EL3_RESET_VAL msr cptr_el3, x0 /* @@ -336,14 +208,14 @@ */ mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT)) +#if ENABLE_FEAT_RAS + /* If FEAT_RAS is present assume FEAT_IESB is also present */ + orr x0, x0, #SCTLR_IESB_BIT +#endif msr sctlr_el3, x0 isb .endif /* _init_sctlr */ -#if DISABLE_MTPMU - bl mtpmu_disable -#endif - .if \_warm_boot_mailbox /* ------------------------------------------------------------- * This code will be executed for both warm and cold resets. @@ -573,4 +445,20 @@ #endif .endm +/* ----------------------------------------------------------------- + * The below macro reads SCR_EL3 from the context structure to + * determine the security state of the context upon ERET. + * ------------------------------------------------------------------ + */ + .macro get_security_state _ret:req, _scr_reg:req + ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1 + cmp \_ret, #1 + beq realm_state + bfi \_ret, \_scr_reg, #0, #1 + b end + realm_state: + mov \_ret, #2 + end: + .endm + #endif /* EL3_COMMON_MACROS_S */
diff --git a/include/bl31/ea_handle.h b/include/bl31/ea_handle.h index 68f012c..7cd7b6a 100644 --- a/include/bl31/ea_handle.h +++ b/include/bl31/ea_handle.h
@@ -21,4 +21,6 @@ /* RAS event signalled as peripheral interrupt */ #define ERROR_INTERRUPT 3 +#define ASYNC_EA_REPLAY_COUNTER U(100) + #endif /* EA_HANDLE_H */
diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 539280e..4c8a17c 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h
@@ -85,6 +85,10 @@ #define __EL3_LP_DESCS_START__ Load$$__EL3_LP_DESCS__$$Base #define __EL3_LP_DESCS_END__ Load$$__EL3_LP_DESCS__$$Limit #endif +#if ENABLE_SPMD_LP +#define __SPMD_LP_DESCS_START__ Load$$__SPMD_LP_DESCS__$$Base +#define __SPMD_LP_DESCS_END__ Load$$__SPMD_LP_DESCS__$$Limit +#endif #define __RW_START__ Load$$LR$$LR_RW_DATA$$Base #define __RW_END__ Load$$LR$$LR_END$$Base #define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h index c9bed1a..b6dd0f0 100644 --- a/include/common/bl_common.ld.h +++ b/include/common/bl_common.ld.h
@@ -49,6 +49,15 @@ #define EL3_LP_DESCS #endif +#if ENABLE_SPMD_LP +#define SPMD_LP_DESCS \ + . = ALIGN(STRUCT_ALIGN); \ + __SPMD_LP_DESCS_START__ = .; \ + KEEP(*(.spmd_lp_descs)) \ + __SPMD_LP_DESCS_END__ = .; +#else +#define SPMD_LP_DESCS +#endif #define PMF_SVC_DESCS \ . = ALIGN(STRUCT_ALIGN); \ __PMF_SVC_DESCS_START__ = .; \ @@ -100,7 +109,8 @@ CPU_OPS \ GOT \ BASE_XLAT_TABLE_RO \ - EL3_LP_DESCS + EL3_LP_DESCS \ + SPMD_LP_DESCS /* * .data must be placed at a lower address than the stacks if the stack
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h index b16510f..abbf976 100644 --- a/include/common/fdt_wrappers.h +++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,7 +49,7 @@ static inline uint32_t fdt_blob_size(const void *dtb) { - const uint32_t *dtb_header = dtb; + const uint32_t *dtb_header = (const uint32_t *)dtb; return fdt32_to_cpu(dtb_header[1]); } @@ -60,7 +60,8 @@ const void *prop = fdt_getprop(fdt, node, "status", &len); /* A non-existing status property means the device is enabled. */ - return (prop == NULL) || (len == 5 && strcmp(prop, "okay") == 0); + return (prop == NULL) || (len == 5 && strcmp((const char *)prop, + "okay") == 0); } #define fdt_for_each_compatible_node(dtb, node, compatible_str) \
diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h index 822c474..bf23917 100644 --- a/include/common/tbbr/cot_def.h +++ b/include/common/tbbr/cot_def.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,7 +32,12 @@ * buffers must be big enough to hold either. As RSA keys are bigger than ECDSA * ones for all key sizes we support, they impose the minimum size of these * buffers. + * + * If the platform employs its own mbedTLS configuration, it is the platform's + * responsibility to define TF_MBEDTLS_USE_RSA or TF_MBEDTLS_USE_ECDSA to + * establish the appropriate PK_DER_LEN size. */ +#ifdef MBEDTLS_CONFIG_FILE #if TF_MBEDTLS_USE_RSA #if TF_MBEDTLS_KEY_SIZE == 1024 #define PK_DER_LEN 162 @@ -45,9 +50,17 @@ #else #error "Invalid value for TF_MBEDTLS_KEY_SIZE" #endif -#else /* Only using ECDSA keys. */ +#elif TF_MBEDTLS_USE_ECDSA +#if TF_MBEDTLS_KEY_SIZE == 384 +#define PK_DER_LEN 120 +#elif TF_MBEDTLS_KEY_SIZE == 256 #define PK_DER_LEN 92 +#else +#error "Invalid value for TF_MBEDTLS_KEY_SIZE" #endif +#else +#error "Invalid value of algorithm" +#endif /* TF_MBEDTLS_USE_RSA */ #if TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA256 #define HASH_DER_LEN 51 @@ -58,5 +71,6 @@ #else #error "Invalid value for TF_MBEDTLS_HASH_ALG_ID" #endif +#endif /* MBEDTLS_CONFIG_FILE */ #endif /* COT_DEF_H */
diff --git a/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h b/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h deleted file mode 100644 index 2cb8938..0000000 --- a/include/drivers/arm/cryptocell/712/cc_crypto_boot_defs.h +++ /dev/null
@@ -1,34 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_CRYPTO_BOOT_DEFS_H -#define _CC_CRYPTO_BOOT_DEFS_H - -/*! @file -@brief This file contains SBROM definitions -*/ - -/*! Version counters value. */ -typedef enum { - - CC_SW_VERSION_COUNTER1 = 1, /*!< Counter 1 - trusted version. */ - CC_SW_VERSION_COUNTER2, /*!< Counter 2 - non trusted version. */ - - CC_SW_VERSION_MAX = 0x7FFFFFFF - -} CCSbSwVersionId_t; - -/* HASH boot key definition */ -typedef enum { - CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< 128-bit truncated SHA256 digest of public key 0. */ - CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< 128-bit truncated SHA256 digest of public key 1. */ - CC_SB_HASH_BOOT_KEY_256B = 2, /*!< 256-bit SHA256 digest of public key. */ - CC_SB_HASH_BOOT_NOT_USED = 0xFF, - CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!\internal use external 128-bit truncated SHA256 digest */ -} CCSbPubKeyIndexType_t; - - -#endif
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h deleted file mode 100644 index 212a710..0000000 --- a/include/drivers/arm/cryptocell/712/cc_pal_sb_plat.h +++ /dev/null
@@ -1,33 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! -@file -@brief This file contains the platform-dependent definitions that are used in the SBROM code. -*/ - -#ifndef _CC_PAL_SB_PLAT_H -#define _CC_PAL_SB_PLAT_H - -#include "cc_pal_types.h" - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */ -typedef uint64_t CCDmaAddr_t; -/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */ -typedef uintptr_t CCAddr_t; - - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types.h b/include/drivers/arm/cryptocell/712/cc_pal_types.h deleted file mode 100644 index 8c09b23..0000000 --- a/include/drivers/arm/cryptocell/712/cc_pal_types.h +++ /dev/null
@@ -1,40 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CC_PAL_TYPES_H -#define CC_PAL_TYPES_H - -/*! -@file -@brief This file contains platform-dependent definitions and types. -*/ - -#include "cc_pal_types_plat.h" - -typedef enum { - CC_FALSE = 0, - CC_TRUE = 1 -} CCBool; - -#define CC_SUCCESS 0UL -#define CC_FAIL 1UL - -#define CC_1K_SIZE_IN_BYTES 1024 -#define CC_BITS_IN_BYTE 8 -#define CC_BITS_IN_32BIT_WORD 32 -#define CC_32BIT_WORD_SIZE (sizeof(uint32_t)) - -#define CC_OK CC_SUCCESS - -#define CC_UNUSED_PARAM(prm) ((void)prm) - -#define CC_MAX_UINT32_VAL (0xFFFFFFFF) - -#define CALC_FULL_BYTES(numBits) (((numBits) + (CC_BITS_IN_BYTE - 1))/CC_BITS_IN_BYTE) -#define CALC_FULL_32BIT_WORDS(numBits) (((numBits) + (CC_BITS_IN_32BIT_WORD - 1))/CC_BITS_IN_32BIT_WRD) -#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) (((sizeBytes) + CC_32BIT_WORD_SIZE - 1)/CC_32BIT_WORD_SIZE) - -#endif
diff --git a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h deleted file mode 100644 index f6d41d7..0000000 --- a/include/drivers/arm/cryptocell/712/cc_pal_types_plat.h +++ /dev/null
@@ -1,25 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! @file -@brief This file contains basic type definitions that are platform-dependent. -*/ -#ifndef _CC_PAL_TYPES_PLAT_H -#define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compliant platforms */ - -#include <stddef.h> -#include <stdint.h> - -typedef uint32_t CCStatus; - -#define CCError_t CCStatus -#define CC_INFINITE 0xFFFFFFFF - -#define CEXPORT_C -#define CIMPORT_C - -#endif /*_CC_PAL_TYPES_PLAT_H*/
diff --git a/include/drivers/arm/cryptocell/712/cc_sec_defs.h b/include/drivers/arm/cryptocell/712/cc_sec_defs.h deleted file mode 100644 index d419218..0000000 --- a/include/drivers/arm/cryptocell/712/cc_sec_defs.h +++ /dev/null
@@ -1,34 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_SEC_DEFS_H -#define _CC_SEC_DEFS_H - -/*! -@file -@brief This file contains general hash definitions and types. -*/ - - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! The hashblock size in words. */ -#define HASH_BLOCK_SIZE_IN_WORDS 16 -/*! The hash - SHA2 results in words. */ -#define HASH_RESULT_SIZE_IN_WORDS 8 -#define HASH_RESULT_SIZE_IN_BYTES 32 - -/*! Definition for hash result array. */ -typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS]; - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/crypto_driver.h b/include/drivers/arm/cryptocell/712/crypto_driver.h deleted file mode 100644 index 18104dd..0000000 --- a/include/drivers/arm/cryptocell/712/crypto_driver.h +++ /dev/null
@@ -1,35 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CRYPTO_DRIVER_H -#define _CRYPTO_DRIVER_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_sb_plat.h" -#include "cc_sec_defs.h" - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ -/*! - * @brief This function gives the functionality of integrated hash - * - * @param[in] hwBaseAddress - CryptoCell base address - * @param[out] hashResult - the HASH result. - * - */ -CCError_t SBROM_CryptoHash(unsigned long hwBaseAddress, CCDmaAddr_t inputDataAddr, uint32_t BlockSize, - CCHashResult_t hashResult); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/nvm.h b/include/drivers/arm/cryptocell/712/nvm.h deleted file mode 100644 index a70289f..0000000 --- a/include/drivers/arm/cryptocell/712/nvm.h +++ /dev/null
@@ -1,55 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _NVM__H -#define _NVM__H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_crypto_boot_defs.h" -#include "cc_pal_types.h" -#include "cc_sec_defs.h" - -/*------------------------------------ - DEFINES --------------------------------------*/ - -/** - * @brief This function reads the LCS from the SRAM/NVM - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in/out] lcs_ptr - pointer to memory to store the LCS - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ -CCError_t NVM_GetLCS(unsigned long hwBaseAddress, uint32_t *lcs_ptr); - -/** - * @brief The NVM_ReadHASHPubKey function is a NVM interface function - - * The function retrieves the HASH of the device Public key from the SRAM/NVM - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in] pubKeyIndex - Index of HASH in the OTP - * - * @param[out] PubKeyHASH - the public key HASH. - * - * @param[in] hashSizeInWords - hash size (valid values: 4W, 8W) - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ - -CCError_t NVM_ReadHASHPubKey(unsigned long hwBaseAddress, CCSbPubKeyIndexType_t pubKeyIndex, CCHashResult_t PubKeyHASH, uint32_t hashSizeInWords); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/nvm_otp.h b/include/drivers/arm/cryptocell/712/nvm_otp.h deleted file mode 100644 index 390d62b..0000000 --- a/include/drivers/arm/cryptocell/712/nvm_otp.h +++ /dev/null
@@ -1,59 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _NVM_OTP_H -#define _NVM_OTP_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_crypto_boot_defs.h" -#include "cc_pal_types.h" - -/*------------------------------------ - DEFINES --------------------------------------*/ - - - -/** - * @brief The NVM_GetSwVersion function is a NVM interface function - - * The function retrieves the SW version from the SRAM/NVM. - * In case of OTP, we support up to 16 anti-rollback counters (taken from the certificate) - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in] counterId - relevant only for OTP (valid values: 1,2) - * - * @param[out] swVersion - the minimum SW version - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ -CCError_t NVM_GetSwVersion(unsigned long hwBaseAddress, CCSbSwVersionId_t counterId, uint32_t *swVersion); - - -/** - * @brief The NVM_SetSwVersion function is a NVM interface function - - * The function writes the SW version into the SRAM/NVM. - * In case of OTP, we support up to 16 anti-rollback counters (taken from the certificate) - * - * @param[in] hwBaseAddress - CryptoCell base address - * - * @param[in] counterId - relevant only for OTP (valid values: 1,2) - * - * @param[in] swVersion - the minimum SW version - * - * @return CCError_t - On success the value CC_OK is returned, and on failure -a value from NVM_error.h - */ -CCError_t NVM_SetSwVersion(unsigned long hwBaseAddress, CCSbSwVersionId_t counterId, uint32_t swVersion); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/rsa.h b/include/drivers/arm/cryptocell/712/rsa.h deleted file mode 100644 index 825214d..0000000 --- a/include/drivers/arm/cryptocell/712/rsa.h +++ /dev/null
@@ -1,57 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RSA_H -#define RSA_H - -/* - * All the includes that are needed for code using this module to - * compile correctly should be #included here. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" - -/************************ Defines ******************************/ - -/* the modulus size in bits */ -#if (KEY_SIZE == 2048) -#define RSA_MOD_SIZE_IN_BITS 2048UL -#elif (KEY_SIZE == 3072) -#define RSA_MOD_SIZE_IN_BITS 3072UL -#else -#error Unsupported CryptoCell key size requested -#endif - -#define RSA_MOD_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_MOD_SIZE_IN_BITS)) -#define RSA_MOD_SIZE_IN_WORDS (CALC_FULL_32BIT_WORDS(RSA_MOD_SIZE_IN_BITS)) -#define RSA_MOD_SIZE_IN_256BITS (RSA_MOD_SIZE_IN_WORDS/8) -#define RSA_EXP_SIZE_IN_BITS 17UL -#define RSA_EXP_SIZE_IN_BYTES (CALC_FULL_BYTES(RSA_EXP_SIZE_IN_BITS)) - -/* - * @brief The RSA_CalcNp calculates Np value and saves it into Np_ptr: - * - * - - * @param[in] hwBaseAddress - HW base address. Relevant for HW - * implementation, for SW it is ignored. - * @N_ptr[in] - The pointer to the modulus buffer. - * @Np_ptr[out] - pointer to Np vector buffer. Its size must be >= 160. - */ -void RSA_CalcNp(unsigned long hwBaseAddress, - uint32_t *N_ptr, - uint32_t *Np_ptr); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h b/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h deleted file mode 100644 index de83546..0000000 --- a/include/drivers/arm/cryptocell/712/sbrom_bsv_api.h +++ /dev/null
@@ -1,72 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SBROM_BSV_API_H -#define _SBROM_BSV_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! @file -@brief This file contains all SBROM library APIs and definitions. -*/ -#include "cc_pal_types.h" - -/* Life cycle state definitions */ -#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< CM lifecycle value. */ -#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< DM lifecycle value. */ -#define CC_BSV_SECURITY_DISABLED_LCS 0x3 /*!< SD lifecycle value. */ -#define CC_BSV_SECURE_LCS 0x5 /*!< Secure lifecycle value. */ -#define CC_BSV_RMA_LCS 0x7 /*!< RMA lifecycle value. */ - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/*! -@brief This function should be the first ARM TrustZone CryptoCell TEE SBROM library API called. -It verifies the HW product and version numbers. - -@return CC_OK On success. -@return A non-zero value from sbrom_bsv_error.h on failure. -*/ -CCError_t CC_BsvSbromInit( - unsigned long hwBaseAddress /*!< [in] HW registers base address. */ - ); - - -/*! -@brief This function can be used for checking the LCS value, after CC_BsvLcsGetAndInit was called by the Boot ROM. - -@return CC_OK On success. -@return A non-zero value from sbrom_bsv_error.h on failure. -*/ -CCError_t CC_BsvLcsGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - uint32_t *pLcs /*!< [out] Returned lifecycle state. */ - ); - -/*! -@brief This function retrieves the HW security lifecycle state, performs validity checks, -and additional initializations in case the LCS is RMA (sets the Kce to fixed value). -\note Invalid LCS results in an error returned. -In this case, the customer's code must completely disable the device. - -@return CC_OK On success. -@return A non-zero value from sbrom_bsv_error.h on failure. -*/ -CCError_t CC_BsvLcsGetAndInit( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - uint32_t *pLcs /*!< [out] Returned lifecycle state. */ - ); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/secureboot_base_func.h b/include/drivers/arm/cryptocell/712/secureboot_base_func.h deleted file mode 100644 index 6db596e..0000000 --- a/include/drivers/arm/cryptocell/712/secureboot_base_func.h +++ /dev/null
@@ -1,49 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SECURE_BOOT_BASE_FUNC_H -#define _SECURE_BOOT_BASE_FUNC_H - - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" -#include "secureboot_gen_defs.h" - - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/** - * @brief This function calculates the HASH over the given data and than verify - * RSA signature on that hashed data - * - * @param[in] hwBaseAddr - CryptoCell base address - * @param[in] pData - pointer to the data to be verified - * @param[in] pNParams - a pointer to the public key parameters - * @param[in] pSignature - a pointer to the signature structure - * @param[in] sizeOfData - size of the data to calculate the HASH on (in bytes) - * @param[in] RSAAlg - RSA algorithm to use - * - * @return CCError_t - On success the value CC_OK is returned, - * on failure - a value from BootImagesVerifier_error.h - */ -CCError_t CCSbVerifySignature(unsigned long hwBaseAddress, - uint32_t *pData, - CCSbNParams_t *pNParams, - CCSbSignature_t *pSignature, - uint32_t sizeOfData, - CCSbRsaAlg_t RSAAlg); - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h b/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h deleted file mode 100644 index ed1f283..0000000 --- a/include/drivers/arm/cryptocell/712/secureboot_gen_defs.h +++ /dev/null
@@ -1,66 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SECURE_BOOT_GEN_DEFS_H -#define _SECURE_BOOT_GEN_DEFS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! @file -@brief This file contains all of the definitions and structures that are used for the secure boot. -*/ - -#include "cc_pal_sb_plat.h" -#include "cc_sec_defs.h" - - -/* General definitions */ -/***********************/ - -/*RSA definitions*/ -#if (KEY_SIZE == 2048) -#define SB_RSA_MOD_SIZE_IN_WORDS 64 -#elif (KEY_SIZE == 3072) -#define SB_RSA_MOD_SIZE_IN_WORDS 96 -#else -#error Unsupported CryptoCell key size requested -#endif - -#define SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS 5 - - -/*! Public key data structure. */ -typedef struct { - uint32_t N[SB_RSA_MOD_SIZE_IN_WORDS]; /*!< N public key, big endian representation. */ - uint32_t Np[SB_RSA_HW_PKI_PKA_BARRETT_MOD_TAG_SIZE_IN_WORDS]; /*!< Np (Barrett n' value). */ -} CCSbNParams_t; - -/*! Signature structure. */ -typedef struct { - uint32_t sig[SB_RSA_MOD_SIZE_IN_WORDS]; /*!< RSA PSS signature. */ -} CCSbSignature_t; - - -/********* Supported algorithms definitions ***********/ - -/*! RSA supported algorithms */ -/* Note: this applies to either 2k or 3k based on CryptoCell SBROM library - * version - it means 2k in version 1 and 3k in version 2 (yes, really). - */ -typedef enum { - RSA_PSS = 0x01, /*!< RSA PSS after hash SHA 256 */ - RSA_PKCS15 = 0x02, /*!< RSA PKX15 */ - RSA_Last = 0x7FFFFFFF -} CCSbRsaAlg_t; - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/712/util.h b/include/drivers/arm/cryptocell/712/util.h deleted file mode 100644 index 18fb599..0000000 --- a/include/drivers/arm/cryptocell/712/util.h +++ /dev/null
@@ -1,72 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef UTIL_H -#define UTIL_H - -/* - * All the includes that are needed for code using this module to - * compile correctly should be #included here. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/************************ Defines ******************************/ - -/* invers the bytes on a word- used for output from HASH */ -#ifdef BIG__ENDIAN -#define UTIL_INVERSE_UINT32_BYTES(val) (val) -#else -#define UTIL_INVERSE_UINT32_BYTES(val) \ - (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF) << 24)) -#endif - -/* invers the bytes on a word - used for input data for HASH */ -#ifdef BIG__ENDIAN -#define UTIL_REVERT_UINT32_BYTES(val) \ - (((val) >> 24) | (((val) & 0x00FF0000) >> 8) | (((val) & 0x0000FF00) << 8) | (((val) & 0x000000FF) << 24)) -#else -#define UTIL_REVERT_UINT32_BYTES(val) (val) -#endif - - /* ------------------------------------------------------------ - ** - * @brief This function executes a reverse bytes copying from one buffer to another buffer. - * - * @param[in] dst_ptr - The pointer to destination buffer. - * @param[in] src_ptr - The pointer to source buffer. - * @param[in] size - The size in bytes. - * - */ - -void UTIL_ReverseMemCopy(uint8_t *dst_ptr, uint8_t *src_ptr, uint32_t size); - - - /* ------------------------------------------------------------ - ** - * @brief This function executes a reversed byte copy on a specified buffer. - * - * on a 6 byte byffer: - * - * buff[5] <---> buff[0] - * buff[4] <---> buff[1] - * buff[3] <---> buff[2] - * - * @param[in] dst_ptr - The counter buffer. - * @param[in] src_ptr - The counter size in bytes. - * - */ -void UTIL_ReverseBuff(uint8_t *buff_ptr, uint32_t size); - - -#ifdef __cplusplus -} -#endif - -#endif
diff --git a/include/drivers/arm/cryptocell/713/bsv_api.h b/include/drivers/arm/cryptocell/713/bsv_api.h deleted file mode 100644 index dc49473..0000000 --- a/include/drivers/arm/cryptocell/713/bsv_api.h +++ /dev/null
@@ -1,221 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_API_H -#define _BSV_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the Boot Services APIs and definitions. - -@defgroup cc_bsv_api CryptoCell Boot Services APIs and definitions -@{ -@ingroup cc_bsv -*/ - -#include "cc_pal_types.h" -#include "cc_sec_defs.h" -#include "cc_boot_defs.h" - -/* Life cycle state definitions. */ -#define CC_BSV_CHIP_MANUFACTURE_LCS 0x0 /*!< The CM life-cycle state (LCS) value. */ -#define CC_BSV_DEVICE_MANUFACTURE_LCS 0x1 /*!< The DM life-cycle state (LCS) value. */ -#define CC_BSV_SECURE_LCS 0x5 /*!< The Secure life-cycle state (LCS) value. */ -#define CC_BSV_RMA_LCS 0x7 /*!< The RMA life-cycle state (LCS) value. */ -#define CC_BSV_INVALID_LCS 0xff /*!< The invalid life-cycle state (LCS) value. */ - -/*---------------------------- - TYPES ------------------------------------*/ - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - - -/*! -@brief This function verifies the product and version numbers of the HW, and initializes it. - -\warning This function must be the first CryptoCell-7xx SBROM library API called. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvInit( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function retrieves the HW LCS and performs validity checks. - -If the LCS is RMA, it also sets the OTP secret keys to a fixed value. - -@note An error is returned if there is an invalid LCS. If this happens, your code must -completely disable the device. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvGetAndInitLcs( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - uint32_t *pLcs /*!< [out] The value of the current LCS. */ - ); - -/*! -@brief This function retrieves the LCS from the NVM manager. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvLcsGet( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - uint32_t *pLcs /*!< [out] The value of the current LCS. */ - ); - -/*! -@brief This function reads software revocation counter from OTP memory, according to the provided sw version index. -SW version is stored in NVM counter and represented by ones. Meaning seVersion=5 would be stored as binary 0b11111; -hence: - the maximal of trusted is 32 - the maximal of non-trusted is 224 - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSwVersionGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */ - uint32_t *swVersion /*!< [out] The value of the requested counter as read from OTP memory. */ - ); - -/*! -@brief This function sets the NVM counter according to swVersionID (trusted/non-trusted). - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSwVersionSet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCSbSwVersionId_t id, /*!< [in] Enumeration defining the trusted/non-trusted counter to read. */ - uint32_t swVersion /*!< [in] New value of the counter to be programmed in OTP memory. */ - ); - -/*! -@brief This function sets the "fatal error" flag in the NVM manager, to disable the use of -any HW keys or security services. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvFatalErrorSet( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function retrieves the public key hash from OTP memory, according to the provided index. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvPubKeyHashGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCSbPubKeyIndexType_t keyIndex, /*!< [in] Enumeration defining the key hash to retrieve: 128-bit HBK0, 128-bit HBK1, or 256-bit HBK. */ - uint32_t *hashedPubKey, /*!< [out] A buffer to contain the public key HASH. */ - uint32_t hashResultSizeWords /*!< [in] The size of the hash in 32-bit words: - - Must be 4 for 128-bit hash. - - Must be 8 for 256bit hash. */ - ); - -/*! -@brief This function permanently sets the RMA LCS for the ICV and the OEM. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvRMAModeEnable( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function is called by the ICV code, to disable the OEM code from changing the ICV RMA bit flag. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvICVRMAFlagBitLock( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); - -/*! -@brief This function locks the defined ICV class keys from further usage. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvICVKeyLock( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCBool_t isICVProvisioningKeyLock, /*!< [in] Should the provisioning key be locked. */ - CCBool_t isICVCodeEncKeyLock /*!< [in] Should the encryption key be locked. */ - ); - - -/*! -@brief This function retrieves the value of "secure disable" bit. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSecureDisableGet( - unsigned long hwBaseAddress, /*!< [in] HW registers base address. */ - CCBool_t *isSDEnabled /*!< [out] The value of the SD Enable bit. */ - ); - - -/*! -@brief This function derives the platform key (Kplt) from the Kpicv, and then decrypts the customer key (Kcst) -from the EKcst (burned in the OTP). The decryption is done only in Secure and RMA LCS mode using AES-ECB. -The customer ROM should invoke this function during early boot, prior to running any non-ROM code, only if Kcst exists. -The resulting Kcst is saved in a HW register. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvCustomerKeyDecrypt( - unsigned long hwBaseAddress /*!< [in] The base address of the CryptoCell HW registers. */ - ); -#ifdef __cplusplus -} -#endif - -/*! -@brief This function derives the unique SoC_ID for the device, as hashed (Hbk || AES_CMAC (HUK)). - -@note SoC_ID is required to create debug certificates. - -The OEM or ICV must provide a method for a developer to discover the SoC_ID of a target -device without having to first enable debugging. -One suggested implementation is to have the device ROM code compute the SoC_ID and place -it in a specific location in the flash memory, from where it can be accessed by the developer. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSocIDCompute( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCHashResult_t hashResult /*!< [out] The derived SoC_ID. */ - ); - -#endif /* _BSV_API_H */ - -/** -@} - */ -
diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_api.h deleted file mode 100644 index 1e60579..0000000 --- a/include/drivers/arm/cryptocell/713/bsv_crypto_api.h +++ /dev/null
@@ -1,76 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_CRYPTO_API_H -#define _BSV_CRYPTO_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the cryptographic ROM APIs of the Boot Services. - -@defgroup cc_bsv_crypto_api CryptoCell Boot Services cryptographic ROM APIs -@{ -@ingroup cc_bsv -*/ - -#include "cc_pal_types.h" -#include "cc_sec_defs.h" -#include "cc_address_defs.h" -#include "bsv_crypto_defs.h" - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/*! -@brief This function calculates the SHA-256 digest over contiguous memory -in an integrated operation. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvSha256( - unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - uint8_t *pDataIn, /*!< [in] A pointer to the input buffer to be hashed. The buffer must be contiguous. */ - size_t dataSize, /*!< [in] The size of the data to be hashed, in bytes. */ - CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte buffer. */ - ); - - -/*! -@brief This function allows you to calculate SHA256 digest of an image with decryption base on AES-CTR, -with HW or user key. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. (in this case, hashBuff will be returned clean, while the output data should be cleaned by the user). -*/ -CCError_t CC_BsvCryptoImageDecrypt( unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCBsvflowMode_t flow, /*!< [in] The supported operations are: HASH, AES to HASH, AES and HASH. */ - CCBsvKeyType_t keyType, /*!< [in] The key type to use: Kce, Kceicv, or user key. */ - uint8_t *pUserKey, /*!< [in] A pointer to the user key buffer in case keyType is CC_BSV_USER_KEY. */ - size_t userKeySize, /*!< [in] The user key size in bytes (128bits) in case keyType is CC_BSV_USER_KEY. */ - uint8_t *pIvBuf, /*!< [in] A pointer to the IV / counter buffer. */ - uint8_t *pInputData, /*!< [in] A pointer to the input data. */ - uint8_t *pOutputData, /*!< [out] A pointer to the output buffer. (optional – should be null in case of hash only). */ - size_t dataSize, /*!< [in] The size of the input data in bytes. MUST be multiple of AES block size. */ - CCHashResult_t hashBuff /*!< [out] A pointer to a word-aligned 32-byte digest output buffer. */ - ); - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ -
diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h b/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h deleted file mode 100644 index 406e1ef..0000000 --- a/include/drivers/arm/cryptocell/713/bsv_crypto_asym_api.h +++ /dev/null
@@ -1,100 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_CRYPTO_ASYM_API_H -#define _BSV_CRYPTO_ASYM_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the cryptographic Asymmetric ROM APIs of the Boot Services. - -@defgroup cc_bsv_crypto_asym_api CryptoCell Boot Services cryptographic Asymmetric ROM APIs -@{ -@ingroup cc_bsv -*/ - -#include "cc_pal_types.h" -#include "cc_pka_hw_plat_defs.h" -#include "cc_sec_defs.h" -#include "bsv_crypto_api.h" - -/*! Defines the workspace size in bytes needed for internal Asymmetric operations. */ -#define BSV_RSA_WORKSPACE_MIN_SIZE (4*BSV_CERT_RSA_KEY_SIZE_IN_BYTES +\ - 2*RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES) - -/*! Definition for the RSA public modulus array. */ -typedef uint32_t CCBsvNBuff_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS]; - -/*! Definition for the RSA Barrett mod tag array. */ -typedef uint32_t CCBsvNpBuff_t[RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES]; - -/*! Definition for the RSA signature array. */ -typedef uint32_t CCBsvSignature_t[BSV_CERT_RSA_KEY_SIZE_IN_WORDS]; - - -/*---------------------------- - PUBLIC FUNCTIONS ------------------------------------*/ - -/*! -@brief This function performs the primitive operation of RSA, meaning exponent and modulus. - outBuff = (pInBuff ^ Exp) mod NBuff. ( Exp = 0x10001 ) - - The function supports 2k and 3K bit size of modulus, based on compile time define. - There are no restriction on pInBuff location, however its size must be equal to BSV_RSA_KEY_SIZE_IN_BYTES and its - value must be smaller than the modulus. - - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvRsaPrimVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */ - CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */ - uint32_t *pInBuff, /*!< [in] The DataIn buffer to be encrypted. */ - size_t inBuffSize, /*!< [in] The DataIn buffer size in bytes, must be BSV_RSA_KEY_SIZE_IN_BYTES. */ - CCBsvSignature_t pOutBuff, /*!< [out] The encrypted buffer in big endian format. */ - uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */ - size_t workBufferSize /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */ -); - - -/*! -@brief This function performs RSA PSS verify. - - The function should support 2k and 3K bit size of modulus, based on compile time define. - -@return \c CC_OK on success. -@return A non-zero value from bsv_error.h on failure. -*/ -CCError_t CC_BsvRsaPssVerify (unsigned long hwBaseAddress, /*!< [in] The base address of the CryptoCell HW registers. */ - CCBsvNBuff_t NBuff, /*!< [in] The modulus buffer big endian format. */ - CCBsvNpBuff_t NpBuff, /*!< [in] The barret tag buffer big endian format - optional. */ - CCBsvSignature_t signature, /*!< [in] The signature buffer to verify - big endian format. */ - CCHashResult_t hashedData, /*!< [in] The data-in buffer to be verified as sha256 digest. */ - uint32_t *pWorkSpace, /*!< [in] The pointer to user allocated buffer for internal use. */ - size_t workBufferSize, /*!< [in] The size in bytes of pWorkSpace, must be at-least BSV_RSA_WORKSPACE_MIN_SIZE. */ - CCBool_t *pIsVerified /*!< [out] The flag indicates whether the signature is verified or not. - If verified value will be CC_TRUE, otherwise CC_FALSE */ -); - - - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ -
diff --git a/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h b/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h deleted file mode 100644 index 9ea354d..0000000 --- a/include/drivers/arm/cryptocell/713/bsv_crypto_defs.h +++ /dev/null
@@ -1,94 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_CRYPTO_DEFS_H -#define _BSV_CRYPTO_DEFS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file contains the definitions of the cryptographic ROM APIs. - -@defgroup cc_bsv_crypto_defs CryptoCell Boot Services cryptographic ROM API definitions -@{ -@ingroup cc_bsv -*/ - -/*! AES supported HW key code table. */ -typedef enum { - - CC_BSV_USER_KEY = 0, /*!< Definition for a user key. */ - CC_BSV_HUK_KEY = 1, /*!< Definition for the HW unique key. */ - CC_BSV_RTL_KEY = 2, /*!< Definition for the RTL key. */ - CC_BSV_SESSION_KEY = 3, /*!< Definition for the Session key. */ - CC_BSV_CE_KEY = 4, /*!< Definition for the Kce. */ - CC_BSV_PLT_KEY = 5, /*!< Definition for the Platform key. */ - CC_BSV_KCST_KEY = 6, /*!< Definition for Kcst. */ - CC_BSV_ICV_PROV_KEY = 0xd, /*!< Definition for the Kpicv. */ - CC_BSV_ICV_CE_KEY = 0xe, /*!< Definition for the Kceicv. */ - CC_BSV_PROV_KEY = 0xf, /*!< Definition for the Kcp. */ - CC_BSV_END_OF_KEY_TYPE = INT32_MAX, /*!< Reserved. */ -}CCBsvKeyType_t; - -/*! AES directions. */ -typedef enum bsvAesDirection { - BSV_AES_DIRECTION_ENCRYPT = 0, /*!< Encrypt.*/ - BSV_AES_DIRECTION_DECRYPT = 1, /*!< Decrypt.*/ - BSV_AES_NUM_OF_ENCRYPT_MODES, /*!< The maximal number of operations. */ - BSV_AES_DIRECTION_RESERVE32B = INT32_MAX /*!< Reserved.*/ -}bsvAesDirection_t; - -/*! Definitions of the cryptographic flow supported as part of the Secure Boot. */ -typedef enum { - CC_BSV_CRYPTO_HASH_MODE = 0, /*!< Hash mode only. */ - CC_BSV_CRYPTO_AES_CTR_AND_HASH_MODE = 1, /*!< Data goes into the AES and Hash engines. */ - CC_BSV_CRYPTO_AES_CTR_TO_HASH_MODE = 2 /*!< Data goes into the AES and from the AES to the Hash engine. */ -}CCBsvflowMode_t; - -/*! CryptoImage HW completion sequence mode */ -typedef enum -{ - BSV_CRYPTO_COMPLETION_NO_WAIT = 0, /*!< The driver waits only before reading the output. */ - BSV_CRYPTO_COMPLETION_WAIT_UPON_END = 1 /*!< The driver waits after each chunk of data. */ -}bsvCryptoCompletionMode_t; - - -/*! AES-CMAC result size, in words. */ -#define CC_BSV_CMAC_RESULT_SIZE_IN_WORDS 4 /* 128b */ -/*! AES-CMAC result size, in bytes. */ -#define CC_BSV_CMAC_RESULT_SIZE_IN_BYTES 16 /* 128b */ -/*! AES-CCM 128bit key size, in bytes. */ -#define CC_BSV_CCM_KEY_SIZE_BYTES 16 -/*! AES-CCM 128bit key size, in words. */ -#define CC_BSV_CCM_KEY_SIZE_WORDS 4 -/*! AES-CCM NONCE size, in bytes. */ -#define CC_BSV_CCM_NONCE_SIZE_BYTES 12 - - -/*! AES-CMAC result buffer. */ -typedef uint32_t CCBsvCmacResult_t[CC_BSV_CMAC_RESULT_SIZE_IN_WORDS]; -/*! AES-CCM key buffer.*/ -typedef uint32_t CCBsvCcmKey_t[CC_BSV_CCM_KEY_SIZE_WORDS]; -/*! AES-CCM nonce buffer.*/ -typedef uint8_t CCBsvCcmNonce_t[CC_BSV_CCM_NONCE_SIZE_BYTES]; -/*! AES-CCM MAC buffer.*/ -typedef uint8_t CCBsvCcmMacRes_t[CC_BSV_CMAC_RESULT_SIZE_IN_BYTES]; - - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ -
diff --git a/include/drivers/arm/cryptocell/713/bsv_error.h b/include/drivers/arm/cryptocell/713/bsv_error.h deleted file mode 100644 index 4d72e60..0000000 --- a/include/drivers/arm/cryptocell/713/bsv_error.h +++ /dev/null
@@ -1,161 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BSV_ERROR_H -#define _BSV_ERROR_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! -@file -@brief This file defines the error code types that are returned from the Boot Services APIs. - -@defgroup cc_bsv_error CryptoCell Boot Services error codes -@{ -@ingroup cc_bsv -*/ - -/*! Defines the base address for Boot Services errors. */ -#define CC_BSV_BASE_ERROR 0x0B000000 -/*! Defines the base address for Boot Services cryptographic errors. */ -#define CC_BSV_CRYPTO_ERROR 0x0C000000 - -/*! Illegal input parameter. */ -#define CC_BSV_ILLEGAL_INPUT_PARAM_ERR (CC_BSV_BASE_ERROR + 0x00000001) -/*! Illegal HUK value. */ -#define CC_BSV_ILLEGAL_HUK_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000002) -/*! Illegal Kcp value. */ -#define CC_BSV_ILLEGAL_KCP_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000003) -/*! Illegal Kce value. */ -#define CC_BSV_ILLEGAL_KCE_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000004) -/*! Illegal Kpicv value. */ -#define CC_BSV_ILLEGAL_KPICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000005) -/*! Illegal Kceicv value. */ -#define CC_BSV_ILLEGAL_KCEICV_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000006) -/*! Illegal EKcst value. */ -#define CC_BSV_ILLEGAL_EKCST_VALUE_ERR (CC_BSV_BASE_ERROR + 0x00000007) -/*! Hash boot key not programmed in the OTP. */ -#define CC_BSV_HASH_NOT_PROGRAMMED_ERR (CC_BSV_BASE_ERROR + 0x00000008) -/*! Illegal Hash boot key zero count in the OTP. */ -#define CC_BSV_HBK_ZERO_COUNT_ERR (CC_BSV_BASE_ERROR + 0x00000009) -/*! Illegal LCS. */ -#define CC_BSV_ILLEGAL_LCS_ERR (CC_BSV_BASE_ERROR + 0x0000000A) -/*! OTP write compare failure. */ -#define CC_BSV_OTP_WRITE_CMP_FAIL_ERR (CC_BSV_BASE_ERROR + 0x0000000B) -/*! OTP access error */ -#define CC_BSV_OTP_ACCESS_ERR (CC_BSV_BASE_ERROR + 0x0000000C) -/*! Erase key in OTP failed. */ -#define CC_BSV_ERASE_KEY_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000000D) -/*! Illegal PIDR. */ -#define CC_BSV_ILLEGAL_PIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000E) -/*! Illegal CIDR. */ -#define CC_BSV_ILLEGAL_CIDR_ERR (CC_BSV_BASE_ERROR + 0x0000000F) -/*! Device failed to move to fatal error state. */ -#define CC_BSV_FAILED_TO_SET_FATAL_ERR (CC_BSV_BASE_ERROR + 0x00000010) -/*! Failed to set RMA LCS. */ -#define CC_BSV_FAILED_TO_SET_RMA_ERR (CC_BSV_BASE_ERROR + 0x00000011) -/*! Illegal RMA indication. */ -#define CC_BSV_ILLEGAL_RMA_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000012) -/*! Boot Services version is not initialized. */ -#define CC_BSV_VER_IS_NOT_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x00000013) -/*! APB secure mode is locked. */ -#define CC_BSV_APB_SECURE_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000014) -/*! APB privilege mode is locked. */ -#define CC_BSV_APB_PRIVILEG_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000015) -/*! Illegal operation. */ -#define CC_BSV_ILLEGAL_OPERATION_ERR (CC_BSV_BASE_ERROR + 0x00000016) -/*! Illegal asset size. */ -#define CC_BSV_ILLEGAL_ASSET_SIZE_ERR (CC_BSV_BASE_ERROR + 0x00000017) -/*! Illegal asset value. */ -#define CC_BSV_ILLEGAL_ASSET_VAL_ERR (CC_BSV_BASE_ERROR + 0x00000018) -/*! Kpicv is locked. */ -#define CC_BSV_KPICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000019) -/*! Illegal SW version. */ -#define CC_BSV_ILLEGAL_SW_VERSION_ERR (CC_BSV_BASE_ERROR + 0x0000001A) -/*! AO write operation. */ -#define CC_BSV_AO_WRITE_FAILED_ERR (CC_BSV_BASE_ERROR + 0x0000001B) -/*! Chip state is already initialized. */ -#define CC_BSV_CHIP_INITIALIZED_ERR (CC_BSV_BASE_ERROR + 0x0000001C) -/*! SP is not enabled. */ -#define CC_BSV_SP_NOT_ENABLED_ERR (CC_BSV_BASE_ERROR + 0x0000001D) -/*! Production secure provisioning - header fields. */ -#define CC_BSV_PROD_PKG_HEADER_ERR (CC_BSV_BASE_ERROR + 0x0000001E) -/*! Production secure provisioning - header MAC. */ -#define CC_BSV_PROD_PKG_HEADER_MAC_ERR (CC_BSV_BASE_ERROR + 0x0000001F) -/*! Overrun buffer or size. */ -#define CC_BSV_OVERRUN_ERR (CC_BSV_BASE_ERROR + 0x00000020) -/*! Kceicv is locked. */ -#define CC_BSV_KCEICV_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000021) -/*! Chip indication is CHIP_STATE_ERROR. */ -#define CC_BSV_CHIP_INDICATION_ERR (CC_BSV_BASE_ERROR + 0x00000022) -/*! Device is locked in fatal error state. */ -#define CC_BSV_FATAL_ERR_IS_LOCKED_ERR (CC_BSV_BASE_ERROR + 0x00000023) -/*! Device has security disable feature enabled. */ -#define CC_BSV_SECURE_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000024) -/*! Device has Kcst in disabled state */ -#define CC_BSV_KCST_DISABLE_ERROR (CC_BSV_BASE_ERROR + 0x00000025) - - -/*! Illegal data-in pointer. */ -#define CC_BSV_CRYPTO_INVALID_DATA_IN_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000001) -/*! Illegal data-out pointer. */ -#define CC_BSV_CRYPTO_INVALID_DATA_OUT_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000002) -/*! Illegal data size. */ -#define CC_BSV_CRYPTO_INVALID_DATA_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000003) -/*! Illegal key type. */ -#define CC_BSV_CRYPTO_INVALID_KEY_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000004) -/*! Illegal key size. */ -#define CC_BSV_CRYPTO_INVALID_KEY_SIZE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000005) -/*! Invalid key pointer. */ -#define CC_BSV_CRYPTO_INVALID_KEY_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000006) -/*! Illegal key DMA type. */ -#define CC_BSV_CRYPTO_INVALID_KEY_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000007) -/*! Illegal IV pointer. */ -#define CC_BSV_CRYPTO_INVALID_IV_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000008) -/*! Illegal cipher mode. */ -#define CC_BSV_CRYPTO_INVALID_CIPHER_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000009) -/*! Illegal result buffer pointer. */ -#define CC_BSV_CRYPTO_INVALID_RESULT_BUFFER_POINTER_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000A) -/*! Invalid DMA type. */ -#define CC_BSV_CRYPTO_INVALID_DMA_TYPE_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000B) -/*! Invalid in/out buffers overlapping. */ -#define CC_BSV_CRYPTO_DATA_OUT_DATA_IN_OVERLAP_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000C) -/*! Invalid KDF label size. */ -#define CC_BSV_CRYPTO_ILLEGAL_KDF_LABEL_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000D) -/*! Invalid KDF Context size. */ -#define CC_BSV_CRYPTO_ILLEGAL_KDF_CONTEXT_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000E) -/*! Invalid CCM key. */ -#define CC_BSV_CCM_INVALID_KEY_ERROR (CC_BSV_CRYPTO_ERROR + 0x0000000f) -/*! Invalid CCM Nonce. */ -#define CC_BSV_CCM_INVALID_NONCE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000010) -/*! Invalid CCM associated data. */ -#define CC_BSV_CCM_INVALID_ASSOC_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000011) -/*! Invalid CCM text data. */ -#define CC_BSV_CCM_INVALID_TEXT_DATA_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000012) -/*! Invalid CCM-MAC buffer. */ -#define CC_BSV_CCM_INVALID_MAC_BUF_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000013) -/*! CCM-MAC comparison failed. */ -#define CC_BSV_CCM_TAG_LENGTH_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000014) -/*! CCM-MAC comparison failed. */ -#define CC_BSV_CCM_MAC_INVALID_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000015) -/*! Illegal flow mode. */ -#define CC_BSV_CRYPTO_INVALID_FLOW_MODE_ERROR (CC_BSV_CRYPTO_ERROR + 0x00000016) - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - - -
diff --git a/include/drivers/arm/cryptocell/713/cc_address_defs.h b/include/drivers/arm/cryptocell/713/cc_address_defs.h deleted file mode 100644 index 0abc15c..0000000 --- a/include/drivers/arm/cryptocell/713/cc_address_defs.h +++ /dev/null
@@ -1,50 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_ADDRESS_DEFS_H -#define _CC_ADDRESS_DEFS_H - -/*! -@file -@brief This file contains general definitions. -*/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" - -/************************ Defines ******************************/ - -/** - * Address types within CC - */ -/*! Definition of DMA address type, can be 32 bits or 64 bits according to CryptoCell's HW. */ -typedef uint64_t CCDmaAddr_t; -/*! Definition of CryptoCell address type, can be 32 bits or 64 bits according to platform. */ -typedef uint64_t CCAddr_t; -/*! Definition of CC SRAM address type, can be 32 bits according to CryptoCell's HW. */ -typedef uint32_t CCSramAddr_t; - -/* - * CCSramAddr_t is being cast into pointer type which can be 64 bit. - */ -/*! Definition of MACRO that casts SRAM addresses to pointer types. */ -#define CCSramAddr2Ptr(sramAddr) ((uintptr_t)sramAddr) - -#ifdef __cplusplus -} -#endif - -#endif - -/** - @} - */ - -
diff --git a/include/drivers/arm/cryptocell/713/cc_boot_defs.h b/include/drivers/arm/cryptocell/713/cc_boot_defs.h deleted file mode 100644 index 4d29a6d..0000000 --- a/include/drivers/arm/cryptocell/713/cc_boot_defs.h +++ /dev/null
@@ -1,52 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_BOOT_DEFS_H -#define _CC_BOOT_DEFS_H - -/*! - @file - @brief This file contains general definitions of types and enums of Boot APIs. - */ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! Version counters value. */ -typedef enum { - - CC_SW_VERSION_TRUSTED = 0, /*!< Trusted counter. */ - CC_SW_VERSION_NON_TRUSTED, /*!< Non trusted counter. */ - CC_SW_VERSION_MAX = 0x7FFFFFFF /*!< Reserved */ -} CCSbSwVersionId_t; - -/*! The hash boot key definition. */ -typedef enum { - CC_SB_HASH_BOOT_KEY_0_128B = 0, /*!< Hbk0: 128-bit truncated SHA-256 digest of PubKB0. Used by ICV */ - CC_SB_HASH_BOOT_KEY_1_128B = 1, /*!< Hbk1: 128-bit truncated SHA-256 digest of PubKB1. Used by OEM */ - CC_SB_HASH_BOOT_KEY_256B = 2, /*!< Hbk: 256-bit SHA-256 digest of public key. */ - CC_SB_HASH_BOOT_NOT_USED = 0xF, /*!< Hbk is not used. */ - CC_SB_HASH_MAX_NUM = 0x7FFFFFFF, /*!< Reserved. */ -} CCSbPubKeyIndexType_t; - -/*! Chip state. */ -typedef enum { - CHIP_STATE_NOT_INITIALIZED = 0, /*! Chip is not initialized. */ - CHIP_STATE_TEST = 1, /*! Chip is in Production state. */ - CHIP_STATE_PRODUCTION = 2, /*! Chip is in Production state. */ - CHIP_STATE_ERROR = 3, /*! Chip is in Error state. */ -} CCBsvChipState_t; -#ifdef __cplusplus -} -#endif - -#endif /*_CC_BOOT_DEFS_H */ - -/** -@} - */
diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types.h b/include/drivers/arm/cryptocell/713/cc_pal_types.h deleted file mode 100644 index 4ab3960..0000000 --- a/include/drivers/arm/cryptocell/713/cc_pal_types.h +++ /dev/null
@@ -1,100 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CC_PAL_TYPES_H -#define CC_PAL_TYPES_H - -/*! -@file -@brief This file contains platform-dependent definitions and types of the PAL layer. - -@defgroup cc_pal_types CryptoCell platform-dependent PAL layer definitions and types -@{ -@ingroup cc_pal - - @{ - @ingroup cc_pal - @} -*/ - -#include "cc_pal_types_plat.h" - -/*! Definition of Boolean type.*/ -typedef enum { - /*! Boolean false.*/ - CC_FALSE = 0, - /*! Boolean true.*/ - CC_TRUE = 1 -} CCBool_t; - -/*! Success. */ -#define CC_SUCCESS 0UL -/*! Failure. */ -#define CC_FAIL 1UL - -/*! Success (OK). */ -#define CC_OK 0 - -/*! This macro handles unused parameters in the code, to avoid compilation warnings. */ -#define CC_UNUSED_PARAM(prm) ((void)prm) - -/*! The maximal uint32 value.*/ -#define CC_MAX_UINT32_VAL (0xFFFFFFFF) - - -/* Minimal and Maximal macros */ -#ifdef min -/*! Definition for minimal calculation. */ -#define CC_MIN(a,b) min( a , b ) -#else -/*! Definition for minimal calculation. */ -#define CC_MIN( a , b ) ( ( (a) < (b) ) ? (a) : (b) ) -#endif - -#ifdef max -/*! Definition for maximal calculation. */ -#define CC_MAX(a,b) max( a , b ) -#else -/*! Definition for maximal calculation.. */ -#define CC_MAX( a , b ) ( ( (a) > (b) ) ? (a) : (b) ) -#endif - -/*! This macro calculates the number of full Bytes from bits, where seven bits are one Byte. */ -#define CALC_FULL_BYTES(numBits) ((numBits)/CC_BITS_IN_BYTE + (((numBits) & (CC_BITS_IN_BYTE-1)) > 0)) -/*! This macro calculates the number of full 32-bit words from bits where 31 bits are one word. */ -#define CALC_FULL_32BIT_WORDS(numBits) ((numBits)/CC_BITS_IN_32BIT_WORD + (((numBits) & (CC_BITS_IN_32BIT_WORD-1)) > 0)) -/*! This macro calculates the number of full 32-bit words from Bytes where three Bytes are one word. */ -#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) ((sizeBytes)/CC_32BIT_WORD_SIZE + (((sizeBytes) & (CC_32BIT_WORD_SIZE-1)) > 0)) -/*! This macro calculates the number of full 32-bit words from 64-bits dwords. */ -#define CALC_32BIT_WORDS_FROM_64BIT_DWORD(sizeWords) (sizeWords * CC_32BIT_WORD_IN_64BIT_DWORD) -/*! This macro rounds up bits to 32-bit words. */ -#define ROUNDUP_BITS_TO_32BIT_WORD(numBits) (CALC_FULL_32BIT_WORDS(numBits) * CC_BITS_IN_32BIT_WORD) -/*! This macro rounds up bits to Bytes. */ -#define ROUNDUP_BITS_TO_BYTES(numBits) (CALC_FULL_BYTES(numBits) * CC_BITS_IN_BYTE) -/*! This macro rounds up bytes to 32-bit words. */ -#define ROUNDUP_BYTES_TO_32BIT_WORD(sizeBytes) (CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) * CC_32BIT_WORD_SIZE) -/*! This macro calculates the number Bytes from words. */ -#define CALC_WORDS_TO_BYTES(numwords) ((numwords)*CC_32BIT_WORD_SIZE) -/*! Definition of 1 KB in Bytes. */ -#define CC_1K_SIZE_IN_BYTES 1024 -/*! Definition of number of bits in a Byte. */ -#define CC_BITS_IN_BYTE 8 -/*! Definition of number of bits in a 32-bits word. */ -#define CC_BITS_IN_32BIT_WORD 32 -/*! Definition of number of Bytes in a 32-bits word. */ -#define CC_32BIT_WORD_SIZE 4 -/*! Definition of number of 32-bits words in a 64-bits dword. */ -#define CC_32BIT_WORD_IN_64BIT_DWORD 2 - - -#endif - -/** -@} - */ - - -
diff --git a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h b/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h deleted file mode 100644 index 0c102a0..0000000 --- a/include/drivers/arm/cryptocell/713/cc_pal_types_plat.h +++ /dev/null
@@ -1,25 +0,0 @@ -/* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! @file -@brief This file contains basic type definitions that are platform-dependent. -*/ -#ifndef _CC_PAL_TYPES_PLAT_H -#define _CC_PAL_TYPES_PLAT_H -/* Host specific types for standard (ISO-C99) compliant platforms */ - -#include <stddef.h> -#include <stdint.h> - -typedef uint32_t CCStatus; - -#define CCError_t CCStatus -#define CC_INFINITE 0xFFFFFFFF - -#define CEXPORT_C -#define CIMPORT_C - -#endif /*_CC_PAL_TYPES_PLAT_H*/
diff --git a/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h b/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h deleted file mode 100644 index 1a1bce0..0000000 --- a/include/drivers/arm/cryptocell/713/cc_pka_hw_plat_defs.h +++ /dev/null
@@ -1,62 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_PKA_HW_PLAT_DEFS_H -#define _CC_PKA_HW_PLAT_DEFS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - -#include "cc_pal_types.h" -/*! -@file -@brief Contains the enums and definitions that are used in the PKA code (definitions that are platform dependent). -*/ - -/*! The size of the PKA engine word. */ -#define CC_PKA_WORD_SIZE_IN_BITS 128 - -/*! The maximal supported size of modulus in RSA in bits. */ -#define CC_RSA_MAX_VALID_KEY_SIZE_VALUE_IN_BITS 4096 -/*! The maximal supported size of key-generation in RSA in bits. */ -#define CC_RSA_MAX_KEY_GENERATION_HW_SIZE_BITS 4096 - -/*! Secure boot/debug certificate RSA public modulus key size in bits. */ -#if (KEY_SIZE == 3072) - #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 3072 -#else - #define BSV_CERT_RSA_KEY_SIZE_IN_BITS 2048 -#endif -/*! Secure boot/debug certificate RSA public modulus key size in bytes. */ -#define BSV_CERT_RSA_KEY_SIZE_IN_BYTES (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_BYTE) -/*! Secure boot/debug certificate RSA public modulus key size in words. */ -#define BSV_CERT_RSA_KEY_SIZE_IN_WORDS (BSV_CERT_RSA_KEY_SIZE_IN_BITS/CC_BITS_IN_32BIT_WORD) - -/*! The maximal count of extra bits in PKA operations. */ -#define PKA_EXTRA_BITS 8 -/*! The number of memory registers in PKA operations. */ -#define PKA_MAX_COUNT_OF_PHYS_MEM_REGS 32 - -/*! Size of buffer for Barrett modulus tag in words. */ -#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS 5 -/*! Size of buffer for Barrett modulus tag in bytes. */ -#define RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_BYTES (RSA_PKA_BARRETT_MOD_TAG_BUFF_SIZE_IN_WORDS*CC_32BIT_WORD_SIZE) - - - -#ifdef __cplusplus -} -#endif - -#endif //_CC_PKA_HW_PLAT_DEFS_H - -/** - @} - */ -
diff --git a/include/drivers/arm/cryptocell/713/cc_sec_defs.h b/include/drivers/arm/cryptocell/713/cc_sec_defs.h deleted file mode 100644 index 8fb698f..0000000 --- a/include/drivers/arm/cryptocell/713/cc_sec_defs.h +++ /dev/null
@@ -1,70 +0,0 @@ -/* - * Copyright (c) 2017-2020 ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_SEC_DEFS_H -#define _CC_SEC_DEFS_H - -/*! -@file -@brief This file contains general definitions and types. -*/ - - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "cc_pal_types.h" - -/*! Hashblock size in words. */ -#define HASH_BLOCK_SIZE_IN_WORDS 16 -/*! Hash - SHA2 results in words. */ -#define HASH_RESULT_SIZE_IN_WORDS 8 -/*! Hash - SHA2 results in bytes. */ -#define HASH_RESULT_SIZE_IN_BYTES 32 - -/*! Definition for hash result array. */ -typedef uint32_t CCHashResult_t[HASH_RESULT_SIZE_IN_WORDS]; - -/*! Definition for converting pointer to Host address. */ -#define CONVERT_TO_ADDR(ptr) (unsigned long)ptr - -/*! Definition for converting pointer to SRAM address. */ -#define CONVERT_TO_SRAM_ADDR(ptr) (0xFFFFFFFF & ptr) - -/*! The data size of the signed SW image, in bytes. */ -/*!\internal ContentCertImageRecord_t includes: HS(8W) + 64-b dstAddr(2W) + imgSize(1W) + isCodeEncUsed(1W) */ -#define SW_REC_SIGNED_DATA_SIZE_IN_BYTES 48 - -/*! The data size of the unsigned SW image, in bytes. */ -/*!\internal CCSbSwImgAddData_t includes: 64-b srcAddr(2W)*/ -#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES 8 - -/*! The additional data size - storage address and length of the unsigned SW image, in words. */ -#define SW_REC_NONE_SIGNED_DATA_SIZE_IN_WORDS SW_REC_NONE_SIGNED_DATA_SIZE_IN_BYTES/CC_32BIT_WORD_SIZE - -/*! The additional data section size, in bytes. */ -#define CC_SB_MAX_SIZE_ADDITIONAL_DATA_BYTES 128 - -/*! Indication of whether or not to load the SW image to memory. */ -#define CC_SW_COMP_NO_MEM_LOAD_INDICATION 0xFFFFFFFFFFFFFFFFUL - -/*! Indication of product version, stored in certificate version field. */ -#define CC_SB_CERT_VERSION_PROJ_PRD 0x713 - -#ifdef __cplusplus -} -#endif - -#endif - -/** -@} - */ - - -
diff --git a/include/drivers/arm/cryptocell/cc_rotpk.h b/include/drivers/arm/cryptocell/cc_rotpk.h deleted file mode 100644 index 9398496..0000000 --- a/include/drivers/arm/cryptocell/cc_rotpk.h +++ /dev/null
@@ -1,13 +0,0 @@ -/* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CC_ROTPK_H -#define _CC_ROTPK_H - -int cc_get_rotpk_hash(unsigned char *dst, unsigned int len, - unsigned int *flags); - -#endif
diff --git a/include/drivers/arm/dcc.h b/include/drivers/arm/dcc.h index 1f1fd03..072bed5 100644 --- a/include/drivers/arm/dcc.h +++ b/include/drivers/arm/dcc.h
@@ -15,5 +15,6 @@ * framework. */ int console_dcc_register(void); +void console_dcc_unregister(void); #endif /* DCC */
diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h index 993dd12..51ce65d 100644 --- a/include/drivers/arm/ethosn.h +++ b/include/drivers/arm/ethosn.h
@@ -47,7 +47,7 @@ #define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE) /* Service version */ -#define ETHOSN_VERSION_MAJOR U(3) +#define ETHOSN_VERSION_MAJOR U(4) #define ETHOSN_VERSION_MINOR U(0) /* Return codes for function calls */
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h index cfc168d..bebd9ce 100644 --- a/include/drivers/arm/gicv2.h +++ b/include/drivers/arm/gicv2.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -188,7 +188,7 @@ void gicv2_enable_interrupt(unsigned int id); void gicv2_disable_interrupt(unsigned int id); void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); -void gicv2_set_interrupt_type(unsigned int id, unsigned int type); +void gicv2_set_interrupt_group(unsigned int id, unsigned int group); void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num); void gicv2_set_spi_routing(unsigned int id, int proc_num); void gicv2_set_interrupt_pending(unsigned int id);
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h index 5bb22fd..cf6a746 100644 --- a/include/drivers/arm/gicv3.h +++ b/include/drivers/arm/gicv3.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -556,7 +556,7 @@ void gicv3_cpuif_disable(unsigned int proc_num); unsigned int gicv3_get_pending_interrupt_type(void); unsigned int gicv3_get_pending_interrupt_id(void); -unsigned int gicv3_get_interrupt_type(unsigned int id, +unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num); void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); @@ -579,8 +579,8 @@ void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, unsigned int priority); -void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, - unsigned int type); +void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num, + unsigned int group); void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group, u_register_t target); void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
diff --git a/include/drivers/auth/mbedtls/mbedtls_config-3.h b/include/drivers/auth/mbedtls/mbedtls_config-3.h index ba936a3..923fc54 100644 --- a/include/drivers/auth/mbedtls/mbedtls_config-3.h +++ b/include/drivers/auth/mbedtls/mbedtls_config-3.h
@@ -62,8 +62,12 @@ #if TF_MBEDTLS_USE_ECDSA #define MBEDTLS_ECDSA_C #define MBEDTLS_ECP_C +#if TF_MBEDTLS_KEY_SIZE == 384 +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#else #define MBEDTLS_ECP_DP_SECP256R1_ENABLED #endif +#endif #if TF_MBEDTLS_USE_RSA #define MBEDTLS_RSA_C #define MBEDTLS_X509_RSASSA_PSS_SUPPORT
diff --git a/include/drivers/auth/mbedtls/psa_mbedtls_config.h b/include/drivers/auth/mbedtls/psa_mbedtls_config.h new file mode 100644 index 0000000..ad825f0 --- /dev/null +++ b/include/drivers/auth/mbedtls/psa_mbedtls_config.h
@@ -0,0 +1,28 @@ +/* + * Copyright (c) 2023, Arm Ltd. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PSA_MBEDTLS_CONFIG_H +#define PSA_MBEDTLS_CONFIG_H + +#include "mbedtls_config-3.h" + +#define MBEDTLS_PSA_CRYPTO_C + +/* + * Using PSA crypto API requires an RNG right now. If we don't define the macro + * below then we get build errors. + * + * This is a functionality gap in mbedTLS. The technical limitation is that + * psa_crypto_init() is all-or-nothing, and fixing that would require separate + * initialization of the keystore, the RNG, etc. + * + * By defining MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG, we pretend using an external + * RNG. As a result, the PSA crypto init code does nothing when it comes to + * initializing the RNG, as we are supposed to take care of that ourselves. + */ +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +#endif /* PSA_MBEDTLS_CONFIG_H */
diff --git a/include/drivers/cadence/cdns_combo_phy.h b/include/drivers/cadence/cdns_combo_phy.h new file mode 100644 index 0000000..f5dabda --- /dev/null +++ b/include/drivers/cadence/cdns_combo_phy.h
@@ -0,0 +1,238 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_COMBOPHY_H +#define CDN_COMBOPHY_H + +/* SRS */ +#define SDMMC_CDN_SRS02 0x8 +#define SDMMC_CDN_SRS03 0xC +#define SDMMC_CDN_SRS04 0x10 +#define SDMMC_CDN_SRS05 0x14 +#define SDMMC_CDN_SRS06 0x18 +#define SDMMC_CDN_SRS07 0x1C +#define SDMMC_CDN_SRS09 0x24 +#define SDMMC_CDN_SRS10 0x28 +#define SDMMC_CDN_SRS11 0x2C +#define SDMMC_CDN_SRS12 0x30 +#define SDMMC_CDN_SRS13 0x34 +#define SDMMC_CDN_SRS14 0x38 + +/* SRS03 */ +/* Response Type Select + * Defines the expected response length. + */ +#define SDMMC_CDN_RTS 16 + +/* Command CRC Check Enable + * When set to 1, the host checks if the CRC field of the response is valid. + * When 0, the CRC check is disabled and the CRC field of the response is ignored. + */ +#define SDMMC_CDN_CRCCE 19 + +/* Command Index + * This field contains a command number (index) of the command to be sent. + */ +#define SDMMC_CDN_CIDX 24 + +/* SRS09 */ +/* Card Inserted + * Indicates if the card is inserted inside the slot. + */ +#define SDMMC_CDN_CI 16 + +/* SRS10 */ +/* Data Transfer Width + * Bit used to configure DAT bus width to 1 or 4. + */ +#define SDMMC_CDN_DTW 1 + +/* Extended Data Transfer Width + * This bit is to enable/disable 8-bit DAT bus width mode. + */ +#define SDMMC_CDN_EDTW 5 + +/* SD Bus Power for VDD1 + * When set to 1, the VDD1 voltage is supplied to card/device. + */ +#define SDMMC_CDN_BP 8 + +/* SD Bus Voltage Select + * This field is used to configure VDD1 voltage level. + */ +#define SDMMC_CDN_BVS 9 + +/* SRS11 */ +/* Internal Clock Enable + * This field is designated to controls (enable/disable) external clock generator. + */ +#define SDMMC_CDN_ICE 0 + +/* Internal Clock Stable + * When 1, indicates that the clock on sdmclk pin of the host is stable. + * When 0, indicates that the clock is not stable . + */ +#define SDMMC_CDN_ICS 1 + +/* SD Clock Enable + * When set, SDCLK clock is enabled. + * When clear, SDCLK clock is stopped. + */ +#define SDMMC_CDN_SDCE 2 + +/* USDCLK Frequency Select + * This is used to calculate frequency of USDCLK clock. + */ +#define SDMMC_CDN_USDCLKFS 6 + +/* SDCLK Frequency Select + * This is used to calculate frequency of SDCLK clock. + */ +#define SDMMC_CDN_SDCLKFS 8 + +/* Data Timeout Counter Value + * This value determines the interval by which DAT line timeouts are detected + */ +#define SDMMC_CDN_DTCV 16 + +/* SRS12 */ +/* Command Complete + * Generated when the end bit of the response is received. + */ +#define SDMMC_CDN_CC 0 + +/* Transfer Complete + * Generated when the transfer which uses the DAT line is complete. + */ +#define SDMMC_CDN_TC 1 + +/* Error Interrupt + * The software can check for an error by reading this single bit first. + */ +#define SDMMC_CDN_EINT 15 + +/* SRS14 */ +/* Command Complete Interrupt Enable */ +#define SDMMC_CDN_CC_IE 0 + +/* Transfer Complete Interrupt Enable */ +#define SDMMC_CDN_TC_IE 1 + +/* DMA Interrupt Enable */ +#define SDMMC_CDN_DMAINT_IE 3 + +/* Combo PHY DLL registers */ +#define CP_DLL_REG_BASE (0x10B92000) +#define CP_DLL_DQ_TIMING_REG (0x00) +#define CP_DLL_DQS_TIMING_REG (0x04) +#define CP_DLL_GATE_LPBK_CTRL_REG (0x08) +#define CP_DLL_MASTER_CTRL_REG (0x0C) +#define CP_DLL_SLAVE_CTRL_REG (0x10) +#define CP_DLL_IE_TIMING_REG (0x14) + +#define CP_DQ_TIMING_REG_SDR (0x00000002) +#define CP_DQS_TIMING_REG_SDR (0x00100004) +#define CP_GATE_LPBK_CTRL_REG_SDR (0x00D80000) +#define CP_DLL_MASTER_CTRL_REG_SDR (0x00800000) +#define CP_DLL_SLAVE_CTRL_REG_SDR (0x00000000) + +#define CP_DLL(_reg) (CP_DLL_REG_BASE \ + + (CP_DLL_##_reg)) + +/* Control Timing Block registers */ +#define CP_CTB_REG_BASE (0x10B92080) +#define CP_CTB_CTRL_REG (0x00) +#define CP_CTB_TSEL_REG (0x04) +#define CP_CTB_GPIO_CTRL0 (0x08) +#define CP_CTB_GPIO_CTRL1 (0x0C) +#define CP_CTB_GPIO_STATUS0 (0x10) +#define CP_CTB_GPIO_STATUS1 (0x14) + +#define CP_CTRL_REG_SDR (0x00004040) +#define CP_TSEL_REG_SDR (0x00000000) + +#define CP_CTB(_reg) (CP_CTB_REG_BASE \ + + (CP_CTB_##_reg)) + +/* Combo PHY */ +#define SDMMC_CDN_REG_BASE 0x10808200 +#define PHY_DQ_TIMING_REG 0x2000 +#define PHY_DQS_TIMING_REG 0x2004 +#define PHY_GATE_LPBK_CTRL_REG 0x2008 +#define PHY_DLL_MASTER_CTRL_REG 0x200C +#define PHY_DLL_SLAVE_CTRL_REG 0x2010 +#define PHY_CTRL_REG 0x2080 +#define PHY_REG_ADDR_MASK 0xFFFF +#define PHY_REG_DATA_MASK 0xFFFFFFFF + +/* PHY_DQS_TIMING_REG */ +#define CP_USE_EXT_LPBK_DQS(x) ((x) << 22) //0x1 +#define CP_USE_LPBK_DQS(x) ((x) << 21) //0x1 +#define CP_USE_PHONY_DQS(x) ((x) << 20) //0x1 +#define CP_USE_PHONY_DQS_CMD(x) ((x) << 19) //0x1 + +/* PHY_GATE_LPBK_CTRL_REG */ +#define CP_SYNC_METHOD(x) ((x) << 31) //0x1 +#define CP_SW_HALF_CYCLE_SHIFT(x) ((x) << 28) //0x1 +#define CP_RD_DEL_SEL(x) ((x) << 19) //0x3f +#define CP_UNDERRUN_SUPPRESS(x) ((x) << 18) //0x1 +#define CP_GATE_CFG_ALWAYS_ON(x) ((x) << 6) //0x1 + +/* PHY_DLL_MASTER_CTRL_REG */ +#define CP_DLL_BYPASS_MODE(x) ((x) << 23) //0x1 +#define CP_DLL_START_POINT(x) ((x) << 0) //0xff + +/* PHY_DLL_SLAVE_CTRL_REG */ +#define CP_READ_DQS_CMD_DELAY(x) ((x) << 24) //0xff +#define CP_CLK_WRDQS_DELAY(x) ((x) << 16) //0xff +#define CP_CLK_WR_DELAY(x) ((x) << 8) //0xff +#define CP_READ_DQS_DELAY(x) ((x) << 0) //0xff + +/* PHY_DQ_TIMING_REG */ +#define CP_IO_MASK_ALWAYS_ON(x) ((x) << 31) //0x1 +#define CP_IO_MASK_END(x) ((x) << 27) //0x7 +#define CP_IO_MASK_START(x) ((x) << 24) //0x7 +#define CP_DATA_SELECT_OE_END(x) ((x) << 0) //0x7 + +/* PHY_CTRL_REG */ +#define CP_PHONY_DQS_TIMING_MASK 0x3F +#define CP_PHONY_DQS_TIMING_SHIFT 4 + +/* Shared Macros */ +#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ + (SDMMC_CDN_##_reg)) + +struct cdns_sdmmc_combo_phy { + uint32_t cp_clk_wr_delay; + uint32_t cp_clk_wrdqs_delay; + uint32_t cp_data_select_oe_end; + uint32_t cp_dll_bypass_mode; + uint32_t cp_dll_locked_mode; + uint32_t cp_dll_start_point; + uint32_t cp_gate_cfg_always_on; + uint32_t cp_io_mask_always_on; + uint32_t cp_io_mask_end; + uint32_t cp_io_mask_start; + uint32_t cp_rd_del_sel; + uint32_t cp_read_dqs_cmd_delay; + uint32_t cp_read_dqs_delay; + uint32_t cp_sw_half_cycle_shift; + uint32_t cp_sync_method; + uint32_t cp_underrun_suppress; + uint32_t cp_use_ext_lpbk_dqs; + uint32_t cp_use_lpbk_dqs; + uint32_t cp_use_phony_dqs; + uint32_t cp_use_phony_dqs_cmd; +}; + +/* Function Prototype */ + +int cdns_sdmmc_write_phy_reg(uint32_t phy_reg_addr, uint32_t phy_reg_addr_value, + uint32_t phy_reg_data, uint32_t phy_reg_data_value); +int cdns_sd_card_detect(void); +int cdns_emmc_card_reset(void); + +#endif
diff --git a/include/drivers/cadence/cdns_nand.h b/include/drivers/cadence/cdns_nand.h new file mode 100644 index 0000000..64ba267 --- /dev/null +++ b/include/drivers/cadence/cdns_nand.h
@@ -0,0 +1,256 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_NAND_H +#define CDN_NAND_H + +#include <drivers/cadence/cdns_combo_phy.h> + +/* NAND flash device information */ +typedef struct cnf_dev_info { + uint8_t type; + uint8_t nluns; + uint8_t sector_cnt; + uint16_t npages_per_block; + uint16_t sector_size; + uint16_t last_sector_size; + uint16_t page_size; + uint16_t spare_size; + uint32_t nblocks_per_lun; + uint32_t block_size; + unsigned long long total_size; +} cnf_dev_info_t; + +/* Shared Macros */ + +/* Default values */ +#define CNF_DEF_VOL_ID 0 +#define CNF_DEF_DEVICE 0 +#define CNF_DEF_TRD 0 +#define CNF_READ_SINGLE_PAGE 1 +#define CNF_DEF_DELAY_US 500 +#define CNF_READ_INT_DELAY_US 10 + +/* Work modes */ +#define CNF_WORK_MODE_CDMA 0 +#define CNF_WORK_MODE_PIO 1 + +/* Command types */ +#define CNF_CT_SET_FEATURE 0x0100 +#define CNF_CT_RESET_ASYNC 0x1100 +#define CNF_CT_RESET_SYNC 0x1101 +#define CNF_CT_RESET_LUN 0x1102 +#define CNF_CT_ERASE 0x1000 +#define CNF_CT_PAGE_PROGRAM 0x2100 +#define CNF_CT_PAGE_READ 0x2200 + +/* Interrupts enable or disable */ +#define CNF_INT_EN 1 +#define CNF_INT_DIS 0 + +/* Device types */ +#define CNF_DT_UNKNOWN 0x00 +#define CNF_DT_ONFI 0x01 +#define CNF_DT_JEDEC 0x02 +#define CNF_DT_LEGACY 0x03 + +/* Command and status registers */ +#define CNF_CMDREG_REG_BASE SOCFPGA_NAND_REG_BASE + +/* DMA maximum burst size 0-127*/ +#define CNF_DMA_BURST_SIZE_MAX 127 + +/* DMA settings register field offsets */ +#define CNF_DMA_SETTINGS_BURST 0 +#define CNF_DMA_SETTINGS_OTE 16 +#define CNF_DMA_SETTINGS_SDMA_ERR 17 + +#define CNF_DMA_MASTER_SEL 1 +#define CNF_DMA_SLAVE_SEL 0 + +/* DMA FIFO trigger level register field offsets */ +#define CNF_FIFO_TLEVEL_POS 0 +#define CNF_FIFO_TLEVEL_DMA_SIZE 16 +#define CNF_DMA_PREFETCH_SIZE (1024 / 8) + +#define CNF_GET_CTRL_BUSY(x) (x & (1 << 8)) +#define CNF_GET_INIT_COMP(x) (x & (1 << 9)) + +/* Command register0 field offsets */ +#define CNF_CMDREG0_CT 30 +#define CNF_CMDREG0_TRD 24 +#define CNF_CMDREG0_INTR 20 +#define CNF_CMDREG0_DMA 21 +#define CNF_CMDREG0_VOL 16 +#define CNF_CMDREG0_CMD 0 +#define CNF_CMDREG4_MEM 24 + +/* Command status register field offsets */ +#define CNF_ECMD BIT(0) +#define CNF_EECC BIT(1) +#define CNF_EMAX BIT(2) +#define CNF_EDEV BIT(12) +#define CNF_EDQS BIT(13) +#define CNF_EFAIL BIT(14) +#define CNF_CMPLT BIT(15) +#define CNF_EBUS BIT(16) +#define CNF_EDI BIT(17) +#define CNF_EPAR BIT(18) +#define CNF_ECTX BIT(19) +#define CNF_EPRO BIT(20) +#define CNF_EIDX BIT(24) + +#define CNF_CMDREG_CMD_REG0 0x00 +#define CNF_CMDREG_CMD_REG1 0x04 +#define CNF_CMDREG_CMD_REG2 0x08 +#define CNF_CMDREG_CMD_REG3 0x0C +#define CNF_CMDREG_CMD_STAT_PTR 0x10 +#define CNF_CMDREG_CMD_STAT 0x14 +#define CNF_CMDREG_CMD_REG4 0x20 +#define CNF_CMDREG_CTRL_STATUS 0x118 +#define CNF_CMDREG_TRD_STATUS 0x120 + +#define CNF_CMDREG(_reg) (CNF_CMDREG_REG_BASE \ + + (CNF_CMDREG_##_reg)) + +/* Controller configuration registers */ +#define CNF_LSB16_MASK 0xFFFF +#define CNF_GET_NPAGES_PER_BLOCK(x) (x & CNF_LSB16_MASK) + +#define CNF_GET_SCTR_SIZE(x) (x & CNF_LSB16_MASK) +#define CNF_GET_LAST_SCTR_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) + +#define CNF_GET_PAGE_SIZE(x) (x & CNF_LSB16_MASK) +#define CNF_GET_SPARE_SIZE(x) ((x >> 16) & CNF_LSB16_MASK) + +#define CNF_CTRLCFG_REG_BASE 0x10B80400 +#define CNF_CTRLCFG_TRANS_CFG0 0x00 +#define CNF_CTRLCFG_TRANS_CFG1 0x04 +#define CNF_CTRLCFG_LONG_POLL 0x08 +#define CNF_CTRLCFG_SHORT_POLL 0x0C +#define CNF_CTRLCFG_DEV_STAT 0x10 +#define CNF_CTRLCFG_DEV_LAYOUT 0x24 +#define CNF_CTRLCFG_ECC_CFG0 0x28 +#define CNF_CTRLCFG_ECC_CFG1 0x2C +#define CNF_CTRLCFG_MULTIPLANE_CFG 0x34 +#define CNF_CTRLCFG_CACHE_CFG 0x38 +#define CNF_CTRLCFG_DMA_SETTINGS 0x3C +#define CNF_CTRLCFG_FIFO_TLEVEL 0x54 + +#define CNF_CTRLCFG(_reg) (CNF_CTRLCFG_REG_BASE \ + + (CNF_CTRLCFG_##_reg)) + +/* Data integrity registers */ +#define CNF_DI_PAR_EN 0 +#define CNF_DI_CRC_EN 1 + +#define CNF_DI_REG_BASE 0x10B80700 +#define CNF_DI_CONTROL 0x00 +#define CNF_DI_INJECT0 0x04 +#define CNF_DI_INJECT1 0x08 +#define CNF_DI_ERR_REG_ADDR 0x0C +#define CNF_DI_INJECT2 0x10 + +#define CNF_DI(_reg) (CNF_DI_REG_BASE \ + + (CNF_DI_##_reg)) + +/* Controller parameter registers */ +#define CNF_NTHREADS_MASK 0x07 +#define CNF_GET_NLUNS(x) (x & 0xFF) +#define CNF_GET_DEV_TYPE(x) ((x >> 30) & 0x03) +#define CNF_GET_NTHREADS(x) (1 << (x & CNF_NTHREADS_MASK)) + +#define CNF_CTRLPARAM_REG_BASE 0x10B80800 +#define CNF_CTRLPARAM_VERSION 0x00 +#define CNF_CTRLPARAM_FEATURE 0x04 +#define CNF_CTRLPARAM_MFR_ID 0x08 +#define CNF_CTRLPARAM_DEV_AREA 0x0C +#define CNF_CTRLPARAM_DEV_PARAMS0 0x10 +#define CNF_CTRLPARAM_DEV_PARAMS1 0x14 +#define CNF_CTRLPARAM_DEV_FEATUERS 0x18 +#define CNF_CTRLPARAM_DEV_BLOCKS_PLUN 0x1C + +#define CNF_CTRLPARAM(_reg) (CNF_CTRLPARAM_REG_BASE \ + + (CNF_CTRLPARAM_##_reg)) + +/* Protection mechanism registers */ +#define CNF_PROT_REG_BASE 0x10B80900 +#define CNF_PROT_CTRL0 0x00 +#define CNF_PROT_DOWN0 0x04 +#define CNF_PROT_UP0 0x08 +#define CNF_PROT_CTRL1 0x10 +#define CNF_PROT_DOWN1 0x14 +#define CNF_PROT_UP1 0x18 + +#define CNF_PROT(_reg) (CNF_PROT_REG_BASE \ + + (CNF_PROT_##_reg)) + +/* Mini controller registers */ +#define CNF_MINICTRL_REG_BASE 0x10B81000 + +/* Operation work modes */ +#define CNF_OPR_WORK_MODE_SDR 0 +#define CNF_OPR_WORK_MODE_NVDDR 1 +#define CNF_OPR_WORK_MODE_TOGGLE_NVDDR2_3 2 +#define CNF_OPR_WORK_MODE_RES 3 + +/* Mini controller common settings register field offsets */ +#define CNF_CMN_SETTINGS_WR_WUP 20 +#define CNF_CMN_SETTINGS_RD_WUP 16 +#define CNF_CMN_SETTINGS_DEV16 8 +#define CNF_CMN_SETTINGS_OPR 0 + +/* Async mode register field offsets */ +#define CNF_ASYNC_TIMINGS_TRH 24 +#define CNF_ASYNC_TIMINGS_TRP 16 +#define CNF_ASYNC_TIMINGS_TWH 8 +#define CNF_ASYNC_TIMINGS_TWP 0 + +/* Mini controller DLL PHY controller register field offsets */ +#define CNF_DLL_PHY_RST_N 24 +#define CNF_DLL_PHY_EXT_WR_MODE 17 +#define CNF_DLL_PHY_EXT_RD_MODE 16 + +#define CNF_MINICTRL_WP_SETTINGS 0x00 +#define CNF_MINICTRL_RBN_SETTINGS 0x04 +#define CNF_MINICTRL_CMN_SETTINGS 0x08 +#define CNF_MINICTRL_SKIP_BYTES_CFG 0x0C +#define CNF_MINICTRL_SKIP_BYTES_OFFSET 0x10 +#define CNF_MINICTRL_TOGGLE_TIMINGS0 0x14 +#define CNF_MINICTRL_TOGGLE_TIMINGS1 0x18 +#define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS 0x1C +#define CNF_MINICTRL_SYNC_TIMINGS 0x20 +#define CNF_MINICTRL_DLL_PHY_CTRL 0x34 + +#define CNF_MINICTRL(_reg) (CNF_MINICTRL_REG_BASE \ + + (CNF_MINICTRL_##_reg)) + +/* + * @brief Nand IO MTD initialization routine + * + * @total_size: [out] Total size of the NAND flash device + * @erase_size: [out] Minimum erase size of the NAND flash device + * Return: 0 on success, a negative errno on failure + */ +int cdns_nand_init_mtd(unsigned long long *total_size, + unsigned int *erase_size); + +/* + * @brief Read bytes from the NAND flash device + * + * @offset: Byte offset to read from in device + * @buffer: [out] Bytes read from device + * @length: Number of bytes to read + * @out_length: [out] Number of bytes read from device + * Return: 0 on success, a negative errno on failure + */ +int cdns_nand_read(unsigned int offset, uintptr_t buffer, + size_t length, size_t *out_length); + +/* NAND Flash Controller/Host initialization */ +int cdns_nand_host_init(void); + +#endif
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h new file mode 100644 index 0000000..6452725 --- /dev/null +++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -0,0 +1,474 @@ +/* + * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CDN_MMC_H +#define CDN_MMC_H + +#include <drivers/cadence/cdns_combo_phy.h> +#include <drivers/mmc.h> +#include "socfpga_plat_def.h" + +#if MMC_DEVICE_TYPE == 0 +#define CONFIG_DMA_ADDR_T_64BIT 0 +#endif + +#define MMC_REG_BASE SOCFPGA_MMC_REG_BASE +#define COMBO_PHY_REG 0x0 +#define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7 +#define SDHC_DLL_RESET_MASK 0x00000001 +/* HRS09 */ +#define SDHC_PHY_SW_RESET BIT(0) +#define SDHC_PHY_INIT_COMPLETE BIT(1) +#define SDHC_EXTENDED_RD_MODE(x) ((x) << 2) +#define EXTENDED_WR_MODE 3 +#define SDHC_EXTENDED_WR_MODE(x) ((x) << 3) +#define RDCMD_EN 15 +#define SDHC_RDCMD_EN(x) ((x) << 15) +#define SDHC_RDDATA_EN(x) ((x) << 16) + +/* CMD_DATA_OUTPUT */ +#define SDHC_CDNS_HRS16 0x40 + +/* This value determines the interval by which DAT line timeouts are detected */ +/* The interval can be computed as below: */ +/* • 1111b - Reserved */ +/* • 1110b - t_sdmclk*2(27+2) */ +/* • 1101b - t_sdmclk*2(26+2) */ +#define READ_CLK 0xa << 16 +#define WRITE_CLK 0xe << 16 +#define DTC_VAL 0xE + +/* SRS00 */ +/* System Address / Argument 2 / 32-bit block count + * This field is used as: + * • 32-bit Block Count register + * • SDMA system memory address + * • Auto CMD23 Argument + */ +#define SAAR (1) + +/* SRS01 */ +/* Transfer Block Size + * This field defines block size for block data transfers + */ +#define BLOCK_SIZE 0 + +/* SDMA Buffer Boundary + * System address boundary can be set for SDMA engine. + */ +#define SDMA_BUF 7 << 12 + +/* Block Count For Current Transfer + * To set the number of data blocks can be defined for next transfer + */ +#define BLK_COUNT_CT 16 + +/* SRS03 */ +#define CMD_START (U(1) << 31) +#define CMD_USE_HOLD_REG (1 << 29) +#define CMD_UPDATE_CLK_ONLY (1 << 21) +#define CMD_SEND_INIT (1 << 15) +#define CMD_STOP_ABORT_CMD (4 << 22) +#define CMD_RESUME_CMD (2 << 22) +#define CMD_SUSPEND_CMD (1 << 22) +#define DATA_PRESENT (1 << 21) +#define CMD_IDX_CHK_ENABLE (1 << 20) +#define CMD_WRITE (0 << 4) +#define CMD_READ (1 << 4) +#define MULTI_BLK_READ (1 << 5) +#define RESP_ERR (1 << 7) +#define CMD_CHECK_RESP_CRC (1 << 19) +#define RES_TYPE_SEL_48 (2 << 16) +#define RES_TYPE_SEL_136 (1 << 16) +#define RES_TYPE_SEL_48_B (3 << 16) +#define RES_TYPE_SEL_NO (0 << 16) +#define DMA_ENABLED (1 << 0) +#define BLK_CNT_EN (1 << 1) +#define AUTO_CMD_EN (2 << 2) +#define COM_IDX 24 +#define ERROR_INT (1 << 15) +#define INT_SBE (1 << 13) +#define INT_HLE (1 << 12) +#define INT_FRUN (1 << 11) +#define INT_DRT (1 << 9) +#define INT_RTO (1 << 8) +#define INT_DCRC (1 << 7) +#define INT_RCRC (1 << 6) +#define INT_RXDR (1 << 5) +#define INT_TXDR (1 << 4) +#define INT_DTO (1 << 3) +#define INT_CMD_DONE (1 << 0) +#define TRAN_COMP (1 << 1) + +/* SRS09 */ +#define STATUS_DATA_BUSY BIT(2) + +/* SRS10 */ +/* LED Control + * State of this bit directly drives led port of the host + * in order to control the external LED diode + * Default value 0 << 1 + */ +#define LEDC BIT(0) +#define LEDC_OFF 0 << 1 + +/* Data Transfer Width + * Bit used to configure DAT bus width to 1 or 4 + * Default value 1 << 1 + */ +#define DT_WIDTH BIT(1) +#define DTW_4BIT 1 << 1 + +/* Extended Data Transfer Width + * This bit is to enable/disable 8-bit DAT bus width mode + * Default value 1 << 5 + */ +#define EDTW_8BIT 1 << 5 + +/* High Speed Enable + * Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1) + */ +#define HS_EN BIT(2) + +/* here 0 defines the 64 Kb size */ +#define MAX_64KB_PAGE 0 +#define EMMC_DESC_SIZE (1<<20) + +/* SRS11 */ +/* Software Reset For All + * When set to 1, the entire slot is reset + * After completing the reset operation, SRFA bit is automatically cleared + */ +#define SRFA BIT(24) + +/* Software Reset For CMD Line + * When set to 1, resets the logic related to the command generation and response checking + */ +#define SRCMD BIT(25) + +/* Software Reset For DAT Line + * When set to 1, resets the logic related to the data path, + * including data buffers and the DMA logic + */ +#define SRDAT BIT(26) + +/* SRS15 */ +/* UHS Mode Select + * Used to select one of UHS-I modes. + * • 000b - SDR12 + * • 001b - SDR25 + * • 010b - SDR50 + * • 011b - SDR104 + * • 100b - DDR50 + */ +#define SDR12_MODE 0 << 16 +#define SDR25_MODE 1 << 16 +#define SDR50_MODE 2 << 16 +#define SDR104_MODE 3 << 16 +#define DDR50_MODE 4 << 16 +/* 1.8V Signaling Enable + * • 0 - for Default Speed, High Speed mode + * • 1 - for UHS-I mode + */ +#define V18SE BIT(19) + +/* CMD23 Enable + * In result of Card Identification process, + * Host Driver set this bit to 1 if Card supports CMD23 + */ +#define CMD23_EN BIT(27) + +/* Host Version 4.00 Enable + * • 0 - Version 3.00 + * • 1 - Version 4.00 + */ +#define HV4E BIT(28) +/* Conf depends on SRS15.HV4E */ +#define SDMA 0 << 3 +#define ADMA2_32 2 << 3 +#define ADMA2_64 3 << 3 + +/* Preset Value Enable + * Setting this bit to 1 triggers an automatically update of SRS11 + */ +#define PVE BIT(31) + +#define BIT_AD_32 0 << 29 +#define BIT_AD_64 1 << 29 + +/* SW RESET REG*/ +#define SDHC_CDNS_HRS00 (0x00) +#define SDHC_CDNS_HRS00_SWR BIT(0) + +/* PHY access port */ +#define SDHC_CDNS_HRS04 0x10 +#define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0) + +/* PHY data access port */ +#define SDHC_CDNS_HRS05 0x14 + +/* eMMC control registers */ +#define SDHC_CDNS_HRS06 0x18 + +/* SRS */ +#define SDHC_CDNS_SRS_BASE 0x200 +#define SDHC_CDNS_SRS00 0x200 +#define SDHC_CDNS_SRS01 0x204 +#define SDHC_CDNS_SRS02 0x208 +#define SDHC_CDNS_SRS03 0x20c +#define SDHC_CDNS_SRS04 0x210 +#define SDHC_CDNS_SRS05 0x214 +#define SDHC_CDNS_SRS06 0x218 +#define SDHC_CDNS_SRS07 0x21C +#define SDHC_CDNS_SRS08 0x220 +#define SDHC_CDNS_SRS09 0x224 +#define SDHC_CDNS_SRS09_CI BIT(16) +#define SDHC_CDNS_SRS10 0x228 +#define SDHC_CDNS_SRS11 0x22C +#define SDHC_CDNS_SRS12 0x230 +#define SDHC_CDNS_SRS13 0x234 +#define SDHC_CDNS_SRS14 0x238 +#define SDHC_CDNS_SRS15 0x23c +#define SDHC_CDNS_SRS21 0x254 +#define SDHC_CDNS_SRS22 0x258 +#define SDHC_CDNS_SRS23 0x25c + +/* HRS07 */ +#define SDHC_CDNS_HRS07 0x1c +#define SDHC_IDELAY_VAL(x) ((x) << 0) +#define SDHC_RW_COMPENSATE(x) ((x) << 16) + +/* PHY reset port */ +#define SDHC_CDNS_HRS09 0x24 + +/* HRS10 */ +/* PHY reset port */ +#define SDHC_CDNS_HRS10 0x28 + +/* HCSDCLKADJ DATA; DDR Mode */ +#define SDHC_HCSDCLKADJ(x) ((x) << 16) + +/* Pinmux headers will reomove after ATF driver implementation */ +#define PINMUX_SDMMC_SEL 0x0 +#define PIN0SEL 0x00 +#define PIN1SEL 0x04 +#define PIN2SEL 0x08 +#define PIN3SEL 0x0C +#define PIN4SEL 0x10 +#define PIN5SEL 0x14 +#define PIN6SEL 0x18 +#define PIN7SEL 0x1C +#define PIN8SEL 0x20 +#define PIN9SEL 0x24 +#define PIN10SEL 0x28 + +/* HRS16 */ +#define SDHC_WRCMD0_DLY(x) ((x) << 0) +#define SDHC_WRCMD1_DLY(x) ((x) << 4) +#define SDHC_WRDATA0_DLY(x) ((x) << 8) +#define SDHC_WRDATA1_DLY(x) ((x) << 12) +#define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16) +#define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20) +#define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24) +#define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28) + +/* Shared Macros */ +#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ + (SDMMC_CDN_##_reg)) + +/* Refer to atf/tools/cert_create/include/debug.h */ +#define BIT_32(nr) (U(1) << (nr)) + +/* MMC Peripheral Definition */ +#define SOCFPGA_MMC_BLOCK_SIZE U(8192) +#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1)) +#define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000) +#define MMC_RESPONSE_NONE 0 +#define SDHC_CDNS_SRS03_VALUE 0x01020013 + +/* Value randomly chosen for eMMC RCA, it should be > 1 */ +#define MMC_FIX_RCA 6 +#define RCA_SHIFT_OFFSET 16 + +#define CMD_EXTCSD_PARTITION_CONFIG 179 +#define CMD_EXTCSD_BUS_WIDTH 183 +#define CMD_EXTCSD_HS_TIMING 185 +#define CMD_EXTCSD_SEC_CNT 212 + +#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) +#define PART_CFG_PARTITION1_ACCESS (U(1) << 0) + +/* Values in EXT CSD register */ +#define MMC_BUS_WIDTH_1 U(0) +#define MMC_BUS_WIDTH_4 U(1) +#define MMC_BUS_WIDTH_8 U(2) +#define MMC_BUS_WIDTH_DDR_4 U(5) +#define MMC_BUS_WIDTH_DDR_8 U(6) +#define MMC_BOOT_MODE_BACKWARD (U(0) << 3) +#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) +#define MMC_BOOT_MODE_DDR (U(2) << 3) + +#define EXTCSD_SET_CMD (U(0) << 24) +#define EXTCSD_SET_BITS (U(1) << 24) +#define EXTCSD_CLR_BITS (U(2) << 24) +#define EXTCSD_WRITE_BYTES (U(3) << 24) +#define EXTCSD_CMD(x) (((x) & 0xff) << 16) +#define EXTCSD_VALUE(x) (((x) & 0xff) << 8) +#define EXTCSD_CMD_SET_NORMAL U(1) + +#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) +#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) +#define CSD_TRAN_SPEED_MULT_SHIFT 3 + +#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) +#define STATUS_READY_FOR_DATA BIT(8) +#define STATUS_SWITCH_ERROR BIT(7) +#define MMC_GET_STATE(x) (((x) >> 9) & 0xf) +#define MMC_STATE_IDLE 0 +#define MMC_STATE_READY 1 +#define MMC_STATE_IDENT 2 +#define MMC_STATE_STBY 3 +#define MMC_STATE_TRAN 4 +#define MMC_STATE_DATA 5 +#define MMC_STATE_RCV 6 +#define MMC_STATE_PRG 7 +#define MMC_STATE_DIS 8 +#define MMC_STATE_BTST 9 +#define MMC_STATE_SLP 10 + +#define MMC_FLAG_CMD23 (U(1) << 0) + +#define CMD8_CHECK_PATTERN U(0xAA) +#define VHS_2_7_3_6_V BIT(8) + +/*ADMA table component*/ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 + +enum sd_opcode { + SD_GO_IDLE_STATE = 0, + SD_ALL_SEND_CID = 2, + SD_SEND_RELATIVE_ADDR = 3, + SDIO_SEND_OP_COND = 5, /* SDIO cards only */ + SD_SWITCH = 6, + SD_SELECT_CARD = 7, + SD_SEND_IF_COND = 8, + SD_SEND_CSD = 9, + SD_SEND_CID = 10, + SD_VOL_SWITCH = 11, + SD_STOP_TRANSMISSION = 12, + SD_SEND_STATUS = 13, + SD_GO_INACTIVE_STATE = 15, + SD_SET_BLOCK_SIZE = 16, + SD_READ_SINGLE_BLOCK = 17, + SD_READ_MULTIPLE_BLOCK = 18, + SD_SEND_TUNING_BLOCK = 19, + SD_SET_BLOCK_COUNT = 23, + SD_WRITE_SINGLE_BLOCK = 24, + SD_WRITE_MULTIPLE_BLOCK = 25, + SD_ERASE_BLOCK_START = 32, + SD_ERASE_BLOCK_END = 33, + SD_ERASE_BLOCK_OPERATION = 38, + SD_APP_CMD = 55, + SD_SPI_READ_OCR = 58, /* SPI mode only */ + SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ +}; + +enum sd_app_cmd { + SD_APP_SET_BUS_WIDTH = 6, + SD_APP_SEND_STATUS = 13, + SD_APP_SEND_NUM_WRITTEN_BLK = 22, + SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, + SD_APP_SEND_OP_COND = 41, + SD_APP_CLEAR_CARD_DETECT = 42, + SD_APP_SEND_SCR = 51, +}; + +struct cdns_sdmmc_sdhc { + uint32_t sdhc_extended_rd_mode; + uint32_t sdhc_extended_wr_mode; + uint32_t sdhc_hcsdclkadj; + uint32_t sdhc_idelay_val; + uint32_t sdhc_rdcmd_en; + uint32_t sdhc_rddata_en; + uint32_t sdhc_rw_compensate; + uint32_t sdhc_sdcfsh; + uint32_t sdhc_sdcfsl; + uint32_t sdhc_wrcmd0_dly; + uint32_t sdhc_wrcmd0_sdclk_dly; + uint32_t sdhc_wrcmd1_dly; + uint32_t sdhc_wrcmd1_sdclk_dly; + uint32_t sdhc_wrdata0_dly; + uint32_t sdhc_wrdata0_sdclk_dly; + uint32_t sdhc_wrdata1_dly; + uint32_t sdhc_wrdata1_sdclk_dly; +}; + +enum sdmmc_device_mode { + SD_DS_ID, /* Identification */ + SD_DS, /* Default speed */ + SD_HS, /* High speed */ + SD_UHS_SDR12, /* Ultra high speed SDR12 */ + SD_UHS_SDR25, /* Ultra high speed SDR25 */ + SD_UHS_SDR50, /* Ultra high speed SDR`50 */ + SD_UHS_SDR104, /* Ultra high speed SDR104 */ + SD_UHS_DDR50, /* Ultra high speed DDR50 */ + EMMC_SDR_BC, /* SDR backward compatible */ + EMMC_SDR, /* SDR */ + EMMC_DDR, /* DDR */ + EMMC_HS200, /* High speed 200Mhz in SDR */ + EMMC_HS400, /* High speed 200Mhz in DDR */ + EMMC_HS400es, /* High speed 200Mhz in SDR with enhanced strobe*/ +}; + +struct cdns_sdmmc_params { + uintptr_t reg_base; + uintptr_t reg_pinmux; + uintptr_t reg_phy; + uintptr_t desc_base; + size_t desc_size; + int clk_rate; + int bus_width; + unsigned int flags; + enum sdmmc_device_mode cdn_sdmmc_dev_mode; + enum mmc_device_type cdn_sdmmc_dev_type; + uint32_t combophy; +}; + +/* read and write API */ +size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size); +size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size); + +struct cdns_idmac_desc { + /*8 bit attribute*/ + uint8_t attr; + /*reserved bits in desc*/ + uint8_t reserved; + /*page length for the descriptor*/ + uint16_t len; + /*lower 32 bits for buffer (64 bit addressing)*/ + uint32_t addr_lo; +#if CONFIG_DMA_ADDR_T_64BIT == 1 + /*higher 32 bits for buffer (64 bit addressing)*/ + uint32_t addr_hi; +} __aligned(8); +#else +} __packed; +#endif + + + +/* Function Prototype */ +int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, +struct cdns_sdmmc_sdhc *mmc_sdhc_reg); +void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, +struct cdns_sdmmc_sdhc *sdhc_reg); +#endif
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h index 30ca910..327c1d9 100644 --- a/include/drivers/cadence/cdns_uart.h +++ b/include/drivers/cadence/cdns_uart.h
@@ -22,6 +22,7 @@ #define UART_SR_INTR_REMPTY_BIT 1 #define UART_SR_INTR_TFUL_BIT 4 #define UART_SR_INTR_TEMPTY_BIT 3 +#define UART_SR_INTR_TACTIVE_BIT 11 #define R_UART_TX 0x30 #define R_UART_RX 0x30
diff --git a/include/drivers/console.h b/include/drivers/console.h index f499571..fa4eb94 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h
@@ -12,10 +12,16 @@ #define CONSOLE_T_NEXT (U(0) * REGSZ) #define CONSOLE_T_FLAGS (U(1) * REGSZ) #define CONSOLE_T_PUTC (U(2) * REGSZ) +#if ENABLE_CONSOLE_GETC #define CONSOLE_T_GETC (U(3) * REGSZ) #define CONSOLE_T_FLUSH (U(4) * REGSZ) #define CONSOLE_T_BASE (U(5) * REGSZ) #define CONSOLE_T_DRVDATA (U(6) * REGSZ) +#else +#define CONSOLE_T_FLUSH (U(3) * REGSZ) +#define CONSOLE_T_BASE (U(4) * REGSZ) +#define CONSOLE_T_DRVDATA (U(5) * REGSZ) +#endif #define CONSOLE_FLAG_BOOT (U(1) << 0) #define CONSOLE_FLAG_RUNTIME (U(1) << 1) @@ -42,7 +48,9 @@ */ u_register_t flags; int (*const putc)(int character, struct console *console); +#if ENABLE_CONSOLE_GETC int (*const getc)(struct console *console); +#endif void (*const flush)(struct console *console); uintptr_t base; /* Additional private driver data may follow here. */ @@ -75,8 +83,10 @@ void console_switch_state(unsigned int new_state); /* Output a character on all consoles registered for the current state. */ int console_putc(int c); +#if ENABLE_CONSOLE_GETC /* Read a character (blocking) from any console registered for current state. */ int console_getc(void); +#endif /* Flush all consoles registered for the current state. */ void console_flush(void);
diff --git a/include/drivers/console_assertions.h b/include/drivers/console_assertions.h index 00caa31..9f06573 100644 --- a/include/drivers/console_assertions.h +++ b/include/drivers/console_assertions.h
@@ -19,8 +19,10 @@ assert_console_t_flags_offset_mismatch); CASSERT(CONSOLE_T_PUTC == __builtin_offsetof(console_t, putc), assert_console_t_putc_offset_mismatch); +#if ENABLE_CONSOLE_GETC CASSERT(CONSOLE_T_GETC == __builtin_offsetof(console_t, getc), assert_console_t_getc_offset_mismatch); +#endif CASSERT(CONSOLE_T_FLUSH == __builtin_offsetof(console_t, flush), assert_console_t_flush_offset_mismatch); CASSERT(CONSOLE_T_DRVDATA == sizeof(console_t),
diff --git a/include/drivers/measured_boot/rss/rss_measured_boot.h b/include/drivers/measured_boot/rss/rss_measured_boot.h index fe88576..7ab517c 100644 --- a/include/drivers/measured_boot/rss/rss_measured_boot.h +++ b/include/drivers/measured_boot/rss/rss_measured_boot.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,16 +40,18 @@ size_t version_size; uint8_t sw_type[SW_TYPE_MAX_SIZE]; size_t sw_type_size; + void *pk_oid; bool lock_measurement; }; /* Functions' declarations */ -void rss_measured_boot_init(void); -struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void); -int rss_mboot_measure_and_record(uintptr_t data_base, uint32_t data_size, +void rss_measured_boot_init(struct rss_mboot_metadata *metadata_ptr); +int rss_mboot_measure_and_record(struct rss_mboot_metadata *metadata_ptr, + uintptr_t data_base, uint32_t data_size, uint32_t data_id); -/* TODO: These metadata are currently not available during TF-A boot */ -int rss_mboot_set_signer_id(unsigned int img_id, const void *pk_ptr, size_t pk_len); +int rss_mboot_set_signer_id(struct rss_mboot_metadata *metadata_ptr, + const void *pk_oid, const void *pk_ptr, + size_t pk_len); #endif /* RSS_MEASURED_BOOT_H */
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_clock.h b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h new file mode 100644 index 0000000..3c457d7 --- /dev/null +++ b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h
@@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ARBEL_CLOCK_H_ +#define __ARBEL_CLOCK_H_ + +struct clk_ctl { + unsigned int clken1; + unsigned int clksel; + unsigned int clkdiv1; + unsigned int pllcon0; + unsigned int pllcon1; + unsigned int swrstr; + unsigned char res1[0x8]; + unsigned int ipsrst1; + unsigned int ipsrst2; + unsigned int clken2; + unsigned int clkdiv2; + unsigned int clken3; + unsigned int ipsrst3; + unsigned int wd0rcr; + unsigned int wd1rcr; + unsigned int wd2rcr; + unsigned int swrstc1; + unsigned int swrstc2; + unsigned int swrstc3; + unsigned int tiprstc; + unsigned int pllcon2; + unsigned int clkdiv3; + unsigned int corstc; + unsigned int pllcong; + unsigned int ahbckfi; + unsigned int seccnt; + unsigned int cntr25m; + unsigned int clken4; + unsigned int ipsrst4; + unsigned int busto; + unsigned int clkdiv4; + unsigned int wd0rcrb; + unsigned int wd1rcrb; + unsigned int wd2rcrb; + unsigned int swrstc1b; + unsigned int swrstc2b; + unsigned int swrstc3b; + unsigned int tiprstcb; + unsigned int corstcb; + unsigned int ipsrstdis1; + unsigned int ipsrstdis2; + unsigned int ipsrstdis3; + unsigned int ipsrstdis4; + unsigned char res2[0x10]; + unsigned int thrtl_cnt; +}; + +#endif /* __ARBEL_CLOCK_H_ */
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h new file mode 100644 index 0000000..b9f3048 --- /dev/null +++ b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h
@@ -0,0 +1,127 @@ +/* + * Copyright (C) 2022-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __NPCM845x_GCR_H_ +#define __NPCM845x_GCR_H_ + +struct npcm845x_gcr { + unsigned int pdid; + unsigned int pwron; + unsigned int swstrps; + unsigned int rsvd1[2]; + unsigned int miscpe; + unsigned int spldcnt; + unsigned int rsvd2[1]; + unsigned int flockr2; + unsigned int flockr3; + unsigned int rsvd3[3]; + unsigned int a35_mode; + unsigned int spswc; + unsigned int intcr; + unsigned int intsr; + unsigned int obscr1; + unsigned int obsdr1; + unsigned int rsvd4[1]; + unsigned int hifcr; + unsigned int rsvd5[3]; + unsigned int intcr2; + unsigned int rsvd6[1]; + unsigned int srcnt; + unsigned int ressr; + unsigned int rlockr1; + unsigned int flockr1; + unsigned int dscnt; + unsigned int mdlr; + unsigned int scrpad_c; + unsigned int scrpad_b; + unsigned int rsvd7[4]; + unsigned int daclvlr; + unsigned int intcr3; + unsigned int pcirctl; + unsigned int rsvd8[2]; + unsigned int vsintr; + unsigned int rsvd9[1]; + unsigned int sd2sur1; + unsigned int sd2sur2; + unsigned int sd2irv3; + unsigned int intcr4; + unsigned int obscr2; + unsigned int obsdr2; + unsigned int rsvd10[5]; + unsigned int i2csegsel; + unsigned int i2csegctl; + unsigned int vsrcr; + unsigned int mlockr; + unsigned int rsvd11[8]; + unsigned int etsr; + unsigned int dft1r; + unsigned int dft2r; + unsigned int dft3r; + unsigned int edffsr; + unsigned int rsvd12[1]; + unsigned int intcrpce3; + unsigned int intcrpce2; + unsigned int intcrpce0; + unsigned int intcrpce1; + unsigned int dactest; + unsigned int scrpad; + unsigned int usb1phyctl; + unsigned int usb2phyctl; + unsigned int usb3phyctl; + unsigned int intsr2; + unsigned int intcrpce2b; + unsigned int intcrpce0b; + unsigned int intcrpce1b; + unsigned int intcrpce3b; + unsigned int rsvd13[4]; + unsigned int intcrpce2c; + unsigned int intcrpce0c; + unsigned int intcrpce1c; + unsigned int intcrpce3c; + unsigned int rsvd14[40]; + unsigned int sd2irv4; + unsigned int sd2irv5; + unsigned int sd2irv6; + unsigned int sd2irv7; + unsigned int sd2irv8; + unsigned int sd2irv9; + unsigned int sd2irv10; + unsigned int sd2irv11; + unsigned int rsvd15[8]; + unsigned int mfsel1; + unsigned int mfsel2; + unsigned int mfsel3; + unsigned int mfsel4; + unsigned int mfsel5; + unsigned int mfsel6; + unsigned int mfsel7; + unsigned int rsvd16[1]; + unsigned int mfsel_lk1; + unsigned int mfsel_lk2; + unsigned int mfsel_lk3; + unsigned int mfsel_lk4; + unsigned int mfsel_lk5; + unsigned int mfsel_lk6; + unsigned int mfsel_lk7; + unsigned int rsvd17[1]; + unsigned int mfsel_set1; + unsigned int mfsel_set2; + unsigned int mfsel_set3; + unsigned int mfsel_set4; + unsigned int mfsel_set5; + unsigned int mfsel_set6; + unsigned int mfsel_set7; + unsigned int rsvd18[1]; + unsigned int mfsel_clr1; + unsigned int mfsel_clr2; + unsigned int mfsel_clr3; + unsigned int mfsel_clr4; + unsigned int mfsel_clr5; + unsigned int mfsel_clr6; + unsigned int mfsel_clr7; +}; + +#endif
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h new file mode 100644 index 0000000..8962b90 --- /dev/null +++ b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h
@@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (C) 2022-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +#ifndef __ASSEMBLY__ + +struct npcmX50_uart { + union { + unsigned int rbr; + unsigned int thr; + unsigned int dll; + }; + union { + unsigned int ier; + unsigned int dlm; + }; + union { + unsigned int iir; + unsigned int fcr; + }; + unsigned int lcr; + unsigned int mcr; + unsigned int lsr; + unsigned int msr; + unsigned int tor; +}; + +typedef enum { + /* + * UART0 is a general UART block without modem-I/O-control + * connection to external signals. + */ + UART0_DEV = 0, + /* + * UART1-3 are each a general UART with modem-I/O-control + * connection to external signals. + */ + UART1_DEV, + UART2_DEV, + UART3_DEV, +} UART_DEV_T; + +typedef enum { + /* + * 0 0 0: Mode 1: + * HSP1 connected to SI2, + * HSP2 connected to UART2, + * UART1 snoops HSP1, + * UART3 snoops SI2 + */ + UART_MUX_MODE1 = 0, + /* + * 0 0 1: Mode 2: + * HSP1 connected to UART1, + * HSP2 connected to SI2, + * UART2 snoops HSP2, + * UART3 snoops SI2 + */ + UART_MUX_MODE2, + /* + * 0 1 0: Mode 3: + * HSP1 connected to UART1, + * HSP2 connected to UART2, + * UART3 connected to SI2 + */ + UART_MUX_MODE3, + /* + * 0 1 1: Mode 4: + * HSP1 connected to SI1, + * HSP2 connected to SI2, + * UART1 snoops SI1, + * UART3 snoops SI2, + * UART2 snoops HSP1 (default) + */ + UART_MUX_MODE4, + /* + * 1 0 0: Mode 5: + * HSP1 connected to SI1, + * HSP2 connected to UART2, + * UART1 snoops HSP1, + * UART3 snoops SI1 + */ + UART_MUX_MODE5, + /* + * 1 0 1: Mode 6: + * HSP1 connected to SI1, + * HSP2 connected to SI2, + * UART1 snoops SI1, + * UART3 snoops SI2, + * UART2 snoops HSP2 + */ + UART_MUX_MODE6, + /* + * 1 1 0: Mode 7: + * HSP1 connected to SI1, + * HSP2 connected to UART2, + * UART1 snoops HSP1, + * UART3 connected to SI2 + */ + UART_MUX_MODE7, + /* Skip UART mode configuration. */ + UART_MUX_RESERVED, + /* + * A SW option to allow config of UART + * without touching the UART mux. + */ + UART_MUX_SKIP_CONFIG +} UART_MUX_T; + +/*---------------------------------------------------------------------------*/ +/* Common baudrate definitions */ +/*---------------------------------------------------------------------------*/ +typedef enum { + UART_BAUDRATE_110 = 110, + UART_BAUDRATE_300 = 300, + UART_BAUDRATE_600 = 600, + UART_BAUDRATE_1200 = 1200, + UART_BAUDRATE_2400 = 2400, + UART_BAUDRATE_4800 = 4800, + UART_BAUDRATE_9600 = 9600, + UART_BAUDRATE_14400 = 14400, + UART_BAUDRATE_19200 = 19200, + UART_BAUDRATE_38400 = 38400, + UART_BAUDRATE_57600 = 57600, + UART_BAUDRATE_115200 = 115200, + UART_BAUDRATE_230400 = 230400, + UART_BAUDRATE_380400 = 380400, + UART_BAUDRATE_460800 = 460800, +} UART_BAUDRATE_T; + +/*---------------------------------------------------------------------------*/ +/* UART parity types */ +/*---------------------------------------------------------------------------*/ +typedef enum { + UART_PARITY_NONE = 0, + UART_PARITY_EVEN, + UART_PARITY_ODD, +} UART_PARITY_T; + +/*---------------------------------------------------------------------------*/ +/* Uart stop bits */ +/*---------------------------------------------------------------------------*/ +typedef enum { + UART_STOPBIT_1 = 0x00, + UART_STOPBIT_DYNAMIC, +} UART_STOPBIT_T; + +enum FCR_RFITL_TYPE { + FCR_RFITL_1B = 0x0, + FCR_RFITL_4B = 0x4, + FCR_RFITL_8B = 0x8, + FCR_RFITL_14B = 0xC, +}; + +enum LCR_WLS_TYPE { + LCR_WLS_5bit = 0x0, + LCR_WLS_6bit = 0x1, + LCR_WLS_7bit = 0x2, + LCR_WLS_8bit = 0x3, +}; + +#define IER_DBGACK (1 << 4) +#define IER_MSIE (1 << 3) +#define IER_RLSE (1 << 2) +#define IER_THREIE (1 << 1) +#define IER_RDAIE (1 << 0) + +#define IIR_FMES (1 << 7) +#define IIR_RFTLS (1 << 5) +#define IIR_DMS (1 << 4) +#define IIR_IID (1 << 1) +#define IIR_NIP (1 << 0) + +#define FCR_RFITL_1B (0 << 4) +#define FCR_RFITL_4B (4 << 4) +#define FCR_RFITL_8B (8 << 4) +#define FCR_RFITL_14B (12 << 4) +#define FCR_DMS (1 << 3) +#define FCR_TFR (1 << 2) +#define FCR_RFR (1 << 1) +#define FCR_FME (1 << 0) + +#define LCR_DLAB (1 << 7) +#define LCR_BCB (1 << 6) +#define LCR_SPE (1 << 5) +#define LCR_EPS (1 << 4) +#define LCR_PBE (1 << 3) +#define LCR_NSB (1 << 2) +#define LCR_WLS_8b (3 << 0) +#define LCR_WLS_7b (2 << 0) +#define LCR_WLS_6b (1 << 0) +#define LCR_WLS_5b (0 << 0) + +#define MCR_LBME (1 << 4) +#define MCR_OUT2 (1 << 3) +#define MCR_RTS (1 << 1) +#define MCR_DTR (1 << 0) + +#define LSR_ERR_RX (1 << 7) +#define LSR_TE (1 << 6) +#define LSR_THRE (1 << 5) +#define LSR_BII (1 << 4) +#define LSR_FEI (1 << 3) +#define LSR_PEI (1 << 2) +#define LSR_OEI (1 << 1) +#define LSR_RFDR (1 << 0) + +#define MSR_DCD (1 << 7) +#define MSR_RI (1 << 6) +#define MSR_DSR (1 << 5) +#define MSR_CTS (1 << 4) +#define MSR_DDCD (1 << 3) +#define MSR_DRI (1 << 2) +#define MSR_DDSR (1 << 1) +#define MSR_DCTS (1 << 0) + +#endif /* __ASSEMBLY__ */ + +uintptr_t npcm845x_get_base_uart(UART_DEV_T dev); +void CLK_ResetUART(void); +int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate); + +#endif /* __ASM_ARCH_UART_H_ */
diff --git a/include/drivers/nxp/trdc/imx_trdc.h b/include/drivers/nxp/trdc/imx_trdc.h new file mode 100644 index 0000000..0b41fcf --- /dev/null +++ b/include/drivers/nxp/trdc/imx_trdc.h
@@ -0,0 +1,172 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX_TRDC_H +#define IMX_XRDC_H + +#define MBC_BLK_ALL U(255) +#define MRC_REG_ALL U(16) +#define GLBAC_NUM U(8) + +#define DID_NUM U(16) +#define MBC_MAX_NUM U(4) +#define MRC_MAX_NUM U(2) +#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF) +#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F) + +#define MBC_BLK_NUM(GLBCFG) ((GLBCFG) & 0x3FF) +#define MRC_RGN_NUM(GLBCFG) ((GLBCFG) & 0x1F) + +#define MDAC_W_X(m, r) (0x800 + (m) * 0x20 + (r) * 0x4) + +/* CPU/non-CPU domain common bits */ +#define MDA_VLD BIT(31) +#define MDA_LK1 BIT(30) +#define MDA_DFMT BIT(29) + +/* CPU domain bits */ +#define MDA_DFMT0_DID(x) ((x) & 0xF) +#define MDA_DFMT0_DIDS(x) (((x) & 0x3) << 4) +#define MDA_DFMT0_PE(x) (((x) & 0x3) << 6) +#define MDA_DFMT0_PIDM(x) (((x) & 0x3F) << 8) +#define MDA_DFMT0_SA(x) (((x) & 0x3) << 14) +#define MDA_DFMT0_PID(x) (((x) & 0x3F) << 16) + +/* non-CPU domain bits */ +#define MDA_DFMT1_DID(x) ((x) & 0xF) +#define MDA_DFMT1_PA(x) (((x) & 0x3) << 4) +#define MDA_DFMT1_SA(x) (((x) & 0x3) << 6) +#define MDA_DFMT1_DIDB(x) ((x) << 8) + +#define SP(X) ((X) << 12) +#define SU(X) ((X) << 8) +#define NP(X) ((X) << 4) +#define NU(X) ((X) << 0) + +#define RWX U(7) +#define RW U(6) +#define RX U(5) +#define R U(4) +#define X U(1) + +struct mbc_mem_dom { + uint32_t mem_glbcfg[4]; + uint32_t nse_blk_index; + uint32_t nse_blk_set; + uint32_t nse_blk_clr; + uint32_t nsr_blk_clr_all; + uint32_t memn_glbac[8]; + /* The upper only existed in the beginning of each MBC */ + uint32_t mem0_blk_cfg_w[64]; + uint32_t mem0_blk_nse_w[16]; + uint32_t mem1_blk_cfg_w[8]; + uint32_t mem1_blk_nse_w[2]; + uint32_t mem2_blk_cfg_w[8]; + uint32_t mem2_blk_nse_w[2]; + uint32_t mem3_blk_cfg_w[8]; + uint32_t mem3_blk_nse_w[2]; /*0x1F0, 0x1F4 */ + uint32_t reserved[2]; +}; + +struct mrc_rgn_dom { + uint32_t mrc_glbcfg[4]; + uint32_t nse_rgn_indirect; + uint32_t nse_rgn_set; + uint32_t nse_rgn_clr; + uint32_t nse_rgn_clr_all; + uint32_t memn_glbac[8]; + /* The upper only existed in the beginning of each MRC */ + uint32_t rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */ + uint32_t rgn_nse; + uint32_t reserved2[15]; +}; + +struct mda_inst { + uint32_t mda_w[8]; +}; + +struct trdc_mgr { + uint32_t trdc_cr; + uint32_t res0[59]; + uint32_t trdc_hwcfg0; + uint32_t trdc_hwcfg1; + uint32_t res1[450]; + struct mda_inst mda[128]; +}; + +struct trdc_mbc { + struct mbc_mem_dom mem_dom[DID_NUM]; +}; + +struct trdc_mrc { + struct mrc_rgn_dom mrc_dom[DID_NUM]; +}; + +/*************************************************************** + * Below structs used fro provding the TRDC configuration info + * that will be used to init the TRDC based on use case. + ***************************************************************/ +struct trdc_glbac_config { + uint8_t mbc_mrc_id; + uint8_t glbac_id; + uint32_t glbac_val; +}; + +struct trdc_mbc_config { + uint8_t mbc_id; + uint8_t dom_id; + uint8_t mem_id; + uint8_t blk_id; + uint8_t glbac_id; + bool secure; +}; + +struct trdc_mrc_config { + uint8_t mrc_id; + uint8_t dom_id; + uint8_t region_id; + uint32_t region_start; + uint32_t region_size; + uint8_t glbac_id; + bool secure; +}; + +struct trdc_mgr_info { + uintptr_t trdc_base; + uint8_t mbc_id; + uint8_t mbc_mem_id; + uint8_t blk_mgr; + uint8_t blk_mc; +}; + +struct trdc_config_info { + uintptr_t trdc_base; + struct trdc_glbac_config *mbc_glbac; + uint32_t num_mbc_glbac; + struct trdc_mbc_config *mbc_cfg; + uint32_t num_mbc_cfg; + struct trdc_glbac_config *mrc_glbac; + uint32_t num_mrc_glbac; + struct trdc_mrc_config *mrc_cfg; + uint32_t num_mrc_cfg; +}; + +extern struct trdc_mgr_info trdc_mgr_blks[]; +extern unsigned int trdc_mgr_num; +/* APIs to apply and enable TRDC */ +int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst, + uint32_t mda_reg, uint8_t sa, uint8_t dids, + uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid); + +int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst, + bool did_bypass, uint8_t sa, uint8_t pa, + uint8_t did); + +void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr); +void trdc_setup(struct trdc_config_info *cfg); +void trdc_config(void); + +#endif /* IMX_TRDC_H */
diff --git a/include/drivers/partition/gpt.h b/include/drivers/partition/gpt.h index c2a229e..383c17d 100644 --- a/include/drivers/partition/gpt.h +++ b/include/drivers/partition/gpt.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,10 +12,6 @@ #include <tools_share/uuid.h> #define PARTITION_TYPE_GPT 0xee -#define GPT_HEADER_OFFSET PLAT_PARTITION_BLOCK_SIZE -#define GPT_ENTRY_OFFSET (GPT_HEADER_OFFSET + \ - PLAT_PARTITION_BLOCK_SIZE) - #define GPT_SIGNATURE "EFI PART" typedef struct gpt_entry { @@ -45,7 +41,7 @@ /* size of a single partition entry (usually 128) */ unsigned int part_size; unsigned int part_crc; -} gpt_header_t; +} __packed gpt_header_t; int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry);
diff --git a/include/drivers/partition/partition.h b/include/drivers/partition/partition.h index 6cb59c3..d567d4c 100644 --- a/include/drivers/partition/partition.h +++ b/include/drivers/partition/partition.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,7 +29,7 @@ #define LEGACY_PARTITION_BLOCK_SIZE 512 -#define DEFAULT_GPT_HEADER_SIZE 92 +#define LBA(n) ((unsigned long long)(n) * PLAT_PARTITION_BLOCK_SIZE) typedef struct partition_entry { uint64_t start; @@ -50,5 +50,6 @@ const partition_entry_t *get_partition_entry_by_uuid(const uuid_t *part_uuid); const partition_entry_list_t *get_partition_entry_list(void); void partition_init(unsigned int image_id); +int gpt_partition_init(void); #endif /* PARTITION_H */
diff --git a/include/drivers/scmi-msg.h b/include/drivers/scmi-msg.h index eb90859..c93c455 100644 --- a/include/drivers/scmi-msg.h +++ b/include/drivers/scmi-msg.h
@@ -113,10 +113,12 @@ * @scmi_id: SCMI clock ID * @rates: If NULL, function returns, else output rates array * @nb_elts: Array size of @rates. + * @start_idx: Start index of rates array * Return an SCMI compliant error code */ int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, - unsigned long *rates, size_t *nb_elts); + unsigned long *rates, size_t *nb_elts, + uint32_t start_idx); /* * Get clock possible rate as range with regular steps in Hertz
diff --git a/include/drivers/spi_nand.h b/include/drivers/spi_nand.h index 40e2063..869a0c6 100644 --- a/include/drivers/spi_nand.h +++ b/include/drivers/spi_nand.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -29,9 +29,13 @@ #define SPI_NAND_STATUS_BUSY BIT(0) #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) +/* Flags for specific configuration */ +#define SPI_NAND_HAS_QE_BIT BIT(0) + struct spinand_device { struct nand_device *nand_dev; struct spi_mem_op spi_read_cache_op; + uint32_t flags; uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ };
diff --git a/include/drivers/st/stm32mp25_rcc.h b/include/drivers/st/stm32mp25_rcc.h new file mode 100644 index 0000000..9dd25f3 --- /dev/null +++ b/include/drivers/st/stm32mp25_rcc.h
@@ -0,0 +1,4986 @@ +/* + * Copyright (c) 2023, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef STM32MP2_RCC_H +#define STM32MP2_RCC_H + +#include <lib/utils_def.h> + +#define RCC_SECCFGR0 U(0x0) +#define RCC_SECCFGR1 U(0x4) +#define RCC_SECCFGR2 U(0x8) +#define RCC_SECCFGR3 U(0xC) +#define RCC_PRIVCFGR0 U(0x10) +#define RCC_PRIVCFGR1 U(0x14) +#define RCC_PRIVCFGR2 U(0x18) +#define RCC_PRIVCFGR3 U(0x1C) +#define RCC_RCFGLOCKR0 U(0x20) +#define RCC_RCFGLOCKR1 U(0x24) +#define RCC_RCFGLOCKR2 U(0x28) +#define RCC_RCFGLOCKR3 U(0x2C) +#define RCC_R0CIDCFGR U(0x30) +#define RCC_R0SEMCR U(0x34) +#define RCC_R1CIDCFGR U(0x38) +#define RCC_R1SEMCR U(0x3C) +#define RCC_R2CIDCFGR U(0x40) +#define RCC_R2SEMCR U(0x44) +#define RCC_R3CIDCFGR U(0x48) +#define RCC_R3SEMCR U(0x4C) +#define RCC_R4CIDCFGR U(0x50) +#define RCC_R4SEMCR U(0x54) +#define RCC_R5CIDCFGR U(0x58) +#define RCC_R5SEMCR U(0x5C) +#define RCC_R6CIDCFGR U(0x60) +#define RCC_R6SEMCR U(0x64) +#define RCC_R7CIDCFGR U(0x68) +#define RCC_R7SEMCR U(0x6C) +#define RCC_R8CIDCFGR U(0x70) +#define RCC_R8SEMCR U(0x74) +#define RCC_R9CIDCFGR U(0x78) +#define RCC_R9SEMCR U(0x7C) +#define RCC_R10CIDCFGR U(0x80) +#define RCC_R10SEMCR U(0x84) +#define RCC_R11CIDCFGR U(0x88) +#define RCC_R11SEMCR U(0x8C) +#define RCC_R12CIDCFGR U(0x90) +#define RCC_R12SEMCR U(0x94) +#define RCC_R13CIDCFGR U(0x98) +#define RCC_R13SEMCR U(0x9C) +#define RCC_R14CIDCFGR U(0xA0) +#define RCC_R14SEMCR U(0xA4) +#define RCC_R15CIDCFGR U(0xA8) +#define RCC_R15SEMCR U(0xAC) +#define RCC_R16CIDCFGR U(0xB0) +#define RCC_R16SEMCR U(0xB4) +#define RCC_R17CIDCFGR U(0xB8) +#define RCC_R17SEMCR U(0xBC) +#define RCC_R18CIDCFGR U(0xC0) +#define RCC_R18SEMCR U(0xC4) +#define RCC_R19CIDCFGR U(0xC8) +#define RCC_R19SEMCR U(0xCC) +#define RCC_R20CIDCFGR U(0xD0) +#define RCC_R20SEMCR U(0xD4) +#define RCC_R21CIDCFGR U(0xD8) +#define RCC_R21SEMCR U(0xDC) +#define RCC_R22CIDCFGR U(0xE0) +#define RCC_R22SEMCR U(0xE4) +#define RCC_R23CIDCFGR U(0xE8) +#define RCC_R23SEMCR U(0xEC) +#define RCC_R24CIDCFGR U(0xF0) +#define RCC_R24SEMCR U(0xF4) +#define RCC_R25CIDCFGR U(0xF8) +#define RCC_R25SEMCR U(0xFC) +#define RCC_R26CIDCFGR U(0x100) +#define RCC_R26SEMCR U(0x104) +#define RCC_R27CIDCFGR U(0x108) +#define RCC_R27SEMCR U(0x10C) +#define RCC_R28CIDCFGR U(0x110) +#define RCC_R28SEMCR U(0x114) +#define RCC_R29CIDCFGR U(0x118) +#define RCC_R29SEMCR U(0x11C) +#define RCC_R30CIDCFGR U(0x120) +#define RCC_R30SEMCR U(0x124) +#define RCC_R31CIDCFGR U(0x128) +#define RCC_R31SEMCR U(0x12C) +#define RCC_R32CIDCFGR U(0x130) +#define RCC_R32SEMCR U(0x134) +#define RCC_R33CIDCFGR U(0x138) +#define RCC_R33SEMCR U(0x13C) +#define RCC_R34CIDCFGR U(0x140) +#define RCC_R34SEMCR U(0x144) +#define RCC_R35CIDCFGR U(0x148) +#define RCC_R35SEMCR U(0x14C) +#define RCC_R36CIDCFGR U(0x150) +#define RCC_R36SEMCR U(0x154) +#define RCC_R37CIDCFGR U(0x158) +#define RCC_R37SEMCR U(0x15C) +#define RCC_R38CIDCFGR U(0x160) +#define RCC_R38SEMCR U(0x164) +#define RCC_R39CIDCFGR U(0x168) +#define RCC_R39SEMCR U(0x16C) +#define RCC_R40CIDCFGR U(0x170) +#define RCC_R40SEMCR U(0x174) +#define RCC_R41CIDCFGR U(0x178) +#define RCC_R41SEMCR U(0x17C) +#define RCC_R42CIDCFGR U(0x180) +#define RCC_R42SEMCR U(0x184) +#define RCC_R43CIDCFGR U(0x188) +#define RCC_R43SEMCR U(0x18C) +#define RCC_R44CIDCFGR U(0x190) +#define RCC_R44SEMCR U(0x194) +#define RCC_R45CIDCFGR U(0x198) +#define RCC_R45SEMCR U(0x19C) +#define RCC_R46CIDCFGR U(0x1A0) +#define RCC_R46SEMCR U(0x1A4) +#define RCC_R47CIDCFGR U(0x1A8) +#define RCC_R47SEMCR U(0x1AC) +#define RCC_R48CIDCFGR U(0x1B0) +#define RCC_R48SEMCR U(0x1B4) +#define RCC_R49CIDCFGR U(0x1B8) +#define RCC_R49SEMCR U(0x1BC) +#define RCC_R50CIDCFGR U(0x1C0) +#define RCC_R50SEMCR U(0x1C4) +#define RCC_R51CIDCFGR U(0x1C8) +#define RCC_R51SEMCR U(0x1CC) +#define RCC_R52CIDCFGR U(0x1D0) +#define RCC_R52SEMCR U(0x1D4) +#define RCC_R53CIDCFGR U(0x1D8) +#define RCC_R53SEMCR U(0x1DC) +#define RCC_R54CIDCFGR U(0x1E0) +#define RCC_R54SEMCR U(0x1E4) +#define RCC_R55CIDCFGR U(0x1E8) +#define RCC_R55SEMCR U(0x1EC) +#define RCC_R56CIDCFGR U(0x1F0) +#define RCC_R56SEMCR U(0x1F4) +#define RCC_R57CIDCFGR U(0x1F8) +#define RCC_R57SEMCR U(0x1FC) +#define RCC_R58CIDCFGR U(0x200) +#define RCC_R58SEMCR U(0x204) +#define RCC_R59CIDCFGR U(0x208) +#define RCC_R59SEMCR U(0x20C) +#define RCC_R60CIDCFGR U(0x210) +#define RCC_R60SEMCR U(0x214) +#define RCC_R61CIDCFGR U(0x218) +#define RCC_R61SEMCR U(0x21C) +#define RCC_R62CIDCFGR U(0x220) +#define RCC_R62SEMCR U(0x224) +#define RCC_R63CIDCFGR U(0x228) +#define RCC_R63SEMCR U(0x22C) +#define RCC_R64CIDCFGR U(0x230) +#define RCC_R64SEMCR U(0x234) +#define RCC_R65CIDCFGR U(0x238) +#define RCC_R65SEMCR U(0x23C) +#define RCC_R66CIDCFGR U(0x240) +#define RCC_R66SEMCR U(0x244) +#define RCC_R67CIDCFGR U(0x248) +#define RCC_R67SEMCR U(0x24C) +#define RCC_R68CIDCFGR U(0x250) +#define RCC_R68SEMCR U(0x254) +#define RCC_R69CIDCFGR U(0x258) +#define RCC_R69SEMCR U(0x25C) +#define RCC_R70CIDCFGR U(0x260) +#define RCC_R70SEMCR U(0x264) +#define RCC_R71CIDCFGR U(0x268) +#define RCC_R71SEMCR U(0x26C) +#define RCC_R72CIDCFGR U(0x270) +#define RCC_R72SEMCR U(0x274) +#define RCC_R73CIDCFGR U(0x278) +#define RCC_R73SEMCR U(0x27C) +#define RCC_R74CIDCFGR U(0x280) +#define RCC_R74SEMCR U(0x284) +#define RCC_R75CIDCFGR U(0x288) +#define RCC_R75SEMCR U(0x28C) +#define RCC_R76CIDCFGR U(0x290) +#define RCC_R76SEMCR U(0x294) +#define RCC_R77CIDCFGR U(0x298) +#define RCC_R77SEMCR U(0x29C) +#define RCC_R78CIDCFGR U(0x2A0) +#define RCC_R78SEMCR U(0x2A4) +#define RCC_R79CIDCFGR U(0x2A8) +#define RCC_R79SEMCR U(0x2AC) +#define RCC_R80CIDCFGR U(0x2B0) +#define RCC_R80SEMCR U(0x2B4) +#define RCC_R81CIDCFGR U(0x2B8) +#define RCC_R81SEMCR U(0x2BC) +#define RCC_R82CIDCFGR U(0x2C0) +#define RCC_R82SEMCR U(0x2C4) +#define RCC_R83CIDCFGR U(0x2C8) +#define RCC_R83SEMCR U(0x2CC) +#define RCC_R84CIDCFGR U(0x2D0) +#define RCC_R84SEMCR U(0x2D4) +#define RCC_R85CIDCFGR U(0x2D8) +#define RCC_R85SEMCR U(0x2DC) +#define RCC_R86CIDCFGR U(0x2E0) +#define RCC_R86SEMCR U(0x2E4) +#define RCC_R87CIDCFGR U(0x2E8) +#define RCC_R87SEMCR U(0x2EC) +#define RCC_R88CIDCFGR U(0x2F0) +#define RCC_R88SEMCR U(0x2F4) +#define RCC_R89CIDCFGR U(0x2F8) +#define RCC_R89SEMCR U(0x2FC) +#define RCC_R90CIDCFGR U(0x300) +#define RCC_R90SEMCR U(0x304) +#define RCC_R91CIDCFGR U(0x308) +#define RCC_R91SEMCR U(0x30C) +#define RCC_R92CIDCFGR U(0x310) +#define RCC_R92SEMCR U(0x314) +#define RCC_R93CIDCFGR U(0x318) +#define RCC_R93SEMCR U(0x31C) +#define RCC_R94CIDCFGR U(0x320) +#define RCC_R94SEMCR U(0x324) +#define RCC_R95CIDCFGR U(0x328) +#define RCC_R95SEMCR U(0x32C) +#define RCC_R96CIDCFGR U(0x330) +#define RCC_R96SEMCR U(0x334) +#define RCC_R97CIDCFGR U(0x338) +#define RCC_R97SEMCR U(0x33C) +#define RCC_R98CIDCFGR U(0x340) +#define RCC_R98SEMCR U(0x344) +#define RCC_R99CIDCFGR U(0x348) +#define RCC_R99SEMCR U(0x34C) +#define RCC_R100CIDCFGR U(0x350) +#define RCC_R100SEMCR U(0x354) +#define RCC_R101CIDCFGR U(0x358) +#define RCC_R101SEMCR U(0x35C) +#define RCC_R102CIDCFGR U(0x360) +#define RCC_R102SEMCR U(0x364) +#define RCC_R103CIDCFGR U(0x368) +#define RCC_R103SEMCR U(0x36C) +#define RCC_R104CIDCFGR U(0x370) +#define RCC_R104SEMCR U(0x374) +#define RCC_R105CIDCFGR U(0x378) +#define RCC_R105SEMCR U(0x37C) +#define RCC_R106CIDCFGR U(0x380) +#define RCC_R106SEMCR U(0x384) +#define RCC_R107CIDCFGR U(0x388) +#define RCC_R107SEMCR U(0x38C) +#define RCC_R108CIDCFGR U(0x390) +#define RCC_R108SEMCR U(0x394) +#define RCC_R109CIDCFGR U(0x398) +#define RCC_R109SEMCR U(0x39C) +#define RCC_R110CIDCFGR U(0x3A0) +#define RCC_R110SEMCR U(0x3A4) +#define RCC_R111CIDCFGR U(0x3A8) +#define RCC_R111SEMCR U(0x3AC) +#define RCC_R112CIDCFGR U(0x3B0) +#define RCC_R112SEMCR U(0x3B4) +#define RCC_R113CIDCFGR U(0x3B8) +#define RCC_R113SEMCR U(0x3BC) +#define RCC_GRSTCSETR U(0x400) +#define RCC_C1RSTCSETR U(0x404) +#define RCC_C1P1RSTCSETR U(0x408) +#define RCC_C2RSTCSETR U(0x40C) +#define RCC_HWRSTSCLRR U(0x410) +#define RCC_C1HWRSTSCLRR U(0x414) +#define RCC_C2HWRSTSCLRR U(0x418) +#define RCC_C1BOOTRSTSSETR U(0x41C) +#define RCC_C1BOOTRSTSCLRR U(0x420) +#define RCC_C2BOOTRSTSSETR U(0x424) +#define RCC_C2BOOTRSTSCLRR U(0x428) +#define RCC_C1SREQSETR U(0x42C) +#define RCC_C1SREQCLRR U(0x430) +#define RCC_CPUBOOTCR U(0x434) +#define RCC_STBYBOOTCR U(0x438) +#define RCC_LEGBOOTCR U(0x43C) +#define RCC_BDCR U(0x440) +#define RCC_D3DCR U(0x444) +#define RCC_D3DSR U(0x448) +#define RCC_RDCR U(0x44C) +#define RCC_C1MSRDCR U(0x450) +#define RCC_PWRLPDLYCR U(0x454) +#define RCC_C1CIESETR U(0x458) +#define RCC_C1CIFCLRR U(0x45C) +#define RCC_C2CIESETR U(0x460) +#define RCC_C2CIFCLRR U(0x464) +#define RCC_IWDGC1FZSETR U(0x468) +#define RCC_IWDGC1FZCLRR U(0x46C) +#define RCC_IWDGC1CFGSETR U(0x470) +#define RCC_IWDGC1CFGCLRR U(0x474) +#define RCC_IWDGC2FZSETR U(0x478) +#define RCC_IWDGC2FZCLRR U(0x47C) +#define RCC_IWDGC2CFGSETR U(0x480) +#define RCC_IWDGC2CFGCLRR U(0x484) +#define RCC_IWDGC3CFGSETR U(0x488) +#define RCC_IWDGC3CFGCLRR U(0x48C) +#define RCC_C3CFGR U(0x490) +#define RCC_MCO1CFGR U(0x494) +#define RCC_MCO2CFGR U(0x498) +#define RCC_OCENSETR U(0x49C) +#define RCC_OCENCLRR U(0x4A0) +#define RCC_OCRDYR U(0x4A4) +#define RCC_HSICFGR U(0x4A8) +#define RCC_CSICFGR U(0x4AC) +#define RCC_RTCDIVR U(0x4B0) +#define RCC_APB1DIVR U(0x4B4) +#define RCC_APB2DIVR U(0x4B8) +#define RCC_APB3DIVR U(0x4BC) +#define RCC_APB4DIVR U(0x4C0) +#define RCC_APBDBGDIVR U(0x4C4) +#define RCC_TIMG1PRER U(0x4C8) +#define RCC_TIMG2PRER U(0x4CC) +#define RCC_LSMCUDIVR U(0x4D0) +#define RCC_DDRCPCFGR U(0x4D4) +#define RCC_DDRCAPBCFGR U(0x4D8) +#define RCC_DDRPHYCAPBCFGR U(0x4DC) +#define RCC_DDRPHYCCFGR U(0x4E0) +#define RCC_DDRCFGR U(0x4E4) +#define RCC_DDRITFCFGR U(0x4E8) +#define RCC_SYSRAMCFGR U(0x4F0) +#define RCC_VDERAMCFGR U(0x4F4) +#define RCC_SRAM1CFGR U(0x4F8) +#define RCC_SRAM2CFGR U(0x4FC) +#define RCC_RETRAMCFGR U(0x500) +#define RCC_BKPSRAMCFGR U(0x504) +#define RCC_LPSRAM1CFGR U(0x508) +#define RCC_LPSRAM2CFGR U(0x50C) +#define RCC_LPSRAM3CFGR U(0x510) +#define RCC_OSPI1CFGR U(0x514) +#define RCC_OSPI2CFGR U(0x518) +#define RCC_FMCCFGR U(0x51C) +#define RCC_DBGCFGR U(0x520) +#define RCC_STM500CFGR U(0x524) +#define RCC_ETRCFGR U(0x528) +#define RCC_GPIOACFGR U(0x52C) +#define RCC_GPIOBCFGR U(0x530) +#define RCC_GPIOCCFGR U(0x534) +#define RCC_GPIODCFGR U(0x538) +#define RCC_GPIOECFGR U(0x53C) +#define RCC_GPIOFCFGR U(0x540) +#define RCC_GPIOGCFGR U(0x544) +#define RCC_GPIOHCFGR U(0x548) +#define RCC_GPIOICFGR U(0x54C) +#define RCC_GPIOJCFGR U(0x550) +#define RCC_GPIOKCFGR U(0x554) +#define RCC_GPIOZCFGR U(0x558) +#define RCC_HPDMA1CFGR U(0x55C) +#define RCC_HPDMA2CFGR U(0x560) +#define RCC_HPDMA3CFGR U(0x564) +#define RCC_LPDMACFGR U(0x568) +#define RCC_HSEMCFGR U(0x56C) +#define RCC_IPCC1CFGR U(0x570) +#define RCC_IPCC2CFGR U(0x574) +#define RCC_RTCCFGR U(0x578) +#define RCC_SYSCPU1CFGR U(0x580) +#define RCC_BSECCFGR U(0x584) +#define RCC_IS2MCFGR U(0x58C) +#define RCC_PLL2CFGR1 U(0x590) +#define RCC_PLL2CFGR2 U(0x594) +#define RCC_PLL2CFGR3 U(0x598) +#define RCC_PLL2CFGR4 U(0x59C) +#define RCC_PLL2CFGR5 U(0x5A0) +#define RCC_PLL2CFGR6 U(0x5A8) +#define RCC_PLL2CFGR7 U(0x5AC) +#define RCC_PLL3CFGR1 U(0x5B8) +#define RCC_PLL3CFGR2 U(0x5BC) +#define RCC_PLL3CFGR3 U(0x5C0) +#define RCC_PLL3CFGR4 U(0x5C4) +#define RCC_PLL3CFGR5 U(0x5C8) +#define RCC_PLL3CFGR6 U(0x5D0) +#define RCC_PLL3CFGR7 U(0x5D4) +#define RCC_HSIFMONCR U(0x5E0) +#define RCC_HSIFVALR U(0x5E4) +#define RCC_TIM1CFGR U(0x700) +#define RCC_TIM2CFGR U(0x704) +#define RCC_TIM3CFGR U(0x708) +#define RCC_TIM4CFGR U(0x70C) +#define RCC_TIM5CFGR U(0x710) +#define RCC_TIM6CFGR U(0x714) +#define RCC_TIM7CFGR U(0x718) +#define RCC_TIM8CFGR U(0x71C) +#define RCC_TIM10CFGR U(0x720) +#define RCC_TIM11CFGR U(0x724) +#define RCC_TIM12CFGR U(0x728) +#define RCC_TIM13CFGR U(0x72C) +#define RCC_TIM14CFGR U(0x730) +#define RCC_TIM15CFGR U(0x734) +#define RCC_TIM16CFGR U(0x738) +#define RCC_TIM17CFGR U(0x73C) +#define RCC_TIM20CFGR U(0x740) +#define RCC_LPTIM1CFGR U(0x744) +#define RCC_LPTIM2CFGR U(0x748) +#define RCC_LPTIM3CFGR U(0x74C) +#define RCC_LPTIM4CFGR U(0x750) +#define RCC_LPTIM5CFGR U(0x754) +#define RCC_SPI1CFGR U(0x758) +#define RCC_SPI2CFGR U(0x75C) +#define RCC_SPI3CFGR U(0x760) +#define RCC_SPI4CFGR U(0x764) +#define RCC_SPI5CFGR U(0x768) +#define RCC_SPI6CFGR U(0x76C) +#define RCC_SPI7CFGR U(0x770) +#define RCC_SPI8CFGR U(0x774) +#define RCC_SPDIFRXCFGR U(0x778) +#define RCC_USART1CFGR U(0x77C) +#define RCC_USART2CFGR U(0x780) +#define RCC_USART3CFGR U(0x784) +#define RCC_UART4CFGR U(0x788) +#define RCC_UART5CFGR U(0x78C) +#define RCC_USART6CFGR U(0x790) +#define RCC_UART7CFGR U(0x794) +#define RCC_UART8CFGR U(0x798) +#define RCC_UART9CFGR U(0x79C) +#define RCC_LPUART1CFGR U(0x7A0) +#define RCC_I2C1CFGR U(0x7A4) +#define RCC_I2C2CFGR U(0x7A8) +#define RCC_I2C3CFGR U(0x7AC) +#define RCC_I2C4CFGR U(0x7B0) +#define RCC_I2C5CFGR U(0x7B4) +#define RCC_I2C6CFGR U(0x7B8) +#define RCC_I2C7CFGR U(0x7BC) +#define RCC_I2C8CFGR U(0x7C0) +#define RCC_SAI1CFGR U(0x7C4) +#define RCC_SAI2CFGR U(0x7C8) +#define RCC_SAI3CFGR U(0x7CC) +#define RCC_SAI4CFGR U(0x7D0) +#define RCC_MDF1CFGR U(0x7D8) +#define RCC_ADF1CFGR U(0x7DC) +#define RCC_FDCANCFGR U(0x7E0) +#define RCC_HDPCFGR U(0x7E4) +#define RCC_ADC12CFGR U(0x7E8) +#define RCC_ADC3CFGR U(0x7EC) +#define RCC_ETH1CFGR U(0x7F0) +#define RCC_ETH2CFGR U(0x7F4) +#define RCC_USB2CFGR U(0x7FC) +#define RCC_USB2PHY1CFGR U(0x800) +#define RCC_USB2PHY2CFGR U(0x804) +#define RCC_USB3DRDCFGR U(0x808) +#define RCC_USB3PCIEPHYCFGR U(0x80C) +#define RCC_PCIECFGR U(0x810) +#define RCC_USBTCCFGR U(0x814) +#define RCC_ETHSWCFGR U(0x818) +#define RCC_ETHSWACMCFGR U(0x81C) +#define RCC_ETHSWACMMSGCFGR U(0x820) +#define RCC_STGENCFGR U(0x824) +#define RCC_SDMMC1CFGR U(0x830) +#define RCC_SDMMC2CFGR U(0x834) +#define RCC_SDMMC3CFGR U(0x838) +#define RCC_GPUCFGR U(0x83C) +#define RCC_LTDCCFGR U(0x840) +#define RCC_DSICFGR U(0x844) +#define RCC_LVDSCFGR U(0x850) +#define RCC_CSI2CFGR U(0x858) +#define RCC_DCMIPPCFGR U(0x85C) +#define RCC_CCICFGR U(0x860) +#define RCC_VDECCFGR U(0x864) +#define RCC_VENCCFGR U(0x868) +#define RCC_RNGCFGR U(0x870) +#define RCC_PKACFGR U(0x874) +#define RCC_SAESCFGR U(0x878) +#define RCC_HASHCFGR U(0x87C) +#define RCC_CRYP1CFGR U(0x880) +#define RCC_CRYP2CFGR U(0x884) +#define RCC_IWDG1CFGR U(0x888) +#define RCC_IWDG2CFGR U(0x88C) +#define RCC_IWDG3CFGR U(0x890) +#define RCC_IWDG4CFGR U(0x894) +#define RCC_IWDG5CFGR U(0x898) +#define RCC_WWDG1CFGR U(0x89C) +#define RCC_WWDG2CFGR U(0x8A0) +#define RCC_BUSPERFMCFGR U(0x8A4) +#define RCC_VREFCFGR U(0x8A8) +#define RCC_TMPSENSCFGR U(0x8AC) +#define RCC_CRCCFGR U(0x8B4) +#define RCC_SERCCFGR U(0x8B8) +#define RCC_OSPIIOMCFGR U(0x8BC) +#define RCC_GICV2MCFGR U(0x8C0) +#define RCC_I3C1CFGR U(0x8C8) +#define RCC_I3C2CFGR U(0x8CC) +#define RCC_I3C3CFGR U(0x8D0) +#define RCC_I3C4CFGR U(0x8D4) +#define RCC_MUXSELCFGR U(0x1000) +#define RCC_XBAR0CFGR U(0x1018) +#define RCC_XBAR1CFGR U(0x101C) +#define RCC_XBAR2CFGR U(0x1020) +#define RCC_XBAR3CFGR U(0x1024) +#define RCC_XBAR4CFGR U(0x1028) +#define RCC_XBAR5CFGR U(0x102C) +#define RCC_XBAR6CFGR U(0x1030) +#define RCC_XBAR7CFGR U(0x1034) +#define RCC_XBAR8CFGR U(0x1038) +#define RCC_XBAR9CFGR U(0x103C) +#define RCC_XBAR10CFGR U(0x1040) +#define RCC_XBAR11CFGR U(0x1044) +#define RCC_XBAR12CFGR U(0x1048) +#define RCC_XBAR13CFGR U(0x104C) +#define RCC_XBAR14CFGR U(0x1050) +#define RCC_XBAR15CFGR U(0x1054) +#define RCC_XBAR16CFGR U(0x1058) +#define RCC_XBAR17CFGR U(0x105C) +#define RCC_XBAR18CFGR U(0x1060) +#define RCC_XBAR19CFGR U(0x1064) +#define RCC_XBAR20CFGR U(0x1068) +#define RCC_XBAR21CFGR U(0x106C) +#define RCC_XBAR22CFGR U(0x1070) +#define RCC_XBAR23CFGR U(0x1074) +#define RCC_XBAR24CFGR U(0x1078) +#define RCC_XBAR25CFGR U(0x107C) +#define RCC_XBAR26CFGR U(0x1080) +#define RCC_XBAR27CFGR U(0x1084) +#define RCC_XBAR28CFGR U(0x1088) +#define RCC_XBAR29CFGR U(0x108C) +#define RCC_XBAR30CFGR U(0x1090) +#define RCC_XBAR31CFGR U(0x1094) +#define RCC_XBAR32CFGR U(0x1098) +#define RCC_XBAR33CFGR U(0x109C) +#define RCC_XBAR34CFGR U(0x10A0) +#define RCC_XBAR35CFGR U(0x10A4) +#define RCC_XBAR36CFGR U(0x10A8) +#define RCC_XBAR37CFGR U(0x10AC) +#define RCC_XBAR38CFGR U(0x10B0) +#define RCC_XBAR39CFGR U(0x10B4) +#define RCC_XBAR40CFGR U(0x10B8) +#define RCC_XBAR41CFGR U(0x10BC) +#define RCC_XBAR42CFGR U(0x10C0) +#define RCC_XBAR43CFGR U(0x10C4) +#define RCC_XBAR44CFGR U(0x10C8) +#define RCC_XBAR45CFGR U(0x10CC) +#define RCC_XBAR46CFGR U(0x10D0) +#define RCC_XBAR47CFGR U(0x10D4) +#define RCC_XBAR48CFGR U(0x10D8) +#define RCC_XBAR49CFGR U(0x10DC) +#define RCC_XBAR50CFGR U(0x10E0) +#define RCC_XBAR51CFGR U(0x10E4) +#define RCC_XBAR52CFGR U(0x10E8) +#define RCC_XBAR53CFGR U(0x10EC) +#define RCC_XBAR54CFGR U(0x10F0) +#define RCC_XBAR55CFGR U(0x10F4) +#define RCC_XBAR56CFGR U(0x10F8) +#define RCC_XBAR57CFGR U(0x10FC) +#define RCC_XBAR58CFGR U(0x1100) +#define RCC_XBAR59CFGR U(0x1104) +#define RCC_XBAR60CFGR U(0x1108) +#define RCC_XBAR61CFGR U(0x110C) +#define RCC_XBAR62CFGR U(0x1110) +#define RCC_XBAR63CFGR U(0x1114) +#define RCC_PREDIV0CFGR U(0x1118) +#define RCC_PREDIV1CFGR U(0x111C) +#define RCC_PREDIV2CFGR U(0x1120) +#define RCC_PREDIV3CFGR U(0x1124) +#define RCC_PREDIV4CFGR U(0x1128) +#define RCC_PREDIV5CFGR U(0x112C) +#define RCC_PREDIV6CFGR U(0x1130) +#define RCC_PREDIV7CFGR U(0x1134) +#define RCC_PREDIV8CFGR U(0x1138) +#define RCC_PREDIV9CFGR U(0x113C) +#define RCC_PREDIV10CFGR U(0x1140) +#define RCC_PREDIV11CFGR U(0x1144) +#define RCC_PREDIV12CFGR U(0x1148) +#define RCC_PREDIV13CFGR U(0x114C) +#define RCC_PREDIV14CFGR U(0x1150) +#define RCC_PREDIV15CFGR U(0x1154) +#define RCC_PREDIV16CFGR U(0x1158) +#define RCC_PREDIV17CFGR U(0x115C) +#define RCC_PREDIV18CFGR U(0x1160) +#define RCC_PREDIV19CFGR U(0x1164) +#define RCC_PREDIV20CFGR U(0x1168) +#define RCC_PREDIV21CFGR U(0x116C) +#define RCC_PREDIV22CFGR U(0x1170) +#define RCC_PREDIV23CFGR U(0x1174) +#define RCC_PREDIV24CFGR U(0x1178) +#define RCC_PREDIV25CFGR U(0x117C) +#define RCC_PREDIV26CFGR U(0x1180) +#define RCC_PREDIV27CFGR U(0x1184) +#define RCC_PREDIV28CFGR U(0x1188) +#define RCC_PREDIV29CFGR U(0x118C) +#define RCC_PREDIV30CFGR U(0x1190) +#define RCC_PREDIV31CFGR U(0x1194) +#define RCC_PREDIV32CFGR U(0x1198) +#define RCC_PREDIV33CFGR U(0x119C) +#define RCC_PREDIV34CFGR U(0x11A0) +#define RCC_PREDIV35CFGR U(0x11A4) +#define RCC_PREDIV36CFGR U(0x11A8) +#define RCC_PREDIV37CFGR U(0x11AC) +#define RCC_PREDIV38CFGR U(0x11B0) +#define RCC_PREDIV39CFGR U(0x11B4) +#define RCC_PREDIV40CFGR U(0x11B8) +#define RCC_PREDIV41CFGR U(0x11BC) +#define RCC_PREDIV42CFGR U(0x11C0) +#define RCC_PREDIV43CFGR U(0x11C4) +#define RCC_PREDIV44CFGR U(0x11C8) +#define RCC_PREDIV45CFGR U(0x11CC) +#define RCC_PREDIV46CFGR U(0x11D0) +#define RCC_PREDIV47CFGR U(0x11D4) +#define RCC_PREDIV48CFGR U(0x11D8) +#define RCC_PREDIV49CFGR U(0x11DC) +#define RCC_PREDIV50CFGR U(0x11E0) +#define RCC_PREDIV51CFGR U(0x11E4) +#define RCC_PREDIV52CFGR U(0x11E8) +#define RCC_PREDIV53CFGR U(0x11EC) +#define RCC_PREDIV54CFGR U(0x11F0) +#define RCC_PREDIV55CFGR U(0x11F4) +#define RCC_PREDIV56CFGR U(0x11F8) +#define RCC_PREDIV57CFGR U(0x11FC) +#define RCC_PREDIV58CFGR U(0x1200) +#define RCC_PREDIV59CFGR U(0x1204) +#define RCC_PREDIV60CFGR U(0x1208) +#define RCC_PREDIV61CFGR U(0x120C) +#define RCC_PREDIV62CFGR U(0x1210) +#define RCC_PREDIV63CFGR U(0x1214) +#define RCC_PREDIVSR1 U(0x1218) +#define RCC_PREDIVSR2 U(0x121C) +#define RCC_FINDIV0CFGR U(0x1224) +#define RCC_FINDIV1CFGR U(0x1228) +#define RCC_FINDIV2CFGR U(0x122C) +#define RCC_FINDIV3CFGR U(0x1230) +#define RCC_FINDIV4CFGR U(0x1234) +#define RCC_FINDIV5CFGR U(0x1238) +#define RCC_FINDIV6CFGR U(0x123C) +#define RCC_FINDIV7CFGR U(0x1240) +#define RCC_FINDIV8CFGR U(0x1244) +#define RCC_FINDIV9CFGR U(0x1248) +#define RCC_FINDIV10CFGR U(0x124C) +#define RCC_FINDIV11CFGR U(0x1250) +#define RCC_FINDIV12CFGR U(0x1254) +#define RCC_FINDIV13CFGR U(0x1258) +#define RCC_FINDIV14CFGR U(0x125C) +#define RCC_FINDIV15CFGR U(0x1260) +#define RCC_FINDIV16CFGR U(0x1264) +#define RCC_FINDIV17CFGR U(0x1268) +#define RCC_FINDIV18CFGR U(0x126C) +#define RCC_FINDIV19CFGR U(0x1270) +#define RCC_FINDIV20CFGR U(0x1274) +#define RCC_FINDIV21CFGR U(0x1278) +#define RCC_FINDIV22CFGR U(0x127C) +#define RCC_FINDIV23CFGR U(0x1280) +#define RCC_FINDIV24CFGR U(0x1284) +#define RCC_FINDIV25CFGR U(0x1288) +#define RCC_FINDIV26CFGR U(0x128C) +#define RCC_FINDIV27CFGR U(0x1290) +#define RCC_FINDIV28CFGR U(0x1294) +#define RCC_FINDIV29CFGR U(0x1298) +#define RCC_FINDIV30CFGR U(0x129C) +#define RCC_FINDIV31CFGR U(0x12A0) +#define RCC_FINDIV32CFGR U(0x12A4) +#define RCC_FINDIV33CFGR U(0x12A8) +#define RCC_FINDIV34CFGR U(0x12AC) +#define RCC_FINDIV35CFGR U(0x12B0) +#define RCC_FINDIV36CFGR U(0x12B4) +#define RCC_FINDIV37CFGR U(0x12B8) +#define RCC_FINDIV38CFGR U(0x12BC) +#define RCC_FINDIV39CFGR U(0x12C0) +#define RCC_FINDIV40CFGR U(0x12C4) +#define RCC_FINDIV41CFGR U(0x12C8) +#define RCC_FINDIV42CFGR U(0x12CC) +#define RCC_FINDIV43CFGR U(0x12D0) +#define RCC_FINDIV44CFGR U(0x12D4) +#define RCC_FINDIV45CFGR U(0x12D8) +#define RCC_FINDIV46CFGR U(0x12DC) +#define RCC_FINDIV47CFGR U(0x12E0) +#define RCC_FINDIV48CFGR U(0x12E4) +#define RCC_FINDIV49CFGR U(0x12E8) +#define RCC_FINDIV50CFGR U(0x12EC) +#define RCC_FINDIV51CFGR U(0x12F0) +#define RCC_FINDIV52CFGR U(0x12F4) +#define RCC_FINDIV53CFGR U(0x12F8) +#define RCC_FINDIV54CFGR U(0x12FC) +#define RCC_FINDIV55CFGR U(0x1300) +#define RCC_FINDIV56CFGR U(0x1304) +#define RCC_FINDIV57CFGR U(0x1308) +#define RCC_FINDIV58CFGR U(0x130C) +#define RCC_FINDIV59CFGR U(0x1310) +#define RCC_FINDIV60CFGR U(0x1314) +#define RCC_FINDIV61CFGR U(0x1318) +#define RCC_FINDIV62CFGR U(0x131C) +#define RCC_FINDIV63CFGR U(0x1320) +#define RCC_FINDIVSR1 U(0x1324) +#define RCC_FINDIVSR2 U(0x1328) +#define RCC_FCALCOBS0CFGR U(0x1340) +#define RCC_FCALCOBS1CFGR U(0x1344) +#define RCC_FCALCREFCFGR U(0x1348) +#define RCC_FCALCCR1 U(0x134C) +#define RCC_FCALCCR2 U(0x1354) +#define RCC_FCALCSR U(0x1358) +#define RCC_PLL4CFGR1 U(0x1360) +#define RCC_PLL4CFGR2 U(0x1364) +#define RCC_PLL4CFGR3 U(0x1368) +#define RCC_PLL4CFGR4 U(0x136C) +#define RCC_PLL4CFGR5 U(0x1370) +#define RCC_PLL4CFGR6 U(0x1378) +#define RCC_PLL4CFGR7 U(0x137C) +#define RCC_PLL5CFGR1 U(0x1388) +#define RCC_PLL5CFGR2 U(0x138C) +#define RCC_PLL5CFGR3 U(0x1390) +#define RCC_PLL5CFGR4 U(0x1394) +#define RCC_PLL5CFGR5 U(0x1398) +#define RCC_PLL5CFGR6 U(0x13A0) +#define RCC_PLL5CFGR7 U(0x13A4) +#define RCC_PLL6CFGR1 U(0x13B0) +#define RCC_PLL6CFGR2 U(0x13B4) +#define RCC_PLL6CFGR3 U(0x13B8) +#define RCC_PLL6CFGR4 U(0x13BC) +#define RCC_PLL6CFGR5 U(0x13C0) +#define RCC_PLL6CFGR6 U(0x13C8) +#define RCC_PLL6CFGR7 U(0x13CC) +#define RCC_PLL7CFGR1 U(0x13D8) +#define RCC_PLL7CFGR2 U(0x13DC) +#define RCC_PLL7CFGR3 U(0x13E0) +#define RCC_PLL7CFGR4 U(0x13E4) +#define RCC_PLL7CFGR5 U(0x13E8) +#define RCC_PLL7CFGR6 U(0x13F0) +#define RCC_PLL7CFGR7 U(0x13F4) +#define RCC_PLL8CFGR1 U(0x1400) +#define RCC_PLL8CFGR2 U(0x1404) +#define RCC_PLL8CFGR3 U(0x1408) +#define RCC_PLL8CFGR4 U(0x140C) +#define RCC_PLL8CFGR5 U(0x1410) +#define RCC_PLL8CFGR6 U(0x1418) +#define RCC_PLL8CFGR7 U(0x141C) +#define RCC_VERR U(0xFFF4) +#define RCC_IDR U(0xFFF8) +#define RCC_SIDR U(0xFFFC) + +/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ +#define RCC_MP_ENCLRR_OFFSET U(4) + +/* RCC_SECCFGR3 register fields */ +#define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0) +#define RCC_SECCFGR3_SEC_SHIFT 0 + +/* RCC_PRIVCFGR3 register fields */ +#define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0) +#define RCC_PRIVCFGR3_PRIV_SHIFT 0 + +/* RCC_RCFGLOCKR3 register fields */ +#define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0) +#define RCC_RCFGLOCKR3_RLOCK_SHIFT 0 + +/* RCC_R0CIDCFGR register fields */ +#define RCC_R0CIDCFGR_CFEN BIT(0) +#define RCC_R0CIDCFGR_SEM_EN BIT(1) +#define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R0CIDCFGR_SCID_SHIFT 4 +#define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R0CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R0SEMCR register fields */ +#define RCC_R0SEMCR_SEM_MUTEX BIT(0) +#define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R0SEMCR_SEMCID_SHIFT 4 + +/* RCC_R1CIDCFGR register fields */ +#define RCC_R1CIDCFGR_CFEN BIT(0) +#define RCC_R1CIDCFGR_SEM_EN BIT(1) +#define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R1CIDCFGR_SCID_SHIFT 4 +#define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R1CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R1SEMCR register fields */ +#define RCC_R1SEMCR_SEM_MUTEX BIT(0) +#define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R1SEMCR_SEMCID_SHIFT 4 + +/* RCC_R2CIDCFGR register fields */ +#define RCC_R2CIDCFGR_CFEN BIT(0) +#define RCC_R2CIDCFGR_SEM_EN BIT(1) +#define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R2CIDCFGR_SCID_SHIFT 4 +#define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R2CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R2SEMCR register fields */ +#define RCC_R2SEMCR_SEM_MUTEX BIT(0) +#define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R2SEMCR_SEMCID_SHIFT 4 + +/* RCC_R3CIDCFGR register fields */ +#define RCC_R3CIDCFGR_CFEN BIT(0) +#define RCC_R3CIDCFGR_SEM_EN BIT(1) +#define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R3CIDCFGR_SCID_SHIFT 4 +#define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R3CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R3SEMCR register fields */ +#define RCC_R3SEMCR_SEM_MUTEX BIT(0) +#define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R3SEMCR_SEMCID_SHIFT 4 + +/* RCC_R4CIDCFGR register fields */ +#define RCC_R4CIDCFGR_CFEN BIT(0) +#define RCC_R4CIDCFGR_SEM_EN BIT(1) +#define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R4CIDCFGR_SCID_SHIFT 4 +#define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R4CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R4SEMCR register fields */ +#define RCC_R4SEMCR_SEM_MUTEX BIT(0) +#define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R4SEMCR_SEMCID_SHIFT 4 + +/* RCC_R5CIDCFGR register fields */ +#define RCC_R5CIDCFGR_CFEN BIT(0) +#define RCC_R5CIDCFGR_SEM_EN BIT(1) +#define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R5CIDCFGR_SCID_SHIFT 4 +#define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R5CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R5SEMCR register fields */ +#define RCC_R5SEMCR_SEM_MUTEX BIT(0) +#define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R5SEMCR_SEMCID_SHIFT 4 + +/* RCC_R6CIDCFGR register fields */ +#define RCC_R6CIDCFGR_CFEN BIT(0) +#define RCC_R6CIDCFGR_SEM_EN BIT(1) +#define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R6CIDCFGR_SCID_SHIFT 4 +#define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R6CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R6SEMCR register fields */ +#define RCC_R6SEMCR_SEM_MUTEX BIT(0) +#define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R6SEMCR_SEMCID_SHIFT 4 + +/* RCC_R7CIDCFGR register fields */ +#define RCC_R7CIDCFGR_CFEN BIT(0) +#define RCC_R7CIDCFGR_SEM_EN BIT(1) +#define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R7CIDCFGR_SCID_SHIFT 4 +#define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R7CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R7SEMCR register fields */ +#define RCC_R7SEMCR_SEM_MUTEX BIT(0) +#define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R7SEMCR_SEMCID_SHIFT 4 + +/* RCC_R8CIDCFGR register fields */ +#define RCC_R8CIDCFGR_CFEN BIT(0) +#define RCC_R8CIDCFGR_SEM_EN BIT(1) +#define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R8CIDCFGR_SCID_SHIFT 4 +#define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R8CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R8SEMCR register fields */ +#define RCC_R8SEMCR_SEM_MUTEX BIT(0) +#define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R8SEMCR_SEMCID_SHIFT 4 + +/* RCC_R9CIDCFGR register fields */ +#define RCC_R9CIDCFGR_CFEN BIT(0) +#define RCC_R9CIDCFGR_SEM_EN BIT(1) +#define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R9CIDCFGR_SCID_SHIFT 4 +#define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R9CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R9SEMCR register fields */ +#define RCC_R9SEMCR_SEM_MUTEX BIT(0) +#define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R9SEMCR_SEMCID_SHIFT 4 + +/* RCC_R10CIDCFGR register fields */ +#define RCC_R10CIDCFGR_CFEN BIT(0) +#define RCC_R10CIDCFGR_SEM_EN BIT(1) +#define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R10CIDCFGR_SCID_SHIFT 4 +#define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R10CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R10SEMCR register fields */ +#define RCC_R10SEMCR_SEM_MUTEX BIT(0) +#define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R10SEMCR_SEMCID_SHIFT 4 + +/* RCC_R11CIDCFGR register fields */ +#define RCC_R11CIDCFGR_CFEN BIT(0) +#define RCC_R11CIDCFGR_SEM_EN BIT(1) +#define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R11CIDCFGR_SCID_SHIFT 4 +#define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R11CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R11SEMCR register fields */ +#define RCC_R11SEMCR_SEM_MUTEX BIT(0) +#define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R11SEMCR_SEMCID_SHIFT 4 + +/* RCC_R12CIDCFGR register fields */ +#define RCC_R12CIDCFGR_CFEN BIT(0) +#define RCC_R12CIDCFGR_SEM_EN BIT(1) +#define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R12CIDCFGR_SCID_SHIFT 4 +#define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R12CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R12SEMCR register fields */ +#define RCC_R12SEMCR_SEM_MUTEX BIT(0) +#define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R12SEMCR_SEMCID_SHIFT 4 + +/* RCC_R13CIDCFGR register fields */ +#define RCC_R13CIDCFGR_CFEN BIT(0) +#define RCC_R13CIDCFGR_SEM_EN BIT(1) +#define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R13CIDCFGR_SCID_SHIFT 4 +#define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R13CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R13SEMCR register fields */ +#define RCC_R13SEMCR_SEM_MUTEX BIT(0) +#define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R13SEMCR_SEMCID_SHIFT 4 + +/* RCC_R14CIDCFGR register fields */ +#define RCC_R14CIDCFGR_CFEN BIT(0) +#define RCC_R14CIDCFGR_SEM_EN BIT(1) +#define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R14CIDCFGR_SCID_SHIFT 4 +#define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R14CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R14SEMCR register fields */ +#define RCC_R14SEMCR_SEM_MUTEX BIT(0) +#define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R14SEMCR_SEMCID_SHIFT 4 + +/* RCC_R15CIDCFGR register fields */ +#define RCC_R15CIDCFGR_CFEN BIT(0) +#define RCC_R15CIDCFGR_SEM_EN BIT(1) +#define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R15CIDCFGR_SCID_SHIFT 4 +#define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R15CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R15SEMCR register fields */ +#define RCC_R15SEMCR_SEM_MUTEX BIT(0) +#define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R15SEMCR_SEMCID_SHIFT 4 + +/* RCC_R16CIDCFGR register fields */ +#define RCC_R16CIDCFGR_CFEN BIT(0) +#define RCC_R16CIDCFGR_SEM_EN BIT(1) +#define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R16CIDCFGR_SCID_SHIFT 4 +#define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R16CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R16SEMCR register fields */ +#define RCC_R16SEMCR_SEM_MUTEX BIT(0) +#define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R16SEMCR_SEMCID_SHIFT 4 + +/* RCC_R17CIDCFGR register fields */ +#define RCC_R17CIDCFGR_CFEN BIT(0) +#define RCC_R17CIDCFGR_SEM_EN BIT(1) +#define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R17CIDCFGR_SCID_SHIFT 4 +#define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R17CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R17SEMCR register fields */ +#define RCC_R17SEMCR_SEM_MUTEX BIT(0) +#define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R17SEMCR_SEMCID_SHIFT 4 + +/* RCC_R18CIDCFGR register fields */ +#define RCC_R18CIDCFGR_CFEN BIT(0) +#define RCC_R18CIDCFGR_SEM_EN BIT(1) +#define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R18CIDCFGR_SCID_SHIFT 4 +#define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R18CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R18SEMCR register fields */ +#define RCC_R18SEMCR_SEM_MUTEX BIT(0) +#define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R18SEMCR_SEMCID_SHIFT 4 + +/* RCC_R19CIDCFGR register fields */ +#define RCC_R19CIDCFGR_CFEN BIT(0) +#define RCC_R19CIDCFGR_SEM_EN BIT(1) +#define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R19CIDCFGR_SCID_SHIFT 4 +#define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R19CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R19SEMCR register fields */ +#define RCC_R19SEMCR_SEM_MUTEX BIT(0) +#define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R19SEMCR_SEMCID_SHIFT 4 + +/* RCC_R20CIDCFGR register fields */ +#define RCC_R20CIDCFGR_CFEN BIT(0) +#define RCC_R20CIDCFGR_SEM_EN BIT(1) +#define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R20CIDCFGR_SCID_SHIFT 4 +#define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R20CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R20SEMCR register fields */ +#define RCC_R20SEMCR_SEM_MUTEX BIT(0) +#define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R20SEMCR_SEMCID_SHIFT 4 + +/* RCC_R21CIDCFGR register fields */ +#define RCC_R21CIDCFGR_CFEN BIT(0) +#define RCC_R21CIDCFGR_SEM_EN BIT(1) +#define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R21CIDCFGR_SCID_SHIFT 4 +#define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R21CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R21SEMCR register fields */ +#define RCC_R21SEMCR_SEM_MUTEX BIT(0) +#define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R21SEMCR_SEMCID_SHIFT 4 + +/* RCC_R22CIDCFGR register fields */ +#define RCC_R22CIDCFGR_CFEN BIT(0) +#define RCC_R22CIDCFGR_SEM_EN BIT(1) +#define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R22CIDCFGR_SCID_SHIFT 4 +#define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R22CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R22SEMCR register fields */ +#define RCC_R22SEMCR_SEM_MUTEX BIT(0) +#define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R22SEMCR_SEMCID_SHIFT 4 + +/* RCC_R23CIDCFGR register fields */ +#define RCC_R23CIDCFGR_CFEN BIT(0) +#define RCC_R23CIDCFGR_SEM_EN BIT(1) +#define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R23CIDCFGR_SCID_SHIFT 4 +#define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R23CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R23SEMCR register fields */ +#define RCC_R23SEMCR_SEM_MUTEX BIT(0) +#define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R23SEMCR_SEMCID_SHIFT 4 + +/* RCC_R24CIDCFGR register fields */ +#define RCC_R24CIDCFGR_CFEN BIT(0) +#define RCC_R24CIDCFGR_SEM_EN BIT(1) +#define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R24CIDCFGR_SCID_SHIFT 4 +#define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R24CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R24SEMCR register fields */ +#define RCC_R24SEMCR_SEM_MUTEX BIT(0) +#define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R24SEMCR_SEMCID_SHIFT 4 + +/* RCC_R25CIDCFGR register fields */ +#define RCC_R25CIDCFGR_CFEN BIT(0) +#define RCC_R25CIDCFGR_SEM_EN BIT(1) +#define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R25CIDCFGR_SCID_SHIFT 4 +#define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R25CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R25SEMCR register fields */ +#define RCC_R25SEMCR_SEM_MUTEX BIT(0) +#define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R25SEMCR_SEMCID_SHIFT 4 + +/* RCC_R26CIDCFGR register fields */ +#define RCC_R26CIDCFGR_CFEN BIT(0) +#define RCC_R26CIDCFGR_SEM_EN BIT(1) +#define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R26CIDCFGR_SCID_SHIFT 4 +#define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R26CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R26SEMCR register fields */ +#define RCC_R26SEMCR_SEM_MUTEX BIT(0) +#define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R26SEMCR_SEMCID_SHIFT 4 + +/* RCC_R27CIDCFGR register fields */ +#define RCC_R27CIDCFGR_CFEN BIT(0) +#define RCC_R27CIDCFGR_SEM_EN BIT(1) +#define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R27CIDCFGR_SCID_SHIFT 4 +#define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R27CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R27SEMCR register fields */ +#define RCC_R27SEMCR_SEM_MUTEX BIT(0) +#define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R27SEMCR_SEMCID_SHIFT 4 + +/* RCC_R28CIDCFGR register fields */ +#define RCC_R28CIDCFGR_CFEN BIT(0) +#define RCC_R28CIDCFGR_SEM_EN BIT(1) +#define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R28CIDCFGR_SCID_SHIFT 4 +#define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R28CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R28SEMCR register fields */ +#define RCC_R28SEMCR_SEM_MUTEX BIT(0) +#define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R28SEMCR_SEMCID_SHIFT 4 + +/* RCC_R29CIDCFGR register fields */ +#define RCC_R29CIDCFGR_CFEN BIT(0) +#define RCC_R29CIDCFGR_SEM_EN BIT(1) +#define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R29CIDCFGR_SCID_SHIFT 4 +#define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R29CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R29SEMCR register fields */ +#define RCC_R29SEMCR_SEM_MUTEX BIT(0) +#define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R29SEMCR_SEMCID_SHIFT 4 + +/* RCC_R30CIDCFGR register fields */ +#define RCC_R30CIDCFGR_CFEN BIT(0) +#define RCC_R30CIDCFGR_SEM_EN BIT(1) +#define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R30CIDCFGR_SCID_SHIFT 4 +#define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R30CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R30SEMCR register fields */ +#define RCC_R30SEMCR_SEM_MUTEX BIT(0) +#define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R30SEMCR_SEMCID_SHIFT 4 + +/* RCC_R31CIDCFGR register fields */ +#define RCC_R31CIDCFGR_CFEN BIT(0) +#define RCC_R31CIDCFGR_SEM_EN BIT(1) +#define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R31CIDCFGR_SCID_SHIFT 4 +#define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R31CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R31SEMCR register fields */ +#define RCC_R31SEMCR_SEM_MUTEX BIT(0) +#define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R31SEMCR_SEMCID_SHIFT 4 + +/* RCC_R32CIDCFGR register fields */ +#define RCC_R32CIDCFGR_CFEN BIT(0) +#define RCC_R32CIDCFGR_SEM_EN BIT(1) +#define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R32CIDCFGR_SCID_SHIFT 4 +#define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R32CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R32SEMCR register fields */ +#define RCC_R32SEMCR_SEM_MUTEX BIT(0) +#define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R32SEMCR_SEMCID_SHIFT 4 + +/* RCC_R33CIDCFGR register fields */ +#define RCC_R33CIDCFGR_CFEN BIT(0) +#define RCC_R33CIDCFGR_SEM_EN BIT(1) +#define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R33CIDCFGR_SCID_SHIFT 4 +#define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R33CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R33SEMCR register fields */ +#define RCC_R33SEMCR_SEM_MUTEX BIT(0) +#define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R33SEMCR_SEMCID_SHIFT 4 + +/* RCC_R34CIDCFGR register fields */ +#define RCC_R34CIDCFGR_CFEN BIT(0) +#define RCC_R34CIDCFGR_SEM_EN BIT(1) +#define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R34CIDCFGR_SCID_SHIFT 4 +#define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R34CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R34SEMCR register fields */ +#define RCC_R34SEMCR_SEM_MUTEX BIT(0) +#define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R34SEMCR_SEMCID_SHIFT 4 + +/* RCC_R35CIDCFGR register fields */ +#define RCC_R35CIDCFGR_CFEN BIT(0) +#define RCC_R35CIDCFGR_SEM_EN BIT(1) +#define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R35CIDCFGR_SCID_SHIFT 4 +#define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R35CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R35SEMCR register fields */ +#define RCC_R35SEMCR_SEM_MUTEX BIT(0) +#define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R35SEMCR_SEMCID_SHIFT 4 + +/* RCC_R36CIDCFGR register fields */ +#define RCC_R36CIDCFGR_CFEN BIT(0) +#define RCC_R36CIDCFGR_SEM_EN BIT(1) +#define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R36CIDCFGR_SCID_SHIFT 4 +#define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R36CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R36SEMCR register fields */ +#define RCC_R36SEMCR_SEM_MUTEX BIT(0) +#define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R36SEMCR_SEMCID_SHIFT 4 + +/* RCC_R37CIDCFGR register fields */ +#define RCC_R37CIDCFGR_CFEN BIT(0) +#define RCC_R37CIDCFGR_SEM_EN BIT(1) +#define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R37CIDCFGR_SCID_SHIFT 4 +#define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R37CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R37SEMCR register fields */ +#define RCC_R37SEMCR_SEM_MUTEX BIT(0) +#define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R37SEMCR_SEMCID_SHIFT 4 + +/* RCC_R38CIDCFGR register fields */ +#define RCC_R38CIDCFGR_CFEN BIT(0) +#define RCC_R38CIDCFGR_SEM_EN BIT(1) +#define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R38CIDCFGR_SCID_SHIFT 4 +#define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R38CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R38SEMCR register fields */ +#define RCC_R38SEMCR_SEM_MUTEX BIT(0) +#define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R38SEMCR_SEMCID_SHIFT 4 + +/* RCC_R39CIDCFGR register fields */ +#define RCC_R39CIDCFGR_CFEN BIT(0) +#define RCC_R39CIDCFGR_SEM_EN BIT(1) +#define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R39CIDCFGR_SCID_SHIFT 4 +#define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R39CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R39SEMCR register fields */ +#define RCC_R39SEMCR_SEM_MUTEX BIT(0) +#define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R39SEMCR_SEMCID_SHIFT 4 + +/* RCC_R40CIDCFGR register fields */ +#define RCC_R40CIDCFGR_CFEN BIT(0) +#define RCC_R40CIDCFGR_SEM_EN BIT(1) +#define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R40CIDCFGR_SCID_SHIFT 4 +#define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R40CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R40SEMCR register fields */ +#define RCC_R40SEMCR_SEM_MUTEX BIT(0) +#define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R40SEMCR_SEMCID_SHIFT 4 + +/* RCC_R41CIDCFGR register fields */ +#define RCC_R41CIDCFGR_CFEN BIT(0) +#define RCC_R41CIDCFGR_SEM_EN BIT(1) +#define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R41CIDCFGR_SCID_SHIFT 4 +#define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R41CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R41SEMCR register fields */ +#define RCC_R41SEMCR_SEM_MUTEX BIT(0) +#define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R41SEMCR_SEMCID_SHIFT 4 + +/* RCC_R42CIDCFGR register fields */ +#define RCC_R42CIDCFGR_CFEN BIT(0) +#define RCC_R42CIDCFGR_SEM_EN BIT(1) +#define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R42CIDCFGR_SCID_SHIFT 4 +#define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R42CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R42SEMCR register fields */ +#define RCC_R42SEMCR_SEM_MUTEX BIT(0) +#define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R42SEMCR_SEMCID_SHIFT 4 + +/* RCC_R43CIDCFGR register fields */ +#define RCC_R43CIDCFGR_CFEN BIT(0) +#define RCC_R43CIDCFGR_SEM_EN BIT(1) +#define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R43CIDCFGR_SCID_SHIFT 4 +#define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R43CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R43SEMCR register fields */ +#define RCC_R43SEMCR_SEM_MUTEX BIT(0) +#define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R43SEMCR_SEMCID_SHIFT 4 + +/* RCC_R44CIDCFGR register fields */ +#define RCC_R44CIDCFGR_CFEN BIT(0) +#define RCC_R44CIDCFGR_SEM_EN BIT(1) +#define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R44CIDCFGR_SCID_SHIFT 4 +#define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R44CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R44SEMCR register fields */ +#define RCC_R44SEMCR_SEM_MUTEX BIT(0) +#define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R44SEMCR_SEMCID_SHIFT 4 + +/* RCC_R45CIDCFGR register fields */ +#define RCC_R45CIDCFGR_CFEN BIT(0) +#define RCC_R45CIDCFGR_SEM_EN BIT(1) +#define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R45CIDCFGR_SCID_SHIFT 4 +#define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R45CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R45SEMCR register fields */ +#define RCC_R45SEMCR_SEM_MUTEX BIT(0) +#define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R45SEMCR_SEMCID_SHIFT 4 + +/* RCC_R46CIDCFGR register fields */ +#define RCC_R46CIDCFGR_CFEN BIT(0) +#define RCC_R46CIDCFGR_SEM_EN BIT(1) +#define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R46CIDCFGR_SCID_SHIFT 4 +#define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R46CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R46SEMCR register fields */ +#define RCC_R46SEMCR_SEM_MUTEX BIT(0) +#define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R46SEMCR_SEMCID_SHIFT 4 + +/* RCC_R47CIDCFGR register fields */ +#define RCC_R47CIDCFGR_CFEN BIT(0) +#define RCC_R47CIDCFGR_SEM_EN BIT(1) +#define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R47CIDCFGR_SCID_SHIFT 4 +#define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R47CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R47SEMCR register fields */ +#define RCC_R47SEMCR_SEM_MUTEX BIT(0) +#define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R47SEMCR_SEMCID_SHIFT 4 + +/* RCC_R48CIDCFGR register fields */ +#define RCC_R48CIDCFGR_CFEN BIT(0) +#define RCC_R48CIDCFGR_SEM_EN BIT(1) +#define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R48CIDCFGR_SCID_SHIFT 4 +#define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R48CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R48SEMCR register fields */ +#define RCC_R48SEMCR_SEM_MUTEX BIT(0) +#define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R48SEMCR_SEMCID_SHIFT 4 + +/* RCC_R49CIDCFGR register fields */ +#define RCC_R49CIDCFGR_CFEN BIT(0) +#define RCC_R49CIDCFGR_SEM_EN BIT(1) +#define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R49CIDCFGR_SCID_SHIFT 4 +#define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R49CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R49SEMCR register fields */ +#define RCC_R49SEMCR_SEM_MUTEX BIT(0) +#define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R49SEMCR_SEMCID_SHIFT 4 + +/* RCC_R50CIDCFGR register fields */ +#define RCC_R50CIDCFGR_CFEN BIT(0) +#define RCC_R50CIDCFGR_SEM_EN BIT(1) +#define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R50CIDCFGR_SCID_SHIFT 4 +#define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R50CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R50SEMCR register fields */ +#define RCC_R50SEMCR_SEM_MUTEX BIT(0) +#define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R50SEMCR_SEMCID_SHIFT 4 + +/* RCC_R51CIDCFGR register fields */ +#define RCC_R51CIDCFGR_CFEN BIT(0) +#define RCC_R51CIDCFGR_SEM_EN BIT(1) +#define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R51CIDCFGR_SCID_SHIFT 4 +#define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R51CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R51SEMCR register fields */ +#define RCC_R51SEMCR_SEM_MUTEX BIT(0) +#define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R51SEMCR_SEMCID_SHIFT 4 + +/* RCC_R52CIDCFGR register fields */ +#define RCC_R52CIDCFGR_CFEN BIT(0) +#define RCC_R52CIDCFGR_SEM_EN BIT(1) +#define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R52CIDCFGR_SCID_SHIFT 4 +#define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R52CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R52SEMCR register fields */ +#define RCC_R52SEMCR_SEM_MUTEX BIT(0) +#define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R52SEMCR_SEMCID_SHIFT 4 + +/* RCC_R53CIDCFGR register fields */ +#define RCC_R53CIDCFGR_CFEN BIT(0) +#define RCC_R53CIDCFGR_SEM_EN BIT(1) +#define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R53CIDCFGR_SCID_SHIFT 4 +#define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R53CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R53SEMCR register fields */ +#define RCC_R53SEMCR_SEM_MUTEX BIT(0) +#define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R53SEMCR_SEMCID_SHIFT 4 + +/* RCC_R54CIDCFGR register fields */ +#define RCC_R54CIDCFGR_CFEN BIT(0) +#define RCC_R54CIDCFGR_SEM_EN BIT(1) +#define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R54CIDCFGR_SCID_SHIFT 4 +#define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R54CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R54SEMCR register fields */ +#define RCC_R54SEMCR_SEM_MUTEX BIT(0) +#define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R54SEMCR_SEMCID_SHIFT 4 + +/* RCC_R55CIDCFGR register fields */ +#define RCC_R55CIDCFGR_CFEN BIT(0) +#define RCC_R55CIDCFGR_SEM_EN BIT(1) +#define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R55CIDCFGR_SCID_SHIFT 4 +#define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R55CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R55SEMCR register fields */ +#define RCC_R55SEMCR_SEM_MUTEX BIT(0) +#define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R55SEMCR_SEMCID_SHIFT 4 + +/* RCC_R56CIDCFGR register fields */ +#define RCC_R56CIDCFGR_CFEN BIT(0) +#define RCC_R56CIDCFGR_SEM_EN BIT(1) +#define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R56CIDCFGR_SCID_SHIFT 4 +#define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R56CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R56SEMCR register fields */ +#define RCC_R56SEMCR_SEM_MUTEX BIT(0) +#define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R56SEMCR_SEMCID_SHIFT 4 + +/* RCC_R57CIDCFGR register fields */ +#define RCC_R57CIDCFGR_CFEN BIT(0) +#define RCC_R57CIDCFGR_SEM_EN BIT(1) +#define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R57CIDCFGR_SCID_SHIFT 4 +#define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R57CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R57SEMCR register fields */ +#define RCC_R57SEMCR_SEM_MUTEX BIT(0) +#define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R57SEMCR_SEMCID_SHIFT 4 + +/* RCC_R58CIDCFGR register fields */ +#define RCC_R58CIDCFGR_CFEN BIT(0) +#define RCC_R58CIDCFGR_SEM_EN BIT(1) +#define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R58CIDCFGR_SCID_SHIFT 4 +#define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R58CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R58SEMCR register fields */ +#define RCC_R58SEMCR_SEM_MUTEX BIT(0) +#define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R58SEMCR_SEMCID_SHIFT 4 + +/* RCC_R59CIDCFGR register fields */ +#define RCC_R59CIDCFGR_CFEN BIT(0) +#define RCC_R59CIDCFGR_SEM_EN BIT(1) +#define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R59CIDCFGR_SCID_SHIFT 4 +#define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R59CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R59SEMCR register fields */ +#define RCC_R59SEMCR_SEM_MUTEX BIT(0) +#define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R59SEMCR_SEMCID_SHIFT 4 + +/* RCC_R60CIDCFGR register fields */ +#define RCC_R60CIDCFGR_CFEN BIT(0) +#define RCC_R60CIDCFGR_SEM_EN BIT(1) +#define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R60CIDCFGR_SCID_SHIFT 4 +#define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R60CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R60SEMCR register fields */ +#define RCC_R60SEMCR_SEM_MUTEX BIT(0) +#define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R60SEMCR_SEMCID_SHIFT 4 + +/* RCC_R61CIDCFGR register fields */ +#define RCC_R61CIDCFGR_CFEN BIT(0) +#define RCC_R61CIDCFGR_SEM_EN BIT(1) +#define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R61CIDCFGR_SCID_SHIFT 4 +#define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R61CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R61SEMCR register fields */ +#define RCC_R61SEMCR_SEM_MUTEX BIT(0) +#define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R61SEMCR_SEMCID_SHIFT 4 + +/* RCC_R62CIDCFGR register fields */ +#define RCC_R62CIDCFGR_CFEN BIT(0) +#define RCC_R62CIDCFGR_SEM_EN BIT(1) +#define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R62CIDCFGR_SCID_SHIFT 4 +#define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R62CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R62SEMCR register fields */ +#define RCC_R62SEMCR_SEM_MUTEX BIT(0) +#define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R62SEMCR_SEMCID_SHIFT 4 + +/* RCC_R63CIDCFGR register fields */ +#define RCC_R63CIDCFGR_CFEN BIT(0) +#define RCC_R63CIDCFGR_SEM_EN BIT(1) +#define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R63CIDCFGR_SCID_SHIFT 4 +#define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R63CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R63SEMCR register fields */ +#define RCC_R63SEMCR_SEM_MUTEX BIT(0) +#define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R63SEMCR_SEMCID_SHIFT 4 + +/* RCC_R64CIDCFGR register fields */ +#define RCC_R64CIDCFGR_CFEN BIT(0) +#define RCC_R64CIDCFGR_SEM_EN BIT(1) +#define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R64CIDCFGR_SCID_SHIFT 4 +#define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R64CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R64SEMCR register fields */ +#define RCC_R64SEMCR_SEM_MUTEX BIT(0) +#define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R64SEMCR_SEMCID_SHIFT 4 + +/* RCC_R65CIDCFGR register fields */ +#define RCC_R65CIDCFGR_CFEN BIT(0) +#define RCC_R65CIDCFGR_SEM_EN BIT(1) +#define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R65CIDCFGR_SCID_SHIFT 4 +#define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R65CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R65SEMCR register fields */ +#define RCC_R65SEMCR_SEM_MUTEX BIT(0) +#define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R65SEMCR_SEMCID_SHIFT 4 + +/* RCC_R66CIDCFGR register fields */ +#define RCC_R66CIDCFGR_CFEN BIT(0) +#define RCC_R66CIDCFGR_SEM_EN BIT(1) +#define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R66CIDCFGR_SCID_SHIFT 4 +#define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R66CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R66SEMCR register fields */ +#define RCC_R66SEMCR_SEM_MUTEX BIT(0) +#define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R66SEMCR_SEMCID_SHIFT 4 + +/* RCC_R67CIDCFGR register fields */ +#define RCC_R67CIDCFGR_CFEN BIT(0) +#define RCC_R67CIDCFGR_SEM_EN BIT(1) +#define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R67CIDCFGR_SCID_SHIFT 4 +#define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R67CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R67SEMCR register fields */ +#define RCC_R67SEMCR_SEM_MUTEX BIT(0) +#define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R67SEMCR_SEMCID_SHIFT 4 + +/* RCC_R68CIDCFGR register fields */ +#define RCC_R68CIDCFGR_CFEN BIT(0) +#define RCC_R68CIDCFGR_SEM_EN BIT(1) +#define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R68CIDCFGR_SCID_SHIFT 4 +#define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R68CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R68SEMCR register fields */ +#define RCC_R68SEMCR_SEM_MUTEX BIT(0) +#define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R68SEMCR_SEMCID_SHIFT 4 + +/* RCC_R69CIDCFGR register fields */ +#define RCC_R69CIDCFGR_CFEN BIT(0) +#define RCC_R69CIDCFGR_SEM_EN BIT(1) +#define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R69CIDCFGR_SCID_SHIFT 4 +#define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R69CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R69SEMCR register fields */ +#define RCC_R69SEMCR_SEM_MUTEX BIT(0) +#define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R69SEMCR_SEMCID_SHIFT 4 + +/* RCC_R70CIDCFGR register fields */ +#define RCC_R70CIDCFGR_CFEN BIT(0) +#define RCC_R70CIDCFGR_SEM_EN BIT(1) +#define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R70CIDCFGR_SCID_SHIFT 4 +#define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R70CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R70SEMCR register fields */ +#define RCC_R70SEMCR_SEM_MUTEX BIT(0) +#define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R70SEMCR_SEMCID_SHIFT 4 + +/* RCC_R71CIDCFGR register fields */ +#define RCC_R71CIDCFGR_CFEN BIT(0) +#define RCC_R71CIDCFGR_SEM_EN BIT(1) +#define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R71CIDCFGR_SCID_SHIFT 4 +#define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R71CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R71SEMCR register fields */ +#define RCC_R71SEMCR_SEM_MUTEX BIT(0) +#define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R71SEMCR_SEMCID_SHIFT 4 + +/* RCC_R72CIDCFGR register fields */ +#define RCC_R72CIDCFGR_CFEN BIT(0) +#define RCC_R72CIDCFGR_SEM_EN BIT(1) +#define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R72CIDCFGR_SCID_SHIFT 4 +#define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R72CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R72SEMCR register fields */ +#define RCC_R72SEMCR_SEM_MUTEX BIT(0) +#define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R72SEMCR_SEMCID_SHIFT 4 + +/* RCC_R73CIDCFGR register fields */ +#define RCC_R73CIDCFGR_CFEN BIT(0) +#define RCC_R73CIDCFGR_SEM_EN BIT(1) +#define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R73CIDCFGR_SCID_SHIFT 4 +#define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R73CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R73SEMCR register fields */ +#define RCC_R73SEMCR_SEM_MUTEX BIT(0) +#define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R73SEMCR_SEMCID_SHIFT 4 + +/* RCC_R74CIDCFGR register fields */ +#define RCC_R74CIDCFGR_CFEN BIT(0) +#define RCC_R74CIDCFGR_SEM_EN BIT(1) +#define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R74CIDCFGR_SCID_SHIFT 4 +#define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R74CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R74SEMCR register fields */ +#define RCC_R74SEMCR_SEM_MUTEX BIT(0) +#define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R74SEMCR_SEMCID_SHIFT 4 + +/* RCC_R75CIDCFGR register fields */ +#define RCC_R75CIDCFGR_CFEN BIT(0) +#define RCC_R75CIDCFGR_SEM_EN BIT(1) +#define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R75CIDCFGR_SCID_SHIFT 4 +#define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R75CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R75SEMCR register fields */ +#define RCC_R75SEMCR_SEM_MUTEX BIT(0) +#define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R75SEMCR_SEMCID_SHIFT 4 + +/* RCC_R76CIDCFGR register fields */ +#define RCC_R76CIDCFGR_CFEN BIT(0) +#define RCC_R76CIDCFGR_SEM_EN BIT(1) +#define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R76CIDCFGR_SCID_SHIFT 4 +#define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R76CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R76SEMCR register fields */ +#define RCC_R76SEMCR_SEM_MUTEX BIT(0) +#define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R76SEMCR_SEMCID_SHIFT 4 + +/* RCC_R77CIDCFGR register fields */ +#define RCC_R77CIDCFGR_CFEN BIT(0) +#define RCC_R77CIDCFGR_SEM_EN BIT(1) +#define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R77CIDCFGR_SCID_SHIFT 4 +#define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R77CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R77SEMCR register fields */ +#define RCC_R77SEMCR_SEM_MUTEX BIT(0) +#define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R77SEMCR_SEMCID_SHIFT 4 + +/* RCC_R78CIDCFGR register fields */ +#define RCC_R78CIDCFGR_CFEN BIT(0) +#define RCC_R78CIDCFGR_SEM_EN BIT(1) +#define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R78CIDCFGR_SCID_SHIFT 4 +#define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R78CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R78SEMCR register fields */ +#define RCC_R78SEMCR_SEM_MUTEX BIT(0) +#define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R78SEMCR_SEMCID_SHIFT 4 + +/* RCC_R79CIDCFGR register fields */ +#define RCC_R79CIDCFGR_CFEN BIT(0) +#define RCC_R79CIDCFGR_SEM_EN BIT(1) +#define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R79CIDCFGR_SCID_SHIFT 4 +#define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R79CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R79SEMCR register fields */ +#define RCC_R79SEMCR_SEM_MUTEX BIT(0) +#define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R79SEMCR_SEMCID_SHIFT 4 + +/* RCC_R80CIDCFGR register fields */ +#define RCC_R80CIDCFGR_CFEN BIT(0) +#define RCC_R80CIDCFGR_SEM_EN BIT(1) +#define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R80CIDCFGR_SCID_SHIFT 4 +#define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R80CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R80SEMCR register fields */ +#define RCC_R80SEMCR_SEM_MUTEX BIT(0) +#define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R80SEMCR_SEMCID_SHIFT 4 + +/* RCC_R81CIDCFGR register fields */ +#define RCC_R81CIDCFGR_CFEN BIT(0) +#define RCC_R81CIDCFGR_SEM_EN BIT(1) +#define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R81CIDCFGR_SCID_SHIFT 4 +#define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R81CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R81SEMCR register fields */ +#define RCC_R81SEMCR_SEM_MUTEX BIT(0) +#define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R81SEMCR_SEMCID_SHIFT 4 + +/* RCC_R82CIDCFGR register fields */ +#define RCC_R82CIDCFGR_CFEN BIT(0) +#define RCC_R82CIDCFGR_SEM_EN BIT(1) +#define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R82CIDCFGR_SCID_SHIFT 4 +#define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R82CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R82SEMCR register fields */ +#define RCC_R82SEMCR_SEM_MUTEX BIT(0) +#define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R82SEMCR_SEMCID_SHIFT 4 + +/* RCC_R83CIDCFGR register fields */ +#define RCC_R83CIDCFGR_CFEN BIT(0) +#define RCC_R83CIDCFGR_SEM_EN BIT(1) +#define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R83CIDCFGR_SCID_SHIFT 4 +#define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R83CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R83SEMCR register fields */ +#define RCC_R83SEMCR_SEM_MUTEX BIT(0) +#define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R83SEMCR_SEMCID_SHIFT 4 + +/* RCC_R84CIDCFGR register fields */ +#define RCC_R84CIDCFGR_CFEN BIT(0) +#define RCC_R84CIDCFGR_SEM_EN BIT(1) +#define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R84CIDCFGR_SCID_SHIFT 4 +#define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R84CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R84SEMCR register fields */ +#define RCC_R84SEMCR_SEM_MUTEX BIT(0) +#define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R84SEMCR_SEMCID_SHIFT 4 + +/* RCC_R85CIDCFGR register fields */ +#define RCC_R85CIDCFGR_CFEN BIT(0) +#define RCC_R85CIDCFGR_SEM_EN BIT(1) +#define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R85CIDCFGR_SCID_SHIFT 4 +#define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R85CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R85SEMCR register fields */ +#define RCC_R85SEMCR_SEM_MUTEX BIT(0) +#define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R85SEMCR_SEMCID_SHIFT 4 + +/* RCC_R86CIDCFGR register fields */ +#define RCC_R86CIDCFGR_CFEN BIT(0) +#define RCC_R86CIDCFGR_SEM_EN BIT(1) +#define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R86CIDCFGR_SCID_SHIFT 4 +#define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R86CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R86SEMCR register fields */ +#define RCC_R86SEMCR_SEM_MUTEX BIT(0) +#define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R86SEMCR_SEMCID_SHIFT 4 + +/* RCC_R87CIDCFGR register fields */ +#define RCC_R87CIDCFGR_CFEN BIT(0) +#define RCC_R87CIDCFGR_SEM_EN BIT(1) +#define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R87CIDCFGR_SCID_SHIFT 4 +#define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R87CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R87SEMCR register fields */ +#define RCC_R87SEMCR_SEM_MUTEX BIT(0) +#define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R87SEMCR_SEMCID_SHIFT 4 + +/* RCC_R88CIDCFGR register fields */ +#define RCC_R88CIDCFGR_CFEN BIT(0) +#define RCC_R88CIDCFGR_SEM_EN BIT(1) +#define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R88CIDCFGR_SCID_SHIFT 4 +#define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R88CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R88SEMCR register fields */ +#define RCC_R88SEMCR_SEM_MUTEX BIT(0) +#define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R88SEMCR_SEMCID_SHIFT 4 + +/* RCC_R89CIDCFGR register fields */ +#define RCC_R89CIDCFGR_CFEN BIT(0) +#define RCC_R89CIDCFGR_SEM_EN BIT(1) +#define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R89CIDCFGR_SCID_SHIFT 4 +#define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R89CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R89SEMCR register fields */ +#define RCC_R89SEMCR_SEM_MUTEX BIT(0) +#define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R89SEMCR_SEMCID_SHIFT 4 + +/* RCC_R90CIDCFGR register fields */ +#define RCC_R90CIDCFGR_CFEN BIT(0) +#define RCC_R90CIDCFGR_SEM_EN BIT(1) +#define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R90CIDCFGR_SCID_SHIFT 4 +#define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R90CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R90SEMCR register fields */ +#define RCC_R90SEMCR_SEM_MUTEX BIT(0) +#define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R90SEMCR_SEMCID_SHIFT 4 + +/* RCC_R91CIDCFGR register fields */ +#define RCC_R91CIDCFGR_CFEN BIT(0) +#define RCC_R91CIDCFGR_SEM_EN BIT(1) +#define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R91CIDCFGR_SCID_SHIFT 4 +#define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R91CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R91SEMCR register fields */ +#define RCC_R91SEMCR_SEM_MUTEX BIT(0) +#define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R91SEMCR_SEMCID_SHIFT 4 + +/* RCC_R92CIDCFGR register fields */ +#define RCC_R92CIDCFGR_CFEN BIT(0) +#define RCC_R92CIDCFGR_SEM_EN BIT(1) +#define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R92CIDCFGR_SCID_SHIFT 4 +#define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R92CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R92SEMCR register fields */ +#define RCC_R92SEMCR_SEM_MUTEX BIT(0) +#define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R92SEMCR_SEMCID_SHIFT 4 + +/* RCC_R93CIDCFGR register fields */ +#define RCC_R93CIDCFGR_CFEN BIT(0) +#define RCC_R93CIDCFGR_SEM_EN BIT(1) +#define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R93CIDCFGR_SCID_SHIFT 4 +#define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R93CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R93SEMCR register fields */ +#define RCC_R93SEMCR_SEM_MUTEX BIT(0) +#define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R93SEMCR_SEMCID_SHIFT 4 + +/* RCC_R94CIDCFGR register fields */ +#define RCC_R94CIDCFGR_CFEN BIT(0) +#define RCC_R94CIDCFGR_SEM_EN BIT(1) +#define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R94CIDCFGR_SCID_SHIFT 4 +#define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R94CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R94SEMCR register fields */ +#define RCC_R94SEMCR_SEM_MUTEX BIT(0) +#define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R94SEMCR_SEMCID_SHIFT 4 + +/* RCC_R95CIDCFGR register fields */ +#define RCC_R95CIDCFGR_CFEN BIT(0) +#define RCC_R95CIDCFGR_SEM_EN BIT(1) +#define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R95CIDCFGR_SCID_SHIFT 4 +#define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R95CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R95SEMCR register fields */ +#define RCC_R95SEMCR_SEM_MUTEX BIT(0) +#define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R95SEMCR_SEMCID_SHIFT 4 + +/* RCC_R96CIDCFGR register fields */ +#define RCC_R96CIDCFGR_CFEN BIT(0) +#define RCC_R96CIDCFGR_SEM_EN BIT(1) +#define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R96CIDCFGR_SCID_SHIFT 4 +#define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R96CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R96SEMCR register fields */ +#define RCC_R96SEMCR_SEM_MUTEX BIT(0) +#define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R96SEMCR_SEMCID_SHIFT 4 + +/* RCC_R97CIDCFGR register fields */ +#define RCC_R97CIDCFGR_CFEN BIT(0) +#define RCC_R97CIDCFGR_SEM_EN BIT(1) +#define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R97CIDCFGR_SCID_SHIFT 4 +#define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R97CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R97SEMCR register fields */ +#define RCC_R97SEMCR_SEM_MUTEX BIT(0) +#define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R97SEMCR_SEMCID_SHIFT 4 + +/* RCC_R98CIDCFGR register fields */ +#define RCC_R98CIDCFGR_CFEN BIT(0) +#define RCC_R98CIDCFGR_SEM_EN BIT(1) +#define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R98CIDCFGR_SCID_SHIFT 4 +#define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R98CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R98SEMCR register fields */ +#define RCC_R98SEMCR_SEM_MUTEX BIT(0) +#define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R98SEMCR_SEMCID_SHIFT 4 + +/* RCC_R99CIDCFGR register fields */ +#define RCC_R99CIDCFGR_CFEN BIT(0) +#define RCC_R99CIDCFGR_SEM_EN BIT(1) +#define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R99CIDCFGR_SCID_SHIFT 4 +#define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R99CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R99SEMCR register fields */ +#define RCC_R99SEMCR_SEM_MUTEX BIT(0) +#define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R99SEMCR_SEMCID_SHIFT 4 + +/* RCC_R100CIDCFGR register fields */ +#define RCC_R100CIDCFGR_CFEN BIT(0) +#define RCC_R100CIDCFGR_SEM_EN BIT(1) +#define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R100CIDCFGR_SCID_SHIFT 4 +#define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R100CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R100SEMCR register fields */ +#define RCC_R100SEMCR_SEM_MUTEX BIT(0) +#define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R100SEMCR_SEMCID_SHIFT 4 + +/* RCC_R101CIDCFGR register fields */ +#define RCC_R101CIDCFGR_CFEN BIT(0) +#define RCC_R101CIDCFGR_SEM_EN BIT(1) +#define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R101CIDCFGR_SCID_SHIFT 4 +#define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R101CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R101SEMCR register fields */ +#define RCC_R101SEMCR_SEM_MUTEX BIT(0) +#define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R101SEMCR_SEMCID_SHIFT 4 + +/* RCC_R102CIDCFGR register fields */ +#define RCC_R102CIDCFGR_CFEN BIT(0) +#define RCC_R102CIDCFGR_SEM_EN BIT(1) +#define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R102CIDCFGR_SCID_SHIFT 4 +#define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R102CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R102SEMCR register fields */ +#define RCC_R102SEMCR_SEM_MUTEX BIT(0) +#define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R102SEMCR_SEMCID_SHIFT 4 + +/* RCC_R103CIDCFGR register fields */ +#define RCC_R103CIDCFGR_CFEN BIT(0) +#define RCC_R103CIDCFGR_SEM_EN BIT(1) +#define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R103CIDCFGR_SCID_SHIFT 4 +#define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R103CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R103SEMCR register fields */ +#define RCC_R103SEMCR_SEM_MUTEX BIT(0) +#define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R103SEMCR_SEMCID_SHIFT 4 + +/* RCC_R104CIDCFGR register fields */ +#define RCC_R104CIDCFGR_CFEN BIT(0) +#define RCC_R104CIDCFGR_SEM_EN BIT(1) +#define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R104CIDCFGR_SCID_SHIFT 4 +#define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R104CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R104SEMCR register fields */ +#define RCC_R104SEMCR_SEM_MUTEX BIT(0) +#define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R104SEMCR_SEMCID_SHIFT 4 + +/* RCC_R105CIDCFGR register fields */ +#define RCC_R105CIDCFGR_CFEN BIT(0) +#define RCC_R105CIDCFGR_SEM_EN BIT(1) +#define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R105CIDCFGR_SCID_SHIFT 4 +#define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R105CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R105SEMCR register fields */ +#define RCC_R105SEMCR_SEM_MUTEX BIT(0) +#define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R105SEMCR_SEMCID_SHIFT 4 + +/* RCC_R106CIDCFGR register fields */ +#define RCC_R106CIDCFGR_CFEN BIT(0) +#define RCC_R106CIDCFGR_SEM_EN BIT(1) +#define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R106CIDCFGR_SCID_SHIFT 4 +#define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R106CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R106SEMCR register fields */ +#define RCC_R106SEMCR_SEM_MUTEX BIT(0) +#define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R106SEMCR_SEMCID_SHIFT 4 + +/* RCC_R107CIDCFGR register fields */ +#define RCC_R107CIDCFGR_CFEN BIT(0) +#define RCC_R107CIDCFGR_SEM_EN BIT(1) +#define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R107CIDCFGR_SCID_SHIFT 4 +#define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R107CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R107SEMCR register fields */ +#define RCC_R107SEMCR_SEM_MUTEX BIT(0) +#define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R107SEMCR_SEMCID_SHIFT 4 + +/* RCC_R108CIDCFGR register fields */ +#define RCC_R108CIDCFGR_CFEN BIT(0) +#define RCC_R108CIDCFGR_SEM_EN BIT(1) +#define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R108CIDCFGR_SCID_SHIFT 4 +#define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R108CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R108SEMCR register fields */ +#define RCC_R108SEMCR_SEM_MUTEX BIT(0) +#define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R108SEMCR_SEMCID_SHIFT 4 + +/* RCC_R109CIDCFGR register fields */ +#define RCC_R109CIDCFGR_CFEN BIT(0) +#define RCC_R109CIDCFGR_SEM_EN BIT(1) +#define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R109CIDCFGR_SCID_SHIFT 4 +#define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R109CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R109SEMCR register fields */ +#define RCC_R109SEMCR_SEM_MUTEX BIT(0) +#define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R109SEMCR_SEMCID_SHIFT 4 + +/* RCC_R110CIDCFGR register fields */ +#define RCC_R110CIDCFGR_CFEN BIT(0) +#define RCC_R110CIDCFGR_SEM_EN BIT(1) +#define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R110CIDCFGR_SCID_SHIFT 4 +#define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R110CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R110SEMCR register fields */ +#define RCC_R110SEMCR_SEM_MUTEX BIT(0) +#define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R110SEMCR_SEMCID_SHIFT 4 + +/* RCC_R111CIDCFGR register fields */ +#define RCC_R111CIDCFGR_CFEN BIT(0) +#define RCC_R111CIDCFGR_SEM_EN BIT(1) +#define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R111CIDCFGR_SCID_SHIFT 4 +#define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R111CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R111SEMCR register fields */ +#define RCC_R111SEMCR_SEM_MUTEX BIT(0) +#define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R111SEMCR_SEMCID_SHIFT 4 + +/* RCC_R112CIDCFGR register fields */ +#define RCC_R112CIDCFGR_CFEN BIT(0) +#define RCC_R112CIDCFGR_SEM_EN BIT(1) +#define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R112CIDCFGR_SCID_SHIFT 4 +#define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R112CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R112SEMCR register fields */ +#define RCC_R112SEMCR_SEM_MUTEX BIT(0) +#define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R112SEMCR_SEMCID_SHIFT 4 + +/* RCC_R113CIDCFGR register fields */ +#define RCC_R113CIDCFGR_CFEN BIT(0) +#define RCC_R113CIDCFGR_SEM_EN BIT(1) +#define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_R113CIDCFGR_SCID_SHIFT 4 +#define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_R113CIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_R113SEMCR register fields */ +#define RCC_R113SEMCR_SEM_MUTEX BIT(0) +#define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_R113SEMCR_SEMCID_SHIFT 4 + +/* RCC_RxCIDCFGR register fields */ +#define RCC_RxCIDCFGR_CFEN BIT(0) +#define RCC_RxCIDCFGR_SEM_EN BIT(1) +#define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4) +#define RCC_RxCIDCFGR_SCID_SHIFT 4 +#define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) +#define RCC_RxCIDCFGR_SEMWLC_SHIFT 16 + +/* RCC_RxSEMCR register fields */ +#define RCC_RxSEMCR_SEM_MUTEX BIT(0) +#define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4) +#define RCC_RxSEMCR_SEMCID_SHIFT 4 + +/* RCC_GRSTCSETR register fields */ +#define RCC_GRSTCSETR_SYSRST BIT(0) + +/* RCC_C1RSTCSETR register fields */ +#define RCC_C1RSTCSETR_C1RST BIT(0) + +/* RCC_C1P1RSTCSETR register fields */ +#define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0) +#define RCC_C1P1RSTCSETR_C1P1RST BIT(1) + +/* RCC_C2RSTCSETR register fields */ +#define RCC_C2RSTCSETR_C2RST BIT(0) + +/* RCC_CxRSTCSETR register fields */ +#define RCC_CxRSTCSETR_CxRST BIT(0) + +/* RCC_HWRSTSCLRR register fields */ +#define RCC_HWRSTSCLRR_PORRSTF BIT(0) +#define RCC_HWRSTSCLRR_BORRSTF BIT(1) +#define RCC_HWRSTSCLRR_PADRSTF BIT(2) +#define RCC_HWRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_HWRSTSCLRR_VCORERSTF BIT(4) +#define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5) +#define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6) +#define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7) +#define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8) +#define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9) +#define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10) +#define RCC_HWRSTSCLRR_IWDG5SYSRSTF BIT(11) +#define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12) +#define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13) +#define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14) + +/* RCC_C1HWRSTSCLRR register fields */ +#define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0) +#define RCC_C1HWRSTSCLRR_C1RSTF BIT(1) +#define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2) + +/* RCC_C2HWRSTSCLRR register fields */ +#define RCC_C2HWRSTSCLRR_C2RSTF BIT(0) + +/* RCC_C1BOOTRSTSSETR register fields */ +#define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0) +#define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1) +#define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2) +#define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3) +#define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4) +#define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5) +#define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6) +#define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7) +#define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) +#define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) +#define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) +#define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) +#define RCC_C1BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) +#define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13) +#define RCC_C1BOOTRSTSSETR_C1P1RSTF BIT(16) +#define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17) +#define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20) +#define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22) +#define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23) + +/* RCC_C1BOOTRSTSCLRR register fields */ +#define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0) +#define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1) +#define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2) +#define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4) +#define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5) +#define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6) +#define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7) +#define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) +#define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) +#define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) +#define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) +#define RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) +#define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13) +#define RCC_C1BOOTRSTSCLRR_C1P1RSTF BIT(16) +#define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) +#define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20) +#define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22) +#define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23) + +/* RCC_C2BOOTRSTSSETR register fields */ +#define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0) +#define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1) +#define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2) +#define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3) +#define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4) +#define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6) +#define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7) +#define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) +#define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) +#define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) +#define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) +#define RCC_C2BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) +#define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14) +#define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17) +#define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21) +#define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23) + +/* RCC_C2BOOTRSTSCLRR register fields */ +#define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0) +#define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1) +#define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2) +#define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3) +#define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4) +#define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6) +#define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7) +#define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) +#define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) +#define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) +#define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) +#define RCC_C2BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) +#define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14) +#define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) +#define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) +#define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) +#define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21) +#define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23) + +/* RCC_C1SREQSETR register fields */ +#define RCC_C1SREQSETR_STPREQ_P0 BIT(0) +#define RCC_C1SREQSETR_STPREQ_P1 BIT(1) +#define RCC_C1SREQSETR_ESLPREQ BIT(16) + +/* RCC_C1SREQCLRR register fields */ +#define RCC_C1SREQCLRR_STPREQ_P0 BIT(0) +#define RCC_C1SREQCLRR_STPREQ_P1 BIT(1) +#define RCC_C1SREQCLRR_ESLPREQ BIT(16) + +/* RCC_CPUBOOTCR register fields */ +#define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0) +#define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1) + +/* RCC_STBYBOOTCR register fields */ +#define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1) +#define RCC_STBYBOOTCR_COLD_CPU2 BIT(2) +#define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4) +#define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5) +#define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8) + +/* RCC_LEGBOOTCR register fields */ +#define RCC_LEGBOOTCR_LEGACY_BEN BIT(0) + +/* RCC_BDCR register fields */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_LSEDIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(6) +#define RCC_BDCR_LSEGFON BIT(7) +#define RCC_BDCR_LSECSSD BIT(8) +#define RCC_BDCR_LSION BIT(9) +#define RCC_BDCR_LSIRDY BIT(10) +#define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_MSIFREQSEL BIT(24) +#define RCC_BDCR_C3SYSTICKSEL BIT(25) +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_LSEBYP_BIT 1 +#define RCC_BDCR_LSEDIGBYP_BIT 3 +#define RCC_BDCR_LSECSSON_BIT 6 +#define RCC_BDCR_LSERDY_BIT 2 +#define RCC_BDCR_LSIRDY_BIT 10 + +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSEDRV_WIDTH 2 + +/* RCC_D3DCR register fields */ +#define RCC_D3DCR_CSION BIT(0) +#define RCC_D3DCR_CSIKERON BIT(1) +#define RCC_D3DCR_CSIRDY BIT(2) +#define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16) +#define RCC_D3DCR_D3PERCKSEL_SHIFT 16 +#define RCC_D3DCR_CSIRDY_BIT 2 + +/* RCC_D3DSR register fields */ +#define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0) +#define RCC_D3DSR_D3STATE_SHIFT 0 + +/* RCC_RDCR register fields */ +#define RCC_RDCR_MRD_MASK GENMASK_32(20, 16) +#define RCC_RDCR_MRD_SHIFT 16 +#define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24) +#define RCC_RDCR_EADLY_SHIFT 24 + +/* RCC_C1MSRDCR register fields */ +#define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0) +#define RCC_C1MSRDCR_C1MSRD_SHIFT 0 +#define RCC_C1MSRDCR_C1MSRST BIT(8) + +/* RCC_PWRLPDLYCR register fields */ +#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0) +#define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 +#define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24) + +/* RCC_C1CIESETR register fields */ +#define RCC_C1CIESETR_LSIRDYIE BIT(0) +#define RCC_C1CIESETR_LSERDYIE BIT(1) +#define RCC_C1CIESETR_HSIRDYIE BIT(2) +#define RCC_C1CIESETR_HSERDYIE BIT(3) +#define RCC_C1CIESETR_CSIRDYIE BIT(4) +#define RCC_C1CIESETR_PLL1RDYIE BIT(5) +#define RCC_C1CIESETR_PLL2RDYIE BIT(6) +#define RCC_C1CIESETR_PLL3RDYIE BIT(7) +#define RCC_C1CIESETR_PLL4RDYIE BIT(8) +#define RCC_C1CIESETR_PLL5RDYIE BIT(9) +#define RCC_C1CIESETR_PLL6RDYIE BIT(10) +#define RCC_C1CIESETR_PLL7RDYIE BIT(11) +#define RCC_C1CIESETR_PLL8RDYIE BIT(12) +#define RCC_C1CIESETR_LSECSSIE BIT(16) +#define RCC_C1CIESETR_WKUPIE BIT(20) + +/* RCC_C1CIFCLRR register fields */ +#define RCC_C1CIFCLRR_LSIRDYF BIT(0) +#define RCC_C1CIFCLRR_LSERDYF BIT(1) +#define RCC_C1CIFCLRR_HSIRDYF BIT(2) +#define RCC_C1CIFCLRR_HSERDYF BIT(3) +#define RCC_C1CIFCLRR_CSIRDYF BIT(4) +#define RCC_C1CIFCLRR_PLL1RDYF BIT(5) +#define RCC_C1CIFCLRR_PLL2RDYF BIT(6) +#define RCC_C1CIFCLRR_PLL3RDYF BIT(7) +#define RCC_C1CIFCLRR_PLL4RDYF BIT(8) +#define RCC_C1CIFCLRR_PLL5RDYF BIT(9) +#define RCC_C1CIFCLRR_PLL6RDYF BIT(10) +#define RCC_C1CIFCLRR_PLL7RDYF BIT(11) +#define RCC_C1CIFCLRR_PLL8RDYF BIT(12) +#define RCC_C1CIFCLRR_LSECSSF BIT(16) +#define RCC_C1CIFCLRR_WKUPF BIT(20) + +/* RCC_C2CIESETR register fields */ +#define RCC_C2CIESETR_LSIRDYIE BIT(0) +#define RCC_C2CIESETR_LSERDYIE BIT(1) +#define RCC_C2CIESETR_HSIRDYIE BIT(2) +#define RCC_C2CIESETR_HSERDYIE BIT(3) +#define RCC_C2CIESETR_CSIRDYIE BIT(4) +#define RCC_C2CIESETR_PLL1RDYIE BIT(5) +#define RCC_C2CIESETR_PLL2RDYIE BIT(6) +#define RCC_C2CIESETR_PLL3RDYIE BIT(7) +#define RCC_C2CIESETR_PLL4RDYIE BIT(8) +#define RCC_C2CIESETR_PLL5RDYIE BIT(9) +#define RCC_C2CIESETR_PLL6RDYIE BIT(10) +#define RCC_C2CIESETR_PLL7RDYIE BIT(11) +#define RCC_C2CIESETR_PLL8RDYIE BIT(12) +#define RCC_C2CIESETR_LSECSSIE BIT(16) +#define RCC_C2CIESETR_WKUPIE BIT(20) + +/* RCC_C2CIFCLRR register fields */ +#define RCC_C2CIFCLRR_LSIRDYF BIT(0) +#define RCC_C2CIFCLRR_LSERDYF BIT(1) +#define RCC_C2CIFCLRR_HSIRDYF BIT(2) +#define RCC_C2CIFCLRR_HSERDYF BIT(3) +#define RCC_C2CIFCLRR_CSIRDYF BIT(4) +#define RCC_C2CIFCLRR_PLL1RDYF BIT(5) +#define RCC_C2CIFCLRR_PLL2RDYF BIT(6) +#define RCC_C2CIFCLRR_PLL3RDYF BIT(7) +#define RCC_C2CIFCLRR_PLL4RDYF BIT(8) +#define RCC_C2CIFCLRR_PLL5RDYF BIT(9) +#define RCC_C2CIFCLRR_PLL6RDYF BIT(10) +#define RCC_C2CIFCLRR_PLL7RDYF BIT(11) +#define RCC_C2CIFCLRR_PLL8RDYF BIT(12) +#define RCC_C2CIFCLRR_LSECSSF BIT(16) +#define RCC_C2CIFCLRR_WKUPF BIT(20) + +/* RCC_CxCIESETR register fields */ +#define RCC_CxCIESETR_LSIRDYIE BIT(0) +#define RCC_CxCIESETR_LSERDYIE BIT(1) +#define RCC_CxCIESETR_HSIRDYIE BIT(2) +#define RCC_CxCIESETR_HSERDYIE BIT(3) +#define RCC_CxCIESETR_CSIRDYIE BIT(4) +#define RCC_CxCIESETR_SHSIRDYIE BIT(5) +#define RCC_CxCIESETR_PLL1RDYIE BIT(6) +#define RCC_CxCIESETR_PLL2RDYIE BIT(7) +#define RCC_CxCIESETR_PLL3RDYIE BIT(8) +#define RCC_CxCIESETR_PLL4RDYIE BIT(9) +#define RCC_CxCIESETR_PLL5RDYIE BIT(10) +#define RCC_CxCIESETR_PLL6RDYIE BIT(11) +#define RCC_CxCIESETR_PLL7RDYIE BIT(12) +#define RCC_CxCIESETR_PLL8RDYIE BIT(13) +#define RCC_CxCIESETR_LSECSSIE BIT(16) +#define RCC_CxCIESETR_WKUPIE BIT(20) + +/* RCC_CxCIFCLRR register fields */ +#define RCC_CxCIFCLRR_LSIRDYF BIT(0) +#define RCC_CxCIFCLRR_LSERDYF BIT(1) +#define RCC_CxCIFCLRR_HSIRDYF BIT(2) +#define RCC_CxCIFCLRR_HSERDYF BIT(3) +#define RCC_CxCIFCLRR_CSIRDYF BIT(4) +#define RCC_CxCIFCLRR_SHSIRDYF BIT(5) +#define RCC_CxCIFCLRR_PLL1RDYF BIT(6) +#define RCC_CxCIFCLRR_PLL2RDYF BIT(7) +#define RCC_CxCIFCLRR_PLL3RDYF BIT(8) +#define RCC_CxCIFCLRR_PLL4RDYF BIT(9) +#define RCC_CxCIFCLRR_PLL5RDYF BIT(10) +#define RCC_CxCIFCLRR_PLL6RDYF BIT(11) +#define RCC_CxCIFCLRR_PLL7RDYF BIT(12) +#define RCC_CxCIFCLRR_PLL8RDYF BIT(13) +#define RCC_CxCIFCLRR_LSECSSF BIT(16) +#define RCC_CxCIFCLRR_WKUPF BIT(20) + +/* RCC_IWDGC1FZSETR register fields */ +#define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0) +#define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1) + +/* RCC_IWDGC1FZCLRR register fields */ +#define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0) +#define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1) + +/* RCC_IWDGC1CFGSETR register fields */ +#define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0) +#define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2) +#define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18) + +/* RCC_IWDGC1CFGCLRR register fields */ +#define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0) +#define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2) +#define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18) + +/* RCC_IWDGC2FZSETR register fields */ +#define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0) +#define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1) + +/* RCC_IWDGC2FZCLRR register fields */ +#define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0) +#define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1) + +/* RCC_IWDGC2CFGSETR register fields */ +#define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0) +#define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2) +#define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18) + +/* RCC_IWDGC2CFGCLRR register fields */ +#define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0) +#define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2) +#define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18) + +/* RCC_IWDGC3CFGSETR register fields */ +#define RCC_IWDGC3CFGSETR_IWDG5_SYSRSTEN BIT(0) + +/* RCC_IWDGC3CFGCLRR register fields */ +#define RCC_IWDGC3CFGCLRR_IWDG5_SYSRSTEN BIT(0) + +/* RCC_C3CFGR register fields */ +#define RCC_C3CFGR_C3RST BIT(0) +#define RCC_C3CFGR_C3EN BIT(1) +#define RCC_C3CFGR_C3LPEN BIT(2) +#define RCC_C3CFGR_C3AMEN BIT(3) +#define RCC_C3CFGR_LPTIM3C3EN BIT(16) +#define RCC_C3CFGR_LPTIM4C3EN BIT(17) +#define RCC_C3CFGR_LPTIM5C3EN BIT(18) +#define RCC_C3CFGR_SPI8C3EN BIT(19) +#define RCC_C3CFGR_LPUART1C3EN BIT(20) +#define RCC_C3CFGR_I2C8C3EN BIT(21) +#define RCC_C3CFGR_ADF1C3EN BIT(23) +#define RCC_C3CFGR_GPIOZC3EN BIT(24) +#define RCC_C3CFGR_LPDMAC3EN BIT(25) +#define RCC_C3CFGR_RTCC3EN BIT(26) +#define RCC_C3CFGR_I3C4C3EN BIT(27) + +/* RCC_MCO1CFGR register fields */ +#define RCC_MCO1CFGR_MCO1SEL BIT(0) +#define RCC_MCO1CFGR_MCO1ON BIT(8) + +/* RCC_MCO2CFGR register fields */ +#define RCC_MCO2CFGR_MCO2SEL BIT(0) +#define RCC_MCO2CFGR_MCO2ON BIT(8) + +/* RCC_MCOxCFGR register fields */ +#define RCC_MCOxCFGR_MCOxSEL BIT(0) +#define RCC_MCOxCFGR_MCOxON BIT(8) + +/* RCC_OCENSETR register fields */ +#define RCC_OCENSETR_HSION BIT(0) +#define RCC_OCENSETR_HSIKERON BIT(1) +#define RCC_OCENSETR_HSEDIV2ON BIT(5) +#define RCC_OCENSETR_HSEDIV2BYP BIT(6) +#define RCC_OCENSETR_HSEDIGBYP BIT(7) +#define RCC_OCENSETR_HSEON BIT(8) +#define RCC_OCENSETR_HSEKERON BIT(9) +#define RCC_OCENSETR_HSEBYP BIT(10) +#define RCC_OCENSETR_HSECSSON BIT(11) + +/* RCC_OCENCLRR register fields */ +#define RCC_OCENCLRR_HSION BIT(0) +#define RCC_OCENCLRR_HSIKERON BIT(1) +#define RCC_OCENCLRR_HSEDIV2ON BIT(5) +#define RCC_OCENCLRR_HSEDIV2BYP BIT(6) +#define RCC_OCENCLRR_HSEDIGBYP BIT(7) +#define RCC_OCENCLRR_HSEON BIT(8) +#define RCC_OCENCLRR_HSEKERON BIT(9) +#define RCC_OCENCLRR_HSEBYP BIT(10) + +/* RCC_OCRDYR register fields */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSERDY BIT(8) +#define RCC_OCRDYR_CKREST BIT(25) + +#define RCC_OCRDYR_HSIRDY_BIT 0 +#define RCC_OCRDYR_HSERDY_BIT 8 + +/* RCC_HSICFGR register fields */ +#define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) +#define RCC_HSICFGR_HSITRIM_SHIFT 8 +#define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16) +#define RCC_HSICFGR_HSICAL_SHIFT 16 + +/* RCC_CSICFGR register fields */ +#define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8) +#define RCC_CSICFGR_CSITRIM_SHIFT 8 +#define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16) +#define RCC_CSICFGR_CSICAL_SHIFT 16 + +/* RCC_RTCDIVR register fields */ +#define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0) +#define RCC_RTCDIVR_RTCDIV_SHIFT 0 + +/* RCC_APB1DIVR register fields */ +#define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0) +#define RCC_APB1DIVR_APB1DIV_SHIFT 0 +#define RCC_APB1DIVR_APB1DIVRDY BIT(31) + +/* RCC_APB2DIVR register fields */ +#define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0) +#define RCC_APB2DIVR_APB2DIV_SHIFT 0 +#define RCC_APB2DIVR_APB2DIVRDY BIT(31) + +/* RCC_APB3DIVR register fields */ +#define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0) +#define RCC_APB3DIVR_APB3DIV_SHIFT 0 +#define RCC_APB3DIVR_APB3DIVRDY BIT(31) + +/* RCC_APB4DIVR register fields */ +#define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0) +#define RCC_APB4DIVR_APB4DIV_SHIFT 0 +#define RCC_APB4DIVR_APB4DIVRDY BIT(31) + +/* RCC_APBDBGDIVR register fields */ +#define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0) +#define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0 +#define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31) + +/* RCC_APBxDIVR register fields */ +#define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0) +#define RCC_APBxDIVR_APBxDIV_SHIFT 0 +#define RCC_APBxDIVR_APBxDIVRDY BIT(31) + +/* RCC_TIMG1PRER register fields */ +#define RCC_TIMG1PRER_TIMG1PRE BIT(0) +#define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) + +/* RCC_TIMG2PRER register fields */ +#define RCC_TIMG2PRER_TIMG2PRE BIT(0) +#define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) + +/* RCC_TIMGxPRER register fields */ +#define RCC_TIMGxPRER_TIMGxPRE BIT(0) +#define RCC_TIMGxPRER_TIMGxPRERDY BIT(31) + +/* RCC_LSMCUDIVR register fields */ +#define RCC_LSMCUDIVR_LSMCUDIV BIT(0) +#define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31) + +/* RCC_DDRCPCFGR register fields */ +#define RCC_DDRCPCFGR_DDRCPRST BIT(0) +#define RCC_DDRCPCFGR_DDRCPEN BIT(1) +#define RCC_DDRCPCFGR_DDRCPLPEN BIT(2) + +/* RCC_DDRCAPBCFGR register fields */ +#define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0) +#define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1) +#define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2) + +/* RCC_DDRPHYCAPBCFGR register fields */ +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0) +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1) +#define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2) + +/* RCC_DDRPHYCCFGR register fields */ +#define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1) + +/* RCC_DDRCFGR register fields */ +#define RCC_DDRCFGR_DDRCFGRST BIT(0) +#define RCC_DDRCFGR_DDRCFGEN BIT(1) +#define RCC_DDRCFGR_DDRCFGLPEN BIT(2) + +/* RCC_DDRITFCFGR register fields */ +#define RCC_DDRITFCFGR_DDRRST BIT(0) +#define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4) +#define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4 +#define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5) +#define RCC_DDRITFCFGR_DDRSHR BIT(8) +#define RCC_DDRITFCFGR_DDRPHYDLP BIT(16) + +/* RCC_SYSRAMCFGR register fields */ +#define RCC_SYSRAMCFGR_SYSRAMEN BIT(1) +#define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2) + +/* RCC_VDERAMCFGR register fields */ +#define RCC_VDERAMCFGR_VDERAMEN BIT(1) +#define RCC_VDERAMCFGR_VDERAMLPEN BIT(2) + +/* RCC_SRAM1CFGR register fields */ +#define RCC_SRAM1CFGR_SRAM1EN BIT(1) +#define RCC_SRAM1CFGR_SRAM1LPEN BIT(2) + +/* RCC_SRAM2CFGR register fields */ +#define RCC_SRAM2CFGR_SRAM2EN BIT(1) +#define RCC_SRAM2CFGR_SRAM2LPEN BIT(2) + +/* RCC_RETRAMCFGR register fields */ +#define RCC_RETRAMCFGR_RETRAMEN BIT(1) +#define RCC_RETRAMCFGR_RETRAMLPEN BIT(2) + +/* RCC_BKPSRAMCFGR register fields */ +#define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1) +#define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2) + +/* RCC_LPSRAM1CFGR register fields */ +#define RCC_LPSRAM1CFGR_LPSRAM1EN BIT(1) +#define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2) +#define RCC_LPSRAM1CFGR_LPSRAM1AMEN BIT(3) + +/* RCC_LPSRAM2CFGR register fields */ +#define RCC_LPSRAM2CFGR_LPSRAM2EN BIT(1) +#define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2) +#define RCC_LPSRAM2CFGR_LPSRAM2AMEN BIT(3) + +/* RCC_LPSRAM3CFGR register fields */ +#define RCC_LPSRAM3CFGR_LPSRAM3EN BIT(1) +#define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2) +#define RCC_LPSRAM3CFGR_LPSRAM3AMEN BIT(3) + +/* RCC_OSPI1CFGR register fields */ +#define RCC_OSPI1CFGR_OSPI1RST BIT(0) +#define RCC_OSPI1CFGR_OSPI1EN BIT(1) +#define RCC_OSPI1CFGR_OSPI1LPEN BIT(2) +#define RCC_OSPI1CFGR_OTFDEC1RST BIT(8) +#define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16) + +/* RCC_OSPI2CFGR register fields */ +#define RCC_OSPI2CFGR_OSPI2RST BIT(0) +#define RCC_OSPI2CFGR_OSPI2EN BIT(1) +#define RCC_OSPI2CFGR_OSPI2LPEN BIT(2) +#define RCC_OSPI2CFGR_OTFDEC2RST BIT(8) +#define RCC_OSPI2CFGR_OSPI2DLLRST BIT(16) + +/* RCC_OSPIxCFGR register fields */ +#define RCC_OSPIxCFGR_OSPIxRST BIT(0) +#define RCC_OSPIxCFGR_OSPIxEN BIT(1) +#define RCC_OSPIxCFGR_OSPIxLPEN BIT(2) +#define RCC_OSPIxCFGR_OTFDECxRST BIT(8) +#define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16) + +/* RCC_FMCCFGR register fields */ +#define RCC_FMCCFGR_FMCRST BIT(0) +#define RCC_FMCCFGR_FMCEN BIT(1) +#define RCC_FMCCFGR_FMCLPEN BIT(2) + +/* RCC_DBGCFGR register fields */ +#define RCC_DBGCFGR_DBGEN BIT(8) +#define RCC_DBGCFGR_TRACEEN BIT(9) +#define RCC_DBGCFGR_DBGRST BIT(12) + +/* RCC_STM500CFGR register fields */ +#define RCC_STM500CFGR_STM500EN BIT(1) +#define RCC_STM500CFGR_STM500LPEN BIT(2) + +/* RCC_ETRCFGR register fields */ +#define RCC_ETRCFGR_ETREN BIT(1) +#define RCC_ETRCFGR_ETRLPEN BIT(2) + +/* RCC_GPIOACFGR register fields */ +#define RCC_GPIOACFGR_GPIOARST BIT(0) +#define RCC_GPIOACFGR_GPIOAEN BIT(1) +#define RCC_GPIOACFGR_GPIOALPEN BIT(2) + +/* RCC_GPIOBCFGR register fields */ +#define RCC_GPIOBCFGR_GPIOBRST BIT(0) +#define RCC_GPIOBCFGR_GPIOBEN BIT(1) +#define RCC_GPIOBCFGR_GPIOBLPEN BIT(2) + +/* RCC_GPIOCCFGR register fields */ +#define RCC_GPIOCCFGR_GPIOCRST BIT(0) +#define RCC_GPIOCCFGR_GPIOCEN BIT(1) +#define RCC_GPIOCCFGR_GPIOCLPEN BIT(2) + +/* RCC_GPIODCFGR register fields */ +#define RCC_GPIODCFGR_GPIODRST BIT(0) +#define RCC_GPIODCFGR_GPIODEN BIT(1) +#define RCC_GPIODCFGR_GPIODLPEN BIT(2) + +/* RCC_GPIOECFGR register fields */ +#define RCC_GPIOECFGR_GPIOERST BIT(0) +#define RCC_GPIOECFGR_GPIOEEN BIT(1) +#define RCC_GPIOECFGR_GPIOELPEN BIT(2) + +/* RCC_GPIOFCFGR register fields */ +#define RCC_GPIOFCFGR_GPIOFRST BIT(0) +#define RCC_GPIOFCFGR_GPIOFEN BIT(1) +#define RCC_GPIOFCFGR_GPIOFLPEN BIT(2) + +/* RCC_GPIOGCFGR register fields */ +#define RCC_GPIOGCFGR_GPIOGRST BIT(0) +#define RCC_GPIOGCFGR_GPIOGEN BIT(1) +#define RCC_GPIOGCFGR_GPIOGLPEN BIT(2) + +/* RCC_GPIOHCFGR register fields */ +#define RCC_GPIOHCFGR_GPIOHRST BIT(0) +#define RCC_GPIOHCFGR_GPIOHEN BIT(1) +#define RCC_GPIOHCFGR_GPIOHLPEN BIT(2) + +/* RCC_GPIOICFGR register fields */ +#define RCC_GPIOICFGR_GPIOIRST BIT(0) +#define RCC_GPIOICFGR_GPIOIEN BIT(1) +#define RCC_GPIOICFGR_GPIOILPEN BIT(2) + +/* RCC_GPIOJCFGR register fields */ +#define RCC_GPIOJCFGR_GPIOJRST BIT(0) +#define RCC_GPIOJCFGR_GPIOJEN BIT(1) +#define RCC_GPIOJCFGR_GPIOJLPEN BIT(2) + +/* RCC_GPIOKCFGR register fields */ +#define RCC_GPIOKCFGR_GPIOKRST BIT(0) +#define RCC_GPIOKCFGR_GPIOKEN BIT(1) +#define RCC_GPIOKCFGR_GPIOKLPEN BIT(2) + +/* RCC_GPIOZCFGR register fields */ +#define RCC_GPIOZCFGR_GPIOZRST BIT(0) +#define RCC_GPIOZCFGR_GPIOZEN BIT(1) +#define RCC_GPIOZCFGR_GPIOZLPEN BIT(2) +#define RCC_GPIOZCFGR_GPIOZAMEN BIT(3) + +/* RCC_GPIOxCFGR register fields */ +#define RCC_GPIOxCFGR_GPIOxRST BIT(0) +#define RCC_GPIOxCFGR_GPIOxEN BIT(1) +#define RCC_GPIOxCFGR_GPIOxLPEN BIT(2) +#define RCC_GPIOxCFGR_GPIOxAMEN BIT(3) + +/* RCC_HPDMA1CFGR register fields */ +#define RCC_HPDMA1CFGR_HPDMA1RST BIT(0) +#define RCC_HPDMA1CFGR_HPDMA1EN BIT(1) +#define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2) + +/* RCC_HPDMA2CFGR register fields */ +#define RCC_HPDMA2CFGR_HPDMA2RST BIT(0) +#define RCC_HPDMA2CFGR_HPDMA2EN BIT(1) +#define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2) + +/* RCC_HPDMA3CFGR register fields */ +#define RCC_HPDMA3CFGR_HPDMA3RST BIT(0) +#define RCC_HPDMA3CFGR_HPDMA3EN BIT(1) +#define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2) + +/* RCC_HPDMAxCFGR register fields */ +#define RCC_HPDMAxCFGR_HPDMAxRST BIT(0) +#define RCC_HPDMAxCFGR_HPDMAxEN BIT(1) +#define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2) + +/* RCC_LPDMACFGR register fields */ +#define RCC_LPDMACFGR_LPDMARST BIT(0) +#define RCC_LPDMACFGR_LPDMAEN BIT(1) +#define RCC_LPDMACFGR_LPDMALPEN BIT(2) +#define RCC_LPDMACFGR_LPDMAAMEN BIT(3) + +/* RCC_HSEMCFGR register fields */ +#define RCC_HSEMCFGR_HSEMRST BIT(0) +#define RCC_HSEMCFGR_HSEMEN BIT(1) +#define RCC_HSEMCFGR_HSEMLPEN BIT(2) +#define RCC_HSEMCFGR_HSEMAMEN BIT(3) + +/* RCC_IPCC1CFGR register fields */ +#define RCC_IPCC1CFGR_IPCC1RST BIT(0) +#define RCC_IPCC1CFGR_IPCC1EN BIT(1) +#define RCC_IPCC1CFGR_IPCC1LPEN BIT(2) + +/* RCC_IPCC2CFGR register fields */ +#define RCC_IPCC2CFGR_IPCC2RST BIT(0) +#define RCC_IPCC2CFGR_IPCC2EN BIT(1) +#define RCC_IPCC2CFGR_IPCC2LPEN BIT(2) +#define RCC_IPCC2CFGR_IPCC2AMEN BIT(3) + +/* RCC_RTCCFGR register fields */ +#define RCC_RTCCFGR_RTCEN BIT(1) +#define RCC_RTCCFGR_RTCLPEN BIT(2) +#define RCC_RTCCFGR_RTCAMEN BIT(3) + +/* RCC_SYSCPU1CFGR register fields */ +#define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1) +#define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2) + +/* RCC_BSECCFGR register fields */ +#define RCC_BSECCFGR_BSECEN BIT(1) +#define RCC_BSECCFGR_BSECLPEN BIT(2) + +/* RCC_IS2MCFGR register fields */ +#define RCC_IS2MCFGR_IS2MRST BIT(0) +#define RCC_IS2MCFGR_IS2MEN BIT(1) +#define RCC_IS2MCFGR_IS2MLPEN BIT(2) + +/* RCC_PLL2CFGR1 register fields */ +#define RCC_PLL2CFGR1_SSMODRST BIT(0) +#define RCC_PLL2CFGR1_PLLEN BIT(8) +#define RCC_PLL2CFGR1_PLLRDY BIT(24) +#define RCC_PLL2CFGR1_CKREFST BIT(28) + +/* RCC_PLL2CFGR2 register fields */ +#define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL2CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL2CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL2CFGR3 register fields */ +#define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL2CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL2CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL2CFGR3_DACEN BIT(25) +#define RCC_PLL2CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL2CFGR4 register fields */ +#define RCC_PLL2CFGR4_DSMEN BIT(8) +#define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL2CFGR4_BYPASS BIT(10) + +/* RCC_PLL2CFGR5 register fields */ +#define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL2CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL2CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL2CFGR6 register fields */ +#define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL2CFGR7 register fields */ +#define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL3CFGR1 register fields */ +#define RCC_PLL3CFGR1_SSMODRST BIT(0) +#define RCC_PLL3CFGR1_PLLEN BIT(8) +#define RCC_PLL3CFGR1_PLLRDY BIT(24) +#define RCC_PLL3CFGR1_CKREFST BIT(28) + +/* RCC_PLL3CFGR2 register fields */ +#define RCC_PLL3CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL3CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL3CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL3CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL3CFGR3 register fields */ +#define RCC_PLL3CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL3CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL3CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL3CFGR3_DACEN BIT(25) +#define RCC_PLL3CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL3CFGR4 register fields */ +#define RCC_PLL3CFGR4_DSMEN BIT(8) +#define RCC_PLL3CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL3CFGR4_BYPASS BIT(10) + +/* RCC_PLL3CFGR5 register fields */ +#define RCC_PLL3CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL3CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL3CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL3CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL3CFGR6 register fields */ +#define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL3CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL3CFGR7 register fields */ +#define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL3CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLLxCFGR1 register fields */ +#define RCC_PLLxCFGR1_SSMODRST BIT(0) +#define RCC_PLLxCFGR1_PLLEN BIT(8) +#define RCC_PLLxCFGR1_PLLRDY BIT(24) +#define RCC_PLLxCFGR1_CKREFST BIT(28) + +/* RCC_PLLxCFGR2 register fields */ +#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 +#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLLxCFGR2_FBDIV_SHIFT 16 + +/* RCC_PLLxCFGR3 register fields */ +#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLLxCFGR3_FRACIN_SHIFT 0 +#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) +#define RCC_PLLxCFGR3_DACEN BIT(25) +#define RCC_PLLxCFGR3_SSCGDIS BIT(26) + +/* RCC_PLLxCFGR4 register fields */ +#define RCC_PLLxCFGR4_DSMEN BIT(8) +#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLLxCFGR4_BYPASS BIT(10) + +/* RCC_PLLxCFGR5 register fields */ +#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 +#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLLxCFGR5_SPREAD_SHIFT 16 + +/* RCC_PLLxCFGR6 register fields */ +#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLLxCFGR7 register fields */ +#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 + +/* RCC_HSIFMONCR register fields */ +#define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0) +#define RCC_HSIFMONCR_HSIREF_SHIFT 0 +#define RCC_HSIFMONCR_HSIMONEN BIT(15) +#define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16) +#define RCC_HSIFMONCR_HSIDEV_SHIFT 16 +#define RCC_HSIFMONCR_HSIMONIE BIT(30) +#define RCC_HSIFMONCR_HSIMONF BIT(31) + +/* RCC_HSIFVALR register fields */ +#define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0) +#define RCC_HSIFVALR_HSIVAL_SHIFT 0 + +/* RCC_TIM1CFGR register fields */ +#define RCC_TIM1CFGR_TIM1RST BIT(0) +#define RCC_TIM1CFGR_TIM1EN BIT(1) +#define RCC_TIM1CFGR_TIM1LPEN BIT(2) + +/* RCC_TIM2CFGR register fields */ +#define RCC_TIM2CFGR_TIM2RST BIT(0) +#define RCC_TIM2CFGR_TIM2EN BIT(1) +#define RCC_TIM2CFGR_TIM2LPEN BIT(2) + +/* RCC_TIM3CFGR register fields */ +#define RCC_TIM3CFGR_TIM3RST BIT(0) +#define RCC_TIM3CFGR_TIM3EN BIT(1) +#define RCC_TIM3CFGR_TIM3LPEN BIT(2) + +/* RCC_TIM4CFGR register fields */ +#define RCC_TIM4CFGR_TIM4RST BIT(0) +#define RCC_TIM4CFGR_TIM4EN BIT(1) +#define RCC_TIM4CFGR_TIM4LPEN BIT(2) + +/* RCC_TIM5CFGR register fields */ +#define RCC_TIM5CFGR_TIM5RST BIT(0) +#define RCC_TIM5CFGR_TIM5EN BIT(1) +#define RCC_TIM5CFGR_TIM5LPEN BIT(2) + +/* RCC_TIM6CFGR register fields */ +#define RCC_TIM6CFGR_TIM6RST BIT(0) +#define RCC_TIM6CFGR_TIM6EN BIT(1) +#define RCC_TIM6CFGR_TIM6LPEN BIT(2) + +/* RCC_TIM7CFGR register fields */ +#define RCC_TIM7CFGR_TIM7RST BIT(0) +#define RCC_TIM7CFGR_TIM7EN BIT(1) +#define RCC_TIM7CFGR_TIM7LPEN BIT(2) + +/* RCC_TIM8CFGR register fields */ +#define RCC_TIM8CFGR_TIM8RST BIT(0) +#define RCC_TIM8CFGR_TIM8EN BIT(1) +#define RCC_TIM8CFGR_TIM8LPEN BIT(2) + +/* RCC_TIM10CFGR register fields */ +#define RCC_TIM10CFGR_TIM10RST BIT(0) +#define RCC_TIM10CFGR_TIM10EN BIT(1) +#define RCC_TIM10CFGR_TIM10LPEN BIT(2) + +/* RCC_TIM11CFGR register fields */ +#define RCC_TIM11CFGR_TIM11RST BIT(0) +#define RCC_TIM11CFGR_TIM11EN BIT(1) +#define RCC_TIM11CFGR_TIM11LPEN BIT(2) + +/* RCC_TIM12CFGR register fields */ +#define RCC_TIM12CFGR_TIM12RST BIT(0) +#define RCC_TIM12CFGR_TIM12EN BIT(1) +#define RCC_TIM12CFGR_TIM12LPEN BIT(2) + +/* RCC_TIM13CFGR register fields */ +#define RCC_TIM13CFGR_TIM13RST BIT(0) +#define RCC_TIM13CFGR_TIM13EN BIT(1) +#define RCC_TIM13CFGR_TIM13LPEN BIT(2) + +/* RCC_TIM14CFGR register fields */ +#define RCC_TIM14CFGR_TIM14RST BIT(0) +#define RCC_TIM14CFGR_TIM14EN BIT(1) +#define RCC_TIM14CFGR_TIM14LPEN BIT(2) + +/* RCC_TIM15CFGR register fields */ +#define RCC_TIM15CFGR_TIM15RST BIT(0) +#define RCC_TIM15CFGR_TIM15EN BIT(1) +#define RCC_TIM15CFGR_TIM15LPEN BIT(2) + +/* RCC_TIM16CFGR register fields */ +#define RCC_TIM16CFGR_TIM16RST BIT(0) +#define RCC_TIM16CFGR_TIM16EN BIT(1) +#define RCC_TIM16CFGR_TIM16LPEN BIT(2) + +/* RCC_TIM17CFGR register fields */ +#define RCC_TIM17CFGR_TIM17RST BIT(0) +#define RCC_TIM17CFGR_TIM17EN BIT(1) +#define RCC_TIM17CFGR_TIM17LPEN BIT(2) + +/* RCC_TIM20CFGR register fields */ +#define RCC_TIM20CFGR_TIM20RST BIT(0) +#define RCC_TIM20CFGR_TIM20EN BIT(1) +#define RCC_TIM20CFGR_TIM20LPEN BIT(2) + +/* RCC_LPTIM1CFGR register fields */ +#define RCC_LPTIM1CFGR_LPTIM1RST BIT(0) +#define RCC_LPTIM1CFGR_LPTIM1EN BIT(1) +#define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2) + +/* RCC_LPTIM2CFGR register fields */ +#define RCC_LPTIM2CFGR_LPTIM2RST BIT(0) +#define RCC_LPTIM2CFGR_LPTIM2EN BIT(1) +#define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2) + +/* RCC_LPTIM3CFGR register fields */ +#define RCC_LPTIM3CFGR_LPTIM3RST BIT(0) +#define RCC_LPTIM3CFGR_LPTIM3EN BIT(1) +#define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2) +#define RCC_LPTIM3CFGR_LPTIM3AMEN BIT(3) + +/* RCC_LPTIM4CFGR register fields */ +#define RCC_LPTIM4CFGR_LPTIM4RST BIT(0) +#define RCC_LPTIM4CFGR_LPTIM4EN BIT(1) +#define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2) +#define RCC_LPTIM4CFGR_LPTIM4AMEN BIT(3) + +/* RCC_LPTIM5CFGR register fields */ +#define RCC_LPTIM5CFGR_LPTIM5RST BIT(0) +#define RCC_LPTIM5CFGR_LPTIM5EN BIT(1) +#define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2) +#define RCC_LPTIM5CFGR_LPTIM5AMEN BIT(3) + +/* RCC_LPTIMxCFGR register fields */ +#define RCC_LPTIMxCFGR_LPTIMxRST BIT(0) +#define RCC_LPTIMxCFGR_LPTIMxEN BIT(1) +#define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2) +#define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3) + +/* RCC_SPI1CFGR register fields */ +#define RCC_SPI1CFGR_SPI1RST BIT(0) +#define RCC_SPI1CFGR_SPI1EN BIT(1) +#define RCC_SPI1CFGR_SPI1LPEN BIT(2) + +/* RCC_SPI2CFGR register fields */ +#define RCC_SPI2CFGR_SPI2RST BIT(0) +#define RCC_SPI2CFGR_SPI2EN BIT(1) +#define RCC_SPI2CFGR_SPI2LPEN BIT(2) + +/* RCC_SPI3CFGR register fields */ +#define RCC_SPI3CFGR_SPI3RST BIT(0) +#define RCC_SPI3CFGR_SPI3EN BIT(1) +#define RCC_SPI3CFGR_SPI3LPEN BIT(2) + +/* RCC_SPI4CFGR register fields */ +#define RCC_SPI4CFGR_SPI4RST BIT(0) +#define RCC_SPI4CFGR_SPI4EN BIT(1) +#define RCC_SPI4CFGR_SPI4LPEN BIT(2) + +/* RCC_SPI5CFGR register fields */ +#define RCC_SPI5CFGR_SPI5RST BIT(0) +#define RCC_SPI5CFGR_SPI5EN BIT(1) +#define RCC_SPI5CFGR_SPI5LPEN BIT(2) + +/* RCC_SPI6CFGR register fields */ +#define RCC_SPI6CFGR_SPI6RST BIT(0) +#define RCC_SPI6CFGR_SPI6EN BIT(1) +#define RCC_SPI6CFGR_SPI6LPEN BIT(2) + +/* RCC_SPI7CFGR register fields */ +#define RCC_SPI7CFGR_SPI7RST BIT(0) +#define RCC_SPI7CFGR_SPI7EN BIT(1) +#define RCC_SPI7CFGR_SPI7LPEN BIT(2) + +/* RCC_SPI8CFGR register fields */ +#define RCC_SPI8CFGR_SPI8RST BIT(0) +#define RCC_SPI8CFGR_SPI8EN BIT(1) +#define RCC_SPI8CFGR_SPI8LPEN BIT(2) +#define RCC_SPI8CFGR_SPI8AMEN BIT(3) + +/* RCC_SPIxCFGR register fields */ +#define RCC_SPIxCFGR_SPIxRST BIT(0) +#define RCC_SPIxCFGR_SPIxEN BIT(1) +#define RCC_SPIxCFGR_SPIxLPEN BIT(2) +#define RCC_SPIxCFGR_SPIxAMEN BIT(3) + +/* RCC_SPDIFRXCFGR register fields */ +#define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0) +#define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1) +#define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2) + +/* RCC_USART1CFGR register fields */ +#define RCC_USART1CFGR_USART1RST BIT(0) +#define RCC_USART1CFGR_USART1EN BIT(1) +#define RCC_USART1CFGR_USART1LPEN BIT(2) + +/* RCC_USART2CFGR register fields */ +#define RCC_USART2CFGR_USART2RST BIT(0) +#define RCC_USART2CFGR_USART2EN BIT(1) +#define RCC_USART2CFGR_USART2LPEN BIT(2) + +/* RCC_USART3CFGR register fields */ +#define RCC_USART3CFGR_USART3RST BIT(0) +#define RCC_USART3CFGR_USART3EN BIT(1) +#define RCC_USART3CFGR_USART3LPEN BIT(2) + +/* RCC_UART4CFGR register fields */ +#define RCC_UART4CFGR_UART4RST BIT(0) +#define RCC_UART4CFGR_UART4EN BIT(1) +#define RCC_UART4CFGR_UART4LPEN BIT(2) + +/* RCC_UART5CFGR register fields */ +#define RCC_UART5CFGR_UART5RST BIT(0) +#define RCC_UART5CFGR_UART5EN BIT(1) +#define RCC_UART5CFGR_UART5LPEN BIT(2) + +/* RCC_USART6CFGR register fields */ +#define RCC_USART6CFGR_USART6RST BIT(0) +#define RCC_USART6CFGR_USART6EN BIT(1) +#define RCC_USART6CFGR_USART6LPEN BIT(2) + +/* RCC_UART7CFGR register fields */ +#define RCC_UART7CFGR_UART7RST BIT(0) +#define RCC_UART7CFGR_UART7EN BIT(1) +#define RCC_UART7CFGR_UART7LPEN BIT(2) + +/* RCC_UART8CFGR register fields */ +#define RCC_UART8CFGR_UART8RST BIT(0) +#define RCC_UART8CFGR_UART8EN BIT(1) +#define RCC_UART8CFGR_UART8LPEN BIT(2) + +/* RCC_UART9CFGR register fields */ +#define RCC_UART9CFGR_UART9RST BIT(0) +#define RCC_UART9CFGR_UART9EN BIT(1) +#define RCC_UART9CFGR_UART9LPEN BIT(2) + +/* RCC_USARTxCFGR register fields */ +#define RCC_USARTxCFGR_USARTxRST BIT(0) +#define RCC_USARTxCFGR_USARTxEN BIT(1) +#define RCC_USARTxCFGR_USARTxLPEN BIT(2) + +/* RCC_UARTxCFGR register fields */ +#define RCC_UARTxCFGR_UARTxRST BIT(0) +#define RCC_UARTxCFGR_UARTxEN BIT(1) +#define RCC_UARTxCFGR_UARTxLPEN BIT(2) + +/* RCC_LPUART1CFGR register fields */ +#define RCC_LPUART1CFGR_LPUART1RST BIT(0) +#define RCC_LPUART1CFGR_LPUART1EN BIT(1) +#define RCC_LPUART1CFGR_LPUART1LPEN BIT(2) +#define RCC_LPUART1CFGR_LPUART1AMEN BIT(3) + +/* RCC_I2C1CFGR register fields */ +#define RCC_I2C1CFGR_I2C1RST BIT(0) +#define RCC_I2C1CFGR_I2C1EN BIT(1) +#define RCC_I2C1CFGR_I2C1LPEN BIT(2) + +/* RCC_I2C2CFGR register fields */ +#define RCC_I2C2CFGR_I2C2RST BIT(0) +#define RCC_I2C2CFGR_I2C2EN BIT(1) +#define RCC_I2C2CFGR_I2C2LPEN BIT(2) + +/* RCC_I2C3CFGR register fields */ +#define RCC_I2C3CFGR_I2C3RST BIT(0) +#define RCC_I2C3CFGR_I2C3EN BIT(1) +#define RCC_I2C3CFGR_I2C3LPEN BIT(2) + +/* RCC_I2C4CFGR register fields */ +#define RCC_I2C4CFGR_I2C4RST BIT(0) +#define RCC_I2C4CFGR_I2C4EN BIT(1) +#define RCC_I2C4CFGR_I2C4LPEN BIT(2) + +/* RCC_I2C5CFGR register fields */ +#define RCC_I2C5CFGR_I2C5RST BIT(0) +#define RCC_I2C5CFGR_I2C5EN BIT(1) +#define RCC_I2C5CFGR_I2C5LPEN BIT(2) + +/* RCC_I2C6CFGR register fields */ +#define RCC_I2C6CFGR_I2C6RST BIT(0) +#define RCC_I2C6CFGR_I2C6EN BIT(1) +#define RCC_I2C6CFGR_I2C6LPEN BIT(2) + +/* RCC_I2C7CFGR register fields */ +#define RCC_I2C7CFGR_I2C7RST BIT(0) +#define RCC_I2C7CFGR_I2C7EN BIT(1) +#define RCC_I2C7CFGR_I2C7LPEN BIT(2) + +/* RCC_I2C8CFGR register fields */ +#define RCC_I2C8CFGR_I2C8RST BIT(0) +#define RCC_I2C8CFGR_I2C8EN BIT(1) +#define RCC_I2C8CFGR_I2C8LPEN BIT(2) +#define RCC_I2C8CFGR_I2C8AMEN BIT(3) + +/* RCC_I2CxCFGR register fields */ +#define RCC_I2CxCFGR_I2CxRST BIT(0) +#define RCC_I2CxCFGR_I2CxEN BIT(1) +#define RCC_I2CxCFGR_I2CxLPEN BIT(2) +#define RCC_I2CxCFGR_I2CxAMEN BIT(3) + +/* RCC_SAI1CFGR register fields */ +#define RCC_SAI1CFGR_SAI1RST BIT(0) +#define RCC_SAI1CFGR_SAI1EN BIT(1) +#define RCC_SAI1CFGR_SAI1LPEN BIT(2) + +/* RCC_SAI2CFGR register fields */ +#define RCC_SAI2CFGR_SAI2RST BIT(0) +#define RCC_SAI2CFGR_SAI2EN BIT(1) +#define RCC_SAI2CFGR_SAI2LPEN BIT(2) + +/* RCC_SAI3CFGR register fields */ +#define RCC_SAI3CFGR_SAI3RST BIT(0) +#define RCC_SAI3CFGR_SAI3EN BIT(1) +#define RCC_SAI3CFGR_SAI3LPEN BIT(2) + +/* RCC_SAI4CFGR register fields */ +#define RCC_SAI4CFGR_SAI4RST BIT(0) +#define RCC_SAI4CFGR_SAI4EN BIT(1) +#define RCC_SAI4CFGR_SAI4LPEN BIT(2) + +/* RCC_SAIxCFGR register fields */ +#define RCC_SAIxCFGR_SAIxRST BIT(0) +#define RCC_SAIxCFGR_SAIxEN BIT(1) +#define RCC_SAIxCFGR_SAIxLPEN BIT(2) + +/* RCC_MDF1CFGR register fields */ +#define RCC_MDF1CFGR_MDF1RST BIT(0) +#define RCC_MDF1CFGR_MDF1EN BIT(1) +#define RCC_MDF1CFGR_MDF1LPEN BIT(2) + +/* RCC_ADF1CFGR register fields */ +#define RCC_ADF1CFGR_ADF1RST BIT(0) +#define RCC_ADF1CFGR_ADF1EN BIT(1) +#define RCC_ADF1CFGR_ADF1LPEN BIT(2) +#define RCC_ADF1CFGR_ADF1AMEN BIT(3) + +/* RCC_FDCANCFGR register fields */ +#define RCC_FDCANCFGR_FDCANRST BIT(0) +#define RCC_FDCANCFGR_FDCANEN BIT(1) +#define RCC_FDCANCFGR_FDCANLPEN BIT(2) + +/* RCC_HDPCFGR register fields */ +#define RCC_HDPCFGR_HDPRST BIT(0) +#define RCC_HDPCFGR_HDPEN BIT(1) + +/* RCC_ADC12CFGR register fields */ +#define RCC_ADC12CFGR_ADC12RST BIT(0) +#define RCC_ADC12CFGR_ADC12EN BIT(1) +#define RCC_ADC12CFGR_ADC12LPEN BIT(2) +#define RCC_ADC12CFGR_ADC12KERSEL BIT(12) + +/* RCC_ADC3CFGR register fields */ +#define RCC_ADC3CFGR_ADC3RST BIT(0) +#define RCC_ADC3CFGR_ADC3EN BIT(1) +#define RCC_ADC3CFGR_ADC3LPEN BIT(2) +#define RCC_ADC3CFGR_ADC3KERSEL_MASK GENMASK_32(13, 12) +#define RCC_ADC3CFGR_ADC3KERSEL_SHIFT 12 + +/* RCC_ETH1CFGR register fields */ +#define RCC_ETH1CFGR_ETH1RST BIT(0) +#define RCC_ETH1CFGR_ETH1MACEN BIT(1) +#define RCC_ETH1CFGR_ETH1MACLPEN BIT(2) +#define RCC_ETH1CFGR_ETH1STPEN BIT(4) +#define RCC_ETH1CFGR_ETH1EN BIT(5) +#define RCC_ETH1CFGR_ETH1LPEN BIT(6) +#define RCC_ETH1CFGR_ETH1TXEN BIT(8) +#define RCC_ETH1CFGR_ETH1TXLPEN BIT(9) +#define RCC_ETH1CFGR_ETH1RXEN BIT(10) +#define RCC_ETH1CFGR_ETH1RXLPEN BIT(11) + +/* RCC_ETH2CFGR register fields */ +#define RCC_ETH2CFGR_ETH2RST BIT(0) +#define RCC_ETH2CFGR_ETH2MACEN BIT(1) +#define RCC_ETH2CFGR_ETH2MACLPEN BIT(2) +#define RCC_ETH2CFGR_ETH2STPEN BIT(4) +#define RCC_ETH2CFGR_ETH2EN BIT(5) +#define RCC_ETH2CFGR_ETH2LPEN BIT(6) +#define RCC_ETH2CFGR_ETH2TXEN BIT(8) +#define RCC_ETH2CFGR_ETH2TXLPEN BIT(9) +#define RCC_ETH2CFGR_ETH2RXEN BIT(10) +#define RCC_ETH2CFGR_ETH2RXLPEN BIT(11) + +/* RCC_ETHxCFGR register fields */ +#define RCC_ETHxCFGR_ETHxRST BIT(0) +#define RCC_ETHxCFGR_ETHxMACEN BIT(1) +#define RCC_ETHxCFGR_ETHxMACLPEN BIT(2) +#define RCC_ETHxCFGR_ETHxSTPEN BIT(4) +#define RCC_ETHxCFGR_ETHxEN BIT(5) +#define RCC_ETHxCFGR_ETHxLPEN BIT(6) +#define RCC_ETHxCFGR_ETHxTXEN BIT(8) +#define RCC_ETHxCFGR_ETHxTXLPEN BIT(9) +#define RCC_ETHxCFGR_ETHxRXEN BIT(10) +#define RCC_ETHxCFGR_ETHxRXLPEN BIT(11) + +/* RCC_USB2CFGR register fields */ +#define RCC_USB2CFGR_USB2RST BIT(0) +#define RCC_USB2CFGR_USB2EN BIT(1) +#define RCC_USB2CFGR_USB2LPEN BIT(2) +#define RCC_USB2CFGR_USB2STPEN BIT(4) + +/* RCC_USB2PHY1CFGR register fields */ +#define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0) +#define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1) +#define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2) +#define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4) +#define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15) + +/* RCC_USB2PHY2CFGR register fields */ +#define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0) +#define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1) +#define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2) +#define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4) +#define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15) + +/* RCC_USB2PHYxCFGR register fields */ +#define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0) +#define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1) +#define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2) +#define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4) +#define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15) + +/* RCC_USB3DRDCFGR register fields */ +#define RCC_USB3DRDCFGR_USB3DRDRST BIT(0) +#define RCC_USB3DRDCFGR_USB3DRDEN BIT(1) +#define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2) +#define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4) + +/* RCC_USB3PCIEPHYCFGR register fields */ +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYEN BIT(1) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYSTPEN BIT(4) +#define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYCKREFSEL BIT(15) + +/* RCC_PCIECFGR register fields */ +#define RCC_PCIECFGR_PCIERST BIT(0) +#define RCC_PCIECFGR_PCIEEN BIT(1) +#define RCC_PCIECFGR_PCIELPEN BIT(2) +#define RCC_PCIECFGR_PCIESTPEN BIT(4) + +/* RCC_USBTCCFGR register fields */ +#define RCC_USBTCCFGR_USBTCRST BIT(0) +#define RCC_USBTCCFGR_USBTCEN BIT(1) +#define RCC_USBTCCFGR_USBTCLPEN BIT(2) + +/* RCC_ETHSWCFGR register fields */ +#define RCC_ETHSWCFGR_ETHSWRST BIT(0) +#define RCC_ETHSWCFGR_ETHSWMACEN BIT(1) +#define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2) +#define RCC_ETHSWCFGR_ETHSWEN BIT(5) +#define RCC_ETHSWCFGR_ETHSWLPEN BIT(6) +#define RCC_ETHSWCFGR_ETHSWREFEN BIT(21) +#define RCC_ETHSWCFGR_ETHSWREFLPEN BIT(22) + +/* RCC_ETHSWACMCFGR register fields */ +#define RCC_ETHSWACMCFGR_ETHSWACMEN BIT(1) +#define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2) + +/* RCC_ETHSWACMMSGCFGR register fields */ +#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGEN BIT(1) +#define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2) + +/* RCC_STGENCFGR register fields */ +#define RCC_STGENCFGR_STGENEN BIT(1) +#define RCC_STGENCFGR_STGENLPEN BIT(2) +#define RCC_STGENCFGR_STGENSTPEN BIT(4) + +/* RCC_SDMMC1CFGR register fields */ +#define RCC_SDMMC1CFGR_SDMMC1RST BIT(0) +#define RCC_SDMMC1CFGR_SDMMC1EN BIT(1) +#define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2) +#define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16) + +/* RCC_SDMMC2CFGR register fields */ +#define RCC_SDMMC2CFGR_SDMMC2RST BIT(0) +#define RCC_SDMMC2CFGR_SDMMC2EN BIT(1) +#define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2) +#define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16) + +/* RCC_SDMMC3CFGR register fields */ +#define RCC_SDMMC3CFGR_SDMMC3RST BIT(0) +#define RCC_SDMMC3CFGR_SDMMC3EN BIT(1) +#define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2) +#define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16) + +/* RCC_SDMMCxCFGR register fields */ +#define RCC_SDMMCxCFGR_SDMMC1RST BIT(0) +#define RCC_SDMMCxCFGR_SDMMC1EN BIT(1) +#define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2) +#define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16) + +/* RCC_GPUCFGR register fields */ +#define RCC_GPUCFGR_GPURST BIT(0) +#define RCC_GPUCFGR_GPUEN BIT(1) +#define RCC_GPUCFGR_GPULPEN BIT(2) + +/* RCC_LTDCCFGR register fields */ +#define RCC_LTDCCFGR_LTDCRST BIT(0) +#define RCC_LTDCCFGR_LTDCEN BIT(1) +#define RCC_LTDCCFGR_LTDCLPEN BIT(2) + +/* RCC_DSICFGR register fields */ +#define RCC_DSICFGR_DSIRST BIT(0) +#define RCC_DSICFGR_DSIEN BIT(1) +#define RCC_DSICFGR_DSILPEN BIT(2) +#define RCC_DSICFGR_DSIBLSEL BIT(12) +#define RCC_DSICFGR_DSIPHYCKREFSEL BIT(15) + +/* RCC_LVDSCFGR register fields */ +#define RCC_LVDSCFGR_LVDSRST BIT(0) +#define RCC_LVDSCFGR_LVDSEN BIT(1) +#define RCC_LVDSCFGR_LVDSLPEN BIT(2) +#define RCC_LVDSCFGR_LVDSPHYCKREFSEL BIT(15) + +/* RCC_CSI2CFGR register fields */ +#define RCC_CSI2CFGR_CSI2RST BIT(0) +#define RCC_CSI2CFGR_CSI2EN BIT(1) +#define RCC_CSI2CFGR_CSI2LPEN BIT(2) + +/* RCC_DCMIPPCFGR register fields */ +#define RCC_DCMIPPCFGR_DCMIPPRST BIT(0) +#define RCC_DCMIPPCFGR_DCMIPPEN BIT(1) +#define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2) + +/* RCC_CCICFGR register fields */ +#define RCC_CCICFGR_CCIRST BIT(0) +#define RCC_CCICFGR_CCIEN BIT(1) +#define RCC_CCICFGR_CCILPEN BIT(2) + +/* RCC_VDECCFGR register fields */ +#define RCC_VDECCFGR_VDECRST BIT(0) +#define RCC_VDECCFGR_VDECEN BIT(1) +#define RCC_VDECCFGR_VDECLPEN BIT(2) + +/* RCC_VENCCFGR register fields */ +#define RCC_VENCCFGR_VENCRST BIT(0) +#define RCC_VENCCFGR_VENCEN BIT(1) +#define RCC_VENCCFGR_VENCLPEN BIT(2) + +/* RCC_RNGCFGR register fields */ +#define RCC_RNGCFGR_RNGRST BIT(0) +#define RCC_RNGCFGR_RNGEN BIT(1) +#define RCC_RNGCFGR_RNGLPEN BIT(2) + +/* RCC_PKACFGR register fields */ +#define RCC_PKACFGR_PKARST BIT(0) +#define RCC_PKACFGR_PKAEN BIT(1) +#define RCC_PKACFGR_PKALPEN BIT(2) + +/* RCC_SAESCFGR register fields */ +#define RCC_SAESCFGR_SAESRST BIT(0) +#define RCC_SAESCFGR_SAESEN BIT(1) +#define RCC_SAESCFGR_SAESLPEN BIT(2) + +/* RCC_HASHCFGR register fields */ +#define RCC_HASHCFGR_HASHRST BIT(0) +#define RCC_HASHCFGR_HASHEN BIT(1) +#define RCC_HASHCFGR_HASHLPEN BIT(2) + +/* RCC_CRYP1CFGR register fields */ +#define RCC_CRYP1CFGR_CRYP1RST BIT(0) +#define RCC_CRYP1CFGR_CRYP1EN BIT(1) +#define RCC_CRYP1CFGR_CRYP1LPEN BIT(2) + +/* RCC_CRYP2CFGR register fields */ +#define RCC_CRYP2CFGR_CRYP2RST BIT(0) +#define RCC_CRYP2CFGR_CRYP2EN BIT(1) +#define RCC_CRYP2CFGR_CRYP2LPEN BIT(2) + +/* RCC_CRYPxCFGR register fields */ +#define RCC_CRYPxCFGR_CRYPxRST BIT(0) +#define RCC_CRYPxCFGR_CRYPxEN BIT(1) +#define RCC_CRYPxCFGR_CRYPxLPEN BIT(2) + +/* RCC_IWDG1CFGR register fields */ +#define RCC_IWDG1CFGR_IWDG1EN BIT(1) +#define RCC_IWDG1CFGR_IWDG1LPEN BIT(2) + +/* RCC_IWDG2CFGR register fields */ +#define RCC_IWDG2CFGR_IWDG2EN BIT(1) +#define RCC_IWDG2CFGR_IWDG2LPEN BIT(2) + +/* RCC_IWDG3CFGR register fields */ +#define RCC_IWDG3CFGR_IWDG3EN BIT(1) +#define RCC_IWDG3CFGR_IWDG3LPEN BIT(2) + +/* RCC_IWDG4CFGR register fields */ +#define RCC_IWDG4CFGR_IWDG4EN BIT(1) +#define RCC_IWDG4CFGR_IWDG4LPEN BIT(2) + +/* RCC_IWDGxCFGR register fields */ +#define RCC_IWDGxCFGR_IWDGxEN BIT(1) +#define RCC_IWDGxCFGR_IWDGxLPEN BIT(2) + +/* RCC_IWDG5CFGR register fields */ +#define RCC_IWDG5CFGR_IWDG5EN BIT(1) +#define RCC_IWDG5CFGR_IWDG5LPEN BIT(2) +#define RCC_IWDG5CFGR_IWDG5AMEN BIT(3) + +/* RCC_WWDG1CFGR register fields */ +#define RCC_WWDG1CFGR_WWDG1RST BIT(0) +#define RCC_WWDG1CFGR_WWDG1EN BIT(1) +#define RCC_WWDG1CFGR_WWDG1LPEN BIT(2) + +/* RCC_WWDG2CFGR register fields */ +#define RCC_WWDG2CFGR_WWDG2RST BIT(0) +#define RCC_WWDG2CFGR_WWDG2EN BIT(1) +#define RCC_WWDG2CFGR_WWDG2LPEN BIT(2) +#define RCC_WWDG2CFGR_WWDG2AMEN BIT(3) + +/* RCC_BUSPERFMCFGR register fields */ +#define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0) +#define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1) +#define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2) + +/* RCC_VREFCFGR register fields */ +#define RCC_VREFCFGR_VREFRST BIT(0) +#define RCC_VREFCFGR_VREFEN BIT(1) +#define RCC_VREFCFGR_VREFLPEN BIT(2) + +/* RCC_TMPSENSCFGR register fields */ +#define RCC_TMPSENSCFGR_TMPSENSRST BIT(0) +#define RCC_TMPSENSCFGR_TMPSENSEN BIT(1) +#define RCC_TMPSENSCFGR_TMPSENSLPEN BIT(2) +#define RCC_TMPSENSCFGR_TMPSENSKERSEL_MASK GENMASK_32(13, 12) +#define RCC_TMPSENSCFGR_TMPSENSKERSEL_SHIFT 12 + +/* RCC_CRCCFGR register fields */ +#define RCC_CRCCFGR_CRCRST BIT(0) +#define RCC_CRCCFGR_CRCEN BIT(1) +#define RCC_CRCCFGR_CRCLPEN BIT(2) + +/* RCC_SERCCFGR register fields */ +#define RCC_SERCCFGR_SERCRST BIT(0) +#define RCC_SERCCFGR_SERCEN BIT(1) +#define RCC_SERCCFGR_SERCLPEN BIT(2) + +/* RCC_OSPIIOMCFGR register fields */ +#define RCC_OSPIIOMCFGR_OSPIIOMRST BIT(0) +#define RCC_OSPIIOMCFGR_OSPIIOMEN BIT(1) +#define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2) + +/* RCC_GICV2MCFGR register fields */ +#define RCC_GICV2MCFGR_GICV2MEN BIT(1) +#define RCC_GICV2MCFGR_GICV2MLPEN BIT(2) + +/* RCC_I3C1CFGR register fields */ +#define RCC_I3C1CFGR_I3C1RST BIT(0) +#define RCC_I3C1CFGR_I3C1EN BIT(1) +#define RCC_I3C1CFGR_I3C1LPEN BIT(2) + +/* RCC_I3C2CFGR register fields */ +#define RCC_I3C2CFGR_I3C2RST BIT(0) +#define RCC_I3C2CFGR_I3C2EN BIT(1) +#define RCC_I3C2CFGR_I3C2LPEN BIT(2) + +/* RCC_I3C3CFGR register fields */ +#define RCC_I3C3CFGR_I3C3RST BIT(0) +#define RCC_I3C3CFGR_I3C3EN BIT(1) +#define RCC_I3C3CFGR_I3C3LPEN BIT(2) + +/* RCC_I3C4CFGR register fields */ +#define RCC_I3C4CFGR_I3C4RST BIT(0) +#define RCC_I3C4CFGR_I3C4EN BIT(1) +#define RCC_I3C4CFGR_I3C4LPEN BIT(2) +#define RCC_I3C4CFGR_I3C4AMEN BIT(3) + +/* RCC_I3CxCFGR register fields */ +#define RCC_I3CxCFGR_I3CxRST BIT(0) +#define RCC_I3CxCFGR_I3CxEN BIT(1) +#define RCC_I3CxCFGR_I3CxLPEN BIT(2) +#define RCC_I3CxCFGR_I3CxAMEN BIT(3) + +/* RCC_MUXSELCFGR register fields */ +#define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(1, 0) +#define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0 +#define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(5, 4) +#define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4 +#define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(9, 8) +#define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8 +#define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(13, 12) +#define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12 +#define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(17, 16) +#define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16 +#define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20) +#define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20 +#define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24) +#define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24 +#define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28) +#define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28 + +/* RCC_XBAR0CFGR register fields */ +#define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0 +#define RCC_XBAR0CFGR_XBAR0EN BIT(6) +#define RCC_XBAR0CFGR_XBAR0STS BIT(7) + +/* RCC_XBAR1CFGR register fields */ +#define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0 +#define RCC_XBAR1CFGR_XBAR1EN BIT(6) +#define RCC_XBAR1CFGR_XBAR1STS BIT(7) + +/* RCC_XBAR2CFGR register fields */ +#define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0 +#define RCC_XBAR2CFGR_XBAR2EN BIT(6) +#define RCC_XBAR2CFGR_XBAR2STS BIT(7) + +/* RCC_XBAR3CFGR register fields */ +#define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0 +#define RCC_XBAR3CFGR_XBAR3EN BIT(6) +#define RCC_XBAR3CFGR_XBAR3STS BIT(7) + +/* RCC_XBAR4CFGR register fields */ +#define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0 +#define RCC_XBAR4CFGR_XBAR4EN BIT(6) +#define RCC_XBAR4CFGR_XBAR4STS BIT(7) + +/* RCC_XBAR5CFGR register fields */ +#define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0 +#define RCC_XBAR5CFGR_XBAR5EN BIT(6) +#define RCC_XBAR5CFGR_XBAR5STS BIT(7) + +/* RCC_XBAR6CFGR register fields */ +#define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0 +#define RCC_XBAR6CFGR_XBAR6EN BIT(6) +#define RCC_XBAR6CFGR_XBAR6STS BIT(7) + +/* RCC_XBAR7CFGR register fields */ +#define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0 +#define RCC_XBAR7CFGR_XBAR7EN BIT(6) +#define RCC_XBAR7CFGR_XBAR7STS BIT(7) + +/* RCC_XBAR8CFGR register fields */ +#define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0 +#define RCC_XBAR8CFGR_XBAR8EN BIT(6) +#define RCC_XBAR8CFGR_XBAR8STS BIT(7) + +/* RCC_XBAR9CFGR register fields */ +#define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0 +#define RCC_XBAR9CFGR_XBAR9EN BIT(6) +#define RCC_XBAR9CFGR_XBAR9STS BIT(7) + +/* RCC_XBAR10CFGR register fields */ +#define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0 +#define RCC_XBAR10CFGR_XBAR10EN BIT(6) +#define RCC_XBAR10CFGR_XBAR10STS BIT(7) + +/* RCC_XBAR11CFGR register fields */ +#define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0 +#define RCC_XBAR11CFGR_XBAR11EN BIT(6) +#define RCC_XBAR11CFGR_XBAR11STS BIT(7) + +/* RCC_XBAR12CFGR register fields */ +#define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0 +#define RCC_XBAR12CFGR_XBAR12EN BIT(6) +#define RCC_XBAR12CFGR_XBAR12STS BIT(7) + +/* RCC_XBAR13CFGR register fields */ +#define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0 +#define RCC_XBAR13CFGR_XBAR13EN BIT(6) +#define RCC_XBAR13CFGR_XBAR13STS BIT(7) + +/* RCC_XBAR14CFGR register fields */ +#define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0 +#define RCC_XBAR14CFGR_XBAR14EN BIT(6) +#define RCC_XBAR14CFGR_XBAR14STS BIT(7) + +/* RCC_XBAR15CFGR register fields */ +#define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0 +#define RCC_XBAR15CFGR_XBAR15EN BIT(6) +#define RCC_XBAR15CFGR_XBAR15STS BIT(7) + +/* RCC_XBAR16CFGR register fields */ +#define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0 +#define RCC_XBAR16CFGR_XBAR16EN BIT(6) +#define RCC_XBAR16CFGR_XBAR16STS BIT(7) + +/* RCC_XBAR17CFGR register fields */ +#define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0 +#define RCC_XBAR17CFGR_XBAR17EN BIT(6) +#define RCC_XBAR17CFGR_XBAR17STS BIT(7) + +/* RCC_XBAR18CFGR register fields */ +#define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0 +#define RCC_XBAR18CFGR_XBAR18EN BIT(6) +#define RCC_XBAR18CFGR_XBAR18STS BIT(7) + +/* RCC_XBAR19CFGR register fields */ +#define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0 +#define RCC_XBAR19CFGR_XBAR19EN BIT(6) +#define RCC_XBAR19CFGR_XBAR19STS BIT(7) + +/* RCC_XBAR20CFGR register fields */ +#define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0 +#define RCC_XBAR20CFGR_XBAR20EN BIT(6) +#define RCC_XBAR20CFGR_XBAR20STS BIT(7) + +/* RCC_XBAR21CFGR register fields */ +#define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0 +#define RCC_XBAR21CFGR_XBAR21EN BIT(6) +#define RCC_XBAR21CFGR_XBAR21STS BIT(7) + +/* RCC_XBAR22CFGR register fields */ +#define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0 +#define RCC_XBAR22CFGR_XBAR22EN BIT(6) +#define RCC_XBAR22CFGR_XBAR22STS BIT(7) + +/* RCC_XBAR23CFGR register fields */ +#define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0 +#define RCC_XBAR23CFGR_XBAR23EN BIT(6) +#define RCC_XBAR23CFGR_XBAR23STS BIT(7) + +/* RCC_XBAR24CFGR register fields */ +#define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0 +#define RCC_XBAR24CFGR_XBAR24EN BIT(6) +#define RCC_XBAR24CFGR_XBAR24STS BIT(7) + +/* RCC_XBAR25CFGR register fields */ +#define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0 +#define RCC_XBAR25CFGR_XBAR25EN BIT(6) +#define RCC_XBAR25CFGR_XBAR25STS BIT(7) + +/* RCC_XBAR26CFGR register fields */ +#define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0 +#define RCC_XBAR26CFGR_XBAR26EN BIT(6) +#define RCC_XBAR26CFGR_XBAR26STS BIT(7) + +/* RCC_XBAR27CFGR register fields */ +#define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0 +#define RCC_XBAR27CFGR_XBAR27EN BIT(6) +#define RCC_XBAR27CFGR_XBAR27STS BIT(7) + +/* RCC_XBAR28CFGR register fields */ +#define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0 +#define RCC_XBAR28CFGR_XBAR28EN BIT(6) +#define RCC_XBAR28CFGR_XBAR28STS BIT(7) + +/* RCC_XBAR29CFGR register fields */ +#define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0 +#define RCC_XBAR29CFGR_XBAR29EN BIT(6) +#define RCC_XBAR29CFGR_XBAR29STS BIT(7) + +/* RCC_XBAR30CFGR register fields */ +#define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0 +#define RCC_XBAR30CFGR_XBAR30EN BIT(6) +#define RCC_XBAR30CFGR_XBAR30STS BIT(7) + +/* RCC_XBAR31CFGR register fields */ +#define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0 +#define RCC_XBAR31CFGR_XBAR31EN BIT(6) +#define RCC_XBAR31CFGR_XBAR31STS BIT(7) + +/* RCC_XBAR32CFGR register fields */ +#define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0 +#define RCC_XBAR32CFGR_XBAR32EN BIT(6) +#define RCC_XBAR32CFGR_XBAR32STS BIT(7) + +/* RCC_XBAR33CFGR register fields */ +#define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0 +#define RCC_XBAR33CFGR_XBAR33EN BIT(6) +#define RCC_XBAR33CFGR_XBAR33STS BIT(7) + +/* RCC_XBAR34CFGR register fields */ +#define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0 +#define RCC_XBAR34CFGR_XBAR34EN BIT(6) +#define RCC_XBAR34CFGR_XBAR34STS BIT(7) + +/* RCC_XBAR35CFGR register fields */ +#define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0 +#define RCC_XBAR35CFGR_XBAR35EN BIT(6) +#define RCC_XBAR35CFGR_XBAR35STS BIT(7) + +/* RCC_XBAR36CFGR register fields */ +#define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0 +#define RCC_XBAR36CFGR_XBAR36EN BIT(6) +#define RCC_XBAR36CFGR_XBAR36STS BIT(7) + +/* RCC_XBAR37CFGR register fields */ +#define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0 +#define RCC_XBAR37CFGR_XBAR37EN BIT(6) +#define RCC_XBAR37CFGR_XBAR37STS BIT(7) + +/* RCC_XBAR38CFGR register fields */ +#define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0 +#define RCC_XBAR38CFGR_XBAR38EN BIT(6) +#define RCC_XBAR38CFGR_XBAR38STS BIT(7) + +/* RCC_XBAR39CFGR register fields */ +#define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0 +#define RCC_XBAR39CFGR_XBAR39EN BIT(6) +#define RCC_XBAR39CFGR_XBAR39STS BIT(7) + +/* RCC_XBAR40CFGR register fields */ +#define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0 +#define RCC_XBAR40CFGR_XBAR40EN BIT(6) +#define RCC_XBAR40CFGR_XBAR40STS BIT(7) + +/* RCC_XBAR41CFGR register fields */ +#define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0 +#define RCC_XBAR41CFGR_XBAR41EN BIT(6) +#define RCC_XBAR41CFGR_XBAR41STS BIT(7) + +/* RCC_XBAR42CFGR register fields */ +#define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0 +#define RCC_XBAR42CFGR_XBAR42EN BIT(6) +#define RCC_XBAR42CFGR_XBAR42STS BIT(7) + +/* RCC_XBAR43CFGR register fields */ +#define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0 +#define RCC_XBAR43CFGR_XBAR43EN BIT(6) +#define RCC_XBAR43CFGR_XBAR43STS BIT(7) + +/* RCC_XBAR44CFGR register fields */ +#define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0 +#define RCC_XBAR44CFGR_XBAR44EN BIT(6) +#define RCC_XBAR44CFGR_XBAR44STS BIT(7) + +/* RCC_XBAR45CFGR register fields */ +#define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0 +#define RCC_XBAR45CFGR_XBAR45EN BIT(6) +#define RCC_XBAR45CFGR_XBAR45STS BIT(7) + +/* RCC_XBAR46CFGR register fields */ +#define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0 +#define RCC_XBAR46CFGR_XBAR46EN BIT(6) +#define RCC_XBAR46CFGR_XBAR46STS BIT(7) + +/* RCC_XBAR47CFGR register fields */ +#define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0 +#define RCC_XBAR47CFGR_XBAR47EN BIT(6) +#define RCC_XBAR47CFGR_XBAR47STS BIT(7) + +/* RCC_XBAR48CFGR register fields */ +#define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0 +#define RCC_XBAR48CFGR_XBAR48EN BIT(6) +#define RCC_XBAR48CFGR_XBAR48STS BIT(7) + +/* RCC_XBAR49CFGR register fields */ +#define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0 +#define RCC_XBAR49CFGR_XBAR49EN BIT(6) +#define RCC_XBAR49CFGR_XBAR49STS BIT(7) + +/* RCC_XBAR50CFGR register fields */ +#define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0 +#define RCC_XBAR50CFGR_XBAR50EN BIT(6) +#define RCC_XBAR50CFGR_XBAR50STS BIT(7) + +/* RCC_XBAR51CFGR register fields */ +#define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0 +#define RCC_XBAR51CFGR_XBAR51EN BIT(6) +#define RCC_XBAR51CFGR_XBAR51STS BIT(7) + +/* RCC_XBAR52CFGR register fields */ +#define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0 +#define RCC_XBAR52CFGR_XBAR52EN BIT(6) +#define RCC_XBAR52CFGR_XBAR52STS BIT(7) + +/* RCC_XBAR53CFGR register fields */ +#define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0 +#define RCC_XBAR53CFGR_XBAR53EN BIT(6) +#define RCC_XBAR53CFGR_XBAR53STS BIT(7) + +/* RCC_XBAR54CFGR register fields */ +#define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0 +#define RCC_XBAR54CFGR_XBAR54EN BIT(6) +#define RCC_XBAR54CFGR_XBAR54STS BIT(7) + +/* RCC_XBAR55CFGR register fields */ +#define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0 +#define RCC_XBAR55CFGR_XBAR55EN BIT(6) +#define RCC_XBAR55CFGR_XBAR55STS BIT(7) + +/* RCC_XBAR56CFGR register fields */ +#define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0 +#define RCC_XBAR56CFGR_XBAR56EN BIT(6) +#define RCC_XBAR56CFGR_XBAR56STS BIT(7) + +/* RCC_XBAR57CFGR register fields */ +#define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0 +#define RCC_XBAR57CFGR_XBAR57EN BIT(6) +#define RCC_XBAR57CFGR_XBAR57STS BIT(7) + +/* RCC_XBAR58CFGR register fields */ +#define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0 +#define RCC_XBAR58CFGR_XBAR58EN BIT(6) +#define RCC_XBAR58CFGR_XBAR58STS BIT(7) + +/* RCC_XBAR59CFGR register fields */ +#define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0 +#define RCC_XBAR59CFGR_XBAR59EN BIT(6) +#define RCC_XBAR59CFGR_XBAR59STS BIT(7) + +/* RCC_XBAR60CFGR register fields */ +#define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0 +#define RCC_XBAR60CFGR_XBAR60EN BIT(6) +#define RCC_XBAR60CFGR_XBAR60STS BIT(7) + +/* RCC_XBAR61CFGR register fields */ +#define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0 +#define RCC_XBAR61CFGR_XBAR61EN BIT(6) +#define RCC_XBAR61CFGR_XBAR61STS BIT(7) + +/* RCC_XBAR62CFGR register fields */ +#define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0 +#define RCC_XBAR62CFGR_XBAR62EN BIT(6) +#define RCC_XBAR62CFGR_XBAR62STS BIT(7) + +/* RCC_XBAR63CFGR register fields */ +#define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0) +#define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0 +#define RCC_XBAR63CFGR_XBAR63EN BIT(6) +#define RCC_XBAR63CFGR_XBAR63STS BIT(7) + +/* RCC_XBARxCFGR register fields */ +#define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0) +#define RCC_XBARxCFGR_XBARxSEL_SHIFT 0 +#define RCC_XBARxCFGR_XBARxEN BIT(6) +#define RCC_XBARxCFGR_XBARxSTS BIT(7) + +/* RCC_PREDIV0CFGR register fields */ +#define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0) +#define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0 + +/* RCC_PREDIV1CFGR register fields */ +#define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0) +#define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0 + +/* RCC_PREDIV2CFGR register fields */ +#define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0) +#define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0 + +/* RCC_PREDIV3CFGR register fields */ +#define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0) +#define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0 + +/* RCC_PREDIV4CFGR register fields */ +#define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0) +#define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0 + +/* RCC_PREDIV5CFGR register fields */ +#define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0) +#define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0 + +/* RCC_PREDIV6CFGR register fields */ +#define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0) +#define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0 + +/* RCC_PREDIV7CFGR register fields */ +#define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0) +#define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0 + +/* RCC_PREDIV8CFGR register fields */ +#define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0) +#define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0 + +/* RCC_PREDIV9CFGR register fields */ +#define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0) +#define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0 + +/* RCC_PREDIV10CFGR register fields */ +#define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0) +#define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0 + +/* RCC_PREDIV11CFGR register fields */ +#define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0) +#define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0 + +/* RCC_PREDIV12CFGR register fields */ +#define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0) +#define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0 + +/* RCC_PREDIV13CFGR register fields */ +#define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0) +#define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0 + +/* RCC_PREDIV14CFGR register fields */ +#define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0) +#define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0 + +/* RCC_PREDIV15CFGR register fields */ +#define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0) +#define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0 + +/* RCC_PREDIV16CFGR register fields */ +#define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0) +#define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0 + +/* RCC_PREDIV17CFGR register fields */ +#define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0) +#define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0 + +/* RCC_PREDIV18CFGR register fields */ +#define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0) +#define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0 + +/* RCC_PREDIV19CFGR register fields */ +#define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0) +#define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0 + +/* RCC_PREDIV20CFGR register fields */ +#define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0) +#define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0 + +/* RCC_PREDIV21CFGR register fields */ +#define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0) +#define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0 + +/* RCC_PREDIV22CFGR register fields */ +#define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0) +#define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0 + +/* RCC_PREDIV23CFGR register fields */ +#define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0) +#define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0 + +/* RCC_PREDIV24CFGR register fields */ +#define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0) +#define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0 + +/* RCC_PREDIV25CFGR register fields */ +#define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0) +#define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0 + +/* RCC_PREDIV26CFGR register fields */ +#define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0) +#define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0 + +/* RCC_PREDIV27CFGR register fields */ +#define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0) +#define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0 + +/* RCC_PREDIV28CFGR register fields */ +#define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0) +#define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0 + +/* RCC_PREDIV29CFGR register fields */ +#define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0) +#define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0 + +/* RCC_PREDIV30CFGR register fields */ +#define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0) +#define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0 + +/* RCC_PREDIV31CFGR register fields */ +#define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0) +#define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0 + +/* RCC_PREDIV32CFGR register fields */ +#define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0) +#define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0 + +/* RCC_PREDIV33CFGR register fields */ +#define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0) +#define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0 + +/* RCC_PREDIV34CFGR register fields */ +#define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0) +#define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0 + +/* RCC_PREDIV35CFGR register fields */ +#define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0) +#define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0 + +/* RCC_PREDIV36CFGR register fields */ +#define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0) +#define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0 + +/* RCC_PREDIV37CFGR register fields */ +#define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0) +#define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0 + +/* RCC_PREDIV38CFGR register fields */ +#define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0) +#define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0 + +/* RCC_PREDIV39CFGR register fields */ +#define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0) +#define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0 + +/* RCC_PREDIV40CFGR register fields */ +#define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0) +#define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0 + +/* RCC_PREDIV41CFGR register fields */ +#define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0) +#define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0 + +/* RCC_PREDIV42CFGR register fields */ +#define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0) +#define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0 + +/* RCC_PREDIV43CFGR register fields */ +#define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0) +#define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0 + +/* RCC_PREDIV44CFGR register fields */ +#define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0) +#define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0 + +/* RCC_PREDIV45CFGR register fields */ +#define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0) +#define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0 + +/* RCC_PREDIV46CFGR register fields */ +#define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0) +#define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0 + +/* RCC_PREDIV47CFGR register fields */ +#define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0) +#define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0 + +/* RCC_PREDIV48CFGR register fields */ +#define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0) +#define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0 + +/* RCC_PREDIV49CFGR register fields */ +#define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0) +#define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0 + +/* RCC_PREDIV50CFGR register fields */ +#define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0) +#define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0 + +/* RCC_PREDIV51CFGR register fields */ +#define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0) +#define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0 + +/* RCC_PREDIV52CFGR register fields */ +#define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0) +#define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0 + +/* RCC_PREDIV53CFGR register fields */ +#define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0) +#define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0 + +/* RCC_PREDIV54CFGR register fields */ +#define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0) +#define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0 + +/* RCC_PREDIV55CFGR register fields */ +#define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0) +#define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0 + +/* RCC_PREDIV56CFGR register fields */ +#define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0) +#define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0 + +/* RCC_PREDIV57CFGR register fields */ +#define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0) +#define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0 + +/* RCC_PREDIV58CFGR register fields */ +#define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0) +#define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0 + +/* RCC_PREDIV59CFGR register fields */ +#define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0) +#define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0 + +/* RCC_PREDIV60CFGR register fields */ +#define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0) +#define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0 + +/* RCC_PREDIV61CFGR register fields */ +#define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0) +#define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0 + +/* RCC_PREDIV62CFGR register fields */ +#define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0) +#define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0 + +/* RCC_PREDIV63CFGR register fields */ +#define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0) +#define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0 + +/* RCC_PREDIVxCFGR register fields */ +#define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0) +#define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0 + +/* RCC_FINDIV0CFGR register fields */ +#define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) +#define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0 +#define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) + +/* RCC_FINDIV1CFGR register fields */ +#define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0) +#define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0 +#define RCC_FINDIV1CFGR_FINDIV1EN BIT(6) + +/* RCC_FINDIV2CFGR register fields */ +#define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0) +#define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0 +#define RCC_FINDIV2CFGR_FINDIV2EN BIT(6) + +/* RCC_FINDIV3CFGR register fields */ +#define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0) +#define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0 +#define RCC_FINDIV3CFGR_FINDIV3EN BIT(6) + +/* RCC_FINDIV4CFGR register fields */ +#define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0) +#define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0 +#define RCC_FINDIV4CFGR_FINDIV4EN BIT(6) + +/* RCC_FINDIV5CFGR register fields */ +#define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0) +#define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0 +#define RCC_FINDIV5CFGR_FINDIV5EN BIT(6) + +/* RCC_FINDIV6CFGR register fields */ +#define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0) +#define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0 +#define RCC_FINDIV6CFGR_FINDIV6EN BIT(6) + +/* RCC_FINDIV7CFGR register fields */ +#define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0) +#define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0 +#define RCC_FINDIV7CFGR_FINDIV7EN BIT(6) + +/* RCC_FINDIV8CFGR register fields */ +#define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0) +#define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0 +#define RCC_FINDIV8CFGR_FINDIV8EN BIT(6) + +/* RCC_FINDIV9CFGR register fields */ +#define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0) +#define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0 +#define RCC_FINDIV9CFGR_FINDIV9EN BIT(6) + +/* RCC_FINDIV10CFGR register fields */ +#define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0) +#define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0 +#define RCC_FINDIV10CFGR_FINDIV10EN BIT(6) + +/* RCC_FINDIV11CFGR register fields */ +#define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0) +#define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0 +#define RCC_FINDIV11CFGR_FINDIV11EN BIT(6) + +/* RCC_FINDIV12CFGR register fields */ +#define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0) +#define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0 +#define RCC_FINDIV12CFGR_FINDIV12EN BIT(6) + +/* RCC_FINDIV13CFGR register fields */ +#define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0) +#define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0 +#define RCC_FINDIV13CFGR_FINDIV13EN BIT(6) + +/* RCC_FINDIV14CFGR register fields */ +#define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0) +#define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0 +#define RCC_FINDIV14CFGR_FINDIV14EN BIT(6) + +/* RCC_FINDIV15CFGR register fields */ +#define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0) +#define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0 +#define RCC_FINDIV15CFGR_FINDIV15EN BIT(6) + +/* RCC_FINDIV16CFGR register fields */ +#define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0) +#define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0 +#define RCC_FINDIV16CFGR_FINDIV16EN BIT(6) + +/* RCC_FINDIV17CFGR register fields */ +#define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0) +#define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0 +#define RCC_FINDIV17CFGR_FINDIV17EN BIT(6) + +/* RCC_FINDIV18CFGR register fields */ +#define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0) +#define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0 +#define RCC_FINDIV18CFGR_FINDIV18EN BIT(6) + +/* RCC_FINDIV19CFGR register fields */ +#define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0) +#define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0 +#define RCC_FINDIV19CFGR_FINDIV19EN BIT(6) + +/* RCC_FINDIV20CFGR register fields */ +#define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0) +#define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0 +#define RCC_FINDIV20CFGR_FINDIV20EN BIT(6) + +/* RCC_FINDIV21CFGR register fields */ +#define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0) +#define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0 +#define RCC_FINDIV21CFGR_FINDIV21EN BIT(6) + +/* RCC_FINDIV22CFGR register fields */ +#define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0) +#define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0 +#define RCC_FINDIV22CFGR_FINDIV22EN BIT(6) + +/* RCC_FINDIV23CFGR register fields */ +#define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0) +#define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0 +#define RCC_FINDIV23CFGR_FINDIV23EN BIT(6) + +/* RCC_FINDIV24CFGR register fields */ +#define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0) +#define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0 +#define RCC_FINDIV24CFGR_FINDIV24EN BIT(6) + +/* RCC_FINDIV25CFGR register fields */ +#define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0) +#define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0 +#define RCC_FINDIV25CFGR_FINDIV25EN BIT(6) + +/* RCC_FINDIV26CFGR register fields */ +#define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0) +#define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0 +#define RCC_FINDIV26CFGR_FINDIV26EN BIT(6) + +/* RCC_FINDIV27CFGR register fields */ +#define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0) +#define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0 +#define RCC_FINDIV27CFGR_FINDIV27EN BIT(6) + +/* RCC_FINDIV28CFGR register fields */ +#define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0) +#define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0 +#define RCC_FINDIV28CFGR_FINDIV28EN BIT(6) + +/* RCC_FINDIV29CFGR register fields */ +#define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0) +#define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0 +#define RCC_FINDIV29CFGR_FINDIV29EN BIT(6) + +/* RCC_FINDIV30CFGR register fields */ +#define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0) +#define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0 +#define RCC_FINDIV30CFGR_FINDIV30EN BIT(6) + +/* RCC_FINDIV31CFGR register fields */ +#define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0) +#define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0 +#define RCC_FINDIV31CFGR_FINDIV31EN BIT(6) + +/* RCC_FINDIV32CFGR register fields */ +#define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0) +#define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0 +#define RCC_FINDIV32CFGR_FINDIV32EN BIT(6) + +/* RCC_FINDIV33CFGR register fields */ +#define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0) +#define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0 +#define RCC_FINDIV33CFGR_FINDIV33EN BIT(6) + +/* RCC_FINDIV34CFGR register fields */ +#define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0) +#define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0 +#define RCC_FINDIV34CFGR_FINDIV34EN BIT(6) + +/* RCC_FINDIV35CFGR register fields */ +#define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0) +#define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0 +#define RCC_FINDIV35CFGR_FINDIV35EN BIT(6) + +/* RCC_FINDIV36CFGR register fields */ +#define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0) +#define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0 +#define RCC_FINDIV36CFGR_FINDIV36EN BIT(6) + +/* RCC_FINDIV37CFGR register fields */ +#define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0) +#define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0 +#define RCC_FINDIV37CFGR_FINDIV37EN BIT(6) + +/* RCC_FINDIV38CFGR register fields */ +#define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0) +#define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0 +#define RCC_FINDIV38CFGR_FINDIV38EN BIT(6) + +/* RCC_FINDIV39CFGR register fields */ +#define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0) +#define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0 +#define RCC_FINDIV39CFGR_FINDIV39EN BIT(6) + +/* RCC_FINDIV40CFGR register fields */ +#define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0) +#define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0 +#define RCC_FINDIV40CFGR_FINDIV40EN BIT(6) + +/* RCC_FINDIV41CFGR register fields */ +#define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0) +#define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0 +#define RCC_FINDIV41CFGR_FINDIV41EN BIT(6) + +/* RCC_FINDIV42CFGR register fields */ +#define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0) +#define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0 +#define RCC_FINDIV42CFGR_FINDIV42EN BIT(6) + +/* RCC_FINDIV43CFGR register fields */ +#define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0) +#define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0 +#define RCC_FINDIV43CFGR_FINDIV43EN BIT(6) + +/* RCC_FINDIV44CFGR register fields */ +#define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0) +#define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0 +#define RCC_FINDIV44CFGR_FINDIV44EN BIT(6) + +/* RCC_FINDIV45CFGR register fields */ +#define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0) +#define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0 +#define RCC_FINDIV45CFGR_FINDIV45EN BIT(6) + +/* RCC_FINDIV46CFGR register fields */ +#define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0) +#define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0 +#define RCC_FINDIV46CFGR_FINDIV46EN BIT(6) + +/* RCC_FINDIV47CFGR register fields */ +#define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0) +#define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0 +#define RCC_FINDIV47CFGR_FINDIV47EN BIT(6) + +/* RCC_FINDIV48CFGR register fields */ +#define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0) +#define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0 +#define RCC_FINDIV48CFGR_FINDIV48EN BIT(6) + +/* RCC_FINDIV49CFGR register fields */ +#define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0) +#define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0 +#define RCC_FINDIV49CFGR_FINDIV49EN BIT(6) + +/* RCC_FINDIV50CFGR register fields */ +#define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0) +#define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0 +#define RCC_FINDIV50CFGR_FINDIV50EN BIT(6) + +/* RCC_FINDIV51CFGR register fields */ +#define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0) +#define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0 +#define RCC_FINDIV51CFGR_FINDIV51EN BIT(6) + +/* RCC_FINDIV52CFGR register fields */ +#define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0) +#define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0 +#define RCC_FINDIV52CFGR_FINDIV52EN BIT(6) + +/* RCC_FINDIV53CFGR register fields */ +#define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0) +#define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0 +#define RCC_FINDIV53CFGR_FINDIV53EN BIT(6) + +/* RCC_FINDIV54CFGR register fields */ +#define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0) +#define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0 +#define RCC_FINDIV54CFGR_FINDIV54EN BIT(6) + +/* RCC_FINDIV55CFGR register fields */ +#define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0) +#define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0 +#define RCC_FINDIV55CFGR_FINDIV55EN BIT(6) + +/* RCC_FINDIV56CFGR register fields */ +#define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0) +#define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0 +#define RCC_FINDIV56CFGR_FINDIV56EN BIT(6) + +/* RCC_FINDIV57CFGR register fields */ +#define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0) +#define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0 +#define RCC_FINDIV57CFGR_FINDIV57EN BIT(6) + +/* RCC_FINDIV58CFGR register fields */ +#define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0) +#define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0 +#define RCC_FINDIV58CFGR_FINDIV58EN BIT(6) + +/* RCC_FINDIV59CFGR register fields */ +#define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0) +#define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0 +#define RCC_FINDIV59CFGR_FINDIV59EN BIT(6) + +/* RCC_FINDIV60CFGR register fields */ +#define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0) +#define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0 +#define RCC_FINDIV60CFGR_FINDIV60EN BIT(6) + +/* RCC_FINDIV61CFGR register fields */ +#define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0) +#define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0 +#define RCC_FINDIV61CFGR_FINDIV61EN BIT(6) + +/* RCC_FINDIV62CFGR register fields */ +#define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0) +#define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0 +#define RCC_FINDIV62CFGR_FINDIV62EN BIT(6) + +/* RCC_FINDIV63CFGR register fields */ +#define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0) +#define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0 +#define RCC_FINDIV63CFGR_FINDIV63EN BIT(6) + +/* RCC_FINDIVxCFGR register fields */ +#define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0) +#define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0 +#define RCC_FINDIVxCFGR_FINDIVxEN BIT(6) + +/* RCC_FCALCOBS0CFGR register fields */ +#define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0) +#define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0 +#define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) +#define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8 +#define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15) +#define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16) +#define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17) +#define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18) +#define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) +#define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22 +#define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25) +#define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26) + +/* RCC_FCALCOBS1CFGR register fields */ +#define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0) +#define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0 +#define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) +#define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8 +#define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16) +#define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18) +#define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) +#define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22 +#define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26) +#define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27) + +/* RCC_FCALCREFCFGR register fields */ +#define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0) +#define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0 + +/* RCC_FCALCCR1 register fields */ +#define RCC_FCALCCR1_FCALCRUN BIT(0) + +/* RCC_FCALCCR2 register fields */ +#define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3) +#define RCC_FCALCCR2_FCALCMD_SHIFT 3 +#define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11) +#define RCC_FCALCCR2_FCALCTWC_SHIFT 11 +#define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17) +#define RCC_FCALCCR2_FCALCTYP_SHIFT 17 + +/* RCC_FCALCSR register fields */ +#define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0) +#define RCC_FCALCSR_FVAL_SHIFT 0 +#define RCC_FCALCSR_FCALCSTS BIT(19) + +/* RCC_PLL4CFGR1 register fields */ +#define RCC_PLL4CFGR1_SSMODRST BIT(0) +#define RCC_PLL4CFGR1_PLLEN BIT(8) +#define RCC_PLL4CFGR1_PLLRDY BIT(24) +#define RCC_PLL4CFGR1_CKREFST BIT(28) + +/* RCC_PLL4CFGR2 register fields */ +#define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL4CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL4CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL4CFGR3 register fields */ +#define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL4CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL4CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL4CFGR3_DACEN BIT(25) +#define RCC_PLL4CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL4CFGR4 register fields */ +#define RCC_PLL4CFGR4_DSMEN BIT(8) +#define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL4CFGR4_BYPASS BIT(10) + +/* RCC_PLL4CFGR5 register fields */ +#define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL4CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL4CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL4CFGR6 register fields */ +#define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL4CFGR7 register fields */ +#define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL5CFGR1 register fields */ +#define RCC_PLL5CFGR1_SSMODRST BIT(0) +#define RCC_PLL5CFGR1_PLLEN BIT(8) +#define RCC_PLL5CFGR1_PLLRDY BIT(24) +#define RCC_PLL5CFGR1_CKREFST BIT(28) + +/* RCC_PLL5CFGR2 register fields */ +#define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL5CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL5CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL5CFGR3 register fields */ +#define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL5CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL5CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL5CFGR3_DACEN BIT(25) +#define RCC_PLL5CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL5CFGR4 register fields */ +#define RCC_PLL5CFGR4_DSMEN BIT(8) +#define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL5CFGR4_BYPASS BIT(10) + +/* RCC_PLL5CFGR5 register fields */ +#define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL5CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL5CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL5CFGR6 register fields */ +#define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL5CFGR7 register fields */ +#define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL6CFGR1 register fields */ +#define RCC_PLL6CFGR1_SSMODRST BIT(0) +#define RCC_PLL6CFGR1_PLLEN BIT(8) +#define RCC_PLL6CFGR1_PLLRDY BIT(24) +#define RCC_PLL6CFGR1_CKREFST BIT(28) + +/* RCC_PLL6CFGR2 register fields */ +#define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL6CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL6CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL6CFGR3 register fields */ +#define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL6CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL6CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL6CFGR3_DACEN BIT(25) +#define RCC_PLL6CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL6CFGR4 register fields */ +#define RCC_PLL6CFGR4_DSMEN BIT(8) +#define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL6CFGR4_BYPASS BIT(10) + +/* RCC_PLL6CFGR5 register fields */ +#define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL6CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL6CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL6CFGR6 register fields */ +#define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL6CFGR7 register fields */ +#define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL7CFGR1 register fields */ +#define RCC_PLL7CFGR1_SSMODRST BIT(0) +#define RCC_PLL7CFGR1_PLLEN BIT(8) +#define RCC_PLL7CFGR1_PLLRDY BIT(24) +#define RCC_PLL7CFGR1_CKREFST BIT(28) + +/* RCC_PLL7CFGR2 register fields */ +#define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL7CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL7CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL7CFGR3 register fields */ +#define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL7CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL7CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL7CFGR3_DACEN BIT(25) +#define RCC_PLL7CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL7CFGR4 register fields */ +#define RCC_PLL7CFGR4_DSMEN BIT(8) +#define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL7CFGR4_BYPASS BIT(10) + +/* RCC_PLL7CFGR5 register fields */ +#define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL7CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL7CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL7CFGR6 register fields */ +#define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL7CFGR7 register fields */ +#define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLL8CFGR1 register fields */ +#define RCC_PLL8CFGR1_SSMODRST BIT(0) +#define RCC_PLL8CFGR1_PLLEN BIT(8) +#define RCC_PLL8CFGR1_PLLRDY BIT(24) +#define RCC_PLL8CFGR1_CKREFST BIT(28) + +/* RCC_PLL8CFGR2 register fields */ +#define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLL8CFGR2_FREFDIV_SHIFT 0 +#define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLL8CFGR2_FBDIV_SHIFT 16 + +/* RCC_PLL8CFGR3 register fields */ +#define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLL8CFGR3_FRACIN_SHIFT 0 +#define RCC_PLL8CFGR3_DOWNSPREAD BIT(24) +#define RCC_PLL8CFGR3_DACEN BIT(25) +#define RCC_PLL8CFGR3_SSCGDIS BIT(26) + +/* RCC_PLL8CFGR4 register fields */ +#define RCC_PLL8CFGR4_DSMEN BIT(8) +#define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLL8CFGR4_BYPASS BIT(10) + +/* RCC_PLL8CFGR5 register fields */ +#define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLL8CFGR5_DIVVAL_SHIFT 0 +#define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLL8CFGR5_SPREAD_SHIFT 16 + +/* RCC_PLL8CFGR6 register fields */ +#define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLL8CFGR7 register fields */ +#define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0 + +/* RCC_PLLxCFGR1 register fields */ +#define RCC_PLLxCFGR1_SSMODRST BIT(0) +#define RCC_PLLxCFGR1_PLLEN BIT(8) +#define RCC_PLLxCFGR1_PLLRDY BIT(24) +#define RCC_PLLxCFGR1_CKREFST BIT(28) + +/* RCC_PLLxCFGR2 register fields */ +#define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) +#define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 +#define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) +#define RCC_PLLxCFGR2_FBDIV_SHIFT 16 + +/* RCC_PLLxCFGR3 register fields */ +#define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) +#define RCC_PLLxCFGR3_FRACIN_SHIFT 0 +#define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) +#define RCC_PLLxCFGR3_DACEN BIT(25) +#define RCC_PLLxCFGR3_SSCGDIS BIT(26) + +/* RCC_PLLxCFGR4 register fields */ +#define RCC_PLLxCFGR4_DSMEN BIT(8) +#define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) +#define RCC_PLLxCFGR4_BYPASS BIT(10) + +/* RCC_PLLxCFGR5 register fields */ +#define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) +#define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 +#define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) +#define RCC_PLLxCFGR5_SPREAD_SHIFT 16 + +/* RCC_PLLxCFGR6 register fields */ +#define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 + +/* RCC_PLLxCFGR7 register fields */ +#define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) +#define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 + +/* RCC_VERR register fields */ +#define RCC_VERR_MINREV_MASK GENMASK_32(3, 0) +#define RCC_VERR_MINREV_SHIFT 0 +#define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4) +#define RCC_VERR_MAJREV_SHIFT 4 + +#endif /* STM32MP2_RCC_H */
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h index 1efca42..4535e3c 100644 --- a/include/drivers/st/stm32mp_ddr.h +++ b/include/drivers/st/stm32mp_ddr.h
@@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -53,8 +53,8 @@ struct stm32mp_ddr_info { const char *name; - uint32_t speed; /* in kHZ */ - uint32_t size; /* Memory size in byte = col * row * width */ + uint32_t speed; /* in kHz */ + size_t size; /* Memory size in byte = col * row * width */ }; #define TIMEOUT_US_1S 1000000U
diff --git a/include/drivers/st/stm32mp_ddr_test.h b/include/drivers/st/stm32mp_ddr_test.h index 34e522a..cef5b48 100644 --- a/include/drivers/st/stm32mp_ddr_test.h +++ b/include/drivers/st/stm32mp_ddr_test.h
@@ -1,5 +1,5 @@ /* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,9 +9,9 @@ #include <stdint.h> -uint32_t stm32mp_ddr_test_rw_access(void); -uint32_t stm32mp_ddr_test_data_bus(void); -uint32_t stm32mp_ddr_test_addr_bus(uint64_t size); -uint32_t stm32mp_ddr_check_size(void); +uintptr_t stm32mp_ddr_test_rw_access(void); +uintptr_t stm32mp_ddr_test_data_bus(void); +uintptr_t stm32mp_ddr_test_addr_bus(size_t size); +size_t stm32mp_ddr_check_size(void); #endif /* STM32MP_DDR_TEST_H */
diff --git a/include/dt-bindings/clock/stm32mp25-clks.h b/include/dt-bindings/clock/stm32mp25-clks.h new file mode 100644 index 0000000..c4ff9cf --- /dev/null +++ b/include/dt-bindings/clock/stm32mp25-clks.h
@@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_ +#define _DT_BINDINGS_STM32MP25_CLKS_H_ + +/* INTERNAL/EXTERNAL OSCILLATORS */ +#define HSI_CK 0 +#define HSE_CK 1 +#define MSI_CK 2 +#define LSI_CK 3 +#define LSE_CK 4 +#define I2S_CK 5 +#define RTC_CK 6 +#define SPDIF_CK_SYMB 7 + +/* PLL CLOCKS */ +#define PLL1_CK 8 +#define PLL2_CK 9 +#define PLL3_CK 10 +#define PLL4_CK 11 +#define PLL5_CK 12 +#define PLL6_CK 13 +#define PLL7_CK 14 +#define PLL8_CK 15 + +#define CK_CPU1 16 + +/* APB DIV CLOCKS */ +#define CK_ICN_APB1 17 +#define CK_ICN_APB2 18 +#define CK_ICN_APB3 19 +#define CK_ICN_APB4 20 +#define CK_ICN_APBDBG 21 + +/* GLOBAL TIMER */ +#define TIMG1_CK 22 +#define TIMG2_CK 23 + +/* FLEXGEN CLOCKS */ +#define CK_ICN_HS_MCU 24 +#define CK_ICN_SDMMC 25 +#define CK_ICN_DDR 26 +#define CK_ICN_DISPLAY 27 +#define CK_ICN_HSL 28 +#define CK_ICN_NIC 29 +#define CK_ICN_VID 30 +#define CK_FLEXGEN_07 31 +#define CK_FLEXGEN_08 32 +#define CK_FLEXGEN_09 33 +#define CK_FLEXGEN_10 34 +#define CK_FLEXGEN_11 35 +#define CK_FLEXGEN_12 36 +#define CK_FLEXGEN_13 37 +#define CK_FLEXGEN_14 38 +#define CK_FLEXGEN_15 39 +#define CK_FLEXGEN_16 40 +#define CK_FLEXGEN_17 41 +#define CK_FLEXGEN_18 42 +#define CK_FLEXGEN_19 43 +#define CK_FLEXGEN_20 44 +#define CK_FLEXGEN_21 45 +#define CK_FLEXGEN_22 46 +#define CK_FLEXGEN_23 47 +#define CK_FLEXGEN_24 48 +#define CK_FLEXGEN_25 49 +#define CK_FLEXGEN_26 50 +#define CK_FLEXGEN_27 51 +#define CK_FLEXGEN_28 52 +#define CK_FLEXGEN_29 53 +#define CK_FLEXGEN_30 54 +#define CK_FLEXGEN_31 55 +#define CK_FLEXGEN_32 56 +#define CK_FLEXGEN_33 57 +#define CK_FLEXGEN_34 58 +#define CK_FLEXGEN_35 59 +#define CK_FLEXGEN_36 60 +#define CK_FLEXGEN_37 61 +#define CK_FLEXGEN_38 62 +#define CK_FLEXGEN_39 63 +#define CK_FLEXGEN_40 64 +#define CK_FLEXGEN_41 65 +#define CK_FLEXGEN_42 66 +#define CK_FLEXGEN_43 67 +#define CK_FLEXGEN_44 68 +#define CK_FLEXGEN_45 69 +#define CK_FLEXGEN_46 70 +#define CK_FLEXGEN_47 71 +#define CK_FLEXGEN_48 72 +#define CK_FLEXGEN_49 73 +#define CK_FLEXGEN_50 74 +#define CK_FLEXGEN_51 75 +#define CK_FLEXGEN_52 76 +#define CK_FLEXGEN_53 77 +#define CK_FLEXGEN_54 78 +#define CK_FLEXGEN_55 79 +#define CK_FLEXGEN_56 80 +#define CK_FLEXGEN_57 81 +#define CK_FLEXGEN_58 82 +#define CK_FLEXGEN_59 83 +#define CK_FLEXGEN_60 84 +#define CK_FLEXGEN_61 85 +#define CK_FLEXGEN_62 86 +#define CK_FLEXGEN_63 87 + +/* LOW SPEED MCU CLOCK */ +#define CK_ICN_LS_MCU 88 + +#define CK_BUS_STM500 89 +#define CK_BUS_FMC 90 +#define CK_BUS_GPU 91 +#define CK_BUS_ETH1 92 +#define CK_BUS_ETH2 93 +#define CK_BUS_PCIE 94 +#define CK_BUS_DDRPHYC 95 +#define CK_BUS_SYSCPU1 96 +#define CK_BUS_ETHSW 97 +#define CK_BUS_HPDMA1 98 +#define CK_BUS_HPDMA2 99 +#define CK_BUS_HPDMA3 100 +#define CK_BUS_ADC12 101 +#define CK_BUS_ADC3 102 +#define CK_BUS_IPCC1 103 +#define CK_BUS_CCI 104 +#define CK_BUS_CRC 105 +#define CK_BUS_MDF1 106 +#define CK_BUS_OSPIIOM 107 +#define CK_BUS_BKPSRAM 108 +#define CK_BUS_HASH 109 +#define CK_BUS_RNG 110 +#define CK_BUS_CRYP1 111 +#define CK_BUS_CRYP2 112 +#define CK_BUS_SAES 113 +#define CK_BUS_PKA 114 +#define CK_BUS_GPIOA 115 +#define CK_BUS_GPIOB 116 +#define CK_BUS_GPIOC 117 +#define CK_BUS_GPIOD 118 +#define CK_BUS_GPIOE 119 +#define CK_BUS_GPIOF 120 +#define CK_BUS_GPIOG 121 +#define CK_BUS_GPIOH 122 +#define CK_BUS_GPIOI 123 +#define CK_BUS_GPIOJ 124 +#define CK_BUS_GPIOK 125 +#define CK_BUS_LPSRAM1 126 +#define CK_BUS_LPSRAM2 127 +#define CK_BUS_LPSRAM3 128 +#define CK_BUS_GPIOZ 129 +#define CK_BUS_LPDMA 130 +#define CK_BUS_HSEM 131 +#define CK_BUS_IPCC2 132 +#define CK_BUS_RTC 133 +#define CK_BUS_SPI8 134 +#define CK_BUS_LPUART1 135 +#define CK_BUS_I2C8 136 +#define CK_BUS_LPTIM3 137 +#define CK_BUS_LPTIM4 138 +#define CK_BUS_LPTIM5 139 +#define CK_BUS_IWDG5 140 +#define CK_BUS_WWDG2 141 +#define CK_BUS_I3C4 142 +#define CK_BUS_TIM2 143 +#define CK_BUS_TIM3 144 +#define CK_BUS_TIM4 145 +#define CK_BUS_TIM5 146 +#define CK_BUS_TIM6 147 +#define CK_BUS_TIM7 148 +#define CK_BUS_TIM10 149 +#define CK_BUS_TIM11 150 +#define CK_BUS_TIM12 151 +#define CK_BUS_TIM13 152 +#define CK_BUS_TIM14 153 +#define CK_BUS_LPTIM1 154 +#define CK_BUS_LPTIM2 155 +#define CK_BUS_SPI2 156 +#define CK_BUS_SPI3 157 +#define CK_BUS_SPDIFRX 158 +#define CK_BUS_USART2 159 +#define CK_BUS_USART3 160 +#define CK_BUS_UART4 161 +#define CK_BUS_UART5 162 +#define CK_BUS_I2C1 163 +#define CK_BUS_I2C2 164 +#define CK_BUS_I2C3 165 +#define CK_BUS_I2C4 166 +#define CK_BUS_I2C5 167 +#define CK_BUS_I2C6 168 +#define CK_BUS_I2C7 169 +#define CK_BUS_I3C1 170 +#define CK_BUS_I3C2 171 +#define CK_BUS_I3C3 172 +#define CK_BUS_TIM1 173 +#define CK_BUS_TIM8 174 +#define CK_BUS_TIM15 175 +#define CK_BUS_TIM16 176 +#define CK_BUS_TIM17 177 +#define CK_BUS_TIM20 178 +#define CK_BUS_SAI1 179 +#define CK_BUS_SAI2 180 +#define CK_BUS_SAI3 181 +#define CK_BUS_SAI4 182 +#define CK_BUS_USART1 183 +#define CK_BUS_USART6 184 +#define CK_BUS_UART7 185 +#define CK_BUS_UART8 186 +#define CK_BUS_UART9 187 +#define CK_BUS_FDCAN 188 +#define CK_BUS_SPI1 189 +#define CK_BUS_SPI4 190 +#define CK_BUS_SPI5 191 +#define CK_BUS_SPI6 192 +#define CK_BUS_SPI7 193 +#define CK_BUS_BSEC 194 +#define CK_BUS_IWDG1 195 +#define CK_BUS_IWDG2 196 +#define CK_BUS_IWDG3 197 +#define CK_BUS_IWDG4 198 +#define CK_BUS_WWDG1 199 +#define CK_BUS_VREF 200 +#define CK_BUS_DTS 201 +#define CK_BUS_SERC 202 +#define CK_BUS_HDP 203 +#define CK_BUS_IS2M 204 +#define CK_BUS_DSI 205 +#define CK_BUS_LTDC 206 +#define CK_BUS_CSI 207 +#define CK_BUS_DCMIPP 208 +#define CK_BUS_DDRC 209 +#define CK_BUS_DDRCFG 210 +#define CK_BUS_GICV2M 211 +#define CK_BUS_USBTC 212 +#define CK_BUS_BUSPERFM 213 +#define CK_BUS_USB3PCIEPHY 214 +#define CK_BUS_STGEN 215 +#define CK_BUS_VDEC 216 +#define CK_BUS_VENC 217 +#define CK_SYSDBG 218 +#define CK_KER_TIM2 219 +#define CK_KER_TIM3 220 +#define CK_KER_TIM4 221 +#define CK_KER_TIM5 222 +#define CK_KER_TIM6 223 +#define CK_KER_TIM7 224 +#define CK_KER_TIM10 225 +#define CK_KER_TIM11 226 +#define CK_KER_TIM12 227 +#define CK_KER_TIM13 228 +#define CK_KER_TIM14 229 +#define CK_KER_TIM1 230 +#define CK_KER_TIM8 231 +#define CK_KER_TIM15 232 +#define CK_KER_TIM16 233 +#define CK_KER_TIM17 234 +#define CK_KER_TIM20 235 +#define CK_BUS_SYSRAM 236 +#define CK_BUS_VDERAM 237 +#define CK_BUS_RETRAM 238 +#define CK_BUS_OSPI1 239 +#define CK_BUS_OSPI2 240 +#define CK_BUS_OTFD1 241 +#define CK_BUS_OTFD2 242 +#define CK_BUS_SRAM1 243 +#define CK_BUS_SRAM2 244 +#define CK_BUS_SDMMC1 245 +#define CK_BUS_SDMMC2 246 +#define CK_BUS_SDMMC3 247 +#define CK_BUS_DDR 248 +#define CK_BUS_RISAF4 249 +#define CK_BUS_USB2OHCI 250 +#define CK_BUS_USB2EHCI 251 +#define CK_BUS_USB3DRD 252 +#define CK_KER_LPTIM1 253 +#define CK_KER_LPTIM2 254 +#define CK_KER_USART2 255 +#define CK_KER_UART4 256 +#define CK_KER_USART3 257 +#define CK_KER_UART5 258 +#define CK_KER_SPI2 259 +#define CK_KER_SPI3 260 +#define CK_KER_SPDIFRX 261 +#define CK_KER_I2C1 262 +#define CK_KER_I2C2 263 +#define CK_KER_I3C1 264 +#define CK_KER_I3C2 265 +#define CK_KER_I2C3 266 +#define CK_KER_I2C5 267 +#define CK_KER_I3C3 268 +#define CK_KER_I2C4 269 +#define CK_KER_I2C6 270 +#define CK_KER_I2C7 271 +#define CK_KER_SPI1 272 +#define CK_KER_SPI4 273 +#define CK_KER_SPI5 274 +#define CK_KER_SPI6 275 +#define CK_KER_SPI7 276 +#define CK_KER_USART1 277 +#define CK_KER_USART6 278 +#define CK_KER_UART7 279 +#define CK_KER_UART8 280 +#define CK_KER_UART9 281 +#define CK_KER_MDF1 282 +#define CK_KER_SAI1 283 +#define CK_KER_SAI2 284 +#define CK_KER_SAI3 285 +#define CK_KER_SAI4 286 +#define CK_KER_FDCAN 287 +#define CK_KER_DSIBLANE 288 +#define CK_KER_DSIPHY 289 +#define CK_KER_CSI 290 +#define CK_KER_CSITXESC 291 +#define CK_KER_CSIPHY 292 +#define CK_KER_LVDSPHY 293 +#define CK_KER_STGEN 294 +#define CK_KER_USB3PCIEPHY 295 +#define CK_KER_USB2PHY2EN 296 +#define CK_KER_I3C4 297 +#define CK_KER_SPI8 298 +#define CK_KER_I2C8 299 +#define CK_KER_LPUART1 300 +#define CK_KER_LPTIM3 301 +#define CK_KER_LPTIM4 302 +#define CK_KER_LPTIM5 303 +#define CK_KER_TSDBG 304 +#define CK_KER_TPIU 305 +#define CK_BUS_ETR 306 +#define CK_BUS_SYSATB 307 +#define CK_KER_ADC12 308 +#define CK_KER_ADC3 309 +#define CK_KER_OSPI1 310 +#define CK_KER_OSPI2 311 +#define CK_KER_FMC 312 +#define CK_KER_SDMMC1 313 +#define CK_KER_SDMMC2 314 +#define CK_KER_SDMMC3 315 +#define CK_KER_ETH1 316 +#define CK_KER_ETH2 317 +#define CK_KER_ETH1PTP 318 +#define CK_KER_ETH2PTP 319 +#define CK_KER_USB2PHY1 320 +#define CK_KER_USB2PHY2 321 +#define CK_KER_ETHSW 322 +#define CK_KER_ETHSWREF 323 +#define CK_MCO1 324 +#define CK_MCO2 325 +#define CK_KER_DTS 326 +#define CK_ETH1_RX 327 +#define CK_ETH1_TX 328 +#define CK_ETH1_MAC 329 +#define CK_ETH2_RX 330 +#define CK_ETH2_TX 331 +#define CK_ETH2_MAC 332 +#define CK_ETH1_STP 333 +#define CK_ETH2_STP 334 +#define CK_KER_USBTC 335 +#define CK_BUS_ADF1 336 +#define CK_KER_ADF1 337 +#define CK_BUS_LVDS 338 +#define CK_KER_LTDC 339 +#define CK_KER_GPU 340 +#define CK_BUS_ETHSWACMCFG 341 +#define CK_BUS_ETHSWACMMSG 342 +#define HSE_DIV2_CK 343 + +#define STM32MP25_LAST_CLK 344 + +#define CK_SCMI_ICN_HS_MCU 0 +#define CK_SCMI_ICN_SDMMC 1 +#define CK_SCMI_ICN_DDR 2 +#define CK_SCMI_ICN_DISPLAY 3 +#define CK_SCMI_ICN_HSL 4 +#define CK_SCMI_ICN_NIC 5 +#define CK_SCMI_ICN_VID 6 +#define CK_SCMI_FLEXGEN_07 7 +#define CK_SCMI_FLEXGEN_08 8 +#define CK_SCMI_FLEXGEN_09 9 +#define CK_SCMI_FLEXGEN_10 10 +#define CK_SCMI_FLEXGEN_11 11 +#define CK_SCMI_FLEXGEN_12 12 +#define CK_SCMI_FLEXGEN_13 13 +#define CK_SCMI_FLEXGEN_14 14 +#define CK_SCMI_FLEXGEN_15 15 +#define CK_SCMI_FLEXGEN_16 16 +#define CK_SCMI_FLEXGEN_17 17 +#define CK_SCMI_FLEXGEN_18 18 +#define CK_SCMI_FLEXGEN_19 19 +#define CK_SCMI_FLEXGEN_20 20 +#define CK_SCMI_FLEXGEN_21 21 +#define CK_SCMI_FLEXGEN_22 22 +#define CK_SCMI_FLEXGEN_23 23 +#define CK_SCMI_FLEXGEN_24 24 +#define CK_SCMI_FLEXGEN_25 25 +#define CK_SCMI_FLEXGEN_26 26 +#define CK_SCMI_FLEXGEN_27 27 +#define CK_SCMI_FLEXGEN_28 28 +#define CK_SCMI_FLEXGEN_29 29 +#define CK_SCMI_FLEXGEN_30 30 +#define CK_SCMI_FLEXGEN_31 31 +#define CK_SCMI_FLEXGEN_32 32 +#define CK_SCMI_FLEXGEN_33 33 +#define CK_SCMI_FLEXGEN_34 34 +#define CK_SCMI_FLEXGEN_35 35 +#define CK_SCMI_FLEXGEN_36 36 +#define CK_SCMI_FLEXGEN_37 37 +#define CK_SCMI_FLEXGEN_38 38 +#define CK_SCMI_FLEXGEN_39 39 +#define CK_SCMI_FLEXGEN_40 40 +#define CK_SCMI_FLEXGEN_41 41 +#define CK_SCMI_FLEXGEN_42 42 +#define CK_SCMI_FLEXGEN_43 43 +#define CK_SCMI_FLEXGEN_44 44 +#define CK_SCMI_FLEXGEN_45 45 +#define CK_SCMI_FLEXGEN_46 46 +#define CK_SCMI_FLEXGEN_47 47 +#define CK_SCMI_FLEXGEN_48 48 +#define CK_SCMI_FLEXGEN_49 49 +#define CK_SCMI_FLEXGEN_50 50 +#define CK_SCMI_FLEXGEN_51 51 +#define CK_SCMI_FLEXGEN_52 52 +#define CK_SCMI_FLEXGEN_53 53 +#define CK_SCMI_FLEXGEN_54 54 +#define CK_SCMI_FLEXGEN_55 55 +#define CK_SCMI_FLEXGEN_56 56 +#define CK_SCMI_FLEXGEN_57 57 +#define CK_SCMI_FLEXGEN_58 58 +#define CK_SCMI_FLEXGEN_59 59 +#define CK_SCMI_FLEXGEN_60 60 +#define CK_SCMI_FLEXGEN_61 61 +#define CK_SCMI_FLEXGEN_62 62 +#define CK_SCMI_FLEXGEN_63 63 +#define CK_SCMI_ICN_LS_MCU 64 +#define CK_SCMI_HSE 65 +#define CK_SCMI_LSE 66 +#define CK_SCMI_HSI 67 +#define CK_SCMI_LSI 68 +#define CK_SCMI_MSI 69 +#define CK_SCMI_HSE_DIV2 70 +#define CK_SCMI_CPU1 71 +#define CK_SCMI_SYSCPU1 72 +#define CK_SCMI_PLL2 73 +#define CK_SCMI_PLL3 74 +#define CK_SCMI_RTC 75 +#define CK_SCMI_RTCCK 76 +#define CK_SCMI_ICN_APB1 77 +#define CK_SCMI_ICN_APB2 78 +#define CK_SCMI_ICN_APB3 79 +#define CK_SCMI_ICN_APB4 80 +#define CK_SCMI_ICN_APBDBG 81 +#define CK_SCMI_TIMG1 82 +#define CK_SCMI_TIMG2 83 +#define CK_SCMI_BKPSRAM 84 +#define CK_SCMI_BSEC 85 +#define CK_SCMI_BUSPERFM 86 +#define CK_SCMI_ETR 87 +#define CK_SCMI_FMC 88 +#define CK_SCMI_GPIOA 89 +#define CK_SCMI_GPIOB 90 +#define CK_SCMI_GPIOC 91 +#define CK_SCMI_GPIOD 92 +#define CK_SCMI_GPIOE 93 +#define CK_SCMI_GPIOF 94 +#define CK_SCMI_GPIOG 95 +#define CK_SCMI_GPIOH 96 +#define CK_SCMI_GPIOI 97 +#define CK_SCMI_GPIOJ 98 +#define CK_SCMI_GPIOK 99 +#define CK_SCMI_GPIOZ 100 +#define CK_SCMI_HPDMA1 101 +#define CK_SCMI_HPDMA2 102 +#define CK_SCMI_HPDMA3 103 +#define CK_SCMI_HSEM 104 +#define CK_SCMI_IPCC1 105 +#define CK_SCMI_IPCC2 106 +#define CK_SCMI_LPDMA 107 +#define CK_SCMI_RETRAM 108 +#define CK_SCMI_SRAM1 109 +#define CK_SCMI_SRAM2 110 +#define CK_SCMI_LPSRAM1 111 +#define CK_SCMI_LPSRAM2 112 +#define CK_SCMI_LPSRAM3 113 +#define CK_SCMI_VDERAM 114 +#define CK_SCMI_SYSRAM 115 +#define CK_SCMI_OSPI1 116 +#define CK_SCMI_OSPI2 117 +#define CK_SCMI_TPIU 118 +#define CK_SCMI_SYSDBG 119 +#define CK_SCMI_SYSATB 120 +#define CK_SCMI_TSDBG 121 +#define CK_SCMI_STM500 122 + +#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp25-clksrc.h b/include/dt-bindings/clock/stm32mp25-clksrc.h new file mode 100644 index 0000000..e6f7154 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp25-clksrc.h
@@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ + +#define CMD_DIV 0 +#define CMD_MUX 1 +#define CMD_CLK 2 +#define CMD_FLEXGEN 3 + +#define CMD_ADDR_BIT 0x80000000 + +#define CMD_SHIFT 26 +#define CMD_MASK 0xFC000000 +#define CMD_DATA_MASK 0x03FFFFFF + +#define DIV_ID_SHIFT 8 +#define DIV_ID_MASK 0x0000FF00 + +#define DIV_DIVN_SHIFT 0 +#define DIV_DIVN_MASK 0x000000FF + +#define MUX_ID_SHIFT 4 +#define MUX_ID_MASK 0x00000FF0 + +#define MUX_SEL_SHIFT 0 +#define MUX_SEL_MASK 0x0000000F + +/* CLK define */ +#define CLK_ON_MASK BIT(21) +#define CLK_ON_SHIFT 21 + +#define CLK_ID_MASK GENMASK_32(20, 12) +#define CLK_ID_SHIFT 12 + +#define CLK_NO_DIV_MASK 0x0000080 +#define CLK_DIV_MASK GENMASK_32(10, 5) +#define CLK_DIV_SHIFT 5 + +#define CLK_NO_SEL_MASK 0x00000010 +#define CLK_SEL_MASK GENMASK_32(3, 0) +#define CLK_SEL_SHIFT 0 + +#define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ + ((state) << CLK_ON_SHIFT) |\ + ((clk_id) << CLK_ID_SHIFT) |\ + ((div) << CLK_DIV_SHIFT) |\ + ((sel) << CLK_SEL_SHIFT)) + +#define CLK_OFF 0 +#define CLK_ON 1 +#define CLK_NODIV 0x00000040 +#define CLK_NOMUX 0x00000010 + +/* Flexgen define */ +#define FLEX_ID_SHIFT 13 +#define FLEX_SEL_SHIFT 9 +#define FLEX_PDIV_SHIFT 6 +#define FLEX_FDIV_SHIFT 0 + +#define FLEX_ID_MASK GENMASK_32(18, 13) +#define FLEX_SEL_MASK GENMASK_32(12, 9) +#define FLEX_PDIV_MASK GENMASK_32(8, 6) +#define FLEX_FDIV_MASK GENMASK_32(5, 0) + +#define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ + ((div_id) << DIV_ID_SHIFT |\ + (div))) + +#define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ + ((mux_id) << MUX_ID_SHIFT |\ + (sel))) + +#define CLK_ADDR_SHIFT 16 +#define CLK_ADDR_MASK 0x7FFF0000 +#define CLK_ADDR_VAL_MASK 0xFFFF + +#define DIV_LSMCU 0 +#define DIV_APB1 1 +#define DIV_APB2 2 +#define DIV_APB3 3 +#define DIV_APB4 4 +#define DIV_APBDBG 5 +#define DIV_RTC 6 +#define DIV_NB 7 + +#define MUX_MUXSEL0 0 +#define MUX_MUXSEL1 1 +#define MUX_MUXSEL2 2 +#define MUX_MUXSEL3 3 +#define MUX_MUXSEL4 4 +#define MUX_MUXSEL5 5 +#define MUX_MUXSEL6 6 +#define MUX_MUXSEL7 7 +#define MUX_XBARSEL 8 +#define MUX_RTC 9 +#define MUX_MCO1 10 +#define MUX_MCO2 11 +#define MUX_ADC12 12 +#define MUX_ADC3 13 +#define MUX_USB2PHY1 14 +#define MUX_USB2PHY2 15 +#define MUX_USB3PCIEPHY 16 +#define MUX_DSIBLANE 17 +#define MUX_DSIPHY 18 +#define MUX_LVDSPHY 19 +#define MUX_DTS 20 +#define MUX_CPU1 21 +#define MUX_D3PER 22 +#define MUX_NB 23 + +#define MUXSEL_HSI 0 +#define MUXSEL_HSE 1 +#define MUXSEL_MSI 2 + +/* KERNEL source clocks */ +#define MUX_RTC_DISABLED 0x0 +#define MUX_RTC_LSE 0x1 +#define MUX_RTC_LSI 0x2 +#define MUX_RTC_HSE 0x3 + +#define MUX_MCO1_FLEX61 0x0 +#define MUX_MCO1_OBSER0 0x1 + +#define MUX_MCO2_FLEX62 0x0 +#define MUX_MCO2_OBSER1 0x1 + +#define MUX_ADC12_FLEX46 0x0 +#define MUX_ADC12_LSMCU 0x1 + +#define MUX_ADC3_FLEX47 0x0 +#define MUX_ADC3_LSMCU 0x1 +#define MUX_ADC3_FLEX46 0x2 + +#define MUX_USB2PHY1_FLEX57 0x0 +#define MUX_USB2PHY1_HSE 0x1 + +#define MUX_USB2PHY2_FLEX58 0x0 +#define MUX_USB2PHY2_HSE 0x1 + +#define MUX_USB3PCIEPHY_FLEX34 0x0 +#define MUX_USB3PCIEPHY_HSE 0x1 + +#define MUX_DSIBLANE_FLEX28 0x0 +#define MUX_DSIBLANE_FLEX27 0x1 + +#define MUX_DSIPHY_FLEX28 0x0 +#define MUX_DSIPHY_HSE 0x1 + +#define MUX_LVDSPHY_FLEX32 0x0 +#define MUX_LVDSPHY_HSE 0x1 + +#define MUX_DTS_HSI 0x0 +#define MUX_DTS_HSE 0x1 +#define MUX_DTS_MSI 0x2 + +#define MUX_D3PER_MSI 0x0 +#define MUX_D3PER_LSI 0x1 +#define MUX_D3PER_LSE 0x2 + +/* PLLs source clocks */ +#define PLL_SRC_HSI 0x0 +#define PLL_SRC_HSE 0x1 +#define PLL_SRC_MSI 0x2 +#define PLL_SRC_DISABLED 0x3 + +/* XBAR source clocks */ +#define XBAR_SRC_PLL4 0x0 +#define XBAR_SRC_PLL5 0x1 +#define XBAR_SRC_PLL6 0x2 +#define XBAR_SRC_PLL7 0x3 +#define XBAR_SRC_PLL8 0x4 +#define XBAR_SRC_HSI 0x5 +#define XBAR_SRC_HSE 0x6 +#define XBAR_SRC_MSI 0x7 +#define XBAR_SRC_HSI_KER 0x8 +#define XBAR_SRC_HSE_KER 0x9 +#define XBAR_SRC_MSI_KER 0xA +#define XBAR_SRC_SPDIF_SYMB 0xB +#define XBAR_SRC_I2S 0xC +#define XBAR_SRC_LSI 0xD +#define XBAR_SRC_LSE 0xE + +/* + * Configure a XBAR channel with its clock source + * channel_nb: XBAR channel number from 0 to 63 + * channel_src: one of the 15 previous XBAR source clocks defines + * channel_prediv: value of the PREDIV in channel RCC_PREDIVxCFGR register + * can be either 1, 2, 4 or 1024 + * channel_findiv: value of the FINDIV in channel RCC_FINDIVxCFGR register + * from 1 to 64 + */ + +#define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ + ((ch) << FLEX_ID_SHIFT) |\ + ((sel) << FLEX_SEL_SHIFT) |\ + ((pdiv) << FLEX_PDIV_SHIFT) |\ + ((fdiv) << FLEX_FDIV_SHIFT)) + +/* Register addresses of MCO1 & MCO2 */ +#define MCO1 0x494 +#define MCO2 0x498 + +#define MCO_OFF 0 +#define MCO_ON 1 +#define MCO_STATUS_SHIFT 8 + +#define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ + ((addr) << CLK_ADDR_SHIFT) |\ + ((status) << MCO_STATUS_SHIFT) |\ + (sel)) + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */
diff --git a/include/dt-bindings/reset/stm32mp25-resets.h b/include/dt-bindings/reset/stm32mp25-resets.h new file mode 100644 index 0000000..c34fe2a --- /dev/null +++ b/include/dt-bindings/reset/stm32mp25-resets.h
@@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. + */ + +#ifndef _DT_BINDINGS_STM32MP25_RESET_H_ +#define _DT_BINDINGS_STM32MP25_RESET_H_ + +#define SYS_R 8192 +#define C1_R 8224 +#define C1P1POR_R 8256 +#define C1P1_R 8257 +#define C2_R 8288 +#define C2_HOLDBOOT_R 8608 +#define C1_HOLDBOOT_R 8609 +#define VSW_R 8703 +#define C1MS_R 8808 +#define IWDG2_KER_R 9074 +#define IWDG4_KER_R 9202 +#define C3_R 9312 +#define DDRCP_R 9856 +#define DDRCAPB_R 9888 +#define DDRPHYCAPB_R 9920 +#define DDRCFG_R 9984 +#define DDR_R 10016 +#define OSPI1_R 10400 +#define OSPI1DLL_R 10416 +#define OSPI2_R 10432 +#define OSPI2DLL_R 10448 +#define FMC_R 10464 +#define DBG_R 10508 +#define GPIOA_R 10592 +#define GPIOB_R 10624 +#define GPIOC_R 10656 +#define GPIOD_R 10688 +#define GPIOE_R 10720 +#define GPIOF_R 10752 +#define GPIOG_R 10784 +#define GPIOH_R 10816 +#define GPIOI_R 10848 +#define GPIOJ_R 10880 +#define GPIOK_R 10912 +#define GPIOZ_R 10944 +#define HPDMA1_R 10976 +#define HPDMA2_R 11008 +#define HPDMA3_R 11040 +#define LPDMA_R 11072 +#define HSEM_R 11104 +#define IPCC1_R 11136 +#define IPCC2_R 11168 +#define IS2M_R 11360 +#define SSMOD_R 11392 +#define TIM1_R 14336 +#define TIM2_R 14368 +#define TIM3_R 14400 +#define TIM4_R 14432 +#define TIM5_R 14464 +#define TIM6_R 14496 +#define TIM7_R 14528 +#define TIM8_R 14560 +#define TIM10_R 14592 +#define TIM11_R 14624 +#define TIM12_R 14656 +#define TIM13_R 14688 +#define TIM14_R 14720 +#define TIM15_R 14752 +#define TIM16_R 14784 +#define TIM17_R 14816 +#define TIM20_R 14848 +#define LPTIM1_R 14880 +#define LPTIM2_R 14912 +#define LPTIM3_R 14944 +#define LPTIM4_R 14976 +#define LPTIM5_R 15008 +#define SPI1_R 15040 +#define SPI2_R 15072 +#define SPI3_R 15104 +#define SPI4_R 15136 +#define SPI5_R 15168 +#define SPI6_R 15200 +#define SPI7_R 15232 +#define SPI8_R 15264 +#define SPDIFRX_R 15296 +#define USART1_R 15328 +#define USART2_R 15360 +#define USART3_R 15392 +#define UART4_R 15424 +#define UART5_R 15456 +#define USART6_R 15488 +#define UART7_R 15520 +#define UART8_R 15552 +#define UART9_R 15584 +#define LPUART1_R 15616 +#define I2C1_R 15648 +#define I2C2_R 15680 +#define I2C3_R 15712 +#define I2C4_R 15744 +#define I2C5_R 15776 +#define I2C6_R 15808 +#define I2C7_R 15840 +#define I2C8_R 15872 +#define SAI1_R 15904 +#define SAI2_R 15936 +#define SAI3_R 15968 +#define SAI4_R 16000 +#define MDF1_R 16064 +#define MDF2_R 16096 +#define FDCAN_R 16128 +#define HDP_R 16160 +#define ADC12_R 16192 +#define ADC3_R 16224 +#define ETH1_R 16256 +#define ETH2_R 16288 +#define USB2_R 16352 +#define USB2PHY1_R 16384 +#define USB2PHY2_R 16416 +#define USB3DRD_R 16448 +#define USB3PCIEPHY_R 16480 +#define PCIE_R 16512 +#define USBTC_R 16544 +#define ETHSW_R 16576 +#define SDMMC1_R 16768 +#define SDMMC1DLL_R 16784 +#define SDMMC2_R 16800 +#define SDMMC2DLL_R 16816 +#define SDMMC3_R 16832 +#define SDMMC3DLL_R 16848 +#define GPU_R 16864 +#define LTDC_R 16896 +#define DSI_R 16928 +#define LVDS_R 17024 +#define CSI_R 17088 +#define DCMIPP_R 17120 +#define CCI_R 17152 +#define VDEC_R 17184 +#define VENC_R 17216 +#define RNG_R 17280 +#define PKA_R 17312 +#define SAES_R 17344 +#define HASH_R 17376 +#define CRYP1_R 17408 +#define CRYP2_R 17440 +#define WWDG1_R 17632 +#define WWDG2_R 17664 +#define BUSPERFM_R 17696 +#define VREF_R 17728 +#define DTS_R 17760 +#define CRC_R 17824 +#define SERC_R 17856 +#define OSPIIOM_R 17888 +#define I3C1_R 17984 +#define I3C2_R 18016 +#define I3C3_R 18048 +#define I3C4_R 18080 + +#define RST_SCMI_C1_R 0 +#define RST_SCMI_C2_R 1 +#define RST_SCMI_C1_HOLDBOOT_R 2 +#define RST_SCMI_C2_HOLDBOOT_R 3 +#define RST_SCMI_FMC 4 +#define RST_SCMI_PCIE 5 + +#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h index 98a0099..ce17b4a 100644 --- a/include/export/common/tbbr/tbbr_img_def_exp.h +++ b/include/export/common/tbbr/tbbr_img_def_exp.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,41 +79,44 @@ /* NT_FW_CONFIG */ #define NT_FW_CONFIG_ID U(27) -/* GPT Partition */ +/* GPT primary header and entries */ #define GPT_IMAGE_ID U(28) +/* GPT backup header and entries */ +#define BKUP_GPT_IMAGE_ID U(29) + /* Binary with STM32 header */ -#define STM32_IMAGE_ID U(29) +#define STM32_IMAGE_ID U(30) /* Encrypted image identifier */ -#define ENC_IMAGE_ID U(30) +#define ENC_IMAGE_ID U(31) /* FW_CONFIG */ -#define FW_CONFIG_ID U(31) +#define FW_CONFIG_ID U(32) /* * Primary FWU metadata image ID */ -#define FWU_METADATA_IMAGE_ID U(32) +#define FWU_METADATA_IMAGE_ID U(33) /* * Backup FWU metadata image ID */ -#define BKUP_FWU_METADATA_IMAGE_ID U(33) +#define BKUP_FWU_METADATA_IMAGE_ID U(34) /* Realm Monitor Manager (RMM) */ -#define RMM_IMAGE_ID U(34) +#define RMM_IMAGE_ID U(35) /* CCA Content Certificate ID */ -#define CCA_CONTENT_CERT_ID U(35) +#define CCA_CONTENT_CERT_ID U(36) /* Core SWD Key Certificate ID */ -#define CORE_SWD_KEY_CERT_ID U(36) +#define CORE_SWD_KEY_CERT_ID U(37) /* Platform Key Certificate ID */ -#define PLAT_KEY_CERT_ID U(37) +#define PLAT_KEY_CERT_ID U(38) /* Max Images */ -#define MAX_IMAGE_IDS U(38) +#define MAX_IMAGE_IDS U(39) #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */
diff --git a/include/export/lib/bl_aux_params/bl_aux_params_exp.h b/include/export/lib/bl_aux_params/bl_aux_params_exp.h index 7391dec..5ae1d64 100644 --- a/include/export/lib/bl_aux_params/bl_aux_params_exp.h +++ b/include/export/lib/bl_aux_params/bl_aux_params_exp.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/export/lib/utils_def_exp.h b/include/export/lib/utils_def_exp.h index d4a4a85..8c58cbb 100644 --- a/include/export/lib/utils_def_exp.h +++ b/include/export/lib/utils_def_exp.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,10 +27,14 @@ #else # define U_(_x) (_x##U) # define U(_x) U_(_x) -# define UL(_x) (_x##UL) -# define ULL(_x) (_x##ULL) -# define L(_x) (_x##L) -# define LL(_x) (_x##LL) +# define UL_(_x) (_x##UL) +# define UL(_x) UL_(_x) +# define ULL_(_x) (_x##ULL) +# define ULL(_x) ULL_(_x) +# define L_(_x) (_x##L) +# define L(_x) L_(_x) +# define LL_(_x) (_x##LL) +# define LL(_x) LL_(_x) #endif
diff --git a/include/lib/bakery_lock.h b/include/lib/bakery_lock.h index 2cf2b44..5d165c9 100644 --- a/include/lib/bakery_lock.h +++ b/include/lib/bakery_lock.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/bl_aux_params/bl_aux_params.h b/include/lib/bl_aux_params/bl_aux_params.h index 072a29d..c2da96c 100644 --- a/include/lib/bl_aux_params/bl_aux_params.h +++ b/include/lib/bl_aux_params/bl_aux_params.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/bootmarker_capture.h b/include/lib/bootmarker_capture.h new file mode 100644 index 0000000..31fe048 --- /dev/null +++ b/include/lib/bootmarker_capture.h
@@ -0,0 +1,22 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOTMARKER_CAPTURE_H +#define BOOTMARKER_CAPTURE_H + +#define BL1_ENTRY U(0) +#define BL1_EXIT U(1) +#define BL2_ENTRY U(2) +#define BL2_EXIT U(3) +#define BL31_ENTRY U(4) +#define BL31_EXIT U(5) +#define BL_TOTAL_IDS U(6) + +#ifdef __ASSEMBLER__ +PMF_DECLARE_CAPTURE_TIMESTAMP(bl_svc) +#endif /*__ASSEMBLER__*/ + +#endif /*BOOTMARKER_CAPTURE_H*/
diff --git a/include/lib/cassert.h b/include/lib/cassert.h index bbfdfdb..512a2ad 100644 --- a/include/lib/cassert.h +++ b/include/lib/cassert.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h index 42d4149..c8e1b2d 100644 --- a/include/lib/coreboot.h +++ b/include/lib/coreboot.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/aem_generic.h b/include/lib/cpus/aarch32/aem_generic.h index 1d40cec..f631f26 100644 --- a/include/lib/cpus/aarch32/aem_generic.h +++ b/include/lib/cpus/aarch32/aem_generic.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a12.h b/include/lib/cpus/aarch32/cortex_a12.h index abacdba..789b4cf 100644 --- a/include/lib/cpus/aarch32/cortex_a12.h +++ b/include/lib/cpus/aarch32/cortex_a12.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a15.h b/include/lib/cpus/aarch32/cortex_a15.h index 9526a9c..aca4d34 100644 --- a/include/lib/cpus/aarch32/cortex_a15.h +++ b/include/lib/cpus/aarch32/cortex_a15.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a17.h b/include/lib/cpus/aarch32/cortex_a17.h index 89a8eb6..b9e754a 100644 --- a/include/lib/cpus/aarch32/cortex_a17.h +++ b/include/lib/cpus/aarch32/cortex_a17.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a32.h b/include/lib/cpus/aarch32/cortex_a32.h index 6ddd533..841898a 100644 --- a/include/lib/cpus/aarch32/cortex_a32.h +++ b/include/lib/cpus/aarch32/cortex_a32.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a5.h b/include/lib/cpus/aarch32/cortex_a5.h index 76703b7..c0763f9 100644 --- a/include/lib/cpus/aarch32/cortex_a5.h +++ b/include/lib/cpus/aarch32/cortex_a5.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index 8dd0192..b9bb310 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index ffabd61..bb977ff 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a7.h b/include/lib/cpus/aarch32/cortex_a7.h index 730fdb5..16fbfaa 100644 --- a/include/lib/cpus/aarch32/cortex_a7.h +++ b/include/lib/cpus/aarch32/cortex_a7.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 954f7361..0a3a23a 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cortex_a9.h b/include/lib/cpus/aarch32/cortex_a9.h index a8c978a..337bad9 100644 --- a/include/lib/cpus/aarch32/cortex_a9.h +++ b/include/lib/cpus/aarch32/cortex_a9.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index ab2f2c6..096e0b1 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S
@@ -1,82 +1,13 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef CPU_MACROS_S #define CPU_MACROS_S -#include <arch.h> -#include <lib/cpus/errata_report.h> - -#if defined(IMAGE_BL1) || defined(IMAGE_BL32) \ - || (defined(IMAGE_BL2) && RESET_TO_BL2) -#define IMAGE_AT_EL3 -#endif - -#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ - (MIDR_PN_MASK << MIDR_PN_SHIFT) - -/* The number of CPU operations allowed */ -#define CPU_MAX_PWR_DWN_OPS 2 - -/* Special constant to specify that CPU has no reset function */ -#define CPU_NO_RESET_FUNC 0 - -/* Word size for 32-bit CPUs */ -#define CPU_WORD_SIZE 4 - -/* - * Whether errata status needs reporting. Errata status is printed in debug - * builds for both BL1 and BL32 images. - */ -#if (defined(IMAGE_BL1) || defined(IMAGE_BL32)) && DEBUG -# define REPORT_ERRATA 1 -#else -# define REPORT_ERRATA 0 -#endif - - - .equ CPU_MIDR_SIZE, CPU_WORD_SIZE - .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS - .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE - -#ifndef IMAGE_AT_EL3 - .equ CPU_RESET_FUNC_SIZE, 0 -#endif - -/* The power down core and cluster is needed only in BL32 */ -#ifndef IMAGE_BL32 - .equ CPU_PWR_DWN_OPS_SIZE, 0 -#endif - -/* Fields required to print errata status */ -#if !REPORT_ERRATA - .equ CPU_ERRATA_FUNC_SIZE, 0 -#endif - -/* Only BL32 requires mutual exclusion and printed flag. */ -#if !(REPORT_ERRATA && defined(IMAGE_BL32)) - .equ CPU_ERRATA_LOCK_SIZE, 0 - .equ CPU_ERRATA_PRINTED_SIZE, 0 -#endif - - -/* - * Define the offsets to the fields in cpu_ops structure. - * Every offset is defined based on the offset and size of the previous - * field. - */ - .equ CPU_MIDR, 0 - .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE - .equ CPU_PWR_DWN_OPS, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE - .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE - .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE - .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE - .equ CPU_OPS_SIZE, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> /* * Write given expressions as words @@ -142,6 +73,29 @@ fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops #endif + /* + * It is possible (although unlikely) that a cpu may have no errata in + * code. In that case the start label will not be defined. The list is + * inteded to be used in a loop, so define it as zero-length for + * predictable behaviour. Since this macro is always called at the end + * of the cpu file (after all errata have been parsed) we can be sure + * that we are at the end of the list. Some cpus call the macro twice, + * so only do this once. + */ + .pushsection .rodata.errata_entries + .ifndef \_name\()_errata_list_start + \_name\()_errata_list_start: + .endif + /* some call this multiple times, so only do this once */ + .ifndef \_name\()_errata_list_end + \_name\()_errata_list_end: + .endif + .popsection + + /* and now put them in cpu_ops */ + .word \_name\()_errata_list_start + .word \_name\()_errata_list_end + #if REPORT_ERRATA .ifndef \_name\()_cpu_str /* @@ -166,6 +120,7 @@ * this class. */ .word \_name\()_errata_report + .word \_name\()_cpu_str #ifdef IMAGE_BL32 /* Pointers to errata lock and reported flag */ @@ -228,4 +183,77 @@ beq \_label .endm +/* + * NOTE an erratum and CVE id could clash. However, both numbers are very large + * and the probablity is minuscule. Working around this makes code very + * complicated and extremely difficult to read so it is not considered. In the + * unlikely event that this does happen, prepending the CVE id with a 0 should + * resolve the conflict + */ + +/* + * Add an entry for this erratum to the errata framework + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with the previous field with the + * ERRATUM or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _special: + * The special non-standard name of an erratum + */ +.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _special + .pushsection .rodata.errata_entries + .align 2 + .ifndef \_cpu\()_errata_list_start + \_cpu\()_errata_list_start: + .endif + + /* unused on AArch32, maintain for portability */ + .word 0 + /* TODO(errata ABI): this prevents all checker functions from + * being optimised away. Can be done away with unless the ABI + * needs them */ + .ifnb \_special + .word check_errata_\_special + .elseif \_cve + .word check_errata_cve_\_cve\()_\_id + .else + .word check_errata_\_id + .endif + /* Will fit CVEs with up to 10 character in the ID field */ + .word \_id + .hword \_cve + .byte \_chosen + /* TODO(errata ABI): mitigated field for known but unmitigated + * errata*/ + .byte 0x1 + .popsection +.endm + +/* + * Maintain compatibility with the old scheme of "each cpu has its own reporter". + * TODO remove entirely once all cpus have been converted. This includes the + * cpu_ops entry, as print_errata_status can call this directly for all cpus + */ +.macro errata_report_shim _cpu:req + #if REPORT_ERRATA + func \_cpu\()_errata_report + push {r12, lr} + + bl generic_errata_report + + pop {r12, lr} + bx lr + endfunc \_cpu\()_errata_report + #endif +.endm #endif /* CPU_MACROS_S */
diff --git a/include/lib/cpus/aarch64/aem_generic.h b/include/lib/cpus/aarch64/aem_generic.h index 6bb30a2..acb6adb 100644 --- a/include/lib/cpus/aarch64/aem_generic.h +++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a35.h b/include/lib/cpus/aarch64/cortex_a35.h index 5421478..cef2960 100644 --- a/include/lib/cpus/aarch64/cortex_a35.h +++ b/include/lib/cpus/aarch64/cortex_a35.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 6af85a8..337aac3 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,11 +14,13 @@ ******************************************************************************/ #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) +#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) -#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) /******************************************************************************* * CPU Power Control register specific definitions @@ -30,6 +32,12 @@ * Complex auxiliary control register specific definitions ******************************************************************************/ #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) +#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) +#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) /******************************************************************************* * Auxiliary control register specific definitions @@ -37,5 +45,11 @@ #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) +#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) -#endif /* CORTEX_A510_H */ \ No newline at end of file +#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a520.h b/include/lib/cpus/aarch64/cortex_a520.h new file mode 100644 index 0000000..4176981 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a520.h
@@ -0,0 +1,23 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A520_H +#define CORTEX_A520_H + +#define CORTEX_A520_MIDR U(0x410FD800) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A520_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A520_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A520_H */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 54e646c..18796ee 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a55.h b/include/lib/cpus/aarch64/cortex_a55.h index 60ed957..0a1593a 100644 --- a/include/lib/cpus/aarch64/cortex_a55.h +++ b/include/lib/cpus/aarch64/cortex_a55.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index dc40e31..19ac513 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h new file mode 100644 index 0000000..950d02f --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a715.h
@@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A715_H +#define CORTEX_A715_H + +#define CORTEX_A715_MIDR U(0x410FD4D0) + +/* Cortex-A715 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A715_BHB_LOOP_COUNT U(38) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A715_H */
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index bef9337..a00f6d6 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h new file mode 100644 index 0000000..47bbbc0 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a720.h
@@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A720_H +#define CORTEX_A720_H + +#define CORTEX_A720_MIDR U(0x410FD810) + +/* Cortex A720 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_A720_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_A720_H */
diff --git a/include/lib/cpus/aarch64/cortex_a73.h b/include/lib/cpus/aarch64/cortex_a73.h index 271a333..ede76d1 100644 --- a/include/lib/cpus/aarch64/cortex_a73.h +++ b/include/lib/cpus/aarch64/cortex_a73.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index e5ca1ba..ca79991 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h index 74fb6e9..b2ec8aa 100644 --- a/include/lib/cpus/aarch64/cortex_a76.h +++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,6 +36,7 @@ #define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index a9b4546..39717a3 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 66f565d..2984f82 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h index b68ec1e..4ada845 100644 --- a/include/lib/cpus/aarch64/cortex_a78_ae.h +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/cpus/aarch64/cortex_gelas.h b/include/lib/cpus/aarch64/cortex_gelas.h new file mode 100644 index 0000000..90bb78f --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_gelas.h
@@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_GELAS_H +#define CORTEX_GELAS_H + +#include <lib/utils_def.h> + +#define CORTEX_GELAS_MIDR U(0x410FD8B0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_GELAS_IMP_CPUECTLR_EL1 S3_0_C15_C1_5 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_GELAS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define CORTEX_GELAS_SVCRSM S0_3_C4_C2_3 +#define CORTEX_GELAS_SVCRZA S0_3_C4_C4_3 + +#endif /* CORTEX_GELAS_H */
diff --git a/include/lib/cpus/aarch64/cortex_hayes.h b/include/lib/cpus/aarch64/cortex_hayes.h deleted file mode 100644 index 82022e9..0000000 --- a/include/lib/cpus/aarch64/cortex_hayes.h +++ /dev/null
@@ -1,23 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_HAYES_H -#define CORTEX_HAYES_H - -#define CORTEX_HAYES_MIDR U(0x410FD800) - -/******************************************************************************* - * CPU Extended Control register specific definitions - ******************************************************************************/ -#define CORTEX_HAYES_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions - ******************************************************************************/ -#define CORTEX_HAYES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) - -#endif /* CORTEX_HAYES_H */
diff --git a/include/lib/cpus/aarch64/cortex_hunter.h b/include/lib/cpus/aarch64/cortex_hunter.h deleted file mode 100644 index 24bd217..0000000 --- a/include/lib/cpus/aarch64/cortex_hunter.h +++ /dev/null
@@ -1,26 +0,0 @@ -/* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_HUNTER_H -#define CORTEX_HUNTER_H - -#define CORTEX_HUNTER_MIDR U(0x410FD810) - -/* Cortex Hunter loop count for CVE-2022-23960 mitigation */ -#define CORTEX_HUNTER_BHB_LOOP_COUNT U(132) - -/******************************************************************************* - * CPU Extended Control register specific definitions - ******************************************************************************/ -#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions - ******************************************************************************/ -#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) - -#endif /* CORTEX_HUNTER_H */
diff --git a/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h b/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h deleted file mode 100644 index f9bb0f3..0000000 --- a/include/lib/cpus/aarch64/cortex_hunter_elp_arm.h +++ /dev/null
@@ -1,26 +0,0 @@ -/* - * Copyright (c) 2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_HUNTER_ELP_ARM_H -#define CORTEX_HUNTER_ELP_ARM_H - -#define CORTEX_HUNTER_ELP_ARM_MIDR U(0x410FD821) - -/* Cortex Hunter ELP loop count for CVE-2022-23960 mitigation */ -#define CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT U(132) - -/******************************************************************************* - * CPU Extended Control register specific definitions - ******************************************************************************/ -#define CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions - ******************************************************************************/ -#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) - -#endif /* CORTEX_HUNTER_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/cortex_makalu.h b/include/lib/cpus/aarch64/cortex_makalu.h deleted file mode 100644 index ee59657..0000000 --- a/include/lib/cpus/aarch64/cortex_makalu.h +++ /dev/null
@@ -1,26 +0,0 @@ -/* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_MAKALU_H -#define CORTEX_MAKALU_H - -#define CORTEX_MAKALU_MIDR U(0x410FD4D0) - -/* Cortex Makalu loop count for CVE-2022-23960 mitigation */ -#define CORTEX_MAKALU_BHB_LOOP_COUNT U(38) - -/******************************************************************************* - * CPU Extended Control register specific definitions - ******************************************************************************/ -#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions - ******************************************************************************/ -#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) - -#endif /* CORTEX_MAKALU_H */
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h index ceafe66..04548ea 100644 --- a/include/lib/cpus/aarch64/cortex_x3.h +++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -31,4 +31,20 @@ #define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36) +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) + +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5 + +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9) + #endif /* CORTEX_X3_H */
diff --git a/include/lib/cpus/aarch64/cortex_x4.h b/include/lib/cpus/aarch64/cortex_x4.h new file mode 100644 index 0000000..17d07c8 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_x4.h
@@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_X4_H +#define CORTEX_X4_H + +#define CORTEX_X4_MIDR U(0x410FD821) + +/* Cortex X4 loop count for CVE-2022-23960 mitigation */ +#define CORTEX_X4_BHB_LOOP_COUNT U(132) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_X4_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define CORTEX_X4_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* CORTEX_X4_H */
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 041be51..6faef5d 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,95 +1,14 @@ /* - * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef CPU_MACROS_S #define CPU_MACROS_S -#include <arch.h> #include <assert_macros.S> -#include <lib/cpus/errata_report.h> - -#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ - (MIDR_PN_MASK << MIDR_PN_SHIFT) - -/* The number of CPU operations allowed */ -#define CPU_MAX_PWR_DWN_OPS 2 - -/* Special constant to specify that CPU has no reset function */ -#define CPU_NO_RESET_FUNC 0 - -#define CPU_NO_EXTRA1_FUNC 0 -#define CPU_NO_EXTRA2_FUNC 0 -#define CPU_NO_EXTRA3_FUNC 0 - -/* Word size for 64-bit CPUs */ -#define CPU_WORD_SIZE 8 - -/* - * Whether errata status needs reporting. Errata status is printed in debug - * builds for both BL1 and BL31 images. - */ -#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG -# define REPORT_ERRATA 1 -#else -# define REPORT_ERRATA 0 -#endif - - - .equ CPU_MIDR_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA3_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS - .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE - .equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE - -#ifndef IMAGE_AT_EL3 - .equ CPU_RESET_FUNC_SIZE, 0 -#endif - -/* The power down core and cluster is needed only in BL31 */ -#ifndef IMAGE_BL31 - .equ CPU_PWR_DWN_OPS_SIZE, 0 -#endif - -/* Fields required to print errata status. */ -#if !REPORT_ERRATA - .equ CPU_ERRATA_FUNC_SIZE, 0 -#endif - -/* Only BL31 requieres mutual exclusion and printed flag. */ -#if !(REPORT_ERRATA && defined(IMAGE_BL31)) - .equ CPU_ERRATA_LOCK_SIZE, 0 - .equ CPU_ERRATA_PRINTED_SIZE, 0 -#endif - -#if !defined(IMAGE_BL31) || !CRASH_REPORTING - .equ CPU_REG_DUMP_SIZE, 0 -#endif - -/* - * Define the offsets to the fields in cpu_ops structure. - * Every offset is defined based in the offset and size of the previous - * field. - */ - .equ CPU_MIDR, 0 - .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE - .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE - .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE - .equ CPU_EXTRA3_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE - .equ CPU_E_HANDLER_FUNC, CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE - .equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE - .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE - .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE - .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE - .equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE - .equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> /* * Write given expressions as quad words @@ -172,6 +91,27 @@ /* Insert list of functions */ fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops #endif + /* + * It is possible (although unlikely) that a cpu may have no errata in + * code. In that case the start label will not be defined. The list is + * intended to be used in a loop, so define it as zero-length for + * predictable behaviour. Since this macro is always called at the end + * of the cpu file (after all errata have been parsed) we can be sure + * that we are at the end of the list. Some cpus call declare_cpu_ops + * twice, so only do this once. + */ + .pushsection .rodata.errata_entries + .ifndef \_name\()_errata_list_start + \_name\()_errata_list_start: + .endif + .ifndef \_name\()_errata_list_end + \_name\()_errata_list_end: + .endif + .popsection + + /* and now put them in cpu_ops */ + .quad \_name\()_errata_list_start + .quad \_name\()_errata_list_end #if REPORT_ERRATA .ifndef \_name\()_cpu_str @@ -192,18 +132,20 @@ .popsection .endif + /* * Mandatory errata status printing function for CPUs of * this class. */ .quad \_name\()_errata_report + .quad \_name\()_cpu_str #ifdef IMAGE_BL31 /* Pointers to errata lock and reported flag */ .quad \_name\()_errata_lock .quad \_name\()_errata_reported -#endif -#endif +#endif /* IMAGE_BL31 */ +#endif /* REPORT_ERRATA */ #if defined(IMAGE_BL31) && CRASH_REPORTING .quad \_name\()_cpu_reg_dump @@ -229,6 +171,7 @@ \_extra1, \_extra2, \_extra3, 0, \_power_down_ops .endm +/* TODO can be deleted once all CPUs have been converted */ #if REPORT_ERRATA /* * Print status of a CPU errata @@ -311,4 +254,383 @@ b.eq \_label .endm + +/* + * Workaround wrappers for errata that apply at reset or runtime. Reset errata + * will be applied automatically + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _apply_at_reset: + * Whether the erratum should be automatically applied at reset + */ +.macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req + .pushsection .rodata.errata_entries + .align 3 + .ifndef \_cpu\()_errata_list_start + \_cpu\()_errata_list_start: + .endif + + /* check if unused and compile out if no references */ + .if \_apply_at_reset && \_chosen + .quad erratum_\_cpu\()_\_id\()_wa + .else + .quad 0 + .endif + /* TODO(errata ABI): this prevents all checker functions from + * being optimised away. Can be done away with unless the ABI + * needs them */ + .quad check_erratum_\_cpu\()_\_id + /* Will fit CVEs with up to 10 character in the ID field */ + .word \_id + .hword \_cve + .byte \_chosen + /* TODO(errata ABI): mitigated field for known but unmitigated + * errata */ + .byte 0x1 + .popsection +.endm + +.macro _workaround_start _cpu:req, _cve:req, _id:req, _chosen:req, _apply_at_reset:req + add_erratum_entry \_cpu, \_cve, \_id, \_chosen, \_apply_at_reset + + func erratum_\_cpu\()_\_id\()_wa + mov x8, x30 + + /* save rev_var for workarounds that might need it but don't + * restore to x0 because few will care */ + mov x7, x0 + bl check_erratum_\_cpu\()_\_id + cbz x0, erratum_\_cpu\()_\_id\()_skip +.endm + +.macro _workaround_end _cpu:req, _id:req + erratum_\_cpu\()_\_id\()_skip: + ret x8 + endfunc erratum_\_cpu\()_\_id\()_wa +.endm + +/******************************************************************************* + * Errata workaround wrappers + ******************************************************************************/ +/* + * Workaround wrappers for errata that apply at reset or runtime. Reset errata + * will be applied automatically + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * in body: + * clobber x0 to x7 (please only use those) + * argument x7 - cpu_rev_var + * + * _wa clobbers: x0-x8 (PCS compliant) + */ +.macro workaround_reset_start _cpu:req, _cve:req, _id:req, _chosen:req + _workaround_start \_cpu, \_cve, \_id, \_chosen, 1 +.endm + +/* + * See `workaround_reset_start` for usage info. Additional arguments: + * + * _midr: + * Check if CPU's MIDR matches the CPU it's meant for. Must be specified + * for errata applied in generic code + */ +.macro workaround_runtime_start _cpu:req, _cve:req, _id:req, _chosen:req, _midr + /* + * Let errata specify if they need MIDR checking. Sadly, storing the + * MIDR in an .equ to retrieve automatically blows up as it stores some + * brackets in the symbol + */ + .ifnb \_midr + jump_if_cpu_midr \_midr, 1f + b erratum_\_cpu\()_\_id\()_skip + + 1: + .endif + _workaround_start \_cpu, \_cve, \_id, \_chosen, 0 +.endm + +/* + * Usage and arguments identical to `workaround_reset_start`. The _cve argument + * is kept here so the same #define can be used as that macro + */ +.macro workaround_reset_end _cpu:req, _cve:req, _id:req + _workaround_end \_cpu, \_id +.endm + +/* + * See `workaround_reset_start` for usage info. The _cve argument is kept here + * so the same #define can be used as that macro. Additional arguments: + * + * _no_isb: + * Optionally do not include the trailing isb. Please disable with the + * NO_ISB macro + */ +.macro workaround_runtime_end _cpu:req, _cve:req, _id:req, _no_isb + /* + * Runtime errata do not have a reset function to call the isb for them + * and missing the isb could be very problematic. It is also likely as + * they tend to be scattered in generic code. + */ + .ifb \_no_isb + isb + .endif + _workaround_end \_cpu, \_id +.endm + +/******************************************************************************* + * Errata workaround helpers + ******************************************************************************/ +/* + * Set a bit in a system register. Can set multiple bits but is limited by the + * way the ORR instruction encodes them. + * + * _reg: + * Register to write to + * + * _bit: + * Bit to set. Please use a descriptive #define + * + * _assert: + * Optionally whether to read back and assert that the bit has been + * written. Please disable with NO_ASSERT macro + * + * clobbers: x1 + */ +.macro sysreg_bit_set _reg:req, _bit:req, _assert=1 + mrs x1, \_reg + orr x1, x1, #\_bit + msr \_reg, x1 +.endm + +/* + * Clear a bit in a system register. Can clear multiple bits but is limited by + * the way the BIC instrucion encodes them. + * + * see sysreg_bit_set for usage + */ +.macro sysreg_bit_clear _reg:req, _bit:req + mrs x1, \_reg + bic x1, x1, #\_bit + msr \_reg, x1 +.endm + +.macro override_vector_table _table:req + adr x1, \_table + msr vbar_el3, x1 +.endm + +/* + * BFI : Inserts bitfield into a system register. + * + * BFI{cond} Rd, Rn, #lsb, #width + */ +.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req + /* Source value for BFI */ + mov x1, #\_src + mrs x0, \_reg + bfi x0, x1, #\_lsb, #\_width + msr \_reg, x0 +.endm + +/* + * Apply erratum + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _chosen: + * Compile time flag on whether the erratum is included + * + * _get_rev: + * Optional parameter that determines whether to insert a call to the CPU revision fetching + * procedure. Stores the result of this in the temporary register x10. + * + * clobbers: x0-x10 (PCS compliant) + */ +.macro apply_erratum _cpu:req, _cve:req, _id:req, _chosen:req, _get_rev=GET_CPU_REV + .if (\_chosen & \_get_rev) + mov x9, x30 + bl cpu_get_rev_var + mov x10, x0 + .elseif (\_chosen) + mov x9, x30 + mov x0, x10 + .endif + + .if \_chosen + bl erratum_\_cpu\()_\_id\()_wa + mov x30, x9 + .endif +.endm + +/* + * Helpers to select which revisions errata apply to. Don't leave a link + * register as the cpu_rev_var_*** will call the ret and we can save on one. + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * _cve: + * Whether erratum is a CVE. CVE year if yes, 0 otherwise + * + * _id: + * Erratum or CVE number. Please combine with previous field with ERRATUM + * or CVE macros + * + * _rev_num: + * Revision to apply to + * + * in body: + * clobber: x0 to x4 + * argument: x0 - cpu_rev_var + */ +.macro check_erratum_ls _cpu:req, _cve:req, _id:req, _rev_num:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num + b cpu_rev_var_ls + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_hs _cpu:req, _cve:req, _id:req, _rev_num:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num + b cpu_rev_var_hs + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_range _cpu:req, _cve:req, _id:req, _rev_num_lo:req, _rev_num_hi:req + func check_erratum_\_cpu\()_\_id + mov x1, #\_rev_num_lo + mov x2, #\_rev_num_hi + b cpu_rev_var_range + endfunc check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_chosen _cpu:req, _cve:req, _id:req, _chosen:req + func check_erratum_\_cpu\()_\_id + .if \_chosen + mov x0, #ERRATA_APPLIES + .else + mov x0, #ERRATA_MISSING + .endif + ret + endfunc check_erratum_\_cpu\()_\_id +.endm + +/* provide a shorthand for the name format for annoying errata */ +.macro check_erratum_custom_start _cpu:req, _cve:req, _id:req + func check_erratum_\_cpu\()_\_id +.endm + +.macro check_erratum_custom_end _cpu:req, _cve:req, _id:req + endfunc check_erratum_\_cpu\()_\_id +.endm + + +/******************************************************************************* + * CPU reset function wrapper + ******************************************************************************/ + +/* + * Wrapper to automatically apply all reset-time errata. Will end with an isb. + * + * _cpu: + * Name of cpu as given to declare_cpu_ops + * + * in body: + * clobber x8 to x14 + * argument x14 - cpu_rev_var + */ +.macro cpu_reset_func_start _cpu:req + func \_cpu\()_reset_func + mov x15, x30 + bl cpu_get_rev_var + mov x14, x0 + + /* short circuit the location to avoid searching the list */ + adrp x12, \_cpu\()_errata_list_start + add x12, x12, :lo12:\_cpu\()_errata_list_start + adrp x13, \_cpu\()_errata_list_end + add x13, x13, :lo12:\_cpu\()_errata_list_end + + errata_begin: + /* if head catches up with end of list, exit */ + cmp x12, x13 + b.eq errata_end + + ldr x10, [x12, #ERRATUM_WA_FUNC] + /* TODO(errata ABI): check mitigated and checker function fields + * for 0 */ + ldrb w11, [x12, #ERRATUM_CHOSEN] + + /* skip if not chosen */ + cbz x11, 1f + /* skip if runtime erratum */ + cbz x10, 1f + + /* put cpu revision in x0 and call workaround */ + mov x0, x14 + blr x10 + 1: + add x12, x12, #ERRATUM_ENTRY_SIZE + b errata_begin + errata_end: +.endm + +.macro cpu_reset_func_end _cpu:req + isb + ret x15 + endfunc \_cpu\()_reset_func +.endm + +/* + * Maintain compatibility with the old scheme of each cpu has its own reporting. + * TODO remove entirely once all cpus have been converted. This includes the + * cpu_ops entry, as print_errata_status can call this directly for all cpus + */ +.macro errata_report_shim _cpu:req + #if REPORT_ERRATA + func \_cpu\()_errata_report + /* normal stack frame for pretty debugging */ + stp x29, x30, [sp, #-16]! + mov x29, sp + + bl generic_errata_report + + ldp x29, x30, [sp], #16 + ret + endfunc \_cpu\()_errata_report + #endif +.endm #endif /* CPU_MACROS_S */
diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h index 463f890..cb004bf 100644 --- a/include/lib/cpus/aarch64/cpuamu.h +++ b/include/lib/cpus/aarch64/cpuamu.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index 24b6a87..84ab6bb 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h index 96b4661..6e784f6 100644 --- a/include/lib/cpus/aarch64/neoverse_e1.h +++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/neoverse_hermes.h b/include/lib/cpus/aarch64/neoverse_hermes.h new file mode 100644 index 0000000..22492c3 --- /dev/null +++ b/include/lib/cpus/aarch64/neoverse_hermes.h
@@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEOVERSE_HERMES_H +#define NEOVERSE_HERMES_H + +#define NEOVERSE_HERMES_MIDR U(0x410FD8E0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_HERMES_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEOVERSE_HERMES_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) + +#endif /* NEOVERSE_HERMES_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b6b8d8d..0ba5ad1 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index cb1be5b..b379fab 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,9 +43,17 @@ #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) /******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +/******************************************************************************* * CPU Auxiliary Control register 5 specific definitions. ******************************************************************************/ #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) @@ -57,5 +65,8 @@ #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) #define CPUECTLR2_EL1_PF_MODE_LSB U(11) #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) +#define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0) +#define CPUECTLR2_EL1_TXREQ_LSB U(0) +#define CPUECTLR2_EL1_TXREQ_WIDTH U(3) #endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h index 798ecd1..202ef5c 100644 --- a/include/lib/cpus/aarch64/neoverse_poseidon.h +++ b/include/lib/cpus/aarch64/neoverse_poseidon.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited. All rights reserved. + * Copyright (c) 2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index 3d48623..d618994 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -42,7 +42,10 @@ #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) #define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47) #define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0 +#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55) +#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56) #endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h index efb960e..68c1558 100644 --- a/include/lib/cpus/aarch64/neoverse_v2.h +++ b/include/lib/cpus/aarch64/neoverse_v2.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,4 +23,31 @@ #define NEOVERSE_V2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * CPU Extended Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) + +/******************************************************************************* + * CPU Auxiliary Control register 3 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR3_EL1 S3_0_C15_C1_2 +#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47) + +/******************************************************************************* + * CPU Auxiliary Control register 5 specific definitions. + ******************************************************************************/ +#define NEOVERSE_V2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56) +#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55) + #endif /* NEOVERSE_V2_H */
diff --git a/include/lib/cpus/aarch64/nevis.h b/include/lib/cpus/aarch64/nevis.h new file mode 100644 index 0000000..7006a29 --- /dev/null +++ b/include/lib/cpus/aarch64/nevis.h
@@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NEVIS_H +#define NEVIS_H + +#define NEVIS_MIDR U(0x410FD8A0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define NEVIS_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define NEVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +#endif /* NEVIS_H */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h index 14da170..58923d2 100644 --- a/include/lib/cpus/aarch64/qemu_max.h +++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/aarch64/travis.h b/include/lib/cpus/aarch64/travis.h new file mode 100644 index 0000000..a8a2556 --- /dev/null +++ b/include/lib/cpus/aarch64/travis.h
@@ -0,0 +1,29 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TRAVIS_H +#define TRAVIS_H + +#define TRAVIS_MIDR U(0x410FD8C0) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ +#define TRAVIS_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) + +/******************************************************************************* + * SME Control registers + ******************************************************************************/ +#define TRAVIS_SVCRSM S0_3_C4_C2_3 +#define TRAVIS_SVCRZA S0_3_C4_C4_3 + +#endif /* TRAVIS_H */
diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h new file mode 100644 index 0000000..8b36ff1 --- /dev/null +++ b/include/lib/cpus/cpu_ops.h
@@ -0,0 +1,152 @@ +/* + * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CPU_OPS_H +#define CPU_OPS_H + +#include <arch.h> + +#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ + (MIDR_PN_MASK << MIDR_PN_SHIFT) + +/* Hardcode to keep compatible with assembly. sizeof(uintptr_t) */ +#if __aarch64__ +#define CPU_WORD_SIZE 8 +#else +#define CPU_WORD_SIZE 4 +#endif /* __aarch64__ */ + +/* The number of CPU operations allowed */ +#define CPU_MAX_PWR_DWN_OPS 2 +/* Special constant to specify that CPU has no reset function */ +#define CPU_NO_RESET_FUNC 0 + +#if __aarch64__ +#define CPU_NO_EXTRA1_FUNC 0 +#define CPU_NO_EXTRA2_FUNC 0 +#define CPU_NO_EXTRA3_FUNC 0 +#endif /* __aarch64__ */ + + +/* + * Define the sizes of the fields in the cpu_ops structure. Word size is set per + * Aarch so keep these definitions the same and each can include whatever it + * needs. + */ +#define CPU_MIDR_SIZE CPU_WORD_SIZE +#ifdef IMAGE_AT_EL3 +#define CPU_RESET_FUNC_SIZE CPU_WORD_SIZE +#else +#define CPU_RESET_FUNC_SIZE 0 +#endif /* IMAGE_AT_EL3 */ +#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE +#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE +#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE +#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE +/* The power down core and cluster is needed only in BL31 and BL32 */ +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +#define CPU_PWR_DWN_OPS_SIZE CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS +#else +#define CPU_PWR_DWN_OPS_SIZE 0 +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ + +#define CPU_ERRATA_LIST_START_SIZE CPU_WORD_SIZE +#define CPU_ERRATA_LIST_END_SIZE CPU_WORD_SIZE +/* Fields required to print errata status */ +#if REPORT_ERRATA +#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE +#define CPU_CPU_STR_SIZE CPU_WORD_SIZE +/* BL1 doesn't require mutual exclusion and printed flag. */ +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +#define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE +#define CPU_ERRATA_PRINTED_SIZE CPU_WORD_SIZE +#else +#define CPU_ERRATA_LOCK_SIZE 0 +#define CPU_ERRATA_PRINTED_SIZE 0 +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ +#else +#define CPU_ERRATA_FUNC_SIZE 0 +#define CPU_CPU_STR_SIZE 0 +#define CPU_ERRATA_LOCK_SIZE 0 +#define CPU_ERRATA_PRINTED_SIZE 0 +#endif /* REPORT_ERRATA */ + +#if defined(IMAGE_BL31) && CRASH_REPORTING +#define CPU_REG_DUMP_SIZE CPU_WORD_SIZE +#else +#define CPU_REG_DUMP_SIZE 0 +#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */ + + +/* + * Define the offsets to the fields in cpu_ops structure. Every offset is + * defined based on the offset and size of the previous field. + */ +#define CPU_MIDR 0 +#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE +#if __aarch64__ +#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE +#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE +#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE +#define CPU_E_HANDLER_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE +#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE +#else +#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE +#endif /* __aarch64__ */ +#define CPU_ERRATA_LIST_START CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE +#define CPU_ERRATA_LIST_END CPU_ERRATA_LIST_START + CPU_ERRATA_LIST_START_SIZE +#define CPU_ERRATA_FUNC CPU_ERRATA_LIST_END + CPU_ERRATA_LIST_END_SIZE +#define CPU_CPU_STR CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE +#define CPU_ERRATA_LOCK CPU_CPU_STR + CPU_CPU_STR_SIZE +#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE +#if __aarch64__ +#define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#define CPU_OPS_SIZE CPU_REG_DUMP + CPU_REG_DUMP_SIZE +#else +#define CPU_OPS_SIZE CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#endif /* __aarch64__ */ + +#ifndef __ASSEMBLER__ +#include <lib/cassert.h> +#include <lib/spinlock.h> + +struct cpu_ops { + unsigned long midr; +#ifdef IMAGE_AT_EL3 + void (*reset_func)(void); +#endif /* IMAGE_AT_EL3 */ +#if __aarch64__ + void (*extra1_func)(void); + void (*extra2_func)(void); + void (*extra3_func)(void); + void (*e_handler_func)(long es); +#endif /* __aarch64__ */ +#if (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS + void (*pwr_dwn_ops[CPU_MAX_PWR_DWN_OPS])(void); +#endif /* (defined(IMAGE_BL31) || defined(IMAGE_BL32)) && CPU_MAX_PWR_DWN_OPS */ + void *errata_list_start; + void *errata_list_end; +#if REPORT_ERRATA + void (*errata_func)(void); + char *cpu_str; +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) + spinlock_t *errata_lock; + unsigned int *errata_reported; +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ +#endif /* REPORT_ERRATA */ +#if defined(IMAGE_BL31) && CRASH_REPORTING + void (*reg_dump)(void); +#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */ +} __packed; + +CASSERT(sizeof(struct cpu_ops) == CPU_OPS_SIZE, + assert_cpu_ops_asm_c_different_sizes); + +long cpu_get_rev_var(void); +void *get_cpu_ops_ptr(void); + +#endif /* __ASSEMBLER__ */ +#endif /* CPU_OPS_H */
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h new file mode 100644 index 0000000..2080898 --- /dev/null +++ b/include/lib/cpus/errata.h
@@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ERRATA_REPORT_H +#define ERRATA_REPORT_H + +#include <lib/cpus/cpu_ops.h> + + +#define ERRATUM_WA_FUNC_SIZE CPU_WORD_SIZE +#define ERRATUM_CHECK_FUNC_SIZE CPU_WORD_SIZE +#define ERRATUM_ID_SIZE 4 +#define ERRATUM_CVE_SIZE 2 +#define ERRATUM_CHOSEN_SIZE 1 +#define ERRATUM_MITIGATED_SIZE 1 + +#define ERRATUM_WA_FUNC 0 +#define ERRATUM_CHECK_FUNC ERRATUM_WA_FUNC + ERRATUM_WA_FUNC_SIZE +#define ERRATUM_ID ERRATUM_CHECK_FUNC + ERRATUM_CHECK_FUNC_SIZE +#define ERRATUM_CVE ERRATUM_ID + ERRATUM_ID_SIZE +#define ERRATUM_CHOSEN ERRATUM_CVE + ERRATUM_CVE_SIZE +#define ERRATUM_MITIGATED ERRATUM_CHOSEN + ERRATUM_CHOSEN_SIZE +#define ERRATUM_ENTRY_SIZE ERRATUM_MITIGATED + ERRATUM_MITIGATED_SIZE + +#ifndef __ASSEMBLER__ +#include <lib/cassert.h> + +void print_errata_status(void); +void errata_print_msg(unsigned int status, const char *cpu, const char *id); + +/* + * NOTE that this structure will be different on AArch32 and AArch64. The + * uintptr_t will reflect the change and the alignment will be correct in both. + */ +struct erratum_entry { + uintptr_t (*wa_func)(uint64_t cpu_rev); + uintptr_t (*check_func)(uint64_t cpu_rev); + /* Will fit CVEs with up to 10 character in the ID field */ + uint32_t id; + /* Denote CVEs with their year or errata with 0 */ + uint16_t cve; + uint8_t chosen; + /* TODO(errata ABI): placeholder for the mitigated field */ + uint8_t _mitigated; +} __packed; + +CASSERT(sizeof(struct erratum_entry) == ERRATUM_ENTRY_SIZE, + assert_erratum_entry_asm_c_different_sizes); +#else + +/* + * errata framework macro helpers + * + * NOTE an erratum and CVE id could clash. However, both numbers are very large + * and the probablity is minuscule. Working around this makes code very + * complicated and extremely difficult to read so it is not considered. In the + * unlikely event that this does happen, prepending the CVE id with a 0 should + * resolve the conflict + */ +#define ERRATUM(id) 0, id +#define CVE(year, id) year, id +#define NO_ISB 1 +#define NO_ASSERT 0 +#define NO_APPLY_AT_RESET 0 +#define APPLY_AT_RESET 1 +#define GET_CPU_REV 1 +#define NO_GET_CPU_REV 0 + +/* useful for errata that end up always being worked around */ +#define ERRATUM_ALWAYS_CHOSEN 1 + +#endif /* __ASSEMBLER__ */ + +/* Errata status */ +#define ERRATA_NOT_APPLIES 0 +#define ERRATA_APPLIES 1 +#define ERRATA_MISSING 2 + +/* Macro to get CPU revision code for checking errata version compatibility. */ +#define CPU_REV(r, p) ((r << 4) | p) + +#endif /* ERRATA_REPORT_H */
diff --git a/include/lib/cpus/errata_report.h b/include/lib/cpus/errata_report.h deleted file mode 100644 index efdedf0..0000000 --- a/include/lib/cpus/errata_report.h +++ /dev/null
@@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef ERRATA_REPORT_H -#define ERRATA_REPORT_H - -#ifndef __ASSEMBLER__ - -#include <arch.h> -#include <arch_helpers.h> -#include <lib/spinlock.h> -#include <lib/utils_def.h> - -#if DEBUG -void print_errata_status(void); -#else -static inline void print_errata_status(void) {} -#endif - -void errata_print_msg(unsigned int status, const char *cpu, const char *id); -int errata_needs_reporting(spinlock_t *lock, uint32_t *reported); - -#endif /* __ASSEMBLER__ */ - -/* Errata status */ -#define ERRATA_NOT_APPLIES 0 -#define ERRATA_APPLIES 1 -#define ERRATA_MISSING 2 - -/* Macro to get CPU revision code for checking errata version compatibility. */ -#define CPU_REV(r, p) ((r << 4) | p) - -#endif /* ERRATA_REPORT_H */
diff --git a/include/lib/cpus/wa_cve_2017_5715.h b/include/lib/cpus/wa_cve_2017_5715.h index 940fc65..2ad56e1 100644 --- a/include/lib/cpus/wa_cve_2017_5715.h +++ b/include/lib/cpus/wa_cve_2017_5715.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/wa_cve_2018_3639.h b/include/lib/cpus/wa_cve_2018_3639.h index e37db37..5a7c9bf 100644 --- a/include/lib/cpus/wa_cve_2018_3639.h +++ b/include/lib/cpus/wa_cve_2018_3639.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/cpus/wa_cve_2022_23960.h b/include/lib/cpus/wa_cve_2022_23960.h index 35b3fd8..50c0f76 100644 --- a/include/lib/cpus/wa_cve_2022_23960.h +++ b/include/lib/cpus/wa_cve_2022_23960.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/el3_runtime/aarch32/context.h b/include/lib/el3_runtime/aarch32/context.h index df77c0f..3b698e3 100644 --- a/include/lib/el3_runtime/aarch32/context.h +++ b/include/lib/el3_runtime/aarch32/context.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index e6af43e..47d91de 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef CONTEXT_H #define CONTEXT_H +#include <lib/el3_runtime/cpu_data.h> #include <lib/utils_def.h> /******************************************************************************* @@ -61,9 +62,23 @@ #define CTX_ELR_EL3 U(0x20) #define CTX_PMCR_EL0 U(0x28) #define CTX_IS_IN_EL3 U(0x30) -#define CTX_CPTR_EL3 U(0x38) -#define CTX_ZCR_EL3 U(0x40) -#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ +#define CTX_MPAM3_EL3 U(0x38) +/* Constants required in supporting nested exception in EL3 */ +#define CTX_SAVED_ELR_EL3 U(0x40) +/* + * General purpose flag, to save various EL3 states + * FFH mode : Used to identify if handling nested exception + * KFH mode : Used as counter value + */ +#define CTX_NESTED_EA_FLAG U(0x48) +#if FFH_SUPPORT + #define CTX_SAVED_ESR_EL3 U(0x50) + #define CTX_SAVED_SPSR_EL3 U(0x58) + #define CTX_SAVED_GPREG_LR U(0x60) + #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */ +#else + #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ +#endif /******************************************************************************* * Constants that allow assembler code to access members of and the @@ -323,6 +338,13 @@ #define CTX_PAUTH_REGS_END U(0) #endif /* CTX_INCLUDE_PAUTH_REGS */ +/******************************************************************************* + * Registers initialised in a per-world context. + ******************************************************************************/ +#define CTX_CPTR_EL3 U(0x0) +#define CTX_ZCR_EL3 U(0x8) +#define CTX_GLOBAL_EL3STATE_END U(0x10) + #ifndef __ASSEMBLER__ #include <stdint.h> @@ -433,6 +455,17 @@ #endif } cpu_context_t; +/* + * Per-World Context. + * It stores registers whose values can be shared across CPUs. + */ +typedef struct per_world_context { + uint64_t ctx_cptr_el3; + uint64_t ctx_zcr_el3; +} per_world_context_t; + +extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; + /* Macros to access members of the 'cpu_context_t' structure */ #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) #if CTX_INCLUDE_FPREGS @@ -516,15 +549,6 @@ void el1_sysregs_context_save(el1_sysregs_t *regs); void el1_sysregs_context_restore(el1_sysregs_t *regs); -#if CTX_INCLUDE_EL2_REGS -void el2_sysregs_context_save_common(el2_sysregs_t *regs); -void el2_sysregs_context_restore_common(el2_sysregs_t *regs); -#if CTX_INCLUDE_MTE_REGS -void el2_sysregs_context_save_mte(el2_sysregs_t *regs); -void el2_sysregs_context_restore_mte(el2_sysregs_t *regs); -#endif /* CTX_INCLUDE_MTE_REGS */ -#endif /* CTX_INCLUDE_EL2_REGS */ - #if CTX_INCLUDE_FPREGS void fpregs_context_save(fp_regs_t *regs); void fpregs_context_restore(fp_regs_t *regs);
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index 1a76d8e..b2bdaf5 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -37,6 +37,10 @@ void cm_prepare_el3_exit_ns(void); #ifdef __aarch64__ +#if IMAGE_BL31 +void cm_manage_extensions_el3(void); +void manage_extensions_nonsecure_per_world(void); +#endif #if CTX_INCLUDE_EL2_REGS void cm_el2_sysregs_context_save(uint32_t security_state); void cm_el2_sysregs_context_restore(uint32_t security_state); @@ -84,6 +88,8 @@ #else void *cm_get_next_context(void); void cm_set_next_context(void *context); +static inline void cm_manage_extensions_el3(void) {} +static inline void manage_extensions_nonsecure_per_world(void) {} #endif /* __aarch64__ */ #endif /* CONTEXT_MGMT_H */
diff --git a/include/lib/el3_runtime/pubsub_events.h b/include/lib/el3_runtime/pubsub_events.h index 5012082..d0c0502 100644 --- a/include/lib/el3_runtime/pubsub_events.h +++ b/include/lib/el3_runtime/pubsub_events.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h index de476e4..a396b99 100644 --- a/include/lib/extensions/amu.h +++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,21 +16,34 @@ #if ENABLE_FEAT_AMU #if __aarch64__ -void amu_enable(bool el2_unused, cpu_context_t *ctx); +void amu_enable(cpu_context_t *ctx); +void amu_init_el3(void); +void amu_init_el2_unused(void); +void amu_enable_per_world(per_world_context_t *per_world_ctx); #else void amu_enable(bool el2_unused); -#endif +#endif /* __aarch64__ */ + #else #if __aarch64__ -static inline void amu_enable(bool el2_unused, cpu_context_t *ctx) +void amu_enable(cpu_context_t *ctx) +{ +} +void amu_init_el3(void) +{ +} +void amu_init_el2_unused(void) +{ +} +void amu_enable_per_world(per_world_context_t *per_world_ctx) { } #else static inline void amu_enable(bool el2_unused) { } -#endif -#endif +#endif /*__aarch64__ */ +#endif /* ENABLE_FEAT_AMU */ #if ENABLE_AMU_AUXILIARY_COUNTERS /*
diff --git a/include/lib/extensions/brbe.h b/include/lib/extensions/brbe.h index 9ee2444..194efba 100644 --- a/include/lib/extensions/brbe.h +++ b/include/lib/extensions/brbe.h
@@ -8,9 +8,9 @@ #define BRBE_H #if ENABLE_BRBE_FOR_NS -void brbe_enable(void); +void brbe_init_el3(void); #else -static inline void brbe_enable(void) +static inline void brbe_init_el3(void) { } #endif /* ENABLE_BRBE_FOR_NS */
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h index 4327278..170f919 100644 --- a/include/lib/extensions/mpam.h +++ b/include/lib/extensions/mpam.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,12 +9,18 @@ #include <stdbool.h> -#if ENABLE_MPAM_FOR_LOWER_ELS -void mpam_enable(bool el2_unused); +#include <context.h> + +#if ENABLE_FEAT_MPAM +void mpam_enable(cpu_context_t *context); +void mpam_init_el2_unused(void); #else -static inline void mpam_enable(bool el2_unused) +static inline void mpam_enable(cpu_context_t *context) { } -#endif +static inline void mpam_init_el2_unused(void) +{ +} +#endif /* ENABLE_FEAT_MPAM */ #endif /* MPAM_H */
diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h index 2e780de..dbc2226 100644 --- a/include/lib/extensions/pauth.h +++ b/include/lib/extensions/pauth.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/extensions/pmuv3.h b/include/lib/extensions/pmuv3.h new file mode 100644 index 0000000..62fee7b --- /dev/null +++ b/include/lib/extensions/pmuv3.h
@@ -0,0 +1,19 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PMUV3_H +#define PMUV3_H + +#include <context.h> + +void pmuv3_init_el3(void); + +#ifdef __aarch64__ +void pmuv3_enable(cpu_context_t *ctx); +void pmuv3_init_el2_unused(void); +#endif /* __aarch64__ */ + +#endif /* PMUV3_H */
diff --git a/include/lib/extensions/ras.h b/include/lib/extensions/ras.h index 793ab9f..6997da0 100644 --- a/include/lib/extensions/ras.h +++ b/include/lib/extensions/ras.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h index 55760b0..e0aee50 100644 --- a/include/lib/extensions/ras_arch.h +++ b/include/lib/extensions/ras_arch.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
diff --git a/include/lib/extensions/sme.h b/include/lib/extensions/sme.h index 0e9c4b9..bd7948e 100644 --- a/include/lib/extensions/sme.h +++ b/include/lib/extensions/sme.h
@@ -21,15 +21,31 @@ #define SME_SMCR_LEN_MAX U(0x1FF) #if ENABLE_SME_FOR_NS +void sme_init_el3(void); +void sme_init_el2_unused(void); void sme_enable(cpu_context_t *context); void sme_disable(cpu_context_t *context); +void sme_enable_per_world(per_world_context_t *per_world_ctx); +void sme_disable_per_world(per_world_context_t *per_world_ctx); #else +static inline void sme_init_el3(void) +{ +} +static inline void sme_init_el2_unused(void) +{ +} static inline void sme_enable(cpu_context_t *context) { } static inline void sme_disable(cpu_context_t *context) { } +static inline void sme_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sme_disable_per_world(per_world_context_t *per_world_ctx) +{ +} #endif /* ENABLE_SME_FOR_NS */ #endif /* SME_H */
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h index 02fccae..7b39037 100644 --- a/include/lib/extensions/spe.h +++ b/include/lib/extensions/spe.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,15 +10,19 @@ #include <stdbool.h> #if ENABLE_SPE_FOR_NS -void spe_enable(bool el2_unused); +void spe_init_el3(void); +void spe_init_el2_unused(void); void spe_disable(void); #else -static inline void spe_enable(bool el2_unused) +static inline void spe_init_el3(void) +{ +} +static inline void spe_init_el2_unused(void) { } static inline void spe_disable(void) { } -#endif +#endif /* ENABLE_SPE_FOR_NS */ #endif /* SPE_H */
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h index 1faed2d..947c905 100644 --- a/include/lib/extensions/sve.h +++ b/include/lib/extensions/sve.h
@@ -10,13 +10,17 @@ #include <context.h> #if (ENABLE_SME_FOR_NS || ENABLE_SVE_FOR_NS) -void sve_enable(cpu_context_t *context); -void sve_disable(cpu_context_t *context); +void sve_init_el2_unused(void); +void sve_enable_per_world(per_world_context_t *per_world_ctx); +void sve_disable_per_world(per_world_context_t *per_world_ctx); #else -static inline void sve_enable(cpu_context_t *context) +static inline void sve_init_el2_unused(void) { } -static inline void sve_disable(cpu_context_t *context) +static inline void sve_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sve_disable_per_world(per_world_context_t *per_world_ctx) { } #endif /* ( ENABLE_SME_FOR_NS | ENABLE_SVE_FOR_NS ) */
diff --git a/include/lib/extensions/sys_reg_trace.h b/include/lib/extensions/sys_reg_trace.h index 5915c55..7004267 100644 --- a/include/lib/extensions/sys_reg_trace.h +++ b/include/lib/extensions/sys_reg_trace.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,23 +10,33 @@ #include <context.h> #if ENABLE_SYS_REG_TRACE_FOR_NS + #if __aarch64__ -void sys_reg_trace_enable(cpu_context_t *context); +void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx); +void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx); +void sys_reg_trace_init_el2_unused(void); #else -void sys_reg_trace_enable(void); +void sys_reg_trace_init_el3(void); #endif /* __aarch64__ */ #else /* !ENABLE_SYS_REG_TRACE_FOR_NS */ #if __aarch64__ -static inline void sys_reg_trace_enable(cpu_context_t *context) +static inline void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx) +{ +} +static inline void sys_reg_trace_init_el2_unused(void) { } #else -static inline void sys_reg_trace_enable(void) +static inline void sys_reg_trace_init_el3(void) { } #endif /* __aarch64__ */ + #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */ #endif /* SYS_REG_TRACE_H */
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h index 861a4ad..0bed433 100644 --- a/include/lib/extensions/trbe.h +++ b/include/lib/extensions/trbe.h
@@ -8,9 +8,13 @@ #define TRBE_H #if ENABLE_TRBE_FOR_NS -void trbe_enable(void); +void trbe_init_el3(void); +void trbe_init_el2_unused(void); #else -static inline void trbe_enable(void) +static inline void trbe_init_el3(void) +{ +} +static inline void trbe_init_el2_unused(void) { } #endif /* ENABLE_TRBE_FOR_NS */
diff --git a/include/lib/extensions/trf.h b/include/lib/extensions/trf.h index 91a9615..1ac7cda 100644 --- a/include/lib/extensions/trf.h +++ b/include/lib/extensions/trf.h
@@ -8,9 +8,13 @@ #define TRF_H #if ENABLE_TRF_FOR_NS -void trf_enable(void); +void trf_init_el3(void); +void trf_init_el2_unused(void); #else -static inline void trf_enable(void) +static inline void trf_init_el3(void) +{ +} +static inline void trf_init_el2_unused(void) { } #endif /* ENABLE_TRF_FOR_NS */
diff --git a/include/lib/fconf/fconf.h b/include/lib/fconf/fconf.h index 3762021..5b54c04 100644 --- a/include/lib/fconf/fconf.h +++ b/include/lib/fconf/fconf.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/fconf/fconf_tbbr_getter.h b/include/lib/fconf/fconf_tbbr_getter.h index db98b68..541a396 100644 --- a/include/lib/fconf/fconf_tbbr_getter.h +++ b/include/lib/fconf/fconf_tbbr_getter.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch32/endian_.h b/include/lib/libc/aarch32/endian_.h index 0cf2c75..edca496 100644 --- a/include/lib/libc/aarch32/endian_.h +++ b/include/lib/libc/aarch32/endian_.h
@@ -32,7 +32,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/aarch32/inttypes_.h b/include/lib/libc/aarch32/inttypes_.h index ef3fb8f..0888bf0 100644 --- a/include/lib/libc/aarch32/inttypes_.h +++ b/include/lib/libc/aarch32/inttypes_.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2020, ARM Limited and Contributors. + * Portions copyright (c) 2020, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/aarch32/limits_.h b/include/lib/libc/aarch32/limits_.h index a67ec53..5b0516a 100644 --- a/include/lib/libc/aarch32/limits_.h +++ b/include/lib/libc/aarch32/limits_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch32/stddef_.h b/include/lib/libc/aarch32/stddef_.h index 36dc20b..14ed094 100644 --- a/include/lib/libc/aarch32/stddef_.h +++ b/include/lib/libc/aarch32/stddef_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch32/stdint_.h b/include/lib/libc/aarch32/stdint_.h index dafe142..6e2deed 100644 --- a/include/lib/libc/aarch32/stdint_.h +++ b/include/lib/libc/aarch32/stdint_.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2020, ARM Limited and Contributors. + * Portions copyright (c) 2020, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/aarch32/stdio_.h b/include/lib/libc/aarch32/stdio_.h index 5e49425..7042664 100644 --- a/include/lib/libc/aarch32/stdio_.h +++ b/include/lib/libc/aarch32/stdio_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch64/endian_.h b/include/lib/libc/aarch64/endian_.h index 7c79fd4..58273d7 100644 --- a/include/lib/libc/aarch64/endian_.h +++ b/include/lib/libc/aarch64/endian_.h
@@ -32,7 +32,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/aarch64/inttypes_.h b/include/lib/libc/aarch64/inttypes_.h index f25882f..6109084 100644 --- a/include/lib/libc/aarch64/inttypes_.h +++ b/include/lib/libc/aarch64/inttypes_.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2020, ARM Limited and Contributors. + * Portions copyright (c) 2020, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/aarch64/limits_.h b/include/lib/libc/aarch64/limits_.h index 1bb0681..834439e 100644 --- a/include/lib/libc/aarch64/limits_.h +++ b/include/lib/libc/aarch64/limits_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch64/setjmp_.h b/include/lib/libc/aarch64/setjmp_.h index f880a17..a7d0b5c 100644 --- a/include/lib/libc/aarch64/setjmp_.h +++ b/include/lib/libc/aarch64/setjmp_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch64/stddef_.h b/include/lib/libc/aarch64/stddef_.h index 6ecc606..963048e 100644 --- a/include/lib/libc/aarch64/stddef_.h +++ b/include/lib/libc/aarch64/stddef_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/aarch64/stdint_.h b/include/lib/libc/aarch64/stdint_.h index 56e9f1b..34a75ec 100644 --- a/include/lib/libc/aarch64/stdint_.h +++ b/include/lib/libc/aarch64/stdint_.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2020, ARM Limited and Contributors. + * Portions copyright (c) 2020, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/aarch64/stdio_.h b/include/lib/libc/aarch64/stdio_.h index afaeadc..331bcaa 100644 --- a/include/lib/libc/aarch64/stdio_.h +++ b/include/lib/libc/aarch64/stdio_.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h index eb08552..d1bc0f9 100644 --- a/include/lib/libc/arm_acle.h +++ b/include/lib/libc/arm_acle.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 ARM Limited + * Copyright (c) 2021 Arm Limited * * SPDX-License-Identifier: BSD-3-Clause *
diff --git a/include/lib/libc/assert.h b/include/lib/libc/assert.h index 462bb43..acfd147 100644 --- a/include/lib/libc/assert.h +++ b/include/lib/libc/assert.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h index 2423f38..b11d072 100644 --- a/include/lib/libc/cdefs.h +++ b/include/lib/libc/cdefs.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/endian.h b/include/lib/libc/endian.h index 4100f57..9c9fd58 100644 --- a/include/lib/libc/endian.h +++ b/include/lib/libc/endian.h
@@ -28,7 +28,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/errno.h b/include/lib/libc/errno.h index 029912f..b536fe9 100644 --- a/include/lib/libc/errno.h +++ b/include/lib/libc/errno.h
@@ -37,7 +37,7 @@ * $FreeBSD$ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/inttypes.h b/include/lib/libc/inttypes.h index 6ad1c9e..344b71c 100644 --- a/include/lib/libc/inttypes.h +++ b/include/lib/libc/inttypes.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2020, ARM Limited and Contributors. + * Portions copyright (c) 2020, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/limits.h b/include/lib/libc/limits.h index 41bb658..c5c8764 100644 --- a/include/lib/libc/limits.h +++ b/include/lib/libc/limits.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/setjmp.h b/include/lib/libc/setjmp.h index be8e2c0..871c868 100644 --- a/include/lib/libc/setjmp.h +++ b/include/lib/libc/setjmp.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/stdarg.h b/include/lib/libc/stdarg.h index e260b9b..2d1f785 100644 --- a/include/lib/libc/stdarg.h +++ b/include/lib/libc/stdarg.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/stdbool.h b/include/lib/libc/stdbool.h index b58334c..c2c9b22 100644 --- a/include/lib/libc/stdbool.h +++ b/include/lib/libc/stdbool.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/libc/stddef.h b/include/lib/libc/stddef.h index 58a519e..aaad673 100644 --- a/include/lib/libc/stddef.h +++ b/include/lib/libc/stddef.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/stdint.h b/include/lib/libc/stdint.h index e96a25c..88502e7 100644 --- a/include/lib/libc/stdint.h +++ b/include/lib/libc/stdint.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/stdio.h b/include/lib/libc/stdio.h index ba13683..5ceaf68 100644 --- a/include/lib/libc/stdio.h +++ b/include/lib/libc/stdio.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/stdlib.h b/include/lib/libc/stdlib.h index 4641e56..4e5a824 100644 --- a/include/lib/libc/stdlib.h +++ b/include/lib/libc/stdlib.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h index 9894483..8129404 100644 --- a/include/lib/libc/string.h +++ b/include/lib/libc/string.h
@@ -4,7 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2020, ARM Limited and Contributors. + * Portions copyright (c) 2018-2020, Arm Limited and Contributors. + * Portions copyright (c) 2023, Intel Corporation. All rights reserved. * All rights reserved. */ @@ -14,6 +15,7 @@ #include <stddef.h> void *memcpy(void *dst, const void *src, size_t len); +int memcpy_s(void *dst, size_t dsize, void *src, size_t ssize); void *memmove(void *dst, const void *src, size_t len); int memcmp(const void *s1, const void *s2, size_t len); int strcmp(const char *s1, const char *s2);
diff --git a/include/lib/libc/time.h b/include/lib/libc/time.h index c1c95e5..e1eb2a5 100644 --- a/include/lib/libc/time.h +++ b/include/lib/libc/time.h
@@ -4,7 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ /* - * Portions copyright (c) 2018-2019, ARM Limited and Contributors. + * Portions copyright (c) 2018-2019, Arm Limited and Contributors. * All rights reserved. */
diff --git a/include/lib/libfdt/fdt.h b/include/lib/libfdt/fdt.h index eb9edb7..c9acc0c 100644 --- a/include/lib/libfdt/fdt.h +++ b/include/lib/libfdt/fdt.h
@@ -35,14 +35,14 @@ struct fdt_node_header { fdt32_t tag; - char name[0]; + char name[]; }; struct fdt_property { fdt32_t tag; fdt32_t len; fdt32_t nameoff; - char data[0]; + char data[]; }; #endif /* !__ASSEMBLER__*/
diff --git a/include/lib/libfdt/libfdt.h b/include/lib/libfdt/libfdt.h index a7f432c..d0a2ed2 100644 --- a/include/lib/libfdt/libfdt.h +++ b/include/lib/libfdt/libfdt.h
@@ -660,6 +660,13 @@ const struct fdt_property *fdt_get_property_by_offset(const void *fdt, int offset, int *lenp); +static inline struct fdt_property *fdt_get_property_by_offset_w(void *fdt, + int offset, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property_by_offset(fdt, offset, lenp); +} /** * fdt_get_property_namelen - find a property based on substring
diff --git a/include/lib/mmio.h b/include/lib/mmio.h index 3242a7c..591d7b6 100644 --- a/include/lib/mmio.h +++ b/include/lib/mmio.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/object_pool.h b/include/lib/object_pool.h index 66e8c47..49584eb 100644 --- a/include/lib/object_pool.h +++ b/include/lib/object_pool.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/optee_utils.h b/include/lib/optee_utils.h index 8224d50..e1e9d80 100644 --- a/include/lib/optee_utils.h +++ b/include/lib/optee_utils.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/pmf/aarch64/pmf_asm_macros.S b/include/lib/pmf/aarch64/pmf_asm_macros.S index 5f3e6b7..792ede9 100644 --- a/include/lib/pmf/aarch64/pmf_asm_macros.S +++ b/include/lib/pmf/aarch64/pmf_asm_macros.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index fa990d2..9d901e2 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index 01cc179..f5f040b 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/psa/measured_boot.h b/include/lib/psa/measured_boot.h index 231da2c..af624a6 100644 --- a/include/lib/psa/measured_boot.h +++ b/include/lib/psa/measured_boot.h
@@ -36,10 +36,10 @@ * signer_id Pointer to signer_id buffer. * signer_id_size Size of the signer_id in bytes. * version Pointer to version buffer. - * version_size Size of the version string in bytes (with \0). + * version_size Size of the version string in bytes. * measurement_algo Algorithm identifier used for measurement. * sw_type Pointer to sw_type buffer. - * sw_type_size Size of the sw_type string in bytes (with \0). + * sw_type_size Size of the sw_type string in bytes. * measurement_value Pointer to measurement_value buffer. * measurement_value_size Size of the measurement_value in bytes. * lock_measurement Boolean flag requesting whether the measurement
diff --git a/include/lib/psa/psa_manifest/sid.h b/include/lib/psa/psa_manifest/sid.h index be78bae..7183112 100644 --- a/include/lib/psa/psa_manifest/sid.h +++ b/include/lib/psa/psa_manifest/sid.h
@@ -8,6 +8,9 @@ #ifndef PSA_MANIFEST_SID_H #define PSA_MANIFEST_SID_H +/******** RSS_SP_CRYPTO ********/ +#define RSS_CRYPTO_HANDLE (0x40000100U) + /******** RSS_SP_PLATFORM ********/ #define RSS_PLATFORM_SERVICE_HANDLE (0x40000105U)
diff --git a/include/lib/psa/rss_crypto_defs.h b/include/lib/psa/rss_crypto_defs.h new file mode 100644 index 0000000..b8c7426 --- /dev/null +++ b/include/lib/psa/rss_crypto_defs.h
@@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef RSS_CRYPTO_DEFS_H +#define RSS_CRYPTO_DEFS_H + +/* Declares types that encode errors, algorithms, key types, policies, etc. */ +#include "psa/crypto_types.h" + +/* + * Value identifying export public key function API, used to dispatch the request + * to the corresponding API implementation in the Crypto service backend. + * + */ +#define RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID (uint16_t)(0x701) + +/* + * The persistent key identifiers for RSS builtin keys. + */ +enum rss_key_id_builtin_t { + RSS_BUILTIN_KEY_ID_HOST_S_ROTPK = 0x7FFF816Cu, + RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK, + RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK, +}; + +/* + * This type is used to overcome a limitation within RSS firmware in the number of maximum + * IOVECs it can use especially in psa_aead_encrypt and psa_aead_decrypt. + */ +#define RSS_CRYPTO_MAX_NONCE_LENGTH (16u) +struct rss_crypto_aead_pack_input { + uint8_t nonce[RSS_CRYPTO_MAX_NONCE_LENGTH]; + uint32_t nonce_length; +}; + +/* + * Structure used to pack non-pointer types in a call + */ +struct rss_crypto_pack_iovec { + psa_key_id_t key_id; /* Key id */ + psa_algorithm_t alg; /* Algorithm */ + uint32_t op_handle; /* Frontend context handle associated + to a multipart operation */ + uint32_t capacity; /* Key derivation capacity */ + uint32_t ad_length; /* Additional Data length for multipart AEAD */ + uint32_t plaintext_length; /* Plaintext length for multipart AEAD */ + struct rss_crypto_aead_pack_input aead_in; /* Packs AEAD-related inputs */ + uint16_t function_id; /* Used to identify the function in the API dispatcher + to the service backend. See rss_crypto_func_sid for + detail */ + uint16_t step; /* Key derivation step */ +}; + +#endif /* RSS_CRYPTO_DEFS_H */
diff --git a/include/lib/psa/rss_platform_api.h b/include/lib/psa/rss_platform_api.h index 1dd7d05..8f74a51 100644 --- a/include/lib/psa/rss_platform_api.h +++ b/include/lib/psa/rss_platform_api.h
@@ -11,6 +11,7 @@ #include <stdint.h> #include "psa/error.h" +#include <rss_crypto_defs.h> #define RSS_PLATFORM_API_ID_NV_READ (1010) #define RSS_PLATFORM_API_ID_NV_INCREMENT (1011) @@ -41,4 +42,19 @@ rss_platform_nv_counter_read(uint32_t counter_id, uint32_t size, uint8_t *val); +/* + * Reads the public key or the public part of a key pair in binary format. + * + * key Identifier of the key to export. + * data Buffer where the key data is to be written. + * data_size Size of the data buffer in bytes. + * data_length On success, the number of bytes that make up the key data. + * + * PSA_SUCCESS if the value is read correctly. Otherwise, + * it returns a PSA_ERROR. + */ +psa_status_t +rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data, + size_t data_size, size_t *data_length); + #endif /* RSS_PLATFORM_API_H */
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index 4d7e58e..c40f955 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -319,13 +319,13 @@ int (*pwr_domain_on)(u_register_t mpidr); void (*pwr_domain_off)(const psci_power_state_t *target_state); int (*pwr_domain_off_early)(const psci_power_state_t *target_state); +#if PSCI_OS_INIT_MODE + int (*pwr_domain_validate_suspend)( + const psci_power_state_t *target_state); +#endif void (*pwr_domain_suspend_pwrdown_early)( const psci_power_state_t *target_state); -#if PSCI_OS_INIT_MODE - int (*pwr_domain_suspend)(const psci_power_state_t *target_state); -#else void (*pwr_domain_suspend)(const psci_power_state_t *target_state); -#endif void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); void (*pwr_domain_on_finish_late)( const psci_power_state_t *target_state);
diff --git a/include/lib/runtime_instr.h b/include/lib/runtime_instr.h index 303f27e..65fafa7 100644 --- a/include/lib/runtime_instr.h +++ b/include/lib/runtime_instr.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h index 24b030c..5c72e8b 100644 --- a/include/lib/semihosting.h +++ b/include/lib/semihosting.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 63637d5..8fd6093 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,7 @@ SMCCC_VERSION_MINOR_SHIFT)) #define SMCCC_MAJOR_VERSION U(1) -#define SMCCC_MINOR_VERSION U(2) +#define SMCCC_MINOR_VERSION U(4) /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention
diff --git a/include/lib/spinlock.h b/include/lib/spinlock.h index 0bf3ee0..9fd3fc6 100644 --- a/include/lib/spinlock.h +++ b/include/lib/spinlock.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/transfer_list.h b/include/lib/transfer_list.h new file mode 100644 index 0000000..54c8643 --- /dev/null +++ b/include/lib/transfer_list.h
@@ -0,0 +1,114 @@ +/* + * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __TRANSFER_LIST_H +#define __TRANSFER_LIST_H + +#include <stdbool.h> +#include <stdint.h> + +#include <lib/utils_def.h> + +#define TRANSFER_LIST_SIGNATURE U(0x006ed0ff) +#define TRANSFER_LIST_VERSION U(0x0001) + +// Init value of maximum alignment required by any TE data in the TL +// specified as a power of two +#define TRANSFER_LIST_INIT_MAX_ALIGN U(3) + +// alignment required by TE header start address, in bytes +#define TRANSFER_LIST_GRANULE U(8) + +// version of the register convention used. +// Set to 1 for both AArch64 and AArch32 according to fw handoff spec v0.9 +#define REGISTER_CONVENTION_VERSION_MASK (1 << 24) + +#ifndef __ASSEMBLER__ + +enum transfer_list_tag_id { + TL_TAG_EMPTY = 0, + TL_TAG_FDT = 1, + TL_TAG_HOB_BLOCK = 2, + TL_TAG_HOB_LIST = 3, + TL_TAG_ACPI_TABLE_AGGREGATE = 4, +}; + +enum transfer_list_ops { + TL_OPS_NON, // invalid for any operation + TL_OPS_ALL, // valid for all operations + TL_OPS_RO, // valid for read only + TL_OPS_CUS, // either abort or switch to special code to interpret +}; + +struct transfer_list_header { + uint32_t signature; + uint8_t checksum; + uint8_t version; + uint8_t hdr_size; + uint8_t alignment; // max alignment of TE data + uint32_t size; // TL header + all TEs + uint32_t max_size; + /* + * Commented out element used to visualize dynamic part of the + * data structure. + * + * Note that struct transfer_list_entry also is dynamic in size + * so the elements can't be indexed directly but instead must be + * traversed in order + * + * struct transfer_list_entry entries[]; + */ +}; + +struct transfer_list_entry { + uint16_t tag_id; + uint8_t reserved0; // place holder + uint8_t hdr_size; + uint32_t data_size; + /* + * Commented out element used to visualize dynamic part of the + * data structure. + * + * Note that padding is added at the end of @data to make to reach + * a 8-byte boundary. + * + * uint8_t data[ROUNDUP(data_size, 8)]; + */ +}; + +void transfer_list_dump(struct transfer_list_header *tl); +struct transfer_list_header *transfer_list_init(void *addr, size_t max_size); + +struct transfer_list_header *transfer_list_relocate(struct transfer_list_header *tl, + void *addr, size_t max_size); +enum transfer_list_ops transfer_list_check_header(const struct transfer_list_header *tl); + +void transfer_list_update_checksum(struct transfer_list_header *tl); +bool transfer_list_verify_checksum(const struct transfer_list_header *tl); + +bool transfer_list_set_data_size(struct transfer_list_header *tl, + struct transfer_list_entry *entry, + uint32_t new_data_size); + +void *transfer_list_entry_data(struct transfer_list_entry *entry); +bool transfer_list_rem(struct transfer_list_header *tl, struct transfer_list_entry *entry); + +struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl, + uint16_t tag_id, uint32_t data_size, + const void *data); + +struct transfer_list_entry *transfer_list_add_with_align(struct transfer_list_header *tl, + uint16_t tag_id, uint32_t data_size, + const void *data, uint8_t alignment); + +struct transfer_list_entry *transfer_list_next(struct transfer_list_header *tl, + struct transfer_list_entry *last); + +struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl, + uint16_t tag_id); + +#endif /*__ASSEMBLER__*/ +#endif /*__TRANSFER_LIST_H*/
diff --git a/include/lib/utils.h b/include/lib/utils.h index 17ee9369..ce76de2 100644 --- a/include/lib/utils.h +++ b/include/lib/utils.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 63eda63..a170a09 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -104,6 +104,41 @@ #define round_down(value, boundary) \ ((value) & ~round_boundary(value, boundary)) +/* add operation together with checking whether the operation overflowed + * The result is '*res', + * return 0 on success and 1 on overflow + */ +#define add_overflow(a, b, res) __builtin_add_overflow((a), (b), (res)) + +/* + * Round up a value to align with a given size and + * check whether overflow happens. + * The rounduped value is '*res', + * return 0 on success and 1 on overflow + */ +#define round_up_overflow(v, size, res) (__extension__({ \ + typeof(res) __res = res; \ + typeof(*(__res)) __roundup_tmp = 0; \ + typeof(v) __roundup_mask = (typeof(v))(size) - 1; \ + \ + add_overflow((v), __roundup_mask, &__roundup_tmp) ? 1 : \ + (void)(*(__res) = __roundup_tmp & ~__roundup_mask), 0; \ +})) + +/* + * Add a with b, then round up the result to align with a given size and + * check whether overflow happens. + * The rounduped value is '*res', + * return 0 on success and 1 on overflow + */ +#define add_with_round_up_overflow(a, b, size, res) (__extension__({ \ + typeof(a) __a = (a); \ + typeof(__a) __add_res = 0; \ + \ + add_overflow((__a), (b), &__add_res) ? 1 : \ + round_up_overflow(__add_res, (size), (res)) ? 1 : 0; \ +})) + /** * Helper macro to ensure a value lies on a given boundary. */
diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h index 252b92c..3a470ad 100644 --- a/include/lib/xlat_mpu/xlat_mpu.h +++ b/include/lib/xlat_mpu/xlat_mpu.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h index 30eb5e9..42a48f4 100644 --- a/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h +++ b/include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h index 3014c8f..6c0d73b 100644 --- a/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h +++ b/include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h index 269afd2..fabc494 100644 --- a/include/lib/xlat_tables/xlat_mmu_helpers.h +++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h index a156969..24f833c 100644 --- a/include/lib/xlat_tables/xlat_tables.h +++ b/include/lib/xlat_tables/xlat_tables.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/xlat_tables_arch.h b/include/lib/xlat_tables/xlat_tables_arch.h index 0ce0cac..46e058c 100644 --- a/include/lib/xlat_tables/xlat_tables_arch.h +++ b/include/lib/xlat_tables/xlat_tables_arch.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/xlat_tables_compat.h b/include/lib/xlat_tables/xlat_tables_compat.h index 5f28195..3877c91 100644 --- a/include/lib/xlat_tables/xlat_tables_compat.h +++ b/include/lib/xlat_tables/xlat_tables_compat.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index 4d16ced..64fe5ef 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/xlat_tables/xlat_tables_v2_helpers.h b/include/lib/xlat_tables/xlat_tables_v2_helpers.h index 62f853d..992c94e 100644 --- a/include/lib/xlat_tables/xlat_tables_v2_helpers.h +++ b/include/lib/xlat_tables/xlat_tables_v2_helpers.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/lib/zlib/tf_gunzip.h b/include/lib/zlib/tf_gunzip.h index 741ba50..9435860 100644 --- a/include/lib/zlib/tf_gunzip.h +++ b/include/lib/zlib/tf_gunzip.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/plat/arm/common/aarch64/arm_macros.S b/include/plat/arm/common/aarch64/arm_macros.S index d47e4e0..8aacfb0 100644 --- a/include/plat/arm/common/aarch64/arm_macros.S +++ b/include/plat/arm/common/aarch64/arm_macros.S
@@ -39,11 +39,17 @@ * --------------------------------------------- */ .macro arm_print_gic_regs - /* Check for GICv3 system register access */ + /* Check for GICv3/v4 system register access. + * ID_AA64PFR0_GIC indicates presence of the CPU + * system registers by either 0b0011 or 0xb0001. + * A value of 0b000 means CPU system registers aren't + * available and the code needs to use the memory + * mapped registers like in GICv2. + */ mrs x7, id_aa64pfr0_el1 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH - cmp x7, #1 - b.ne print_gicv2 + cmp x7, #0 + b.eq print_gicv2 /* Check for SRE enable */ mrs x8, ICC_SRE_EL3
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 16be971..e098c10 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h
@@ -24,8 +24,6 @@ */ #define ARM_ROTPK_HEADER_LEN 19 #define ARM_ROTPK_HASH_LEN 32 -/* ARM_ROTPK_KEY_LEN includes DER header + raw key material */ -#define ARM_ROTPK_KEY_LEN 294 /* Special value used to verify platform parameters from BL2 to BL31 */ #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) @@ -198,16 +196,7 @@ ARM_AP_TZC_DRAM1_SIZE - 1U) /* Define the Access permissions for Secure peripherals to NS_DRAM */ -#if ARM_CRYPTOCELL_INTEG -/* - * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. - * This is required by CryptoCell to authenticate BL33 which is loaded - * into the Non Secure DDR. - */ -#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD -#else #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE -#endif #ifdef SPD_opteed /* @@ -539,7 +528,8 @@ * Define limit of firmware configuration memory: * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory */ -#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) +#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) #if ENABLE_RME /* @@ -592,15 +582,15 @@ * As the BL31 image size appears to be increased when built with the ENABLE_PIE * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. */ -#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ - (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ - 0x3000) +#define BL2_OFFSET (0x5000) #else /* Put BL2 towards the middle of the Trusted SRAM */ -#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ - (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ - 0x2000) +#define BL2_OFFSET (0x2000) #endif /* ENABLE_PIE */ + +#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ + (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ + BL2_OFFSET) #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) #else @@ -775,10 +765,15 @@ #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) /* Priority levels for ARM platforms */ +#if ENABLE_FEAT_RAS && FFH_SUPPORT #define PLAT_RAS_PRI 0x10 +#endif #define PLAT_SDEI_CRITICAL_PRI 0x60 #define PLAT_SDEI_NORMAL_PRI 0x70 +/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ +#define PLAT_CORE_FAULT_IRQ 17 + /* ARM platforms use 3 upper bits of secure interrupt priority */ #define PLAT_PRI_BITS 3
diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h index 025d10e..266092e 100644 --- a/include/plat/arm/common/arm_sip_svc.h +++ b/include/plat/arm/common/arm_sip_svc.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019,2021-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019,2021-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,4 +35,21 @@ #define ARM_SIP_SVC_VERSION_MAJOR U(0x0) #define ARM_SIP_SVC_VERSION_MINOR U(0x2) +/* + * Arm SiP SMC calls that are primarily used for testing purposes. + */ +#if PLAT_TEST_SPM +#define ARM_SIP_SET_INTERRUPT_PENDING U(0x82000100) +#endif + +/* SiP handler specific to each Arm platform. */ +uintptr_t plat_arm_sip_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + #endif /* ARM_SIP_SVC_H */
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h index cafbc3e..d45c269 100644 --- a/include/plat/arm/common/fconf_ethosn_getter.h +++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -57,8 +57,6 @@ struct ethosn_device_t devices[ETHOSN_DEV_NUM_MAX]; }; -int fconf_populate_arm_ethosn(uintptr_t config); - extern struct ethosn_config_t ethosn_config; #endif /* FCONF_ETHOSN_GETTER_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index e8461f5..0fb06a6 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h
@@ -39,7 +39,21 @@ * - Region 1 with secure access only; * - the remaining DRAM regions access from the given Non-Secure masters. ******************************************************************************/ -#if SPM_MM + +#if ENABLE_RME +#define ARM_TZC_RME_REGIONS_DEF \ + {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ + {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ + {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + /* Realm and Shared area share the same PAS */ \ + {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} +#endif + +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) #define ARM_TZC_REGIONS_DEF \ {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ TZC_REGION_S_RDWR, 0}, \ @@ -52,16 +66,16 @@ PLAT_ARM_TZC_NS_DEV_ACCESS} #elif ENABLE_RME -#define ARM_TZC_REGIONS_DEF \ - {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ - {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ - {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ - PLAT_ARM_TZC_NS_DEV_ACCESS}, \ - /* Realm and Shared area share the same PAS */ \ - {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ - PLAT_ARM_TZC_NS_DEV_ACCESS}, \ - {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ - PLAT_ARM_TZC_NS_DEV_ACCESS} +#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ +MEASURED_BOOT +#define ARM_TZC_REGIONS_DEF \ + ARM_TZC_RME_REGIONS_DEF, \ + {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ + TZC_REGION_S_RDWR, 0} +#else +#define ARM_TZC_REGIONS_DEF \ + ARM_TZC_RME_REGIONS_DEF +#endif #else #define ARM_TZC_REGIONS_DEF \ @@ -162,10 +176,17 @@ #define STATE_SW_E_DENIED (-3) /* plat_get_rotpk_info() flags */ -#define ARM_ROTPK_REGS_ID 1 -#define ARM_ROTPK_DEVEL_RSA_ID 2 -#define ARM_ROTPK_DEVEL_ECDSA_ID 3 +#define ARM_ROTPK_REGS_ID 1 +#define ARM_ROTPK_DEVEL_RSA_ID 2 +#define ARM_ROTPK_DEVEL_ECDSA_ID 3 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 +#define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 + +#define ARM_USE_DEVEL_ROTPK \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) /* IO storage utility functions */ int arm_io_setup(void);
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index d146a29..4d1b1c1 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h
@@ -80,6 +80,20 @@ int plat_core_pos_by_mpidr(u_register_t mpidr); int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size); +/******************************************************************************* + * Simple routine to determine whether a mpidr is valid or not. + ******************************************************************************/ +static inline bool is_valid_mpidr(u_register_t mpidr) +{ + int pos = plat_core_pos_by_mpidr(mpidr); + + if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) { + return false; + } + + return true; +} + #if STACK_PROTECTOR_ENABLED /* * Return a new value to be used for the stack protection's canary. @@ -111,7 +125,7 @@ unsigned int plat_ic_get_interrupt_active(unsigned int id); void plat_ic_disable_interrupt(unsigned int id); void plat_ic_enable_interrupt(unsigned int id); -int plat_ic_has_interrupt_type(unsigned int type); +bool plat_ic_has_interrupt_type(unsigned int type); void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); @@ -146,6 +160,8 @@ int plat_mboot_measure_critical_data(unsigned int critical_data_id, const void *base, size_t size); +int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, + size_t pk_len); #else static inline int plat_mboot_measure_image(unsigned int image_id __unused, image_info_t *image_data __unused) @@ -159,6 +175,12 @@ { return 0; } +static inline int plat_mboot_measure_key(const void *pk_oid __unused, + const void *pk_ptr __unused, + size_t pk_len __unused) +{ + return 0; +} #endif /* MEASURED_BOOT */ /*******************************************************************************
diff --git a/include/plat/nuvoton/common/npcm845x_arm_def.h b/include/plat/nuvoton/common/npcm845x_arm_def.h new file mode 100644 index 0000000..5a44907 --- /dev/null +++ b/include/plat/nuvoton/common/npcm845x_arm_def.h
@@ -0,0 +1,567 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (C) 2017-2023 Nuvoton Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef NPCM845x_ARM_DEF_H +#define NPCM845x_ARM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +/* This flag will add zones to the MMU so that it will be possible to debug */ +#ifdef NPCM845X_DEBUG +#define ALLOW_DEBUG_MMU +#undef ALLOW_DEBUG_MMU +#endif /* NPCM845X_DEBUG */ + +#undef CONFIG_TARGET_ARBEL_PALLADIUM +/****************************************************************************** + * Definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Root of trust key hash lengths + */ +#define ARM_ROTPK_HEADER_LEN 19 +#define ARM_ROTPK_HASH_LEN 32 + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) + +/* No need for system because we have only one cluster */ +#define ARM_SYSTEM_COUNT U(0) + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. + * The power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +/* In NPCM845x - refers to cores */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 + +/* In NPCM845x - refers to cluster */ +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 + +/* No need for additional settings because the platform doesn't have system */ + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +#define NPCM845x_PLAT_PRIMARY_CPU U(0x0) +#define NPCM845x_CLUSTER_COUNT U(1) + +#ifdef SECONDARY_BRINGUP +#define NPCM845x_MAX_CPU_PER_CLUSTER U(2) +#define NPCM845x_PLATFORM_CORE_COUNT U(2) +#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2) +#else +#define NPCM845x_MAX_CPU_PER_CLUSTER U(4) +#define NPCM845x_PLATFORM_CORE_COUNT U(4) +#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4) +#endif /* SECONDARY_BRINGUP */ + +#define NPCM845x_SYSTEM_COUNT U(0) + +/* Memory mapping for NPCM845x */ +#define NPCM845x_REG_BASE 0xf0000000 +#define NPCM845x_REG_SIZE 0x0ff16000 + +/* + * DRAM + * 0x3fffffff +-------------+ + * | BL33 | (non-secure) + * 0x06200000 +-------------+ + * | BL32 SHARED | (non-secure) + * 0x06000000 +-------------+ + * | BL32 | (secure) + * 0x02100000 +-------------+ + * | BL31 | (secure) + * 0x02000000 +-------------+ + * | | (non-secure) + * 0x00000000 +-------------+ + * + * Trusted ROM + * 0xfff50000 +-------------+ + * | BL1 (ro) | + * 0xfff40000 +-------------+ + */ + +#define ARM_DRAM1_BASE ULL(0x00000000) +#ifndef CONFIG_TARGET_ARBEL_PALLADIUM +/* + * Although npcm845x is 4G, + * consider only 2G Trusted Firmware memory allocation + */ +#define ARM_DRAM1_SIZE ULL(0x37000000) +#else +#define ARM_DRAM1_SIZE ULL(0x10000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U) +#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ + +/* Check for redundancy */ +#ifdef NPCM845X_DEBUG +#define PLAT_ARM_NS_IMAGE_BASE 0x0 +#endif /* NPCM845X_DEBUG */ + +#define ARM_TZC_DRAM1_SIZE UL(0x01000000) +#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE +#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ + ARM_SCP_TZC_DRAM1_SIZE - 1U) + +/* + * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime + * firmware. This region is meant to be NOLOAD and will not be zero + * initialized. Data sections with the attribute `arm_el3_tzc_dram` + * will be placed here. + * + * NPCM845x - Currently the platform doesn't have EL3 implementation + * on secured DRAM. + */ +#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ + ARM_EL3_TZC_DRAM1_SIZE) +#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ +#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ + ARM_EL3_TZC_DRAM1_SIZE - 1U) + +#define ARM_AP_TZC_DRAM1_BASE 0x02100000 +#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ + (ARM_SCP_TZC_DRAM1_SIZE + \ + ARM_EL3_TZC_DRAM1_SIZE)) +#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - 1U) + +/* Define the Access permissions for Secure peripherals to NS_DRAM */ +#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE + +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE +#define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE +#define BL32_BASE ARM_AP_TZC_DRAM1_BASE +#define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) + +#define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \ + ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE) +#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) +#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ + ARM_OPTEE_PAGEABLE_LOAD_BASE, \ + ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager + * when paging support is enabled). + */ +#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1U) + +/* The platform doesn't use DRAM2 but it has to have a value for calculation */ +#define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */ +#define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */ +#define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U) + +#define FIRST_EXT_INTERRUPT_NUM U(32) +#define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM) + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties + * as per GICv3 terminology. On a GICv2 system or mode, + * the lists will be merged and treated as Group 0 interrupts. + */ +#define ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) + +#define ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ + PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ + GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef ALLOW_DEBUG_MMU +/* In order to be able to debug, + * the platform needs to add BL33 and BL32 to MMU as well. + */ +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#ifdef BL32_BASE +#define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* BL32_BASE */ + +#ifdef NPCM845X_DEBUG +#define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \ + 0xFFFB0000, 0x20000, \ + MT_MEMORY | MT_RW | MT_NS) +#endif /* NPCM845X_DEBUG */ +#endif /* BL32_BASE */ + +#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ + ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if ARM_BL31_IN_DRAM +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* ARM_BL31_IN_DRAM */ + +/* Currently the platform doesn't have EL3 implementation on secured DRAM. */ +#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ + ARM_EL3_TZC_DRAM1_BASE, \ + ARM_EL3_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if defined(SPD_spmd) +#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ + PLAT_ARM_TRUSTED_DRAM_BASE, \ + PLAT_ARM_TRUSTED_DRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_spmd */ + +/* + * Mapping for the BL1 RW region. This mapping is needed by BL2 + * in order to share the Mbed TLS heap. Since the heap is allocated + * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access + * to the BL1 RW region in order to be able to access the heap. + */ +#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ + BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \ + MT_MEMORY | MT_RW | EL3_PAS) + +/* + * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region + * for each section, otherwise one region containing both sections + * is defined. + */ +#if SEPARATE_CODE_AND_RODATA +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS), \ + MAP_REGION_FLAT(BL_RO_DATA_BASE, \ + BL_RO_DATA_END - BL_RO_DATA_BASE, \ + MT_RO_DATA | EL3_PAS) +#else +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | EL3_PAS) +#endif /* SEPARATE_CODE_AND_RODATA */ + +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | EL3_PAS) +#endif /* USE_COHERENT_MEM */ + +#if USE_ROMLIB +#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ + ROMLIB_RO_BASE, \ + ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \ + MT_CODE | MT_SECURE) + +#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ + ROMLIB_RW_BASE, \ + ROMLIB_RW_END - ROMLIB_RW_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* USE_ROMLIB */ + +/* + * Map mem_protect flash region with read and write permissions + */ +#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \ + PLAT_ARM_MEM_PROT_ADDR, \ + V2M_FLASH_BLOCK_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +/* + * Map the region for device tree configuration with read and write permissions + */ +#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ + ARM_BL_RAM_BASE, \ + (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * The max number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#define ARM_BL_REGIONS 10 + +#define MAX_MMAP_REGIONS ( \ + PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#define ARM_SYS_CNTCTL_BASE UL(0XF07FC000) + +#define ARM_CONSOLE_BAUDRATE 115200 + +/* + * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) + */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +/****************************************************************************** + * Required platform porting definitions common to all ARM standard platforms + *****************************************************************************/ + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches (64 on Arbel). + */ +#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) + +/* + * To enable FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space of BL2 meminfo. + */ +#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) +#define ARM_FW_CONFIG_LIMIT ( \ + (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U)) + +/* + * Boot parameters passed from BL2 to BL31/BL32 are stored here + */ +#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) +#define ARM_BL2_MEM_DESC_LIMIT ( \ + ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U)) + +/* + * Define limit of firmware configuration memory: + * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory + */ +#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need + * two sets of addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \ + (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE)) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \ + (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)) +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ + (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) + +#define ROMLIB_RO_BASE BL1_RO_LIMIT +#define ROMLIB_RO_LIMIT ( \ + PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) + +#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) +#define ROMLIB_RW_END ( \ + ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) + +/****************************************************************************** + * BL2 specific defines. + *****************************************************************************/ +#if BL2_AT_EL3 +/* Put BL2 towards the middle of the Trusted SRAM */ +#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ + PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) +#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#else +/* + * Put BL2 just below BL1. + */ +#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) +#define BL2_LIMIT BL1_RW_BASE +#endif /* BL2_AT_EL3 */ + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION +/* + * Put BL31 at the bottom of TZC secured DRAM + */ +#define BL31_BASE ARM_AP_TZC_DRAM1_BASE +#define BL31_LIMIT ( \ + ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE) + +/* + * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. + * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. + */ +#if SEPARATE_NOBITS_REGION +#define BL31_NOBITS_BASE BL2_BASE +#define BL31_NOBITS_LIMIT BL2_LIMIT +#endif /* SEPARATE_NOBITS_REGION */ +#elif (RESET_TO_BL31) +/* Ensure Position Independent support (PIE) is enabled for this config.*/ +#if !ENABLE_PIE +#error "BL31 must be a PIE if RESET_TO_BL31=1." +#endif /* !ENABLE_PIE */ +/* + * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely + * used for building BL31 and not used for loading BL31. + */ +#define NEW_SRAM_ALLOCATION + +#ifdef NEW_SRAM_ALLOCATION + #define BL31_BASE 0x20001000 +#else + #define BL31_BASE 0x20001000 +#endif /* NEW_SRAM_ALLOCATION */ + +#define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */ +#else +/* Put BL31 below BL2 in the Trusted SRAM.*/ +#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \ + PLAT_ARM_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL2_BASE + +/* + * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. + * This is because in the BL2_AT_EL3 configuration, BL2 is always resident. + */ +#if BL2_AT_EL3 +#define BL31_LIMIT BL2_BASE +#else +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#endif /* BL2_AT_EL3 */ +#endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */ + +/* + * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is + * no SPD and no SPM-MM, as they are the only ones that can be used as BL32. + */ +#if defined(SPD_none) && !SPM_MM +#undef BL32_BASE +#endif /* SPD_none && !SPM_MM */ + +/****************************************************************************** + * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. + *****************************************************************************/ +#define BL2U_BASE BL2_BASE +#define BL2U_LIMIT BL2_LIMIT + +#define NS_BL2U_BASE ARM_NS_DRAM1_BASE +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) + +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/* + * One cache line needed for bakery locks on ARM platforms + */ +#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) + +/* Priority levels for ARM platforms */ +#define PLAT_RAS_PRI 0x10 +#define PLAT_SDEI_CRITICAL_PRI 0x60 +#define PLAT_SDEI_NORMAL_PRI 0x70 + +/* ARM platforms use 3 upper bits of secure interrupt priority */ +#define ARM_PRI_BITS 3 + +/* SGI used for SDEI signalling */ +#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 + +#if SDEI_IN_FCONF +/* ARM SDEI dynamic private event max count */ +#define ARM_SDEI_DP_EVENT_MAX_CNT 3 + +/* ARM SDEI dynamic shared event max count */ +#define ARM_SDEI_DS_EVENT_MAX_CNT 3 +#else +/* ARM SDEI dynamic private event numbers */ +#define ARM_SDEI_DP_EVENT_0 1000 +#define ARM_SDEI_DP_EVENT_1 1001 +#define ARM_SDEI_DP_EVENT_2 1002 + +/* ARM SDEI dynamic shared event numbers */ +#define ARM_SDEI_DS_EVENT_0 2000 +#define ARM_SDEI_DS_EVENT_1 2001 +#define ARM_SDEI_DS_EVENT_2 2002 + +#define ARM_SDEI_PRIVATE_EVENTS \ + SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) + +#define ARM_SDEI_SHARED_EVENTS \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ + SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) +#endif /* SDEI_IN_FCONF */ + +#endif /* ARM_DEF_H */
diff --git a/include/plat/nuvoton/common/plat_macros.S b/include/plat/nuvoton/common/plat_macros.S new file mode 100644 index 0000000..08f9feb --- /dev/null +++ b/include/plat/nuvoton/common/plat_macros.S
@@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + +#include <arm_macros.S> +#include <cci_macros.S> +#include <platform_def.h> + +/* + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + */ +.macro plat_print_gic_regs +mov_imm x17, BASE_GICC_BASE +mov_imm x16, BASE_GICD_BASE +arm_print_gic_regs +.endm + +/* + * the below macros print out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1 + */ +.macro plat_print_interconnect_regs + /* TODO */ +.endm + +/* + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + */ +.macro plat_crash_print_regs + /* TODO */ +.endm + +#endif /* PLAT_MACROS_S */
diff --git a/include/plat/nuvoton/common/plat_npcm845x.h b/include/plat/nuvoton/common/plat_npcm845x.h new file mode 100644 index 0000000..d90952a --- /dev/null +++ b/include/plat/nuvoton/common/plat_npcm845x.h
@@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_NPCM845X_H +#define PLAT_NPCM845X_H + +#include <drivers/arm/gicv2.h> +#include <lib/psci/psci.h> + +unsigned int plat_calc_core_pos(uint64_t mpidr); +void npcm845x_mailbox_init(uintptr_t base_addr); +void plat_gic_driver_init(void); +void plat_gic_init(void); +void plat_gic_cpuif_enable(void); +void plat_gic_cpuif_disable(void); +void plat_gic_pcpu_init(void); + +void __dead2 npcm845x_system_off(void); +void __dead2 npcm845x_system_reset(void); +void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state); +bool npcm845x_is_wakeup_src_irqsteer(void); +void __dead2 npcm845x_pwr_down_wfi(const psci_power_state_t *target_state); +void npcm845x_cpu_standby(plat_local_state_t cpu_state); +int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint); +int npcm845x_pwr_domain_on(u_register_t mpidr); +int npcm845x_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); + +#if !ARM_BL31_IN_DRAM +void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state); +#endif + +void __dead2 npcm845x_pwr_domain_pwr_down_wfi( + const psci_power_state_t *target_state); +void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state); +void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state); +void npcm845x_pwr_domain_off(const psci_power_state_t *target_state); +void __init npcm845x_bl31_plat_arch_setup(void); + +#endif /* PLAT_NPCM845X_H */
diff --git a/include/plat/nuvoton/npcm845x/platform_def.h b/include/plat/nuvoton/npcm845x/platform_def.h new file mode 100644 index 0000000..09da36b --- /dev/null +++ b/include/plat/nuvoton/npcm845x/platform_def.h
@@ -0,0 +1,303 @@ +/* + * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. + * + * Copyright (c) 2017-2023 Nuvoton Technology Corp. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <common/interrupt_props.h> +#include <common/tbbr/tbbr_img_def.h> +#include <drivers/arm/gic_common.h> +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_defs.h> +#include <npcm845x_arm_def.h> +#include <plat/arm/common/smccc_def.h> +#include <plat/common/common_def.h> + +#define VALUE_TO_STRING(x) #x +#define VALUE(x) VALUE_TO_STRING(x) +#define VAR_NAME_VALUE(var) #var "=" VALUE(var) + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0x400 + +#define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT +#define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT +#define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER +#define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU +#define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN U(0) +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET U(1) +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF U(2) + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF +#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) +#define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL + +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +#ifdef BL32_BASE + +#ifndef CONFIG_TARGET_ARBEL_PALLADIUM +#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE +#else +#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE +#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */ + +#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ +#endif /* BL32_BASE */ + +#define PWR_DOMAIN_AT_MAX_LVL U(1) + +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 16 +#define PLAT_ARM_MMAP_ENTRIES 17 + +#ifdef NPCM845X_DEBUG +#define MAX_MMAP_REGIONS 8 +#define NPCM845X_TZ1_BASE 0xFFFB0000 +#endif /* NPCM845X_DEBUG */ + +#define FIQ_SMP_CALL_SGI 10 + +/* (0x00040000) 128 KB, the rest 128K if it is non secured */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000) + +#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ + +/* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */ +#define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE) + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) + +/* + * PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000 + * because only half is secured in this specific implementation + */ +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) + +#if RESET_TO_BL31 +/* Size of Trusted SRAM - the first 4KB of shared memory */ +#define PLAT_ARM_MAX_BL31_SIZE \ + (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) +#else +/* + * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE + * is calculated using the current BL31 PROGBITS debug size plus the sizes + * of BL2 and BL1-RW + */ +#define PLAT_ARM_MAX_BL31_SIZE \ + (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE) +#endif /* RESET_TO_BL31 */ +/* + * Load address of BL33 for this platform port + */ +#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000)) + +#ifdef NPCM845X_DEBUG +#define COUNTER_FREQUENCY 0x07735940 /* f/4 = 125MHz */ +#endif /* NPCM845X_DEBUG */ + +#define COUNTER_FREQUENCY 0x0EE6B280 /* f/2 = 250MHz */ +#define PLAT_ARM_NSTIMER_FRAME_ID U(1) + +/* GIC parameters */ + +/* Base compatible GIC memory map */ +#define NT_GIC_BASE (0xDFFF8000) +#define BASE_GICD_BASE (NT_GIC_BASE + 0x1000) +#define BASE_GICC_BASE (NT_GIC_BASE + 0x2000) +#define BASE_GICR_BASE (NT_GIC_BASE + 0x200000) +#define BASE_GICH_BASE (NT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (NT_GIC_BASE + 0x6000) + +#define DEVICE1_BASE BASE_GICD_BASE +#define DEVICE1_SIZE 0x7000 + +#ifdef NPCM845X_DEBUG +/* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */ +#define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4) +#endif /* NPCM845X_DEBUG */ + +#define PLAT_REG_BASE NPCM845x_REG_BASE +#define PLAT_REG_SIZE NPCM845x_REG_SIZE + +/* MMU entry for internal (register) space access */ +#define MAP_DEVICE0 \ + MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS) + +#define MAP_DEVICE1 \ + MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Define a list of Group 1 Secure and Group 0 interrupt properties + * as per GICv3 terminology. On a GICv2 system or mode, + * the lists will be merged and treated as Group 0 interrupts. + */ +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ + GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE), \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_EDGE) + +#define PLAT_ARM_G0_IRQ_PROPS(grp) + +/* Required for compilation: */ + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */ +#if USE_ROMLIB +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) +#else +#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) +#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) +#endif /* USE_ROMLIB */ + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION) +#else +/* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */ +#define PLAT_ARM_MAX_BL2_SIZE 0 +#endif /* TRUSTED_BOARD_BOOT */ + +#undef NPCM_PRINT_ONCE +#ifdef NPCM_PRINT_ONCE +#define PRINT_ONLY_ONCE +#pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE)) +#pragma message(VAR_NAME_VALUE(BL31_BASE)) +#pragma message(VAR_NAME_VALUE(BL31_LIMIT)) +#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE)) +#pragma message(VAR_NAME_VALUE(BL32_BASE)) +#pragma message(VAR_NAME_VALUE(BL32_LIMIT)) +#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE) +#pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO)) +#endif /* NPCM_PRINT_ONCE */ + +#define MAX_IO_DEVICES 4 +#define MAX_IO_HANDLES 4 + +#define PLAT_ARM_FIP_BASE 0x0 +#define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE + +#define PLAT_ARM_BOOT_UART_BASE 0xF0000000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200 +#define PLAT_ARM_RUN_UART_BASE 0xF0000000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200 +#define PLAT_ARM_CRASH_UART_BASE 0xF0000000 +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200 + +/* + * Mailbox to control the secondary cores.All secondary cores are held in a wait + * loop in cold boot. To release them perform the following steps (plus any + * additional barriers that may be needed): + * + * uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT; + * *entrypoint = ADDRESS_TO_JUMP_TO; + * + * uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE; + * mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE; + * + * sev(); + */ +#define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE + +/* The secure entry point to be used on warm reset by all CPUs. */ +#define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE +#define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8) + +/* Hold entries for each CPU. */ +#define PLAT_NPCM_TM_HOLD_BASE \ + (PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE) +#define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8) +#define PLAT_NPCM_TM_HOLD_SIZE \ + (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT) +#define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \ + (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE) + +#define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8) + +#define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \ + (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT) + +#define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \ + (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \ + PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE) + +#define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0) +#define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1) +#define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2) + +#define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA) +#define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC) + +#ifdef NPCM845X_DEBUG +#define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000 +#endif /* NPCM845X_DEBUG */ + +#endif /* PLATFORM_DEF_H */
diff --git a/include/services/el3_spmc_ffa_memory.h b/include/services/el3_spmc_ffa_memory.h index 2037eca..5d3af5d 100644 --- a/include/services/el3_spmc_ffa_memory.h +++ b/include/services/el3_spmc_ffa_memory.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -217,6 +217,8 @@ struct ffa_emad_v1_0 emad[]; }; CASSERT(sizeof(struct ffa_mtd_v1_0) == 32, assert_ffa_mtd_size_v1_0_mismatch); +CASSERT(offsetof(struct ffa_mtd_v1_0, emad) == 32, + assert_ffa_mtd_size_v1_0_mismatch_2); /** * struct ffa_mtd - Memory transaction descriptor for FF-A v1.1. @@ -254,5 +256,8 @@ uint64_t reserved_40_47; }; CASSERT(sizeof(struct ffa_mtd) == 48, assert_ffa_mtd_size_mismatch); +CASSERT(offsetof(struct ffa_mtd, emad_count) == + offsetof(struct ffa_mtd_v1_0, emad_count), + assert_ffa_mtd_emad_count_offset_mismatch); #endif /* EL3_SPMC_FFA_MEM_H */
diff --git a/include/services/el3_spmc_logical_sp.h b/include/services/el3_spmc_logical_sp.h index 5ce33ed..dccd362 100644 --- a/include/services/el3_spmc_logical_sp.h +++ b/include/services/el3_spmc_logical_sp.h
@@ -49,8 +49,7 @@ * Function & variable prototypes. ******************************************************************************/ int el3_sp_desc_validate(void); -uintptr_t handle_el3_sp(uint32_t smc_fid, void *cookie, void *handle, - unsigned int flags); + IMPORT_SYM(uintptr_t, __EL3_LP_DESCS_START__, EL3_LP_DESCS_START); IMPORT_SYM(uintptr_t, __EL3_LP_DESCS_END__, EL3_LP_DESCS_END);
diff --git a/include/services/el3_spmd_logical_sp.h b/include/services/el3_spmd_logical_sp.h new file mode 100644 index 0000000..15bea9f --- /dev/null +++ b/include/services/el3_spmd_logical_sp.h
@@ -0,0 +1,168 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef EL3_SPMD_LOGICAL_SP_H +#define EL3_SPMD_LOGICAL_SP_H + +#include <common/bl_common.h> +#include <lib/cassert.h> +#include <services/ffa_svc.h> + +/******************************************************************************* + * Structure definition, typedefs & constants for the SPMD Logical Partitions. + ******************************************************************************/ +typedef struct spmd_spm_core_context spmd_spm_core_context_t; + +/* Prototype for SPMD logical partition initializing function. */ +typedef int32_t (*ffa_spmd_lp_init_t)(void); + +/* SPMD Logical Partition Descriptor. */ +struct spmd_lp_desc { + ffa_spmd_lp_init_t init; + uint16_t sp_id; + uint32_t properties; + uint32_t uuid[4]; /* Little Endian. */ + const char *debug_name; +}; + +struct ffa_value { + uint64_t func; + uint64_t arg1; + uint64_t arg2; + uint64_t arg3; + uint64_t arg4; + uint64_t arg5; + uint64_t arg6; + uint64_t arg7; + uint64_t arg8; + uint64_t arg9; + uint64_t arg10; + uint64_t arg11; + uint64_t arg12; + uint64_t arg13; + uint64_t arg14; + uint64_t arg15; + uint64_t arg16; + uint64_t arg17; +}; + +/* Convenience macro to declare a SPMD logical partition descriptor. */ +#define DECLARE_SPMD_LOGICAL_PARTITION(_name, _init, _sp_id, _uuid, _properties) \ + static const struct spmd_lp_desc __partition_desc_ ## _name \ + __section(".spmd_lp_descs") __used = { \ + .debug_name = #_name, \ + .init = (_init), \ + .sp_id = (_sp_id), \ + .uuid = _uuid, \ + .properties = (_properties), \ + } + +IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_START__, SPMD_LP_DESCS_START); +IMPORT_SYM(uintptr_t, __SPMD_LP_DESCS_END__, SPMD_LP_DESCS_END); + +#define SPMD_LP_DESCS_COUNT ((SPMD_LP_DESCS_END - SPMD_LP_DESCS_START) \ + / sizeof(struct spmd_lp_desc)) +CASSERT(sizeof(struct spmd_lp_desc) == 40, assert_spmd_lp_desc_size_mismatch); + +/* + * Reserve 63 IDs for SPMD Logical Partitions. Currently, 0xFFC0 to 0xFFFE + * is reserved. + */ +#define SPMD_LP_ID_END (SPMD_DIRECT_MSG_ENDPOINT_ID - 1) +#define SPMD_LP_ID_START (SPMD_LP_ID_END - 62) + +/* + * TODO: Arbitrary number. Can make this platform specific in the future, + * no known use cases for more LPs at this point. + */ +#define EL3_SPMD_MAX_NUM_LP U(5) + +static inline bool is_spmd_lp_id(unsigned int id) +{ +#if ENABLE_SPMD_LP + return (id >= SPMD_LP_ID_START && id <= SPMD_LP_ID_END); +#else + return false; +#endif +} + +static inline bool is_ffa_error(struct ffa_value *retval) +{ + return retval->func == FFA_ERROR; +} + +static inline bool is_ffa_success(struct ffa_value *retval) +{ + return (retval->func == FFA_SUCCESS_SMC32) || + (retval->func == FFA_SUCCESS_SMC64); +} + +static inline bool is_ffa_direct_msg_resp(struct ffa_value *retval) +{ + return (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC32) || + (retval->func == FFA_MSG_SEND_DIRECT_RESP_SMC64); +} + +static inline uint16_t ffa_partition_info_regs_get_last_idx( + struct ffa_value *args) +{ + return (uint16_t)(args->arg2 & 0xFFFFU); +} + +static inline uint16_t ffa_partition_info_regs_get_curr_idx( + struct ffa_value *args) +{ + return (uint16_t)((args->arg2 >> 16) & 0xFFFFU); +} + +static inline uint16_t ffa_partition_info_regs_get_tag(struct ffa_value *args) +{ + return (uint16_t)((args->arg2 >> 32) & 0xFFFFU); +} + +static inline uint16_t ffa_partition_info_regs_get_desc_size( + struct ffa_value *args) +{ + return (uint16_t)(args->arg2 >> 48); +} + +uint64_t spmd_el3_populate_logical_partition_info(void *handle, uint64_t x1, + uint64_t x2, uint64_t x3); + +bool ffa_partition_info_regs_get_part_info( + struct ffa_value *args, uint8_t idx, + struct ffa_partition_info_v1_1 *partition_info); + +bool spmd_el3_invoke_partition_info_get( + const uint32_t target_uuid[4], + const uint16_t start_index, + const uint16_t tag, + struct ffa_value *retval); +void spmd_logical_sp_set_spmc_initialized(void); +void spmc_logical_sp_set_spmc_failure(void); + +int32_t spmd_logical_sp_init(void); +bool is_spmd_logical_sp_dir_req_in_progress( + spmd_spm_core_context_t *ctx); + +bool is_spmd_logical_sp_info_regs_req_in_progress( + spmd_spm_core_context_t *ctx); + +bool spmd_el3_ffa_msg_direct_req(uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *handle, + struct ffa_value *retval); + +uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + +#endif /* EL3_SPMD_LOGICAL_SP_H */
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h index 64af437..de56638 100644 --- a/include/services/ffa_svc.h +++ b/include/services/ffa_svc.h
@@ -343,4 +343,28 @@ uint64_t reserved; }; +/* FF-A Partition Info Get related macros. */ +#define FFA_PARTITION_INFO_GET_PROPERTIES_V1_0_MASK U(0x7) +#define FFA_PARTITION_INFO_GET_EXEC_STATE_SHIFT U(8) +#define FFA_PARTITION_INFO_GET_AARCH32_STATE U(0) +#define FFA_PARTITION_INFO_GET_AARCH64_STATE U(1) + +/** + * Holds information returned for each partition by the FFA_PARTITION_INFO_GET + * interface. + */ +struct ffa_partition_info_v1_0 { + uint16_t ep_id; + uint16_t execution_ctx_count; + uint32_t properties; +}; + +/* Extended structure for FF-A v1.1. */ +struct ffa_partition_info_v1_1 { + uint16_t ep_id; + uint16_t execution_ctx_count; + uint32_t properties; + uint32_t uuid[4]; +}; + #endif /* FFA_SVC_H */
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h index de7181c..a567d28 100644 --- a/include/services/rmmd_svc.h +++ b/include/services/rmmd_svc.h
@@ -91,6 +91,10 @@ #define E_RMM_NOMEM -4 #define E_RMM_INVAL -5 +/* Return error codes from RMI SMCs */ +#define RMI_SUCCESS 0 +#define RMI_ERROR_INPUT 1 + /* Acceptable SHA sizes for Challenge object */ #define SHA256_DIGEST_SIZE 32U #define SHA384_DIGEST_SIZE 48U @@ -152,7 +156,7 @@ * Increase this when a bug is fixed, or a feature is added without * breaking compatibility. */ -#define RMM_EL3_IFC_VERSION_MINOR (U(1)) +#define RMM_EL3_IFC_VERSION_MINOR (U(2)) #define RMM_EL3_INTERFACE_VERSION \ (((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \
diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h index e586b8c..8c53ef9 100644 --- a/include/tools_share/cca_oid.h +++ b/include/tools_share/cca_oid.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,4 +25,20 @@ /* Realm Monitor Manager (RMM) Hash */ #define RMM_HASH_OID "1.3.6.1.4.1.4128.2100.1106" +/* CCAFirmwareNVCounter - Non-volatile counter extension */ +#define CCA_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.3" + +/* + * First undef previous definitions from tbbr_oid.h. + * CCA ROTPK authenticates BL31 and its configuration image in + * CCA CoT. + **/ +#undef BL31_IMAGE_KEY_OID +#undef SOC_FW_CONFIG_KEY_OID +#undef HW_CONFIG_KEY_OID +#define BL31_IMAGE_KEY_OID ZERO_OID +#define SOC_FW_CONFIG_KEY_OID ZERO_OID +#define HW_CONFIG_KEY_OID ZERO_OID +#define RMM_IMAGE_KEY_OID ZERO_OID + #endif /* CCA_OID_H */
diff --git a/include/tools_share/dualroot_oid.h b/include/tools_share/dualroot_oid.h index 3e88a6d..3762c79 100644 --- a/include/tools_share/dualroot_oid.h +++ b/include/tools_share/dualroot_oid.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h index 52b43ab..9881d1a 100644 --- a/include/tools_share/tbbr_oid.h +++ b/include/tools_share/tbbr_oid.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #ifndef TBBR_OID_H #define TBBR_OID_H +#include "zero_oid.h" + #define MAX_OID_NAME_LEN 30 /* @@ -160,6 +162,14 @@ #define SP_PKG7_HASH_OID "1.3.6.1.4.1.4128.2100.1307" #define SP_PKG8_HASH_OID "1.3.6.1.4.1.4128.2100.1308" +/* + * Public Keys present in SOC FW content certificates authenticate BL31 and + * its configuration. + */ +#define BL31_IMAGE_KEY_OID SOC_FW_CONTENT_CERT_PK_OID +#define SOC_FW_CONFIG_KEY_OID SOC_FW_CONTENT_CERT_PK_OID +#define HW_CONFIG_KEY_OID ZERO_OID + #ifdef PLAT_DEF_OID #include <platform_oid.h> #endif
diff --git a/include/tools_share/zero_oid.h b/include/tools_share/zero_oid.h new file mode 100644 index 0000000..9b83094 --- /dev/null +++ b/include/tools_share/zero_oid.h
@@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef ZERO_OID_H +#define ZERO_OID_H + +#define ZERO_OID "0.0.0.0.0.0.0.0.0" + +#endif /* ZERO_OID_H */
diff --git a/lib/aarch32/arm32_aeabi_divmod.c b/lib/aarch32/arm32_aeabi_divmod.c index ea8e2bb..89a9033 100644 --- a/lib/aarch32/arm32_aeabi_divmod.c +++ b/lib/aarch32/arm32_aeabi_divmod.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/aarch32/arm32_aeabi_divmod_a32.S b/lib/aarch32/arm32_aeabi_divmod_a32.S index 6915dcd..9155100 100644 --- a/lib/aarch32/arm32_aeabi_divmod_a32.S +++ b/lib/aarch32/arm32_aeabi_divmod_a32.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/aarch32/armclang_printf.S b/lib/aarch32/armclang_printf.S index 2b87bf7..e736a11 100644 --- a/lib/aarch32/armclang_printf.S +++ b/lib/aarch32/armclang_printf.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S index 59e15bd..c010cbc 100644 --- a/lib/aarch32/misc_helpers.S +++ b/lib/aarch32/misc_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/aarch64/armclang_printf.S b/lib/aarch64/armclang_printf.S index 52a6976..f9326fd 100644 --- a/lib/aarch64/armclang_printf.S +++ b/lib/aarch64/armclang_printf.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/bl_aux_params/bl_aux_params.c b/lib/bl_aux_params/bl_aux_params.c index 7f357b7..6e30ecf 100644 --- a/lib/bl_aux_params/bl_aux_params.c +++ b/lib/bl_aux_params/bl_aux_params.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/compiler-rt/builtins/divmoddi4.c b/lib/compiler-rt/builtins/divmoddi4.c index e7cbbb1..64bbb69 100644 --- a/lib/compiler-rt/builtins/divmoddi4.c +++ b/lib/compiler-rt/builtins/divmoddi4.c
@@ -18,8 +18,8 @@ const int bits_in_dword_m1 = (int)(sizeof(di_int) * CHAR_BIT) - 1; di_int s_a = a >> bits_in_dword_m1; // s_a = a < 0 ? -1 : 0 di_int s_b = b >> bits_in_dword_m1; // s_b = b < 0 ? -1 : 0 - a = (a ^ s_a) - s_a; // negate if s_a == -1 - b = (b ^ s_b) - s_b; // negate if s_b == -1 + a = (du_int)(a ^ s_a) - s_a; // negate if s_a == -1 + b = (du_int)(b ^ s_b) - s_b; // negate if s_b == -1 s_b ^= s_a; // sign of quotient du_int r; di_int q = (__udivmoddi4(a, b, &r) ^ s_b) - s_b; // negate if s_b == -1
diff --git a/lib/compiler-rt/builtins/int_lib.h b/lib/compiler-rt/builtins/int_lib.h index fb791eb..04ea2d9 100644 --- a/lib/compiler-rt/builtins/int_lib.h +++ b/lib/compiler-rt/builtins/int_lib.h
@@ -49,7 +49,7 @@ #define SYMBOL_NAME(name) XSTR(__USER_LABEL_PREFIX__) #name #if defined(__ELF__) || defined(__MINGW32__) || defined(__wasm__) || \ - defined(_AIX) + defined(_AIX) || defined(__CYGWIN__) #define COMPILER_RT_ALIAS(name, aliasname) \ COMPILER_RT_ABI __typeof(name) aliasname __attribute__((__alias__(#name))); #elif defined(__APPLE__)
diff --git a/lib/compiler-rt/builtins/int_math.h b/lib/compiler-rt/builtins/int_math.h index 48b9580..74d3e31 100644 --- a/lib/compiler-rt/builtins/int_math.h +++ b/lib/compiler-rt/builtins/int_math.h
@@ -65,6 +65,11 @@ #define crt_copysign(x, y) __builtin_copysign((x), (y)) #define crt_copysignf(x, y) __builtin_copysignf((x), (y)) #define crt_copysignl(x, y) __builtin_copysignl((x), (y)) +#if __has_builtin(__builtin_copysignf128) +#define crt_copysignf128(x, y) __builtin_copysignf128((x), (y)) +#elif __has_builtin(__builtin_copysignq) || (defined(__GNUC__) && __GNUC__ >= 7) +#define crt_copysignf128(x, y) __builtin_copysignq((x), (y)) +#endif #endif #if defined(_MSC_VER) && !defined(__clang__) @@ -75,6 +80,11 @@ #define crt_fabs(x) __builtin_fabs((x)) #define crt_fabsf(x) __builtin_fabsf((x)) #define crt_fabsl(x) __builtin_fabsl((x)) +#if __has_builtin(__builtin_fabsf128) +#define crt_fabsf128(x) __builtin_fabsf128((x)) +#elif __has_builtin(__builtin_fabsq) || (defined(__GNUC__) && __GNUC__ >= 7) +#define crt_fabsf128(x) __builtin_fabsq((x)) +#endif #endif #if defined(_MSC_VER) && !defined(__clang__)
diff --git a/lib/compiler-rt/builtins/int_types.h b/lib/compiler-rt/builtins/int_types.h index e94d315..18bf0a7 100644 --- a/lib/compiler-rt/builtins/int_types.h +++ b/lib/compiler-rt/builtins/int_types.h
@@ -165,16 +165,80 @@ #define HAS_80_BIT_LONG_DOUBLE 0 #endif -#if CRT_HAS_FLOATING_POINT +#if HAS_80_BIT_LONG_DOUBLE +typedef long double xf_float; typedef union { uqwords u; - long double f; -} long_double_bits; + xf_float f; +} xf_bits; +#endif +#ifdef __powerpc64__ +// From https://gcc.gnu.org/wiki/Ieee128PowerPC: +// PowerPC64 uses the following suffixes: +// IFmode: IBM extended double +// KFmode: IEEE 128-bit floating point +// TFmode: Matches the default for long double. With -mabi=ieeelongdouble, +// it is IEEE 128-bit, with -mabi=ibmlongdouble IBM extended double +// Since compiler-rt only implements the tf set of libcalls, we use long double +// for the tf_float typedef. +typedef long double tf_float; +#define CRT_LDBL_128BIT +#define CRT_HAS_F128 +#if __LDBL_MANT_DIG__ == 113 && !defined(__LONG_DOUBLE_IBM128__) +#define CRT_HAS_IEEE_TF +#define CRT_LDBL_IEEE_F128 +#endif +#define TF_C(x) x##L +#elif __LDBL_MANT_DIG__ == 113 +// Use long double instead of __float128 if it matches the IEEE 128-bit format. +#define CRT_LDBL_128BIT +#define CRT_HAS_F128 +#define CRT_HAS_IEEE_TF +#define CRT_LDBL_IEEE_F128 +typedef long double tf_float; +#define TF_C(x) x##L +#elif defined(__FLOAT128__) || defined(__SIZEOF_FLOAT128__) +#define CRT_HAS___FLOAT128_KEYWORD +#define CRT_HAS_F128 +// NB: we assume the __float128 type uses IEEE representation. +#define CRT_HAS_IEEE_TF +typedef __float128 tf_float; +#define TF_C(x) x##Q +#endif + +#ifdef CRT_HAS_F128 +typedef union { + uqwords u; + tf_float f; +} tf_bits; +#endif + +// __(u)int128_t is currently needed to compile the *tf builtins as we would +// otherwise need to manually expand the bit manipulation on two 64-bit value. +#if defined(CRT_HAS_128BIT) && defined(CRT_HAS_F128) +#define CRT_HAS_TF_MODE +#endif + +#if CRT_HAS_FLOATING_POINT #if __STDC_VERSION__ >= 199901L typedef float _Complex Fcomplex; typedef double _Complex Dcomplex; typedef long double _Complex Lcomplex; +#if defined(CRT_LDBL_128BIT) +typedef Lcomplex Qcomplex; +#define CRT_HAS_NATIVE_COMPLEX_F128 +#elif defined(CRT_HAS___FLOAT128_KEYWORD) +#if defined(__clang_major__) && __clang_major__ > 10 +// Clang prior to 11 did not support __float128 _Complex. +typedef __float128 _Complex Qcomplex; +#define CRT_HAS_NATIVE_COMPLEX_F128 +#elif defined(__GNUC__) && __GNUC__ >= 7 +// GCC does not allow __float128 _Complex, but accepts _Float128 _Complex. +typedef _Float128 _Complex Qcomplex; +#define CRT_HAS_NATIVE_COMPLEX_F128 +#endif +#endif #define COMPLEX_REAL(x) __real__(x) #define COMPLEX_IMAGINARY(x) __imag__(x) @@ -194,5 +258,17 @@ #define COMPLEX_REAL(x) (x).real #define COMPLEX_IMAGINARY(x) (x).imaginary #endif + +#ifdef CRT_HAS_NATIVE_COMPLEX_F128 +#define COMPLEXTF_REAL(x) __real__(x) +#define COMPLEXTF_IMAGINARY(x) __imag__(x) +#elif defined(CRT_HAS_F128) +typedef struct { + tf_float real, imaginary; +} Qcomplex; +#define COMPLEXTF_REAL(x) (x).real +#define COMPLEXTF_IMAGINARY(x) (x).imaginary +#endif + #endif #endif // INT_TYPES_H
diff --git a/lib/compiler-rt/compiler-rt.mk b/lib/compiler-rt/compiler-rt.mk index b41c4d0..2b16504 100644 --- a/lib/compiler-rt/compiler-rt.mk +++ b/lib/compiler-rt/compiler-rt.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met:
diff --git a/lib/coreboot/coreboot.mk b/lib/coreboot/coreboot.mk index 4201823..e07d28c 100644 --- a/lib/coreboot/coreboot.mk +++ b/lib/coreboot/coreboot.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c index 43e9835..c954e97 100644 --- a/lib/coreboot/coreboot_table.c +++ b/lib/coreboot/coreboot_table.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S index 7bd586a..9f45e38 100644 --- a/lib/cpus/aarch32/aem_generic.S +++ b/lib/cpus/aarch32/aem_generic.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch32/cortex_a12.S b/lib/cpus/aarch32/cortex_a12.S index 5300fe0..8eec27c 100644 --- a/lib/cpus/aarch32/cortex_a12.S +++ b/lib/cpus/aarch32/cortex_a12.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,19 +64,16 @@ bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a12_disable_smp endfunc cortex_a12_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A12. Must follow AAPCS. - */ -func cortex_a12_errata_report - bx lr -endfunc cortex_a12_errata_report -#endif +errata_report_shim cortex_a12 declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \ cortex_a12_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S index 1143e9b..b41676d 100644 --- a/lib/cpus/aarch32/cortex_a15.S +++ b/lib/cpus/aarch32/cortex_a15.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,6 +62,7 @@ bx lr endfunc check_errata_816470 +add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470 /* ---------------------------------------------------- * Errata Workaround for Cortex A15 Errata #827671. * This applies only to revision >= r3p0 of Cortex A15. @@ -91,6 +92,8 @@ b cpu_rev_var_hs endfunc check_errata_827671 +add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -100,6 +103,8 @@ bx lr endfunc check_errata_cve_2017_5715 +add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov r0, #ERRATA_APPLIES @@ -109,29 +114,7 @@ bx lr endfunc check_errata_cve_2022_23960 -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A15. Must follow AAPCS. - */ -func cortex_a15_errata_report - push {r12, lr} - - bl cpu_get_rev_var - mov r4, r0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A15_816470, cortex_a15, 816470 - report_errata ERRATA_A15_827671, cortex_a15, 827671 - report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715 - report_errata WORKAROUND_CVE_2022_23960, cortex_a15, cve_2022_23960 - - pop {r12, lr} - bx lr -endfunc cortex_a15_errata_report -#endif +add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 func cortex_a15_reset_func mov r5, lr @@ -180,11 +163,17 @@ bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a15_disable_smp endfunc cortex_a15_cluster_pwr_dwn +errata_report_shim cortex_a15 + declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \ cortex_a15_reset_func, \ cortex_a15_core_pwr_dwn, \
diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S index b8abd33..1877570 100644 --- a/lib/cpus/aarch32/cortex_a17.S +++ b/lib/cpus/aarch32/cortex_a17.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,6 +63,8 @@ b cpu_rev_var_ls endfunc check_errata_852421 +add_erratum_entry cortex_a17, ERRATUM(852421), ERRATA_A17_852421 + /* ---------------------------------------------------- * Errata Workaround for Cortex A17 Errata #852423. * This applies only to revision <= r1p2 of Cortex A17. @@ -91,6 +93,8 @@ b cpu_rev_var_ls endfunc check_errata_852423 +add_erratum_entry cortex_a17, ERRATUM(852423), ERRATA_A17_852423 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -100,28 +104,9 @@ bx lr endfunc check_errata_cve_2017_5715 -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A17. Must follow AAPCS. - */ -func cortex_a17_errata_report - push {r12, lr} +add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 - bl cpu_get_rev_var - mov r4, r0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A17_852421, cortex_a17, 852421 - report_errata ERRATA_A17_852423, cortex_a17, 852423 - report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715 - - pop {r12, lr} - bx lr -endfunc cortex_a17_errata_report -#endif +errata_report_shim cortex_a17 func cortex_a17_reset_func mov r5, lr @@ -139,7 +124,7 @@ #endif #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 - ldr r0, =workaround_bpiall_runtime_exceptions + ldr r0, =wa_cve_2017_5715_bpiall_vbar stcopr r0, VBAR stcopr r0, MVBAR /* isb will be applied in the course of the reset func */ @@ -174,6 +159,10 @@ bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a17_disable_smp
diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S index c262276..d08b4ff 100644 --- a/lib/cpus/aarch32/cortex_a32.S +++ b/lib/cpus/aarch32/cortex_a32.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -117,14 +117,7 @@ b cortex_a32_disable_smp endfunc cortex_a32_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A32. Must follow AAPCS. - */ -func cortex_a32_errata_report - bx lr -endfunc cortex_a32_errata_report -#endif +errata_report_shim cortex_a32 declare_cpu_ops cortex_a32, CORTEX_A32_MIDR, \ cortex_a32_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a5.S b/lib/cpus/aarch32/cortex_a5.S index 8abb66f..625ea7b 100644 --- a/lib/cpus/aarch32/cortex_a5.S +++ b/lib/cpus/aarch32/cortex_a5.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,14 +69,7 @@ b cortex_a5_disable_smp endfunc cortex_a5_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A5. Must follow AAPCS. - */ -func cortex_a5_errata_report - bx lr -endfunc cortex_a5_errata_report -#endif +errata_report_shim cortex_a5 declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \ cortex_a5_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index 6e3ff81..89b238a 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,6 +44,8 @@ bx lr endfunc check_errata_819472 +add_erratum_entry cortex_a53, ERRATUM(819472), ERRATA_A53_819472 + /* --------------------------------------------------- * Errata Workaround for Cortex A53 Errata #824069. * This applies only to revision <= r0p2 of Cortex A53. @@ -59,6 +61,8 @@ bx lr endfunc check_errata_824069 +add_erratum_entry cortex_a53, ERRATUM(824069), ERRATA_A53_824069 + /* -------------------------------------------------- * Errata Workaround for Cortex A53 Errata #826319. * This applies only to revision <= r0p2 of Cortex A53. @@ -89,6 +93,8 @@ b cpu_rev_var_ls endfunc check_errata_826319 +add_erratum_entry cortex_a53, ERRATUM(826319), ERRATA_A53_826319 + /* --------------------------------------------------- * Errata Workaround for Cortex A53 Errata #827319. * This applies only to revision <= r0p2 of Cortex A53. @@ -104,6 +110,8 @@ bx lr endfunc check_errata_827319 +add_erratum_entry cortex_a53, ERRATUM(827319), ERRATA_A53_827319 + /* --------------------------------------------------------------------- * Disable the cache non-temporal hint. * @@ -142,6 +150,9 @@ b cpu_rev_var_ls endfunc check_errata_disable_non_temporal_hint +add_erratum_entry cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT, \ + disable_non_temporal_hint + /* -------------------------------------------------- * Errata Workaround for Cortex A53 Errata #855873. * @@ -176,6 +187,8 @@ b cpu_rev_var_hs endfunc check_errata_855873 +add_erratum_entry cortex_a53, ERRATUM(855873), ERRATA_A53_855873 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A53. * Shall clobber: r0-r6 @@ -284,31 +297,7 @@ b cortex_a53_disable_smp endfunc cortex_a53_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A53. Must follow AAPCS. - */ -func cortex_a53_errata_report - push {r12, lr} - - bl cpu_get_rev_var - mov r4, r0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A53_819472, cortex_a53, 819472 - report_errata ERRATA_A53_824069, cortex_a53, 824069 - report_errata ERRATA_A53_826319, cortex_a53, 826319 - report_errata ERRATA_A53_827319, cortex_a53, 827319 - report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint - report_errata ERRATA_A53_855873, cortex_a53, 855873 - - pop {r12, lr} - bx lr -endfunc cortex_a53_errata_report -#endif +errata_report_shim cortex_a53 declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ cortex_a53_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index 18ee1f9..1e5377b 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -86,6 +86,8 @@ b cpu_rev_var_ls endfunc check_errata_806969 +add_erratum_entry cortex_a57, ERRATUM(806969), ERRATA_A57_806969 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #813419. * This applies only to revision r0p0 of Cortex A57. @@ -101,6 +103,8 @@ bx lr endfunc check_errata_813419 +add_erratum_entry cortex_a57, ERRATUM(813419), ERRATA_A57_813419 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #813420. * This applies only to revision r0p0 of Cortex A57. @@ -130,6 +134,8 @@ b cpu_rev_var_ls endfunc check_errata_813420 +add_erratum_entry cortex_a57, ERRATUM(813420), ERRATA_A57_813420 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #814670. * This applies only to revision r0p0 of Cortex A57. @@ -159,6 +165,8 @@ b cpu_rev_var_ls endfunc check_errata_814670 +add_erratum_entry cortex_a57, ERRATUM(814670), ERRATA_A57_814670 + /* ---------------------------------------------------- * Errata Workaround for Cortex A57 Errata #817169. * This applies only to revision <= r0p1 of Cortex A57. @@ -173,6 +181,8 @@ bx lr endfunc check_errata_817169 +add_erratum_entry cortex_a57, ERRATUM(817169), ERRATA_A57_817169 + /* -------------------------------------------------------------------- * Disable the over-read from the LDNP instruction. * @@ -205,6 +215,8 @@ b cpu_rev_var_ls endfunc check_errata_disable_ldnp_overread +add_erratum_entry cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT, disable_ldnp_overread + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #826974. * This applies only to revision <= r1p1 of Cortex A57. @@ -234,6 +246,8 @@ b cpu_rev_var_ls endfunc check_errata_826974 +add_erratum_entry cortex_a57, ERRATUM(826974), ERRATA_A57_826974 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #826977. * This applies only to revision <= r1p1 of Cortex A57. @@ -263,6 +277,8 @@ b cpu_rev_var_ls endfunc check_errata_826977 +add_erratum_entry cortex_a57, ERRATUM(826977), ERRATA_A57_826977 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #828024. * This applies only to revision <= r1p1 of Cortex A57. @@ -298,6 +314,8 @@ b cpu_rev_var_ls endfunc check_errata_828024 +add_erratum_entry cortex_a57, ERRATUM(828024), ERRATA_A57_828024 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #829520. * This applies only to revision <= r1p2 of Cortex A57. @@ -327,6 +345,8 @@ b cpu_rev_var_ls endfunc check_errata_829520 +add_erratum_entry cortex_a57, ERRATUM(829520), ERRATA_A57_829520 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #833471. * This applies only to revision <= r1p2 of Cortex A57. @@ -356,6 +376,8 @@ b cpu_rev_var_ls endfunc check_errata_833471 +add_erratum_entry cortex_a57, ERRATUM(833471), ERRATA_A57_833471 + /* --------------------------------------------------- * Errata Workaround for Cortex A57 Errata #859972. * This applies only to revision <= r1p3 of Cortex A57. @@ -382,11 +404,15 @@ b cpu_rev_var_ls endfunc check_errata_859972 +add_erratum_entry cortex_a57, ERRATUM(859972), ERRATA_A57_859972 + func check_errata_cve_2017_5715 mov r0, #ERRATA_MISSING bx lr endfunc check_errata_cve_2017_5715 +add_erratum_entry cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov r0, #ERRATA_APPLIES @@ -396,11 +422,15 @@ bx lr endfunc check_errata_cve_2018_3639 +add_erratum_entry cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + func check_errata_cve_2022_23960 mov r0, #ERRATA_MISSING bx lr endfunc check_errata_cve_2022_23960 +add_erratum_entry cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A57. * Shall clobber: r0-r6 @@ -576,41 +606,7 @@ b cortex_a57_disable_ext_debug endfunc cortex_a57_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A57. Must follow AAPCS. - */ -func cortex_a57_errata_report - push {r12, lr} - - bl cpu_get_rev_var - mov r4, r0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A57_806969, cortex_a57, 806969 - report_errata ERRATA_A57_813419, cortex_a57, 813419 - report_errata ERRATA_A57_813420, cortex_a57, 813420 - report_errata ERRATA_A57_814670, cortex_a57, 814670 - report_errata ERRATA_A57_817169, cortex_a57, 817169 - report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ - disable_ldnp_overread - report_errata ERRATA_A57_826974, cortex_a57, 826974 - report_errata ERRATA_A57_826977, cortex_a57, 826977 - report_errata ERRATA_A57_828024, cortex_a57, 828024 - report_errata ERRATA_A57_829520, cortex_a57, 829520 - report_errata ERRATA_A57_833471, cortex_a57, 833471 - report_errata ERRATA_A57_859972, cortex_a57, 859972 - report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 - report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960 - - pop {r12, lr} - bx lr -endfunc cortex_a57_errata_report -#endif +errata_report_shim cortex_a57 declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ cortex_a57_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a7.S b/lib/cpus/aarch32/cortex_a7.S index 4d4bb77..4842ca6 100644 --- a/lib/cpus/aarch32/cortex_a7.S +++ b/lib/cpus/aarch32/cortex_a7.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,19 +64,16 @@ bl plat_disable_acp + /* Flush L2 caches */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + /* Exit cluster coherency */ pop {r12, lr} b cortex_a7_disable_smp endfunc cortex_a7_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A7. Must follow AAPCS. - */ -func cortex_a7_errata_report - bx lr -endfunc cortex_a7_errata_report -#endif +errata_report_shim cortex_a7 declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \ cortex_a7_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 03914b2..77cf84d 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -87,11 +87,15 @@ b cpu_rev_var_ls endfunc check_errata_859971 +add_erratum_entry cortex_a72, ERRATUM(859971), ERRATA_A72_859971 + func check_errata_cve_2017_5715 mov r0, #ERRATA_MISSING bx lr endfunc check_errata_cve_2017_5715 +add_erratum_entry cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov r0, #ERRATA_APPLIES @@ -101,11 +105,15 @@ bx lr endfunc check_errata_cve_2018_3639 +add_erratum_entry cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + func check_errata_cve_2022_23960 mov r0, #ERRATA_MISSING bx lr endfunc check_errata_cve_2022_23960 +add_erratum_entry cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A72. * ------------------------------------------------- @@ -248,29 +256,7 @@ b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A72. Must follow AAPCS. - */ -func cortex_a72_errata_report - push {r12, lr} - - bl cpu_get_rev_var - mov r4, r0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A72_859971, cortex_a72, 859971 - report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 - report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960 - - pop {r12, lr} - bx lr -endfunc cortex_a72_errata_report -#endif +errata_report_shim cortex_a72 declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ cortex_a72_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a9.S b/lib/cpus/aarch32/cortex_a9.S index 7200343..1e9757a 100644 --- a/lib/cpus/aarch32/cortex_a9.S +++ b/lib/cpus/aarch32/cortex_a9.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,14 +35,16 @@ bx lr endfunc cortex_a9_enable_smp -func check_errata_a9_794073 +func check_errata_794073 #if ERRATA_A9_794073 mov r0, #ERRATA_APPLIES #else mov r0, #ERRATA_MISSING #endif bx lr -endfunc check_errata_cve_2017_5715 +endfunc check_errata_794073 + +add_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073 func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 @@ -53,31 +55,13 @@ bx lr endfunc check_errata_cve_2017_5715 -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A9. Must follow AAPCS. - */ -func cortex_a9_errata_report - push {r12, lr} +add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 - bl cpu_get_rev_var - mov r4, r0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715 - report_errata ERRATA_A9_794073, cortex_a9, a9_79407 - - pop {r12, lr} - bx lr -endfunc cortex_a9_errata_report -#endif +errata_report_shim cortex_a9 func cortex_a9_reset_func #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 - ldr r0, =workaround_bpiall_runtime_exceptions + ldr r0, =wa_cve_2017_5715_bpiall_vbar stcopr r0, VBAR stcopr r0, MVBAR /* isb will be applied in the course of the reset func */
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index e25ce2a..83e3e49 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <assert_macros.S> #include <cpu_macros.S> #include <common/bl_common.h> +#include <lib/cpus/cpu_ops.h> #include <lib/el3_runtime/cpu_data.h> #if defined(IMAGE_BL1) || defined(IMAGE_BL32) || \ @@ -204,62 +205,3 @@ movlt r0, #ERRATA_NOT_APPLIES bx lr endfunc cpu_rev_var_hs - -#if REPORT_ERRATA -/* - * void print_errata_status(void); - * - * Function to print errata status for CPUs of its class. Must be called only: - * - * - with MMU and data caches are enabled; - * - after cpu_ops have been initialized in per-CPU data. - */ - .globl print_errata_status -func print_errata_status - /* r12 is pushed only for the sake of 8-byte stack alignment */ - push {r4, r5, r12, lr} -#ifdef IMAGE_BL1 - /* - * BL1 doesn't have per-CPU data. So retrieve the CPU operations - * directly. - */ - bl get_cpu_ops_ptr - ldr r0, [r0, #CPU_ERRATA_FUNC] - cmp r0, #0 - blxne r0 -#else - /* - * Retrieve pointer to cpu_ops, and further, the errata printing - * function. If it's non-NULL, jump to the function in turn. - */ - bl _cpu_data -#if ENABLE_ASSERTIONS - cmp r0, #0 - ASM_ASSERT(ne) -#endif - ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] -#if ENABLE_ASSERTIONS - cmp r1, #0 - ASM_ASSERT(ne) -#endif - ldr r0, [r1, #CPU_ERRATA_FUNC] - cmp r0, #0 - beq 1f - - mov r4, r0 - - /* - * Load pointers to errata lock and printed flag. Call - * errata_needs_reporting to check whether this CPU needs to report - * errata status pertaining to its class. - */ - ldr r0, [r1, #CPU_ERRATA_LOCK] - ldr r1, [r1, #CPU_ERRATA_PRINTED] - bl errata_needs_reporting - cmp r0, #0 - blxne r4 -1: -#endif - pop {r4, r5, r12, pc} -endfunc print_errata_status -#endif
diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S index 6291e43..d47279a 100644 --- a/lib/cpus/aarch64/aem_generic.S +++ b/lib/cpus/aarch64/aem_generic.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S index be3c652..6ffb944 100644 --- a/lib/cpus/aarch64/cortex_a35.S +++ b/lib/cpus/aarch64/cortex_a35.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,9 +16,7 @@ * --------------------------------------------- */ func cortex_a35_disable_dcache - mrs x1, sctlr_el3 - bic x1, x1, #SCTLR_C_BIT - msr sctlr_el3, x1 + sysreg_bit_clear sctlr_el3, SCTLR_C_BIT isb ret endfunc cortex_a35_disable_dcache @@ -28,65 +26,29 @@ * --------------------------------------------- */ func cortex_a35_disable_smp - mrs x0, CORTEX_A35_CPUECTLR_EL1 - bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT - msr CORTEX_A35_CPUECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT isb dsb sy ret endfunc cortex_a35_disable_smp - /* --------------------------------------------------- - * Errata Workaround for Cortex A35 Errata #855472. - * This applies to revisions r0p0 of Cortex A35. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a35_855472_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_855472 - cbz x0, 1f - mrs x1, CORTEX_A35_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI - msr CORTEX_A35_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a35_855472_wa +workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 + sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI +workaround_reset_end cortex_a35, ERRATUM(855472) -func check_errata_855472 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_855472 +check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A35. - * Clobbers: x0 * ------------------------------------------------- */ -func cortex_a35_reset_func - mov x19, x30 - bl cpu_get_rev_var - -#if ERRATA_A35_855472 - bl errata_a35_855472_wa -#endif - +cpu_reset_func_start cortex_a35 /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- */ - mrs x0, CORTEX_A35_CPUECTLR_EL1 - orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT - msr CORTEX_A35_CPUECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a35_reset_func + sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT +cpu_reset_func_end cortex_a35 func cortex_a35_core_pwr_dwn mov x18, x30 @@ -149,27 +111,7 @@ b cortex_a35_disable_smp endfunc cortex_a35_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A35. Must follow AAPCS. - */ -func cortex_a35_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A35_855472, cortex_a35, 855472 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a35_errata_report -#endif - +errata_report_shim cortex_a35 /* --------------------------------------------- * This function provides cortex_a35 specific
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index e10ebb0..a59b92c 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S
@@ -21,110 +21,15 @@ #error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #1922240. - * This applies only to revision r0p0 (fixed in r0p1) - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_1922240_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1922240 - cbz x0, 1f - +workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ - mrs x0, CORTEX_A510_CMPXACTLR_EL1 - mov x1, #3 - bfi x0, x1, #10, #2 - msr CORTEX_A510_CMPXACTLR_EL1, x0 + sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ + CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH +workaround_reset_end cortex_a510, ERRATUM(1922240) -1: - ret x17 -endfunc errata_cortex_a510_1922240_wa +check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) -func check_errata_1922240 - /* Applies to r0p0 only */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_1922240 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2288014. - * This applies only to revisions r0p0, r0p1, r0p2, - * r0p3 and r1p0. (fixed in r1p1) - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_2288014_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2288014 - cbz x0, 1f - - /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ - mrs x0, CORTEX_A510_CPUACTLR_EL1 - mov x1, #1 - bfi x0, x1, #18, #1 - msr CORTEX_A510_CPUACTLR_EL1, x0 - -1: - ret x17 -endfunc errata_cortex_a510_2288014_wa - -func check_errata_2288014 - /* Applies to r1p0 and below */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_2288014 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2042739. - * This applies only to revisions r0p0, r0p1 and r0p2. - * (fixed in r0p3) - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_2042739_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2042739 - cbz x0, 1f - - /* Apply the workaround by disabling ReadPreferUnique. */ - mrs x0, CORTEX_A510_CPUECTLR_EL1 - mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE - bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1 - msr CORTEX_A510_CPUECTLR_EL1, x0 - -1: - ret x17 -endfunc errata_cortex_a510_2042739_wa - -func check_errata_2042739 - /* Applies to revisions r0p0 - r0p2 */ - mov x1, #0x02 - b cpu_rev_var_ls -endfunc check_errata_2042739 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2041909. - * This applies only to revision r0p2 and it is fixed in - * r0p3. The issue is also present in r0p0 and r0p1 but - * there is no workaround in those revisions. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x2, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_2041909_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2041909 - cbz x0, 1f - +workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 /* Apply workaround */ mov x0, xzr msr S3_6_C15_C4_0, x0 @@ -140,110 +45,43 @@ mov x0, #0x3F1 movk x0, #0x110, lsl #16 msr S3_6_C15_C4_1, x0 +workaround_reset_end cortex_a510, ERRATUM(2041909) + +check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) + +workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 + /* Apply the workaround by disabling ReadPreferUnique. */ + sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ + CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH +workaround_reset_end cortex_a510, ERRATUM(2042739) + +check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) + +workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326 + /* Apply workaround */ + mov x0, #1 + msr S3_6_C15_C4_0, x0 isb -1: - ret x17 -endfunc errata_cortex_a510_2041909_wa + mov x0, #0x0100 + movk x0, #0x0E08, lsl #16 + msr S3_6_C15_C4_2, x0 -func check_errata_2041909 - /* Applies only to revision r0p2 */ - mov x1, #0x02 - mov x2, #0x02 - b cpu_rev_var_range -endfunc check_errata_2041909 + mov x0, #0x0300 + movk x0, #0x0F1F, lsl #16 + movk x0, #0x0008, lsl #32 + msr S3_6_C15_C4_3, x0 - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2250311. - * This applies only to revisions r0p0, r0p1, r0p2, - * r0p3 and r1p0, and is fixed in r1p1. - * This workaround is not a typical errata fix. MPMM - * is disabled here, but this conflicts with the BL31 - * MPMM support. So in addition to simply disabling - * the feature, a flag is set in the MPMM library - * indicating that it should not be enabled even if - * ENABLE_MPMM=1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_2250311_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2250311 - cbz x0, 1f + mov x0, #0x03F1 + movk x0, #0x00C0, lsl #16 + msr S3_6_C15_C4_1, x0 - /* Disable MPMM */ - mrs x0, CPUMPMMCR_EL3 - bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ - msr CPUMPMMCR_EL3, x0 + isb +workaround_reset_end cortex_a510, ERRATUM(2080326) -#if ENABLE_MPMM && IMAGE_BL31 - /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ - bl mpmm_errata_disable -#endif +check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2) -1: - ret x17 -endfunc errata_cortex_a510_2250311_wa - -func check_errata_2250311 - /* Applies to r1p0 and lower */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_2250311 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2218950. - * This applies only to revisions r0p0, r0p1, r0p2, - * r0p3 and r1p0, and is fixed in r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_2218950_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2218950 - cbz x0, 1f - - /* Source register for BFI */ - mov x1, #1 - - /* Set bit 18 in CPUACTLR_EL1 */ - mrs x0, CORTEX_A510_CPUACTLR_EL1 - bfi x0, x1, #18, #1 - msr CORTEX_A510_CPUACTLR_EL1, x0 - - /* Set bit 25 in CMPXACTLR_EL1 */ - mrs x0, CORTEX_A510_CMPXACTLR_EL1 - bfi x0, x1, #25, #1 - msr CORTEX_A510_CMPXACTLR_EL1, x0 - -1: - ret x17 -endfunc errata_cortex_a510_2218950_wa - -func check_errata_2218950 - /* Applies to r1p0 and lower */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_2218950 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2172148. - * This applies only to revisions r0p0, r0p1, r0p2, - * r0p3 and r1p0, and is fixed in r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_a510_2172148_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2172148 - cbz x0, 1f - +workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 /* * Force L2 allocation of transient lines by setting * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. @@ -253,156 +91,104 @@ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 msr CORTEX_A510_CPUECTLR_EL1, x0 +workaround_reset_end cortex_a510, ERRATUM(2172148) -1: - ret x17 -endfunc errata_cortex_a510_2172148_wa +check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) -func check_errata_2172148 - /* Applies to r1p0 and lower */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_2172148 +workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 + /* Set bit 18 in CPUACTLR_EL1 */ + sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ + CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH - /* ---------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2347730. - * This applies to revisions r0p0 - r0p3, r1p0, r1p1. - * It is fixed in r1p2. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ---------------------------------------------------- + /* Set bit 25 in CMPXACTLR_EL1 */ + sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ + CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH + +workaround_reset_end cortex_a510, ERRATUM(2218950) + +check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) + + /* -------------------------------------------------- + * This workaround is not a typical errata fix. MPMM + * is disabled here, but this conflicts with the BL31 + * MPMM support. So in addition to simply disabling + * the feature, a flag is set in the MPMM library + * indicating that it should not be enabled even if + * ENABLE_MPMM=1. + * -------------------------------------------------- */ -func errata_cortex_a510_2347730_wa - mov x17, x30 - bl check_errata_2347730 - cbz x0, 1f +workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 + /* Disable MPMM */ + mrs x0, CPUMPMMCR_EL3 + bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ + msr CPUMPMMCR_EL3, x0 +#if ENABLE_MPMM && IMAGE_BL31 + /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ + bl mpmm_errata_disable +#endif +workaround_reset_end cortex_a510, ERRATUM(2250311) + +check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) + +workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 + /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ + sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ + CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH +workaround_reset_end cortex_a510, ERRATUM(2288014) + +check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) + +workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 /* * Set CPUACTLR_EL1[17] to 1'b1, which disables * specific microarchitectural clock gating * behaviour. */ - mrs x1, CORTEX_A510_CPUACTLR_EL1 - orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17 - msr CORTEX_A510_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_cortex_a510_2347730_wa + sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 +workaround_reset_end cortex_a510, ERRATUM(2347730) -func check_errata_2347730 - /* Applies to revisions r1p1 and lower. */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2347730 +check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) - /*--------------------------------------------------- - * Errata Workaround for Cortex-A510 Errata #2371937. - * This applies to revisions r1p1 and lower, and is - * fixed in r1p2. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - *--------------------------------------------------- - */ -func errata_cortex_a510_2371937_wa - mov x17, x30 - bl check_errata_2371937 - cbz x0, 1f - +workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 /* * Cacheable atomic operations can be forced * to be executed near by setting * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found * in [40:38] of CPUECTLR_EL1. */ - mrs x0, CORTEX_A510_CPUECTLR_EL1 - mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR - bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3 - msr CORTEX_A510_CPUECTLR_EL1, x0 -1: - ret x17 -endfunc errata_cortex_a510_2371937_wa + sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ + CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH +workaround_reset_end cortex_a510, ERRATUM(2371937) -func check_errata_2371937 - /* Applies to r1p1 and lower */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2371937 +check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) - /* ------------------------------------------------------ - * Errata Workaround for Cortex-A510 Errata #2666669 - * This applies to revisions r1p1 and lower, and is fixed - * in r1p2. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * ------------------------------------------------------ - */ -func errata_cortex_a510_2666669_wa - mov x17, x30 - bl check_errata_2666669 - cbz x0, 1f +workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 + sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 +workaround_reset_end cortex_a510, ERRATUM(2666669) - /* - * Workaround will set IMP_CPUACTLR_EL1[38] - * to 0b1. - */ - mrs x1, CORTEX_A510_CPUACTLR_EL1 - orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38 - msr CORTEX_A510_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_cortex_a510_2666669_wa +check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) -func check_errata_2666669 - /* Applies to r1p1 and lower */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2666669 - -/* ------------------------------------------------------ - * Errata Workaround for Cortex-A510 Erratum 2684597. - * This erratum applies to revision r0p0, r0p1, r0p2, - * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and - * is fixed in r1p3. - * Shall clobber: x0-x17 - * ------------------------------------------------------ - */ - .globl errata_cortex_a510_2684597_wa -func errata_cortex_a510_2684597_wa - mov x17, x30 - /* Ensure this errata is only applied to Cortex-A510 cores */ - jump_if_cpu_midr CORTEX_A510_MIDR, 1f - b 2f - -1: - /* Check workaround compatibility. */ - mov x0, x18 - bl check_errata_2684597 - cbz x0, 2f - +.global erratum_cortex_a510_2684597_wa +workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR /* * Many assemblers do not yet understand the "tsb csync" mnemonic, * so use the equivalent hint instruction. */ hint #18 /* tsb csync */ -2: - ret x17 -endfunc errata_cortex_a510_2684597_wa -/* ------------------------------------------------------ - * Errata Workaround for Cortex-A510 Erratum 2684597. - * This erratum applies to revision r0p0, r0p1, r0p2, - * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and - * is fixed in r1p3. - * Shall clobber: x0-x17 - * ------------------------------------------------------ +workaround_runtime_end cortex_a510, ERRATUM(2684597) + +check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) + +/* + * ERRATA_DSU_2313941 : + * The errata is defined in dsu_helpers.S but applies to cortex_a510 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. */ -func check_errata_2684597 - /* Applies to revision < r1p3 */ - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_2684597 +.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941 +.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa +add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET /* ---------------------------------------------------- * HW will do the cache maintenance while powering down @@ -413,112 +199,17 @@ * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_A510_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT isb ret endfunc cortex_a510_core_pwr_dwn - /* - * Errata printing function for Cortex-A510. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_a510_errata_report - stp x8, x30, [sp, #-16]! +errata_report_shim cortex_a510 - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A510_1922240, cortex_a510, 1922240 - report_errata ERRATA_A510_2041909, cortex_a510, 2041909 - report_errata ERRATA_A510_2042739, cortex_a510, 2042739 - report_errata ERRATA_A510_2172148, cortex_a510, 2172148 - report_errata ERRATA_A510_2218950, cortex_a510, 2218950 - report_errata ERRATA_A510_2250311, cortex_a510, 2250311 - report_errata ERRATA_A510_2288014, cortex_a510, 2288014 - report_errata ERRATA_A510_2347730, cortex_a510, 2347730 - report_errata ERRATA_A510_2371937, cortex_a510, 2371937 - report_errata ERRATA_A510_2666669, cortex_a510, 2666669 - report_errata ERRATA_A510_2684597, cortex_a510, 2684597 - report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a510_errata_report -#endif - -func cortex_a510_reset_func - mov x19, x30 - +cpu_reset_func_start cortex_a510 /* Disable speculative loads */ msr SSBS, xzr - - /* Get the CPU revision and stash it in x18. */ - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_DSU_2313941 - bl errata_dsu_2313941_wa -#endif - -#if ERRATA_A510_1922240 - mov x0, x18 - bl errata_cortex_a510_1922240_wa -#endif - -#if ERRATA_A510_2288014 - mov x0, x18 - bl errata_cortex_a510_2288014_wa -#endif - -#if ERRATA_A510_2042739 - mov x0, x18 - bl errata_cortex_a510_2042739_wa -#endif - -#if ERRATA_A510_2041909 - mov x0, x18 - bl errata_cortex_a510_2041909_wa -#endif - -#if ERRATA_A510_2250311 - mov x0, x18 - bl errata_cortex_a510_2250311_wa -#endif - -#if ERRATA_A510_2218950 - mov x0, x18 - bl errata_cortex_a510_2218950_wa -#endif - -#if ERRATA_A510_2371937 - mov x0, x18 - bl errata_cortex_a510_2371937_wa -#endif - -#if ERRATA_A510_2172148 - mov x0, x18 - bl errata_cortex_a510_2172148_wa -#endif - -#if ERRATA_A510_2347730 - mov x0, x18 - bl errata_cortex_a510_2347730_wa -#endif - -#if ERRATA_A510_2666669 - mov x0, x18 - bl errata_cortex_a510_2666669_wa -#endif - - isb - ret x19 -endfunc cortex_a510_reset_func +cpu_reset_func_end cortex_a510 /* --------------------------------------------- * This function provides Cortex-A510 specific
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S new file mode 100644 index 0000000..6c2f33e --- /dev/null +++ b/lib/cpus/aarch64/cortex_a520.S
@@ -0,0 +1,66 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_a520.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex A520 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex A520 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_a520_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb + ret +endfunc cortex_a520_core_pwr_dwn + +errata_report_shim cortex_a520 + +cpu_reset_func_start cortex_a520 + /* Disable speculative loads */ + msr SSBS, xzr +cpu_reset_func_end cortex_a520 + + /* --------------------------------------------- + * This function provides Cortex A520 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a520_regs, "aS" +cortex_a520_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a520_cpu_reg_dump + adr x6, cortex_a520_regs + mrs x8, CORTEX_A520_CPUECTLR_EL1 + ret +endfunc cortex_a520_cpu_reg_dump + +declare_cpu_ops cortex_a520, CORTEX_A520_MIDR, \ + cortex_a520_reset_func, \ + cortex_a520_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index df11d86..e6fb08a 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,22 +9,15 @@ #include <common/debug.h> #include <cortex_a53.h> #include <cpu_macros.S> -#include <lib/cpus/errata_report.h> #include <plat_macros.S> - -#if A53_DISABLE_NON_TEMPORAL_HINT -#undef ERRATA_A53_836870 -#define ERRATA_A53_836870 1 -#endif +#include <lib/cpus/errata.h> /* --------------------------------------------- * Disable L1 data cache and unified L2 cache * --------------------------------------------- */ func cortex_a53_disable_dcache - mrs x1, sctlr_el3 - bic x1, x1, #SCTLR_C_BIT - msr sctlr_el3, x1 + sysreg_bit_clear sctlr_el3, SCTLR_C_BIT isb ret endfunc cortex_a53_disable_dcache @@ -34,169 +27,38 @@ * --------------------------------------------- */ func cortex_a53_disable_smp - mrs x0, CORTEX_A53_ECTLR_EL1 - bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT - msr CORTEX_A53_ECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT isb dsb sy ret endfunc cortex_a53_disable_smp - /* --------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #819472. - * This applies only to revision <= r0p1 of Cortex A53. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_819472 -#if ERRATA_A53_819472 - mov x0, #ERRATA_APPLIES - ret -#else - mov x1, #0x01 - b cpu_rev_var_ls -#endif -endfunc check_errata_819472 +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_ls cortex_a53, ERRATUM(819472), CPU_REV(0, 1) +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a53, ERRATUM(819472), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET - /* --------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #824069. - * This applies only to revision <= r0p2 of Cortex A53. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_824069 -#if ERRATA_A53_824069 - mov x0, #ERRATA_APPLIES - ret -#else - mov x1, #0x02 - b cpu_rev_var_ls -#endif -endfunc check_errata_824069 +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_ls cortex_a53, ERRATUM(824069), CPU_REV(0, 2) +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a53, ERRATUM(824069), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET - /* -------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #826319. - * This applies only to revision <= r0p2 of Cortex A53. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a53_826319_wa - /* - * Compare x0 against revision r0p2 - */ - mov x17, x30 - bl check_errata_826319 - cbz x0, 1f +workaround_reset_start cortex_a53, ERRATUM(826319), ERRATA_A53_826319 mrs x1, CORTEX_A53_L2ACTLR_EL1 bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH msr CORTEX_A53_L2ACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a53_826319_wa +workaround_reset_end cortex_a53, ERRATUM(826319) -func check_errata_826319 - mov x1, #0x02 - b cpu_rev_var_ls -endfunc check_errata_826319 +check_erratum_ls cortex_a53, ERRATUM(826319), CPU_REV(0, 2) - /* --------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #827319. - * This applies only to revision <= r0p2 of Cortex A53. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_827319 -#if ERRATA_A53_827319 - mov x0, #ERRATA_APPLIES - ret -#else - mov x1, #0x02 - b cpu_rev_var_ls -#endif -endfunc check_errata_827319 +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_ls cortex_a53, ERRATUM(827319), CPU_REV(0, 2) +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a53, ERRATUM(827319), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET - /* --------------------------------------------------------------------- - * Disable the cache non-temporal hint. - * - * This ignores the Transient allocation hint in the MAIR and treats - * allocations the same as non-transient allocation types. As a result, - * the LDNP and STNP instructions in AArch64 behave the same as the - * equivalent LDP and STP instructions. - * - * This is relevant only for revisions <= r0p3 of Cortex-A53. - * From r0p4 and onwards, the bit to disable the hint is enabled by - * default at reset. - * - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func a53_disable_non_temporal_hint - /* - * Compare x0 against revision r0p3 - */ - mov x17, x30 - bl check_errata_disable_non_temporal_hint - cbz x0, 1f - mrs x1, CORTEX_A53_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH - msr CORTEX_A53_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc a53_disable_non_temporal_hint - -func check_errata_disable_non_temporal_hint - mov x1, #0x03 - b cpu_rev_var_ls -endfunc check_errata_disable_non_temporal_hint - - /* -------------------------------------------------- - * Errata Workaround for Cortex A53 Errata #855873. - * - * This applies only to revisions >= r0p3 of Cortex A53. - * Earlier revisions of the core are affected as well, but don't - * have the chicken bit in the CPUACTLR register. It is expected that - * the rich OS takes care of that, especially as the workaround is - * shared with other erratas in those revisions of the CPU. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a53_855873_wa - /* - * Compare x0 against revision r0p3 and higher - */ - mov x17, x30 - bl check_errata_855873 - cbz x0, 1f - - mrs x1, CORTEX_A53_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI - msr CORTEX_A53_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a53_855873_wa - -func check_errata_855873 - mov x1, #0x03 - b cpu_rev_var_hs -endfunc check_errata_855873 - -/* - * Errata workaround for Cortex A53 Errata #835769. - * This applies to revisions <= r0p4 of Cortex A53. - * This workaround is statically enabled at build time. - */ -func check_errata_835769 - cmp x0, #0x04 +check_erratum_custom_start cortex_a53, ERRATUM(835769) + cmp x0, CPU_REV(0, 4) b.hi errata_not_applies /* * Fix potentially available for revisions r0p2, r0p3 and r0p4. @@ -213,17 +75,29 @@ mov x0, #ERRATA_NOT_APPLIES exit_check_errata_835769: ret -endfunc check_errata_835769 +check_erratum_custom_end cortex_a53, ERRATUM(835769) -/* - * Errata workaround for Cortex A53 Errata #843419. - * This applies to revisions <= r0p4 of Cortex A53. - * This workaround is statically enabled at build time. - */ -func check_errata_843419 +/* workaround at build time */ +add_erratum_entry cortex_a53, ERRATUM(835769), ERRATA_A53_835769, NO_APPLY_AT_RESET + + /* + * Disable the cache non-temporal hint. + * + * This ignores the Transient allocation hint in the MAIR and treats + * allocations the same as non-transient allocation types. As a result, + * the LDNP and STNP instructions in AArch64 behave the same as the + * equivalent LDP and STP instructions. + */ +workaround_reset_start cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT + sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_DTAH +workaround_reset_end cortex_a53, ERRATUM(836870) + +check_erratum_ls cortex_a53, ERRATUM(836870), CPU_REV(0, 3) + +check_erratum_custom_start cortex_a53, ERRATUM(843419) mov x1, #ERRATA_APPLIES mov x2, #ERRATA_NOT_APPLIES - cmp x0, #0x04 + cmp x0, CPU_REV(0, 4) csel x0, x1, x2, ls /* * Fix potentially available for revision r0p4. @@ -237,58 +111,32 @@ mov x0, x2 exit_check_errata_843419: ret -endfunc check_errata_843419 +check_erratum_custom_end cortex_a53, ERRATUM(843419) - /* -------------------------------------------------- - * Errata workaround for Cortex A53 Errata #1530924. - * This applies to all revisions of Cortex A53. - * -------------------------------------------------- +/* workaround at build time */ +add_erratum_entry cortex_a53, ERRATUM(843419), ERRATA_A53_843419, NO_APPLY_AT_RESET + + /* + * Earlier revisions of the core are affected as well, but don't + * have the chicken bit in the CPUACTLR register. It is expected that + * the rich OS takes care of that, especially as the workaround is + * shared with other erratas in those revisions of the CPU. */ -func check_errata_1530924 -#if ERRATA_A53_1530924 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_1530924 +workaround_reset_start cortex_a53, ERRATUM(855873), ERRATA_A53_855873 + sysreg_bit_set CORTEX_A53_CPUACTLR_EL1, CORTEX_A53_CPUACTLR_EL1_ENDCCASCI +workaround_reset_end cortex_a53, ERRATUM(855873) - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A53. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_a53_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 +check_erratum_hs cortex_a53, ERRATUM(855873), CPU_REV(0, 3) +check_erratum_chosen cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924 -#if ERRATA_A53_826319 - mov x0, x18 - bl errata_a53_826319_wa -#endif +/* erratum has no workaround in the cpu. Generic code must take care */ +add_erratum_entry cortex_a53, ERRATUM(1530924), ERRATA_A53_1530924, NO_APPLY_AT_RESET -#if ERRATA_A53_836870 - mov x0, x18 - bl a53_disable_non_temporal_hint -#endif - -#if ERRATA_A53_855873 - mov x0, x18 - bl errata_a53_855873_wa -#endif - - /* --------------------------------------------- - * Enable the SMP bit. - * --------------------------------------------- - */ - mrs x0, CORTEX_A53_ECTLR_EL1 - orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT - msr CORTEX_A53_ECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a53_reset_func +cpu_reset_func_start cortex_a53 + /* Enable the SMP bit. */ + sysreg_bit_set CORTEX_A53_ECTLR_EL1, CORTEX_A53_ECTLR_SMP_BIT +cpu_reset_func_end cortex_a53 func cortex_a53_core_pwr_dwn mov x18, x30 @@ -351,34 +199,7 @@ b cortex_a53_disable_smp endfunc cortex_a53_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A53. Must follow AAPCS. - */ -func cortex_a53_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A53_819472, cortex_a53, 819472 - report_errata ERRATA_A53_824069, cortex_a53, 824069 - report_errata ERRATA_A53_826319, cortex_a53, 826319 - report_errata ERRATA_A53_827319, cortex_a53, 827319 - report_errata ERRATA_A53_835769, cortex_a53, 835769 - report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint - report_errata ERRATA_A53_843419, cortex_a53, 843419 - report_errata ERRATA_A53_855873, cortex_a53, 855873 - report_errata ERRATA_A53_1530924, cortex_a53, 1530924 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a53_errata_report -#endif +errata_report_shim cortex_a53 /* --------------------------------------------- * This function provides cortex_a53 specific
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S index 0e0388bc..712b6e0 100644 --- a/lib/cpus/aarch64/cortex_a55.S +++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,63 +18,37 @@ .globl cortex_a55_reset_func .globl cortex_a55_core_pwr_dwn - /* -------------------------------------------------- - * Errata Workaround for Cortex A55 Errata #768277. - * This applies only to revision r0p0 of Cortex A55. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a55_768277_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_768277 - cbz x0, 1f - mrs x1, CORTEX_A55_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE - msr CORTEX_A55_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a55_768277_wa -func check_errata_768277 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_768277 +/* ERRATA_DSU_798953: + * The errata is defined in dsu_helpers.S but applies to cortex_a55 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953 +.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa +add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET - /* ------------------------------------------------------------------ - * Errata Workaround for Cortex A55 Errata #778703. - * This applies only to revision r0p0 of Cortex A55 where L2 cache is - * not configured. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ------------------------------------------------------------------ - */ -func errata_a55_778703_wa - /* - * Compare x0 against revision r0p0 and check that no private L2 cache - * is configured - */ - mov x17, x30 - bl check_errata_778703 - cbz x0, 1f - mrs x1, CORTEX_A55_CPUECTLR_EL1 - orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL - msr CORTEX_A55_CPUECTLR_EL1, x1 - mrs x1, CORTEX_A55_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING - msr CORTEX_A55_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a55_778703_wa +/* ERRATA_DSU_936184: + * The errata is defined in dsu_helpers.S but applies to cortex_a55 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184 +.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa +add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET -func check_errata_778703 +workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277 + sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE +workaround_reset_end cortex_a55, ERRATUM(768277) + +check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0) + +workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703 + sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL + sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING +workaround_reset_end cortex_a55, ERRATUM(778703) + +check_erratum_custom_start cortex_a55, ERRATUM(778703) mov x16, x30 mov x1, #0x00 bl cpu_rev_var_ls @@ -87,111 +61,27 @@ mov x2, #ERRATA_NOT_APPLIES csel x0, x0, x2, eq ret x16 -endfunc check_errata_778703 +check_erratum_custom_end cortex_a55, ERRATUM(778703) - /* -------------------------------------------------- - * Errata Workaround for Cortex A55 Errata #798797. - * This applies only to revision r0p0 of Cortex A55. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a55_798797_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_798797 - cbz x0, 1f - mrs x1, CORTEX_A55_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS - msr CORTEX_A55_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a55_798797_wa +workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797 + sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS +workaround_reset_end cortex_a55, ERRATUM(798797) -func check_errata_798797 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_798797 +check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0) - /* -------------------------------------------------------------------- - * Errata Workaround for Cortex A55 Errata #846532. - * This applies only to revisions <= r0p1 of Cortex A55. - * Disabling dual-issue has a small impact on performance. Disabling a - * power optimization feature is an alternate workaround with no impact - * on performance but with an increase in power consumption (see errata - * notice). - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------------------------- - */ -func errata_a55_846532_wa - /* - * Compare x0 against revision r0p1 - */ - mov x17, x30 - bl check_errata_846532 - cbz x0, 1f - mrs x1, CORTEX_A55_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE - msr CORTEX_A55_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a55_846532_wa +workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532 + sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE +workaround_reset_end cortex_a55, ERRATUM(846532) -func check_errata_846532 - mov x1, #0x01 - b cpu_rev_var_ls -endfunc check_errata_846532 +check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1) - /* ----------------------------------------------------- - * Errata Workaround for Cortex A55 Errata #903758. - * This applies only to revisions <= r0p1 of Cortex A55. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ----------------------------------------------------- - */ -func errata_a55_903758_wa - /* - * Compare x0 against revision r0p1 - */ - mov x17, x30 - bl check_errata_903758 - cbz x0, 1f - mrs x1, CORTEX_A55_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS - msr CORTEX_A55_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a55_903758_wa +workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758 + sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS +workaround_reset_end cortex_a55, ERRATUM(903758) -func check_errata_903758 - mov x1, #0x01 - b cpu_rev_var_ls -endfunc check_errata_903758 +check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1) - /* ----------------------------------------------------- - * Errata Workaround for Cortex A55 Errata #1221012. - * This applies only to revisions <= r1p0 of Cortex A55. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ----------------------------------------------------- - */ -func errata_a55_1221012_wa - /* - * Compare x0 against revision r1p0 - */ - mov x17, x30 - bl check_errata_1221012 - cbz x0, 1f +workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012 mov x0, #0x0020 movk x0, #0x0850, lsl #16 msr CPUPOR_EL3, x0 @@ -214,121 +104,30 @@ mov x0, #0x03fd movk x0, #0x0110, lsl #16 msr CPUPCR_EL3, x0 - isb -1: - ret x17 -endfunc errata_a55_1221012_wa +workaround_reset_end cortex_a55, ERRATUM(1221012) -func check_errata_1221012 - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1221012 +check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0) - /* -------------------------------------------------- - * Errata workaround for Cortex A55 Errata #1530923. - * This applies to all revisions of Cortex A55. - * -------------------------------------------------- - */ -func check_errata_1530923 -#if ERRATA_A55_1530923 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_1530923 +check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923 -func cortex_a55_reset_func - mov x19, x30 +/* erratum has no workaround in the cpu. Generic code must take care */ +add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET -#if ERRATA_DSU_798953 - bl errata_dsu_798953_wa -#endif +cpu_reset_func_start cortex_a55 +cpu_reset_func_end cortex_a55 -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif - - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A55_768277 - mov x0, x18 - bl errata_a55_768277_wa -#endif - -#if ERRATA_A55_778703 - mov x0, x18 - bl errata_a55_778703_wa -#endif - -#if ERRATA_A55_798797 - mov x0, x18 - bl errata_a55_798797_wa -#endif - -#if ERRATA_A55_846532 - mov x0, x18 - bl errata_a55_846532_wa -#endif - -#if ERRATA_A55_903758 - mov x0, x18 - bl errata_a55_903758_wa -#endif - -#if ERRATA_A55_1221012 - mov x0, x18 - bl errata_a55_1221012_wa -#endif - - ret x19 -endfunc cortex_a55_reset_func +errata_report_shim cortex_a55 /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- */ func cortex_a55_core_pwr_dwn - /* --------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------- - */ - mrs x0, CORTEX_A55_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK - msr CORTEX_A55_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK isb ret endfunc cortex_a55_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A55. Must follow AAPCS & can use stack. - */ -func cortex_a55_errata_report - stp x8, x30, [sp, #-16]! - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision variant information is at x8, where - * "report_errata" is expecting it and it doesn't corrupt it. - */ - report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953 - report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184 - report_errata ERRATA_A55_768277, cortex_a55, 768277 - report_errata ERRATA_A55_778703, cortex_a55, 778703 - report_errata ERRATA_A55_798797, cortex_a55, 798797 - report_errata ERRATA_A55_846532, cortex_a55, 846532 - report_errata ERRATA_A55_903758, cortex_a55, 903758 - report_errata ERRATA_A55_1221012, cortex_a55, 1221012 - report_errata ERRATA_A55_1530923, cortex_a55, 1530923 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a55_errata_report -#endif - /* --------------------------------------------- * This function provides cortex_a55 specific * register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 3766ec7..8fafaca 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -18,9 +18,7 @@ * --------------------------------------------- */ func cortex_a57_disable_dcache - mrs x1, sctlr_el3 - bic x1, x1, #SCTLR_C_BIT - msr sctlr_el3, x1 + sysreg_bit_clear sctlr_el3, SCTLR_C_BIT isb ret endfunc cortex_a57_disable_dcache @@ -46,9 +44,7 @@ * --------------------------------------------- */ func cortex_a57_disable_smp - mrs x0, CORTEX_A57_ECTLR_EL1 - bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT - msr CORTEX_A57_ECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT ret endfunc cortex_a57_disable_smp @@ -60,227 +56,66 @@ mov x0, #1 msr osdlr_el1, x0 isb -#if ERRATA_A57_817169 - /* - * Invalidate any TLB address - */ - mov x0, #0 - tlbi vae3, x0 -#endif + + apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169 + dsb sy ret endfunc cortex_a57_disable_ext_debug - /* -------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #806969. - * This applies only to revision r0p0 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a57_806969_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_806969 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_806969_wa +/* + * Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't + * provide and erratum number, so assign it an obvious 1 + */ +workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD +workaround_reset_end cortex_a57, ERRATUM(1) -func check_errata_806969 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_806969 +check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2) - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #813419. - * This applies only to revision r0p0 of Cortex A57. - * --------------------------------------------------- - */ -func check_errata_813419 - /* - * Even though this is only needed for revision r0p0, it - * is always applied due to limitations of the current - * errata framework. - */ - mov x0, #ERRATA_APPLIES - ret -endfunc check_errata_813419 +workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA +workaround_reset_end cortex_a57, ERRATUM(806969) - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #813420. - * This applies only to revision r0p0 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_813420_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_813420 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_813420_wa +check_erratum_ls cortex_a57, ERRATUM(806969), CPU_REV(0, 0) -func check_errata_813420 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_813420 +/* erratum always worked around, but report it correctly */ +check_erratum_ls cortex_a57, ERRATUM(813419), CPU_REV(0, 0) +add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #814670. - * This applies only to revision r0p0 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_814670_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_814670 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION - msr CORTEX_A57_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a57_814670_wa +workaround_reset_start cortex_a57, ERRATUM(813420), ERRATA_A57_813420 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI +workaround_reset_end cortex_a57, ERRATUM(813420) -func check_errata_814670 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_814670 +check_erratum_ls cortex_a57, ERRATUM(813420), CPU_REV(0, 0) - /* ---------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #817169. - * This applies only to revision <= r0p1 of Cortex A57. - * ---------------------------------------------------- - */ -func check_errata_817169 - /* - * Even though this is only needed for revision <= r0p1, it - * is always applied because of the low cost of the workaround. - */ - mov x0, #ERRATA_APPLIES - ret -endfunc check_errata_817169 +workaround_reset_start cortex_a57, ERRATUM(814670), ERRATA_A57_814670 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION +workaround_reset_end cortex_a57, ERRATUM(814670) - /* -------------------------------------------------------------------- - * Disable the over-read from the LDNP instruction. - * - * This applies to all revisions <= r1p2. The performance degradation - * observed with LDNP/STNP has been fixed on r1p3 and onwards. - * - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func a57_disable_ldnp_overread - /* - * Compare x0 against revision r1p2 - */ - mov x17, x30 - bl check_errata_disable_ldnp_overread - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc a57_disable_ldnp_overread +check_erratum_ls cortex_a57, ERRATUM(814670), CPU_REV(0, 0) -func check_errata_disable_ldnp_overread - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_disable_ldnp_overread +workaround_runtime_start cortex_a57, ERRATUM(817169), ERRATA_A57_817169, CORTEX_A57_MIDR + /* Invalidate any TLB address */ + mov x0, #0 + tlbi vae3, x0 +workaround_runtime_end cortex_a57, ERRATUM(817169), NO_ISB - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #826974. - * This applies only to revision <= r1p1 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_826974_wa - /* - * Compare x0 against revision r1p1 - */ - mov x17, x30 - bl check_errata_826974 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_826974_wa +check_erratum_ls cortex_a57, ERRATUM(817169), CPU_REV(0, 1) -func check_errata_826974 - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_826974 +workaround_reset_start cortex_a57, ERRATUM(826974), ERRATA_A57_826974 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB +workaround_reset_end cortex_a57, ERRATUM(826974) - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #826977. - * This applies only to revision <= r1p1 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_826977_wa - /* - * Compare x0 against revision r1p1 - */ - mov x17, x30 - bl check_errata_826977 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_826977_wa +check_erratum_ls cortex_a57, ERRATUM(826974), CPU_REV(1, 1) -func check_errata_826977 - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_826977 +workaround_reset_start cortex_a57, ERRATUM(826977), ERRATA_A57_826977 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE +workaround_reset_end cortex_a57, ERRATUM(826977) - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #828024. - * This applies only to revision <= r1p1 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_828024_wa - /* - * Compare x0 against revision r1p1 - */ - mov x17, x30 - bl check_errata_828024 - cbz x0, 1f +check_erratum_ls cortex_a57, ERRATUM(826977), CPU_REV(1, 1) + +workaround_reset_start cortex_a57, ERRATUM(828024), ERRATA_A57_828024 mrs x1, CORTEX_A57_CPUACTLR_EL1 /* * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 @@ -291,234 +126,64 @@ orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_828024_wa +workaround_reset_end cortex_a57, ERRATUM(828024) -func check_errata_828024 - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_828024 +check_erratum_ls cortex_a57, ERRATUM(828024), CPU_REV(1, 1) - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #829520. - * This applies only to revision <= r1p2 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_829520_wa - /* - * Compare x0 against revision r1p2 - */ - mov x17, x30 - bl check_errata_829520 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_829520_wa +workaround_reset_start cortex_a57, ERRATUM(829520), ERRATA_A57_829520 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR +workaround_reset_end cortex_a57, ERRATUM(829520) -func check_errata_829520 - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_829520 +check_erratum_ls cortex_a57, ERRATUM(829520), CPU_REV(1, 2) - /* --------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #833471. - * This applies only to revision <= r1p2 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a57_833471_wa - /* - * Compare x0 against revision r1p2 - */ - mov x17, x30 - bl check_errata_833471 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_833471_wa +workaround_reset_start cortex_a57, ERRATUM(833471), ERRATA_A57_833471 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH +workaround_reset_end cortex_a57, ERRATUM(833471) -func check_errata_833471 - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_833471 +check_erratum_ls cortex_a57, ERRATUM(833471), CPU_REV(1, 2) - /* -------------------------------------------------- - * Errata Workaround for Cortex A57 Errata #859972. - * This applies only to revision <= r1p3 of Cortex A57. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: - * -------------------------------------------------- - */ -func errata_a57_859972_wa - mov x17, x30 - bl check_errata_859972 - cbz x0, 1f - mrs x1, CORTEX_A57_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH - msr CORTEX_A57_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a57_859972_wa +workaround_reset_start cortex_a57, ERRATUM(859972), ERRATA_A57_859972 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH +workaround_reset_end cortex_a57, ERRATUM(859972) -func check_errata_859972 - mov x1, #0x13 - b cpu_rev_var_ls -endfunc check_errata_859972 +check_erratum_ls cortex_a57, ERRATUM(859972), CPU_REV(1, 3) -func check_errata_cve_2017_5715 -#if WORKAROUND_CVE_2017_5715 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING +check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537 +/* erratum has no workaround in the cpu. Generic code must take care */ +add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537, NO_APPLY_AT_RESET + +workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_mmu_vbar #endif - ret -endfunc check_errata_cve_2017_5715 +workaround_reset_end cortex_a57, CVE(2017, 5715) -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 +check_erratum_chosen cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 - /* -------------------------------------------------- - * Errata workaround for Cortex A57 Errata #1319537. - * This applies to all revisions of Cortex A57. - * -------------------------------------------------- - */ -func check_errata_1319537 -#if ERRATA_A57_1319537 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_1319537 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A57. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_a57_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A57_806969 - mov x0, x18 - bl errata_a57_806969_wa -#endif - -#if ERRATA_A57_813420 - mov x0, x18 - bl errata_a57_813420_wa -#endif - -#if ERRATA_A57_814670 - mov x0, x18 - bl errata_a57_814670_wa -#endif - -#if A57_DISABLE_NON_TEMPORAL_HINT - mov x0, x18 - bl a57_disable_ldnp_overread -#endif - -#if ERRATA_A57_826974 - mov x0, x18 - bl errata_a57_826974_wa -#endif - -#if ERRATA_A57_826977 - mov x0, x18 - bl errata_a57_826977_wa -#endif - -#if ERRATA_A57_828024 - mov x0, x18 - bl errata_a57_828024_wa -#endif - -#if ERRATA_A57_829520 - mov x0, x18 - bl errata_a57_829520_wa -#endif - -#if ERRATA_A57_833471 - mov x0, x18 - bl errata_a57_833471_wa -#endif - -#if ERRATA_A57_859972 - mov x0, x18 - bl errata_a57_859972_wa -#endif - -#if IMAGE_BL31 && ( WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 ) - /* --------------------------------------------------------------- - * Override vector table & enable existing workaround if either of - * the build flags are enabled - * --------------------------------------------------------------- - */ - adr x0, wa_cve_2017_5715_mmu_vbar - msr vbar_el3, x0 - /* isb will be performed before returning from this function */ -#endif - -#if WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A57_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE - msr CORTEX_A57_CPUACTLR_EL1, x0 +workaround_reset_start cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE isb dsb sy -#endif +workaround_reset_end cortex_a57, CVE(2018, 3639) +check_erratum_chosen cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + +workaround_reset_start cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_mmu_vbar +#endif +workaround_reset_end cortex_a57, CVE(2022, 23960) + +check_erratum_chosen cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + +cpu_reset_func_start cortex_a57 #if A57_ENABLE_NONCACHEABLE_LOAD_FWD - /* --------------------------------------------- - * Enable higher performance non-cacheable load - * forwarding - * --------------------------------------------- - */ - mrs x0, CORTEX_A57_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD - msr CORTEX_A57_CPUACTLR_EL1, x0 + /* Enable higher performance non-cacheable load forwarding */ + sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD #endif - - /* --------------------------------------------- - * Enable the SMP bit. - * --------------------------------------------- - */ - mrs x0, CORTEX_A57_ECTLR_EL1 - orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT - msr CORTEX_A57_ECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a57_reset_func - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 + /* Enable the SMP bit. */ + sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT +cpu_reset_func_end cortex_a57 func check_smccc_arch_workaround_3 mov x0, #ERRATA_APPLIES @@ -619,42 +284,7 @@ b cortex_a57_disable_ext_debug endfunc cortex_a57_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A57. Must follow AAPCS. - */ -func cortex_a57_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A57_806969, cortex_a57, 806969 - report_errata ERRATA_A57_813419, cortex_a57, 813419 - report_errata ERRATA_A57_813420, cortex_a57, 813420 - report_errata ERRATA_A57_814670, cortex_a57, 814670 - report_errata ERRATA_A57_817169, cortex_a57, 817169 - report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ - disable_ldnp_overread - report_errata ERRATA_A57_826974, cortex_a57, 826974 - report_errata ERRATA_A57_826977, cortex_a57, 826977 - report_errata ERRATA_A57_828024, cortex_a57, 828024 - report_errata ERRATA_A57_829520, cortex_a57, 829520 - report_errata ERRATA_A57_833471, cortex_a57, 833471 - report_errata ERRATA_A57_859972, cortex_a57, 859972 - report_errata ERRATA_A57_1319537, cortex_a57, 1319537 - report_errata WORKAROUND_CVE_2017_5715, cortex_a57, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a57, cve_2018_3639 - report_errata WORKAROUND_CVE_2022_23960, cortex_a57, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a57_errata_report -#endif +errata_report_shim cortex_a57 /* --------------------------------------------- * This function provides cortex_a57 specific @@ -679,7 +309,7 @@ declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ cortex_a57_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_cortex_a57_5715, \ CPU_NO_EXTRA2_FUNC, \ check_smccc_arch_workaround_3, \ cortex_a57_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S index ac6583e..85d1894 100644 --- a/lib/cpus/aarch64/cortex_a65ae.S +++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,49 +22,26 @@ #error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -/* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A65. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_a65ae_reset_func - mov x19, x30 + /* + * ERRATA_DSU_936184 : + * The errata is defined in dsu_helpers.S but applies to cortex_a65ae + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184 +.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa +add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif - - ret x19 -endfunc cortex_a65ae_reset_func +cpu_reset_func_start cortex_a65ae +cpu_reset_func_end cortex_a65ae func cortex_a65ae_cpu_pwr_dwn - mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT isb ret endfunc cortex_a65ae_cpu_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A65AE. Must follow AAPCS. - */ -func cortex_a65ae_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a65ae_errata_report -#endif +errata_report_shim cortex_a65ae .section .rodata.cortex_a65ae_regs, "aS" cortex_a65ae_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index cebd6f0..f3931d7 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,22 +26,7 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 1987031. - * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still - * open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a710_1987031_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_1987031 - cbz x0, 1f - - /* Apply instruction patching sequence */ +workaround_reset_start cortex_a710, ERRATUM(1987031), ERRATA_A710_1987031 ldr x0,=0x6 msr S3_6_c15_c8_0,x0 ldr x0,=0xF3A08002 @@ -58,373 +43,11 @@ msr S3_6_c15_c8_3,x0 ldr x0,=0x40000001003f3 msr S3_6_c15_c8_1,x0 - isb -1: - ret x17 -endfunc errata_a710_1987031_wa +workaround_reset_end cortex_a710, ERRATUM(1987031) -func check_errata_1987031 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1987031 +check_erratum_ls cortex_a710, ERRATUM(1987031), CPU_REV(2, 0) -/* -------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2081180. - * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. - * It is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a710_2081180_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2081180 - cbz x0, 1f - - /* Apply instruction patching sequence */ - ldr x0,=0x3 - msr S3_6_c15_c8_0,x0 - ldr x0,=0xF3A08002 - msr S3_6_c15_c8_2,x0 - ldr x0,=0xFFF0F7FE - msr S3_6_c15_c8_3,x0 - ldr x0,=0x10002001003FF - msr S3_6_c15_c8_1,x0 - ldr x0,=0x4 - msr S3_6_c15_c8_0,x0 - ldr x0,=0xBF200000 - msr S3_6_c15_c8_2,x0 - ldr x0,=0xFFEF0000 - msr S3_6_c15_c8_3,x0 - ldr x0,=0x10002001003F3 - msr S3_6_c15_c8_1,x0 - isb -1: - ret x17 -endfunc errata_a710_2081180_wa - -func check_errata_2081180 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2081180 - -/* --------------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2055002. - * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func errata_a710_2055002_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2055002 - cbz x0, 1f - mrs x1, CORTEX_A710_CPUACTLR_EL1 - orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 - msr CORTEX_A710_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a710_2055002_wa - -func check_errata_2055002 - /* Applies to r1p0, r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2055002 - -/* ------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2017096. - * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ------------------------------------------------------------- - */ -func errata_a710_2017096_wa - /* Compare x0 against revision r0p0 to r2p0 */ - mov x17, x30 - bl check_errata_2017096 - cbz x0, 1f - mrs x1, CORTEX_A710_CPUECTLR_EL1 - orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT - msr CORTEX_A710_CPUECTLR_EL1, x1 - -1: - ret x17 -endfunc errata_a710_2017096_wa - -func check_errata_2017096 - /* Applies to r0p0, r1p0, r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2017096 - - -/* --------------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2083908. - * This applies to revision r2p0 of Cortex-A710 and is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func errata_a710_2083908_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2083908 - cbz x0, 1f - mrs x1, CORTEX_A710_CPUACTLR5_EL1 - orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 - msr CORTEX_A710_CPUACTLR5_EL1, x1 -1: - ret x17 -endfunc errata_a710_2083908_wa - -func check_errata_2083908 - /* Applies to r2p0 */ - mov x1, #CPU_REV(2, 0) - mov x2, #CPU_REV(2, 0) - b cpu_rev_var_range -endfunc check_errata_2083908 - -/* --------------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2058056. - * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still - * open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------------- - */ -func errata_a710_2058056_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2058056 - cbz x0, 1f - mrs x1, CORTEX_A710_CPUECTLR2_EL1 - mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV - bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH - msr CORTEX_A710_CPUECTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a710_2058056_wa - -func check_errata_2058056 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2058056 - -/* -------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2267065. - * This applies to revisions r0p0, r1p0 and r2p0. - * It is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_a710_2267065_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2267065 - cbz x0, 1f - - /* Apply instruction patching sequence */ - mrs x1, CORTEX_A710_CPUACTLR_EL1 - orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 - msr CORTEX_A710_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a710_2267065_wa - -func check_errata_2267065 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2267065 - -/* --------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2136059. - * This applies to revision r0p0, r1p0 and r2p0. - * It is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------- - */ -func errata_a710_2136059_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2136059 - cbz x0, 1f - - /* Apply the workaround */ - mrs x1, CORTEX_A710_CPUACTLR5_EL1 - orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 - msr CORTEX_A710_CPUACTLR5_EL1, x1 - -1: - ret x17 -endfunc errata_a710_2136059_wa - -func check_errata_2136059 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2136059 - -/* ---------------------------------------------------------------- - * Errata workaround for Cortex-A710 Erratum 2147715. - * This applies to revision r2p0, and is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * ---------------------------------------------------------------- - */ -func errata_a710_2147715_wa - mov x17, x30 - bl check_errata_2147715 - cbz x0, 1f - - /* Apply workaround; set CPUACTLR_EL1[22] - * to 1, which will cause the CFP instruction - * to invalidate all branch predictor resources - * regardless of context. - */ - mrs x1, CORTEX_A710_CPUACTLR_EL1 - orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 - msr CORTEX_A710_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_a710_2147715_wa - -func check_errata_2147715 - mov x1, #0x20 - mov x2, #0x20 - b cpu_rev_var_range -endfunc check_errata_2147715 - -/* --------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2216384. - * This applies to revision r0p0, r1p0 and r2p0. - * It is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------- - */ -func errata_a710_2216384_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2216384 - cbz x0, 1f - - /* Apply workaround: set CPUACTLR5_EL1[17] - * to 1 and the following instruction - * patching sequence. - */ - mrs x1, CORTEX_A710_CPUACTLR5_EL1 - orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 - msr CORTEX_A710_CPUACTLR5_EL1, x1 - - ldr x0,=0x5 - msr CORTEX_A710_CPUPSELR_EL3, x0 - ldr x0,=0x10F600E000 - msr CORTEX_A710_CPUPOR_EL3, x0 - ldr x0,=0x10FF80E000 - msr CORTEX_A710_CPUPMR_EL3, x0 - ldr x0,=0x80000000003FF - msr CORTEX_A710_CPUPCR_EL3, x0 - isb -1: - ret x17 -endfunc errata_a710_2216384_wa - -func check_errata_2216384 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2216384 - -/* --------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2282622. - * This applies to revision r0p0, r1p0, r2p0 and r2p1. - * It is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * --------------------------------------------------------------- - */ -func errata_a710_2282622_wa - /* Compare x0 against revision r2p1 */ - mov x17, x30 - bl check_errata_2282622 - cbz x0, 1f - - /* Apply the workaround */ - mrs x1, CORTEX_A710_CPUACTLR2_EL1 - orr x1, x1, #BIT(0) - msr CORTEX_A710_CPUACTLR2_EL1, x1 - -1: - ret x17 -endfunc errata_a710_2282622_wa - -func check_errata_2282622 - /* Applies to r0p0, r1p0, r2p0 and r2p1 */ - mov x1, #0x21 - b cpu_rev_var_ls -endfunc check_errata_2282622 - -/* ------------------------------------------------------------------------ - * Errata Workaround for Cortex-A710 Erratum 2291219 on power down request. - * This applies to revision <= r2p0 and is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ------------------------------------------------------------------------ - */ -func errata_a710_2291219_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2291219 - cbz x0, 1f - - /* Set bit 36 in ACTLR2_EL1 */ - mrs x1, CORTEX_A710_CPUACTLR2_EL1 - orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_36 - msr CORTEX_A710_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a710_2291219_wa - -func check_errata_2291219 - /* Applies to <= r2p0. */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2291219 - -/* --------------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2008768. - * This applies to revision r0p0, r1p0 and r2p0. - * It is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x2, x17 - * --------------------------------------------------------------- - */ -func errata_a710_2008768_wa - mov x17, x30 - bl check_errata_2008768 - cbz x0, 1f - +workaround_runtime_start cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 /* Stash ERRSELR_EL1 in x2 */ mrs x2, ERRSELR_EL1 @@ -443,237 +66,169 @@ /* Restore ERRSELR_EL1 from x2 */ msr ERRSELR_EL1, x2 +workaround_runtime_end cortex_a710, ERRATUM(2008768), NO_ISB -1: - ret x17 -endfunc errata_a710_2008768_wa +check_erratum_ls cortex_a710, ERRATUM(2008768), CPU_REV(2, 0) -func check_errata_2008768 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2008768 +workaround_reset_start cortex_a710, ERRATUM(2017096), ERRATA_A710_2017096 + sysreg_bit_set CORTEX_A710_CPUECTLR_EL1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT +workaround_reset_end cortex_a710, ERRATUM(2017096) -/* ------------------------------------------------------- - * Errata Workaround for Cortex-A710 Erratum 2371105. - * This applies to revisions <= r2p0 and is fixed in r2p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ------------------------------------------------------- +check_erratum_ls cortex_a710, ERRATUM(2017096), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2055002), ERRATA_A710_2055002 + sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_46 +workaround_reset_end cortex_a710, ERRATUM(2055002) + +check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056 + sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end cortex_a710, ERRATUM(2058056) + +check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1) + +workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180 + ldr x0,=0x3 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xF3A08002 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFF0F7FE + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003FF + msr S3_6_c15_c8_1,x0 + ldr x0,=0x4 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xBF200000 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0000 + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003F3 + msr S3_6_c15_c8_1,x0 +workaround_reset_end cortex_a710, ERRATUM(2081180) + +check_erratum_ls cortex_a710, ERRATUM(2081180), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2083908), ERRATA_A710_2083908 + sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 +workaround_reset_end cortex_a710, ERRATUM(2083908) + +check_erratum_range cortex_a710, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2136059), ERRATA_A710_2136059 + sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 +workaround_reset_end cortex_a710, ERRATUM(2136059) + +check_erratum_ls cortex_a710, ERRATUM(2136059), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2147715), ERRATA_A710_2147715 + sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 +workaround_reset_end cortex_a710, ERRATUM(2147715) + +check_erratum_range cortex_a710, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2216384), ERRATA_A710_2216384 + sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, CORTEX_A710_CPUACTLR5_EL1_BIT_17 + + ldr x0,=0x5 + msr CORTEX_A710_CPUPSELR_EL3, x0 + ldr x0,=0x10F600E000 + msr CORTEX_A710_CPUPOR_EL3, x0 + ldr x0,=0x10FF80E000 + msr CORTEX_A710_CPUPMR_EL3, x0 + ldr x0,=0x80000000003FF + msr CORTEX_A710_CPUPCR_EL3, x0 +workaround_reset_end cortex_a710, ERRATUM(2216384) + +check_erratum_ls cortex_a710, ERRATUM(2216384), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2267065), ERRATA_A710_2267065 + sysreg_bit_set CORTEX_A710_CPUACTLR_EL1, CORTEX_A710_CPUACTLR_EL1_BIT_22 +workaround_reset_end cortex_a710, ERRATUM(2267065) + +check_erratum_ls cortex_a710, ERRATUM(2267065), CPU_REV(2, 0) + +workaround_reset_start cortex_a710, ERRATUM(2282622), ERRATA_A710_2282622 + sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, BIT(0) +workaround_reset_end cortex_a710, ERRATUM(2282622) + +check_erratum_ls cortex_a710, ERRATUM(2282622), CPU_REV(2, 1) + +workaround_runtime_start cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219 + /* Set bit 36 in ACTLR2_EL1 */ + sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_36 +workaround_runtime_end cortex_a710, ERRATUM(2291219), NO_ISB + +check_erratum_ls cortex_a710, ERRATUM(2291219), CPU_REV(2, 0) + +/* + * ERRATA_DSU_2313941 is defined in dsu_helpers.S but applies to Cortex-A710 as + * well. Create a symbollic link to existing errata workaround to get them + * registered under the Errata Framework. */ -func errata_a710_2371105_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2371105 - cbz x0, 1f +.equ check_erratum_cortex_a710_2313941, check_errata_dsu_2313941 +.equ erratum_cortex_a710_2313941_wa, errata_dsu_2313941_wa +add_erratum_entry cortex_a710, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET +workaround_reset_start cortex_a710, ERRATUM(2371105), ERRATA_A710_2371105 /* Set bit 40 in CPUACTLR2_EL1 */ - mrs x1, CORTEX_A710_CPUACTLR2_EL1 - orr x1, x1, #CORTEX_A710_CPUACTLR2_EL1_BIT_40 - msr CORTEX_A710_CPUACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a710_2371105_wa + sysreg_bit_set CORTEX_A710_CPUACTLR2_EL1, CORTEX_A710_CPUACTLR2_EL1_BIT_40 +workaround_reset_end cortex_a710, ERRATUM(2371105) -func check_errata_2371105 - /* Applies to <= r2p0. */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2371105 +check_erratum_ls cortex_a710, ERRATUM(2371105), CPU_REV(2, 0) -/* ---------------------------------------------------- - * Errata Workaround for Cortex-A710 Errata #2768515 - * This applies to revisions <= r2p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_a710_2768515_wa - mov x17, x30 - bl check_errata_2768515 - cbz x0, 1f +workaround_reset_start cortex_a710, ERRATUM(2742423), ERRATA_A710_2742423 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set CORTEX_A710_CPUACTLR5_EL1, BIT(55) + sysreg_bit_clear CORTEX_A710_CPUACTLR5_EL1, BIT(56) +workaround_reset_end cortex_a710, ERRATUM(2742423) +check_erratum_ls cortex_a710, ERRATUM(2742423), CPU_REV(2, 1) + +workaround_runtime_start cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_a710_2768515_wa +workaround_runtime_end cortex_a710, ERRATUM(2768515), NO_ISB -func check_errata_2768515 - /* Applies to all revisions <= r2p1 */ - mov x1, #0x21 - b cpu_rev_var_ls -endfunc check_errata_2768515 +check_erratum_ls cortex_a710, ERRATUM(2768515), CPU_REV(2, 1) -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 +workaround_reset_start cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Cortex-A710 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_cortex_a710 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a710, CVE(2022, 23960) + +check_erratum_chosen cortex_a710, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ func cortex_a710_core_pwr_dwn - -#if ERRATA_A710_2008768 - mov x4, x30 - bl cpu_get_rev_var - bl errata_a710_2008768_wa - mov x30, x4 -#endif - -#if ERRATA_A710_2291219 - mov x15, x30 - bl cpu_get_rev_var - bl errata_a710_2291219_wa - mov x30, x15 -#endif /* ERRATA_A710_2291219 */ + apply_erratum cortex_a710, ERRATUM(2008768), ERRATA_A710_2008768 + apply_erratum cortex_a710, ERRATUM(2291219), ERRATA_A710_2291219, NO_GET_CPU_REV /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_A710_CPUPWRCTLR_EL1, x0 -#if ERRATA_A710_2768515 - mov x15, x30 - bl cpu_get_rev_var - bl errata_a710_2768515_wa - mov x30, x15 -#endif /* ERRATA_A710_2768515 */ + sysreg_bit_set CORTEX_A710_CPUPWRCTLR_EL1, CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + apply_erratum cortex_a710, ERRATUM(2768515), ERRATA_A710_2768515, NO_GET_CPU_REV isb ret endfunc cortex_a710_core_pwr_dwn -#if REPORT_ERRATA - /* - * Errata printing function for Cortex-A710. Must follow AAPCS. - */ -func cortex_a710_errata_report - stp x8, x30, [sp, #-16]! +errata_report_shim cortex_a710 - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A710_1987031, cortex_a710, 1987031 - report_errata ERRATA_A710_2081180, cortex_a710, 2081180 - report_errata ERRATA_A710_2055002, cortex_a710, 2055002 - report_errata ERRATA_A710_2017096, cortex_a710, 2017096 - report_errata ERRATA_A710_2083908, cortex_a710, 2083908 - report_errata ERRATA_A710_2058056, cortex_a710, 2058056 - report_errata ERRATA_A710_2267065, cortex_a710, 2267065 - report_errata ERRATA_A710_2136059, cortex_a710, 2136059 - report_errata ERRATA_A710_2282622, cortex_a710, 2282622 - report_errata ERRATA_A710_2008768, cortex_a710, 2008768 - report_errata ERRATA_A710_2147715, cortex_a710, 2147715 - report_errata ERRATA_A710_2216384, cortex_a710, 2216384 - report_errata ERRATA_A710_2291219, cortex_a710, 2291219 - report_errata ERRATA_A710_2371105, cortex_a710, 2371105 - report_errata ERRATA_A710_2768515, cortex_a710, 2768515 - report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 - report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a710_errata_report -#endif - -func cortex_a710_reset_func - mov x19, x30 - +cpu_reset_func_start cortex_a710 /* Disable speculative loads */ msr SSBS, xzr - - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_DSU_2313941 - bl errata_dsu_2313941_wa -#endif - -#if ERRATA_A710_1987031 - mov x0, x18 - bl errata_a710_1987031_wa -#endif - -#if ERRATA_A710_2081180 - mov x0, x18 - bl errata_a710_2081180_wa -#endif - -#if ERRATA_A710_2055002 - mov x0, x18 - bl errata_a710_2055002_wa -#endif - -#if ERRATA_A710_2017096 - mov x0, x18 - bl errata_a710_2017096_wa -#endif - -#if ERRATA_A710_2083908 - mov x0, x18 - bl errata_a710_2083908_wa -#endif - -#if ERRATA_A710_2058056 - mov x0, x18 - bl errata_a710_2058056_wa -#endif - -#if ERRATA_A710_2267065 - mov x0, x18 - bl errata_a710_2267065_wa -#endif - -#if ERRATA_A710_2136059 - mov x0, x18 - bl errata_a710_2136059_wa -#endif - -#if ERRATA_A710_2147715 - mov x0, x18 - bl errata_a710_2147715_wa -#endif - -#if ERRATA_A710_2216384 - mov x0, x18 - bl errata_a710_2216384_wa -#endif /* ERRATA_A710_2216384 */ - -#if ERRATA_A710_2282622 - mov x0, x18 - bl errata_a710_2282622_wa -#endif - -#if ERRATA_A710_2371105 - mov x0, x18 - bl errata_a710_2371105_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex-A710 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_a710 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc cortex_a710_reset_func +cpu_reset_func_end cortex_a710 /* --------------------------------------------- * This function provides Cortex-A710 specific
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S index 7603210..dd4c307 100644 --- a/lib/cpus/aarch64/cortex_a715.S +++ b/lib/cpus/aarch64/cortex_a715.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,90 +7,62 @@ #include <arch.h> #include <asm_macros.S> #include <common/bl_common.h> -#include <cortex_makalu.h> +#include <cortex_a715.h> #include <cpu_macros.S> #include <plat_macros.S> #include "wa_cve_2022_23960_bhb_vector.S" /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif #if WORKAROUND_CVE_2022_23960 - wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_BHB_LOOP_COUNT, cortex_makalu + wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 #endif /* WORKAROUND_CVE_2022_23960 */ -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func cortex_makalu_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 /* - * The Cortex Makalu generic vectors are overridden to apply errata + * The Cortex-A715 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_cortex_makalu - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + override_vector_table wa_cve_vbar_cortex_a715 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a715, CVE(2022, 23960) - isb - ret -endfunc cortex_makalu_reset_func +check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + +cpu_reset_func_start cortex_a715 + /* Disable speculative loads */ + msr SSBS, xzr +cpu_reset_func_end cortex_a715 /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ -func cortex_makalu_core_pwr_dwn +func cortex_a715_core_pwr_dwn /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0 + mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A715_CPUPWRCTLR_EL1, x0 isb ret -endfunc cortex_makalu_core_pwr_dwn +endfunc cortex_a715_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Makalu. Must follow AAPCS. - */ -func cortex_makalu_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, cortex_makalu, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_makalu_errata_report -#endif +errata_report_shim cortex_a715 /* --------------------------------------------- - * This function provides Cortex Makalu-specific + * This function provides Cortex-A715 specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and @@ -98,16 +70,16 @@ * reported. * --------------------------------------------- */ -.section .rodata.cortex_makalu_regs, "aS" -cortex_makalu_regs: /* The ascii list of register names to be reported */ +.section .rodata.cortex_a715_regs, "aS" +cortex_a715_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" -func cortex_makalu_cpu_reg_dump - adr x6, cortex_makalu_regs - mrs x8, CORTEX_MAKALU_CPUECTLR_EL1 +func cortex_a715_cpu_reg_dump + adr x6, cortex_a715_regs + mrs x8, CORTEX_A715_CPUECTLR_EL1 ret -endfunc cortex_makalu_cpu_reg_dump +endfunc cortex_a715_cpu_reg_dump -declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \ - cortex_makalu_reset_func, \ - cortex_makalu_core_pwr_dwn +declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ + cortex_a715_reset_func, \ + cortex_a715_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index de2d36e..997f261 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,9 +47,7 @@ * --------------------------------------------- */ func cortex_a72_disable_hw_prefetcher - mrs x0, CORTEX_A72_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH - msr CORTEX_A72_CPUACTLR_EL1, x0 + sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH isb dsb ish ret @@ -60,9 +58,7 @@ * --------------------------------------------- */ func cortex_a72_disable_smp - mrs x0, CORTEX_A72_ECTLR_EL1 - bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT - msr CORTEX_A72_ECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT ret endfunc cortex_a72_disable_smp @@ -78,31 +74,33 @@ ret endfunc cortex_a72_disable_ext_debug - /* -------------------------------------------------- - * Errata Workaround for Cortex A72 Errata #859971. - * This applies only to revision <= r0p3 of Cortex A72. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: - * -------------------------------------------------- - */ -func errata_a72_859971_wa - mov x17,x30 - bl check_errata_859971 - cbz x0, 1f - mrs x1, CORTEX_A72_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH - msr CORTEX_A72_CPUACTLR_EL1, x1 +func check_smccc_arch_workaround_3 + cpu_check_csv2 x0, 1f + mov x0, #ERRATA_APPLIES + ret 1: - ret x17 -endfunc errata_a72_859971_wa + mov x0, #ERRATA_NOT_APPLIES + ret +endfunc check_smccc_arch_workaround_3 -func check_errata_859971 - mov x1, #0x03 - b cpu_rev_var_ls -endfunc check_errata_859971 +workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971 + sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH +workaround_reset_end cortex_a72, ERRATUM(859971) -func check_errata_cve_2017_5715 +check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3) + +/* Due to the nature of the errata it is applied unconditionally when chosen */ +check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367 +/* erratum workaround is interleaved with generic code */ +add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET + +workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_mmu_vbar +#endif +workaround_reset_end cortex_a72, CVE(2017, 5715) + +check_erratum_custom_start cortex_a72, CVE(2017, 5715) cpu_check_csv2 x0, 1f #if WORKAROUND_CVE_2017_5715 mov x0, #ERRATA_APPLIES @@ -113,104 +111,58 @@ 1: mov x0, #ERRATA_NOT_APPLIES ret -endfunc check_errata_cve_2017_5715 +check_erratum_custom_end cortex_a72, CVE(2017, 5715) -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 +workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE + isb + dsb sy +workaround_reset_end cortex_a72, CVE(2018, 3639) +check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 - /* -------------------------------------------------- - * Errata workaround for Cortex A72 Errata #1319367. - * This applies to all revisions of Cortex A72. - * -------------------------------------------------- - */ -func check_errata_1319367 -#if ERRATA_A72_1319367 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_1319367 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func check_smccc_arch_workaround_3 - cpu_check_csv2 x0, 1f - mov x0, #ERRATA_APPLIES - ret -1: - mov x0, #ERRATA_NOT_APPLIES - ret -endfunc check_smccc_arch_workaround_3 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A72. - * ------------------------------------------------- - */ -func cortex_a72_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A72_859971 - mov x0, x18 - bl errata_a72_859971_wa -#endif - -#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) - cpu_check_csv2 x0, 1f - adr x0, wa_cve_2017_5715_mmu_vbar - msr vbar_el3, x0 - /* isb will be performed before returning from this function */ - - /* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */ - b 2f -1: -#if WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* Skip installing vector table again if already done for CVE(2017, 5715) */ /* * The Cortex-A72 generic vectors are overridden to apply the - * mitigation on exception entry from lower ELs for revisions >= r1p0 + * mitigation on exception entry from lower ELs for revisions >= r1p0 * which has CSV2 implemented. */ adr x0, wa_cve_vbar_cortex_a72 + mrs x1, vbar_el3 + cmp x0, x1 + b.eq 1f msr vbar_el3, x0 +1: +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a72, CVE(2022, 23960) - /* isb will be performed before returning from this function */ +check_erratum_custom_start cortex_a72, CVE(2022, 23960) +#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 + cpu_check_csv2 x0, 1f + mov x0, #ERRATA_APPLIES + ret +1: +#if WORKAROUND_CVE_2022_23960 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING #endif /* WORKAROUND_CVE_2022_23960 */ -2: -#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ + ret +#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ + mov x0, #ERRATA_MISSING + ret +check_erratum_custom_end cortex_a72, CVE(2022, 23960) -#if WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A72_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE - msr CORTEX_A72_CPUACTLR_EL1, x0 - isb - dsb sy -#endif +cpu_reset_func_start cortex_a72 /* --------------------------------------------- * Enable the SMP bit. * --------------------------------------------- */ - mrs x0, CORTEX_A72_ECTLR_EL1 - orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT - msr CORTEX_A72_ECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a72_reset_func + sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT + +cpu_reset_func_end cortex_a72 /* ---------------------------------------------------- * The CPU Ops core power down function for Cortex-A72. @@ -319,30 +271,7 @@ b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A72. Must follow AAPCS. - */ -func cortex_a72_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A72_859971, cortex_a72, 859971 - report_errata ERRATA_A72_1319367, cortex_a72, 1319367 - report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639 - report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a72_errata_report -#endif +errata_report_shim cortex_a72 /* --------------------------------------------- * This function provides cortex_a72 specific @@ -367,7 +296,7 @@ declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \ cortex_a72_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_cortex_a72_5715, \ CPU_NO_EXTRA2_FUNC, \ check_smccc_arch_workaround_3, \ cortex_a72_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S new file mode 100644 index 0000000..4b28fdb --- /dev/null +++ b/lib/cpus/aarch64/cortex_a720.S
@@ -0,0 +1,84 @@ +/* + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_a720.h> +#include <cpu_macros.S> +#include <plat_macros.S> +#include "wa_cve_2022_23960_bhb_vector.S" + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +#if WORKAROUND_CVE_2022_23960 + wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 +#endif /* WORKAROUND_CVE_2022_23960 */ + +workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Cortex A720 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_cortex_a720 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a720, CVE(2022, 23960) + +check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + +cpu_reset_func_start cortex_a720 + /* Disable speculative loads */ + msr SSBS, xzr +cpu_reset_func_end cortex_a720 + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_a720_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + + isb + ret +endfunc cortex_a720_core_pwr_dwn + +errata_report_shim cortex_a720 + + /* --------------------------------------------- + * This function provides Cortex A720-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a720_regs, "aS" +cortex_a720_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a720_cpu_reg_dump + adr x6, cortex_a720_regs + mrs x8, CORTEX_A720_CPUECTLR_EL1 + ret +endfunc cortex_a720_cpu_reg_dump + +declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ + cortex_a720_reset_func, \ + cortex_a720_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S index edcd1f5..3a6b922 100644 --- a/lib/cpus/aarch64/cortex_a73.S +++ b/lib/cpus/aarch64/cortex_a73.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,9 +15,7 @@ * --------------------------------------------- */ func cortex_a73_disable_dcache - mrs x1, sctlr_el3 - bic x1, x1, #SCTLR_C_BIT - msr sctlr_el3, x1 + sysreg_bit_clear sctlr_el3, SCTLR_C_BIT isb ret endfunc cortex_a73_disable_dcache @@ -27,124 +25,97 @@ * --------------------------------------------- */ func cortex_a73_disable_smp - mrs x0, CORTEX_A73_CPUECTLR_EL1 - bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT - msr CORTEX_A73_CPUECTLR_EL1, x0 + sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT isb dsb sy ret endfunc cortex_a73_disable_smp - /* --------------------------------------------------- - * Errata Workaround for Cortex A73 Errata #852427. - * This applies only to revision r0p0 of Cortex A73. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a73_852427_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_852427 - cbz x0, 1f - mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER - orr x1, x1, #(1 << 12) - msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1 - isb +func check_smccc_arch_workaround_3 + mov x0, #ERRATA_APPLIES + ret +endfunc check_smccc_arch_workaround_3 + +workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427 + sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12) +workaround_reset_end cortex_a73, ERRATUM(852427) + +check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0) + +workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423 + sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7) +workaround_reset_end cortex_a73, ERRATUM(855423) + +check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1) + +workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_bpiall_vbar +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a73, CVE(2017, 5715) + +check_erratum_custom_start cortex_a73, CVE(2017, 5715) + cpu_check_csv2 x0, 1f +#if WORKAROUND_CVE_2017_5715 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING +#endif + ret 1: - ret x17 -endfunc errata_a73_852427_wa + mov x0, #ERRATA_NOT_APPLIES + ret +check_erratum_custom_end cortex_a73, CVE(2017, 5715) -func check_errata_852427 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_852427 +workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE +workaround_reset_end cortex_a73, CVE(2018, 3639) - /* --------------------------------------------------- - * Errata Workaround for Cortex A73 Errata #855423. - * This applies only to revision <= r0p1 of Cortex A73. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------- - */ -func errata_a73_855423_wa - /* - * Compare x0 against revision r0p1 - */ - mov x17, x30 - bl check_errata_855423 - cbz x0, 1f - mrs x1, CORTEX_A73_IMP_DEF_REG2 - orr x1, x1, #(1 << 7) - msr CORTEX_A73_IMP_DEF_REG2, x1 - isb +check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + +workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* Skip installing vector table again for CVE_2022_23960 */ + adr x0, wa_cve_2017_5715_bpiall_vbar + mrs x1, vbar_el3 + + cmp x0, x1 + b.eq 1f + msr vbar_el3, x0 1: - ret x17 -endfunc errata_a73_855423_wa +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a73, CVE(2022, 23960) -func check_errata_855423 - mov x1, #0x01 - b cpu_rev_var_ls -endfunc check_errata_855423 +check_erratum_custom_start cortex_a73, CVE(2022, 23960) +#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 + cpu_check_csv2 x0, 1f + mov x0, #ERRATA_APPLIES + ret + 1: +#if WORKAROUND_CVE_2022_23960 + mov x0, #ERRATA_APPLIES +#else + mov x0, #ERRATA_MISSING +#endif /* WORKAROUND_CVE_2022_23960 */ + ret +#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ + mov x0, #ERRATA_MISSING + ret +check_erratum_custom_end cortex_a73, CVE(2022, 23960) /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A73. * ------------------------------------------------- */ -func cortex_a73_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A73_852427 - mov x0, x18 - bl errata_a73_852427_wa -#endif - -#if ERRATA_A73_855423 - mov x0, x18 - bl errata_a73_855423_wa -#endif - -#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) - cpu_check_csv2 x0, 1f - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 - isb - /* Skip installing vector table again for CVE_2022_23960 */ - b 2f -1: -#if WORKAROUND_CVE_2022_23960 - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 - isb -#endif -2: -#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ - -#if WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A73_IMP_DEF_REG1 - orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE - msr CORTEX_A73_IMP_DEF_REG1, x0 - isb -#endif - +cpu_reset_func_start cortex_a73 /* --------------------------------------------- * Enable the SMP bit. * Clobbers : x0 * --------------------------------------------- */ - mrs x0, CORTEX_A73_CPUECTLR_EL1 - orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT - msr CORTEX_A73_CPUECTLR_EL1, x0 - isb - ret x19 -endfunc cortex_a73_reset_func + sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT +cpu_reset_func_end cortex_a73 func cortex_a73_core_pwr_dwn mov x18, x30 @@ -207,74 +178,8 @@ b cortex_a73_disable_smp endfunc cortex_a73_cluster_pwr_dwn -func check_errata_cve_2017_5715 - cpu_check_csv2 x0, 1f -#if WORKAROUND_CVE_2017_5715 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -1: - mov x0, #ERRATA_NOT_APPLIES - ret -endfunc check_errata_cve_2017_5715 -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 - cpu_check_csv2 x0, 1f - mov x0, #ERRATA_APPLIES - ret - 1: -# if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -# else - mov x0, #ERRATA_MISSING -# endif /* WORKAROUND_CVE_2022_23960 */ - ret -#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ - mov x0, #ERRATA_MISSING - ret -endfunc check_errata_cve_2022_23960 - -func check_smccc_arch_workaround_3 - mov x0, #ERRATA_APPLIES - ret -endfunc check_smccc_arch_workaround_3 - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A75. Must follow AAPCS. - */ -func cortex_a73_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A73_852427, cortex_a73, 852427 - report_errata ERRATA_A73_855423, cortex_a73, 855423 - report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 - report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a73_errata_report -#endif +errata_report_shim cortex_a73 /* --------------------------------------------- * This function provides cortex_a73 specific @@ -298,7 +203,7 @@ declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ cortex_a73_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_cortex_a73_5715, \ CPU_NO_EXTRA2_FUNC, \ check_smccc_arch_workaround_3, \ cortex_a73_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index e22c828..c90be67 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,139 +15,43 @@ #error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif - /* -------------------------------------------------- - * Errata Workaround for Cortex A75 Errata #764081. - * This applies only to revision r0p0 of Cortex A75. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a75_764081_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_764081 - cbz x0, 1f - mrs x1, sctlr_el3 - orr x1, x1 ,#SCTLR_IESB_BIT - msr sctlr_el3, x1 - isb -1: - ret x17 -endfunc errata_a75_764081_wa +workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 + sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT +workaround_reset_end cortex_a75, ERRATUM(764081) -func check_errata_764081 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_764081 +check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A75 Errata #790748. - * This applies only to revision r0p0 of Cortex A75. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a75_790748_wa - /* - * Compare x0 against revision r0p0 - */ - mov x17, x30 - bl check_errata_790748 - cbz x0, 1f - mrs x1, CORTEX_A75_CPUACTLR_EL1 - orr x1, x1 ,#(1 << 13) - msr CORTEX_A75_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a75_790748_wa +workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 + sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) +workaround_reset_end cortex_a75, ERRATUM(790748) -func check_errata_790748 - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_790748 +check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A75. - * ------------------------------------------------- - */ -func cortex_a75_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 +/* ERRATA_DSU_798953 : + * The errata is defined in dsu_helpers.S but applies to cortex_a75 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953 +.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa +add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET -#if ERRATA_A75_764081 - mov x0, x18 - bl errata_a75_764081_wa -#endif +/* ERRATA_DSU_936184 : + * The errata is defined in dsu_helpers.S but applies to cortex_a75 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184 +.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa +add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET -#if ERRATA_A75_790748 - mov x0, x18 - bl errata_a75_790748_wa -#endif +workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + override_vector_table wa_cve_2017_5715_bpiall_vbar +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a75, CVE(2017, 5715) -#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) - cpu_check_csv2 x0, 1f - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 - isb - /* Skip installing vector table again for CVE_2022_23960 */ - b 2f -1: -#if WORKAROUND_CVE_2022_23960 - adr x0, wa_cve_2017_5715_bpiall_vbar - msr vbar_el3, x0 - isb -#endif -2: -#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */ - -#if WORKAROUND_CVE_2018_3639 - mrs x0, CORTEX_A75_CPUACTLR_EL1 - orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE - msr CORTEX_A75_CPUACTLR_EL1, x0 - isb -#endif - -#if ERRATA_DSU_798953 - bl errata_dsu_798953_wa -#endif - -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif - -#if ENABLE_FEAT_AMU - /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT - msr actlr_el3, x0 - isb - - /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT - msr actlr_el2, x0 - isb - - /* Enable group0 counters */ - mov x0, #CORTEX_A75_AMU_GROUP0_MASK - msr CPUAMCNTENSET_EL0, x0 - isb - - /* Enable group1 counters */ - mov x0, #CORTEX_A75_AMU_GROUP1_MASK - msr CPUAMCNTENSET_EL0, x0 - isb -#endif - ret x19 -endfunc cortex_a75_reset_func - -func check_errata_cve_2017_5715 +check_erratum_custom_start cortex_a75, CVE(2017, 5715) cpu_check_csv2 x0, 1f #if WORKAROUND_CVE_2017_5715 mov x0, #ERRATA_APPLIES @@ -158,18 +62,27 @@ 1: mov x0, #ERRATA_NOT_APPLIES ret -endfunc check_errata_cve_2017_5715 +check_erratum_custom_end cortex_a75, CVE(2017, 5715) -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 +workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE +workaround_reset_end cortex_a75, CVE(2018, 3639) -func check_errata_cve_2022_23960 +check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + +workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* Skip installing vector table again if already done for CVE(2017, 5715) */ + adr x0, wa_cve_2017_5715_bpiall_vbar + mrs x1, vbar_el3 + cmp x0, x1 + b.eq 1f + msr vbar_el3, x0 +1: +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a75, CVE(2022, 23960) + +check_erratum_custom_start cortex_a75, CVE(2022, 23960) #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 cpu_check_csv2 x0, 1f mov x0, #ERRATA_APPLIES @@ -184,7 +97,34 @@ #endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ mov x0, #ERRATA_MISSING ret -endfunc check_errata_cve_2022_23960 +check_erratum_custom_end cortex_a75, CVE(2022, 23960) + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A75. + * ------------------------------------------------- + */ + +cpu_reset_func_start cortex_a75 +#if ENABLE_FEAT_AMU + /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ + sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT + isb + + /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ + sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT + isb + + /* Enable group0 counters */ + mov x0, #CORTEX_A75_AMU_GROUP0_MASK + msr CPUAMCNTENSET_EL0, x0 + isb + + /* Enable group1 counters */ + mov x0, #CORTEX_A75_AMU_GROUP1_MASK + msr CPUAMCNTENSET_EL0, x0 + /* isb included in cpu_reset_func_end macro */ +#endif +cpu_reset_func_end cortex_a75 func check_smccc_arch_workaround_3 mov x0, #ERRATA_APPLIES @@ -200,39 +140,13 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK - msr CORTEX_A75_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ + CORTEX_A75_CORE_PWRDN_EN_MASK isb ret endfunc cortex_a75_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A75. Must follow AAPCS. - */ -func cortex_a75_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A75_764081, cortex_a75, 764081 - report_errata ERRATA_A75_790748, cortex_a75, 790748 - report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 - report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953 - report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 - report_errata WORKAROUND_CVE_2022_23960, cortex_a75, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a75_errata_report -#endif +errata_report_shim cortex_a75 /* --------------------------------------------- * This function provides cortex_a75 specific @@ -255,7 +169,7 @@ declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ cortex_a75_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_cortex_a75_5715, \ CPU_NO_EXTRA2_FUNC, \ check_smccc_arch_workaround_3, \ cortex_a75_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c index bd2c697..11190c8 100644 --- a/lib/cpus/aarch64/cortex_a75_pubsub.c +++ b/lib/cpus/aarch64/cortex_a75_pubsub.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 36507de..8b3d730 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -298,154 +298,50 @@ endfunc apply_cve_2018_3639_sync_wa #endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */ - /* -------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1073348. - * This applies only to revision <= r1p0 of Cortex A76. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1073348_wa - /* - * Compare x0 against revision r1p0 - */ - mov x17, x30 - bl check_errata_1073348 - cbz x0, 1f - mrs x1, CORTEX_A76_CPUACTLR_EL1 - orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION - msr CORTEX_A76_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a76_1073348_wa +workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348 + sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION +workaround_reset_end cortex_a76, ERRATUM(1073348) -func check_errata_1073348 - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1073348 +check_erratum_ls cortex_a76, ERRATUM(1073348), CPU_REV(1, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1130799. - * This applies only to revision <= r2p0 of Cortex A76. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1130799_wa - /* - * Compare x0 against revision r2p0 - */ - mov x17, x30 - bl check_errata_1130799 - cbz x0, 1f - mrs x1, CORTEX_A76_CPUACTLR2_EL1 - orr x1, x1 ,#(1 << 59) +workaround_reset_start cortex_a76, ERRATUM(1130799), ERRATA_A76_1130799 + sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_59 msr CORTEX_A76_CPUACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a76_1130799_wa +workaround_reset_end cortex_a76, ERRATUM(1130799) -func check_errata_1130799 - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1130799 +check_erratum_ls cortex_a76, ERRATUM(1130799), CPU_REV(2, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1220197. - * This applies only to revision <= r2p0 of Cortex A76. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1220197_wa -/* - * Compare x0 against revision r2p0 - */ - mov x17, x30 - bl check_errata_1220197 - cbz x0, 1f - mrs x1, CORTEX_A76_CPUECTLR_EL1 - orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 - msr CORTEX_A76_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a76_1220197_wa +workaround_reset_start cortex_a76, ERRATUM(1220197), ERRATA_A76_1220197 + sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 +workaround_reset_end cortex_a76, ERRATUM(1220197) -func check_errata_1220197 - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1220197 +check_erratum_ls cortex_a76, ERRATUM(1220197), CPU_REV(2, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1257314. - * This applies only to revision <= r3p0 of Cortex A76. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1257314_wa - /* - * Compare x0 against revision r3p0 - */ - mov x17, x30 - bl check_errata_1257314 - cbz x0, 1f - mrs x1, CORTEX_A76_CPUACTLR3_EL1 - orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10 - msr CORTEX_A76_CPUACTLR3_EL1, x1 - isb -1: - ret x17 -endfunc errata_a76_1257314_wa +workaround_reset_start cortex_a76, ERRATUM(1257314), ERRATA_A76_1257314 + sysreg_bit_set CORTEX_A76_CPUACTLR3_EL1, CORTEX_A76_CPUACTLR3_EL1_BIT_10 +workaround_reset_end cortex_a76, ERRATUM(1257314) -func check_errata_1257314 - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1257314 +check_erratum_ls cortex_a76, ERRATUM(1257314), CPU_REV(3, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1262888. - * This applies only to revision <= r3p0 of Cortex A76. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1262888_wa - /* - * Compare x0 against revision r3p0 - */ - mov x17, x30 - bl check_errata_1262888 - cbz x0, 1f - mrs x1, CORTEX_A76_CPUECTLR_EL1 - orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51 - msr CORTEX_A76_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a76_1262888_wa +workaround_reset_start cortex_a76, ERRATUM(1262606), ERRATA_A76_1262606 + sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13 +workaround_reset_end cortex_a76, ERRATUM(1262606) -func check_errata_1262888 - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1262888 +check_erratum_ls cortex_a76, ERRATUM(1262606), CPU_REV(3, 0) - /* --------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1286807. - * This applies only to revision <= r3p0 of Cortex A76. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * --------------------------------------------------- - */ -func check_errata_1286807 +workaround_reset_start cortex_a76, ERRATUM(1262888), ERRATA_A76_1262888 + sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_BIT_51 +workaround_reset_end cortex_a76, ERRATUM(1262888) + +check_erratum_ls cortex_a76, ERRATUM(1262888), CPU_REV(3, 0) + +workaround_reset_start cortex_a76, ERRATUM(1275112), ERRATA_A76_1275112 + sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13 +workaround_reset_end cortex_a76, ERRATUM(1275112) + +check_erratum_ls cortex_a76, ERRATUM(1275112), CPU_REV(3, 0) + +check_erratum_custom_start cortex_a76, ERRATUM(1286807) #if ERRATA_A76_1286807 mov x0, #ERRATA_APPLIES ret @@ -453,100 +349,21 @@ mov x1, #0x30 b cpu_rev_var_ls #endif -endfunc check_errata_1286807 +check_erratum_custom_end cortex_a76, ERRATUM(1286807) - /* -------------------------------------------------- - * Errata workaround for Cortex A76 Errata #1791580. - * This applies to revisions <= r4p0 of Cortex A76. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1791580_wa - /* Compare x0 against revision r4p0 */ - mov x17, x30 - bl check_errata_1791580 - cbz x0, 1f - mrs x1, CORTEX_A76_CPUACTLR2_EL1 - orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2 - msr CORTEX_A76_CPUACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a76_1791580_wa +workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580 + sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2 +workaround_reset_end cortex_a76, ERRATUM(1791580) -func check_errata_1791580 - /* Applies to everything <=r4p0. */ - mov x1, #0x40 - b cpu_rev_var_ls -endfunc check_errata_1791580 +check_erratum_ls cortex_a76, ERRATUM(1791580), CPU_REV(4, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1262606, - * #1275112, and #1868343. #1262606 and #1275112 - * apply to revisions <= r3p0 and #1868343 applies to - * revisions <= r4p0. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ +workaround_reset_start cortex_a76, ERRATUM(1868343), ERRATA_A76_1868343 + sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13 +workaround_reset_end cortex_a76, ERRATUM(1868343) -func errata_a76_1262606_1275112_1868343_wa - mov x17, x30 +check_erratum_ls cortex_a76, ERRATUM(1868343), CPU_REV(4, 0) -/* Check for <= r3p0 cases and branch if check passes. */ -#if ERRATA_A76_1262606 || ERRATA_A76_1275112 - bl check_errata_1262606 - cbnz x0, 1f -#endif - -/* Check for <= r4p0 cases and branch if check fails. */ -#if ERRATA_A76_1868343 - bl check_errata_1868343 - cbz x0, 2f -#endif -1: - mrs x1, CORTEX_A76_CPUACTLR_EL1 - orr x1, x1, #CORTEX_A76_CPUACTLR_EL1_BIT_13 - msr CORTEX_A76_CPUACTLR_EL1, x1 - isb -2: - ret x17 -endfunc errata_a76_1262606_1275112_1868343_wa - -func check_errata_1262606 - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1262606 - -func check_errata_1275112 - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1275112 - -func check_errata_1868343 - mov x1, #0x40 - b cpu_rev_var_ls -endfunc check_errata_1868343 - -/* -------------------------------------------------- - * Errata Workaround for A76 Erratum 1946160. - * This applies to revisions r3p0 - r4p1 of A76. - * It also exists in r0p0 - r2p0 but there is no fix - * in those revisions. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a76_1946160_wa - /* Compare x0 against revisions r3p0 - r4p1 */ - mov x17, x30 - bl check_errata_1946160 - cbz x0, 1f - +workaround_reset_start cortex_a76, ERRATUM(1946160), ERRATA_A76_1946160 mov x0, #3 msr S3_6_C15_C8_0, x0 ldr x0, =0x10E3900002 @@ -573,68 +390,33 @@ msr S3_6_C15_C8_3, x0 ldr x0, =0x2001003FF msr S3_6_C15_C8_1, x0 +workaround_reset_end cortex_a76, ERRATUM(1946160) - isb -1: - ret x17 -endfunc errata_a76_1946160_wa +check_erratum_range cortex_a76, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1) -func check_errata_1946160 - /* Applies to revisions r3p0 - r4p1. */ - mov x1, #0x30 - mov x2, #0x41 - b cpu_rev_var_range -endfunc check_errata_1946160 - - /* ---------------------------------------------------- - * Errata Workaround for Cortex-A76 Errata #2743102 - * This applies to revisions <= r4p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_a76_2743102_wa - mov x17, x30 - bl check_errata_2743102 - cbz x0, 1f - +workaround_runtime_start cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_a76_2743102_wa +workaround_runtime_end cortex_a76, ERRATUM(2743102) -func check_errata_2743102 - /* Applies to all revisions <= r4p1 */ - mov x1, #0x41 - b cpu_rev_var_ls -endfunc check_errata_2743102 +check_erratum_ls cortex_a76, ERRATUM(2743102), CPU_REV(4, 1) -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 +check_erratum_chosen cortex_a76, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 func cortex_a76_disable_wa_cve_2018_3639 - mrs x0, CORTEX_A76_CPUACTLR2_EL1 - bic x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE - msr CORTEX_A76_CPUACTLR2_EL1, x0 + sysreg_bit_clear CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE isb ret endfunc cortex_a76_disable_wa_cve_2018_3639 - /* -------------------------------------------------------------- - * Errata Workaround for Cortex A76 Errata #1165522. - * This applies only to revisions <= r3p0 of Cortex A76. - * Due to the nature of the errata it is applied unconditionally - * when built in, report it as applicable in this case - * -------------------------------------------------------------- - */ -func check_errata_1165522 +/* -------------------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1165522. + * This applies only to revisions <= r3p0 of Cortex A76. + * Due to the nature of the errata it is applied unconditionally + * when built in, report it as applicable in this case + * -------------------------------------------------------------- + */ +check_erratum_custom_start cortex_a76, ERRATUM(1165522) #if ERRATA_A76_1165522 mov x0, #ERRATA_APPLIES ret @@ -642,66 +424,32 @@ mov x1, #0x30 b cpu_rev_var_ls #endif -endfunc check_errata_1165522 +check_erratum_custom_end cortex_a76, ERRATUM(1165522) -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif /* WORKAROUND_CVE_2022_23960 */ - ret -endfunc check_errata_cve_2022_23960 +check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A76. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_a76_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 +/* erratum has no workaround in the cpu. Generic code must take care */ +add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960, NO_APPLY_AT_RESET -#if ERRATA_A76_1073348 - mov x0, x18 - bl errata_a76_1073348_wa -#endif +/* ERRATA_DSU_798953 : + * The errata is defined in dsu_helpers.S but applies to cortex_a76 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a76_798953, check_errata_dsu_798953 +.equ erratum_cortex_a76_798953_wa, errata_dsu_798953_wa +add_erratum_entry cortex_a76, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET -#if ERRATA_A76_1130799 - mov x0, x18 - bl errata_a76_1130799_wa -#endif +/* ERRATA_DSU_936184 : + * The errata is defined in dsu_helpers.S but applies to cortex_a76 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_a76_936184, check_errata_dsu_936184 +.equ erratum_cortex_a76_936184_wa, errata_dsu_936184_wa +add_erratum_entry cortex_a76, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET -#if ERRATA_A76_1220197 - mov x0, x18 - bl errata_a76_1220197_wa -#endif - -#if ERRATA_A76_1257314 - mov x0, x18 - bl errata_a76_1257314_wa -#endif - -#if ERRATA_A76_1262606 || ERRATA_A76_1275112 || ERRATA_A76_1868343 - mov x0, x18 - bl errata_a76_1262606_1275112_1868343_wa -#endif - -#if ERRATA_A76_1262888 - mov x0, x18 - bl errata_a76_1262888_wa -#endif - -#if ERRATA_A76_1791580 - mov x0, x18 - bl errata_a76_1791580_wa -#endif - -#if ERRATA_A76_1946160 - mov x0, x18 - bl errata_a76_1946160_wa -#endif +cpu_reset_func_start cortex_a76 #if WORKAROUND_CVE_2018_3639 /* If the PE implements SSBS, we don't need the dynamic workaround */ @@ -714,9 +462,7 @@ #endif #if DYNAMIC_WORKAROUND_CVE_2018_3639 cbnz x0, 1f - mrs x0, CORTEX_A76_CPUACTLR2_EL1 - orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE - msr CORTEX_A76_CPUACTLR2_EL1, x0 + sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE isb #ifdef IMAGE_BL31 @@ -727,8 +473,7 @@ * If the below vector table is used, skip overriding it again for * CVE_2022_23960 as both use the same vbar. */ - adr x0, cortex_a76_wa_cve_vbar - msr vbar_el3, x0 + override_vector_table cortex_a76_wa_cve_vbar isb b 2f #endif /* IMAGE_BL31 */ @@ -743,22 +488,11 @@ * mitigation on exception entry from lower ELs. This will be bypassed * if DYNAMIC_WORKAROUND_CVE_2018_3639 has overridden the vectors. */ - adr x0, cortex_a76_wa_cve_vbar - msr vbar_el3, x0 + override_vector_table cortex_a76_wa_cve_vbar isb #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 2: - -#if ERRATA_DSU_798953 - bl errata_dsu_798953_wa -#endif - -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif - - ret x19 -endfunc cortex_a76_reset_func +cpu_reset_func_end cortex_a76 /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -769,55 +503,15 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, CORTEX_A76_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK - msr CORTEX_A76_CPUPWRCTLR_EL1, x0 -#if ERRATA_A76_2743102 - mov x15, x30 - bl cpu_get_rev_var - bl errata_a76_2743102_wa - mov x30, x15 -#endif /* ERRATA_A76_2743102 */ + sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK + + apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102 + isb ret endfunc cortex_a76_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A76. Must follow AAPCS. - */ -func cortex_a76_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A76_1073348, cortex_a76, 1073348 - report_errata ERRATA_A76_1130799, cortex_a76, 1130799 - report_errata ERRATA_A76_1165522, cortex_a76, 1165522 - report_errata ERRATA_A76_1220197, cortex_a76, 1220197 - report_errata ERRATA_A76_1257314, cortex_a76, 1257314 - report_errata ERRATA_A76_1262606, cortex_a76, 1262606 - report_errata ERRATA_A76_1262888, cortex_a76, 1262888 - report_errata ERRATA_A76_1275112, cortex_a76, 1275112 - report_errata ERRATA_A76_1286807, cortex_a76, 1286807 - report_errata ERRATA_A76_1791580, cortex_a76, 1791580 - report_errata ERRATA_A76_1868343, cortex_a76, 1868343 - report_errata ERRATA_A76_1946160, cortex_a76, 1946160 - report_errata ERRATA_A76_2743102, cortex_a76, 2743102 - report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 - report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953 - report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 - report_errata WORKAROUND_CVE_2022_23960, cortex_a76, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a76_errata_report -#endif +errata_report_shim cortex_a76 /* --------------------------------------------- * This function provides cortex_a76 specific
diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S index 5c19548..08a6ef9 100644 --- a/lib/cpus/aarch64/cortex_a76ae.S +++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Arm Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,71 +25,34 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae #endif /* WORKAROUND_CVE_2022_23960 */ -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif /* WORKAROUND_CVE_2022_23960 */ - ret -endfunc check_errata_cve_2022_23960 +check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 - /* -------------------------------------------- - * The CPU Ops reset function for Cortex-A76AE. - * Shall clobber: x0-x19 - * -------------------------------------------- - */ -func cortex_a76ae_reset_func -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 /* * The Cortex-A76ae generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_cortex_a76ae - msr vbar_el3, x0 + override_vector_table wa_cve_vbar_cortex_a76ae isb -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a76ae, CVE(2022, 23960) - ret -endfunc cortex_a76ae_reset_func +cpu_reset_func_start cortex_a76ae +cpu_reset_func_end cortex_a76ae + +errata_report_shim cortex_a76ae /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ func cortex_a76ae_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK - msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK isb ret endfunc cortex_a76ae_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A76AE. Must follow AAPCS. - */ -func cortex_a76ae_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a76ae_errata_report -#endif /* REPORT_ERRATA */ - /* --------------------------------------------- * This function provides cortex_a76ae specific * register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index 2882df7..86c2561 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,26 +26,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77 #endif /* WORKAROUND_CVE_2022_23960 */ - /* -------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #1508412. - * This applies only to revision <= r1p0 of Cortex A77. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a77_1508412_wa - /* - * Compare x0 against revision r1p0 - */ - mov x17, x30 - bl check_errata_1508412 - cbz x0, 3f - /* - * Compare x0 against revision r0p0 - */ - bl check_errata_1508412_0 +workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412 + /* move cpu revision in again and compare against r0p0 */ + mov x0, x7 + mov x1, #CPU_REV(0, 0) + bl cpu_rev_var_ls cbz x0, 1f + ldr x0, =0x0 msr CORTEX_A77_CPUPSELR_EL3, x0 ldr x0, =0x00E8400000 @@ -75,64 +62,30 @@ 2: ldr x0, =0x04004003FF msr CORTEX_A77_CPUPCR_EL3, x0 - isb -3: - ret x17 -endfunc errata_a77_1508412_wa +workaround_reset_end cortex_a77, ERRATUM(1508412) -func check_errata_1508412 - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1508412 +check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0) -func check_errata_1508412_0 - mov x1, #0x0 - b cpu_rev_var_ls -endfunc check_errata_1508412_0 +workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578 + sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2 +workaround_reset_end cortex_a77, ERRATUM(1791578) - /* -------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #1925769. - * This applies to revision <= r1p1 of Cortex A77. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a77_1925769_wa - /* Compare x0 against revision <= r1p1 */ - mov x17, x30 - bl check_errata_1925769 - cbz x0, 1f +check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1) - /* Set bit 8 in ECTLR_EL1 */ - mrs x1, CORTEX_A77_CPUECTLR_EL1 - orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 - msr CORTEX_A77_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a77_1925769_wa +workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714 + /* Disable allocation of splintered pages in the L2 TLB */ + sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53 +workaround_reset_end cortex_a77, ERRATUM(1800714) -func check_errata_1925769 - /* Applies to everything <= r1p1 */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_1925769 +check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1) - /* -------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #1946167. - * This applies to revision <= r1p1 of Cortex A77. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a77_1946167_wa - /* Compare x0 against revision <= r1p1 */ - mov x17, x30 - bl check_errata_1946167 - cbz x0, 1f +workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 + sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 +workaround_reset_end cortex_a77, ERRATUM(1925769) +check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) + +workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167 ldr x0,=0x4 msr CORTEX_A77_CPUPSELR_EL3,x0 ldr x0,=0x10E3900002 @@ -159,188 +112,42 @@ msr CORTEX_A77_CPUPMR_EL3,x0 ldr x0,=0x2001003FF msr CORTEX_A77_CPUPCR_EL3,x0 +workaround_reset_end cortex_a77, ERRATUM(1946167) - isb -1: - ret x17 -endfunc errata_a77_1946167_wa +check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1) -func check_errata_1946167 - /* Applies to everything <= r1p1 */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_1946167 +workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587 + sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0 +workaround_reset_end cortex_a77, ERRATUM(2356587) - /* -------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #1791578. - * This applies to revisions r0p0, r1p0, and r1p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a77_1791578_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1791578 - cbz x0, 1f +check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1) - /* Set bit 2 in ACTLR2_EL1 */ - mrs x1, CORTEX_A77_ACTLR2_EL1 - orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 - msr CORTEX_A77_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a77_1791578_wa - -func check_errata_1791578 - /* Applies to r0p0, r1p0, and r1p1 right now */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_1791578 - - /* -------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #2356587. - * This applies to revisions r0p0, r1p0, and r1p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a77_2356587_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2356587 - cbz x0, 1f - - /* Set bit 0 in ACTLR2_EL1 */ - mrs x1, CORTEX_A77_ACTLR2_EL1 - orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 - msr CORTEX_A77_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a77_2356587_wa - -func check_errata_2356587 - /* Applies to r0p0, r1p0, and r1p1 right now */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2356587 - - /* ----------------------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #2743100 - * This applies to revisions r0p0, r1p0, and r1p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ----------------------------------------------------------------- - */ -func errata_a77_2743100_wa - mov x17, x30 - bl check_errata_2743100 - cbz x0, 1f - +workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_a77_2743100_wa +workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB -func check_errata_2743100 - /* Applies to r0p0, r1p0, and r1p1 right now */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2743100 +check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1) -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - - /* -------------------------------------------------- - * Errata Workaround for Cortex A77 Errata #1800714. - * This applies to revision <= r1p1 of Cortex A77. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a77_1800714_wa - /* Compare x0 against revision <= r1p1 */ - mov x17, x30 - bl check_errata_1800714 - cbz x0, 1f - - /* Disable allocation of splintered pages in the L2 TLB */ - mrs x1, CORTEX_A77_CPUECTLR_EL1 - orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53 - msr CORTEX_A77_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a77_1800714_wa - -func check_errata_1800714 - /* Applies to everything <= r1p1 */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_1800714 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A77. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_a77_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A77_1508412 - mov x0, x18 - bl errata_a77_1508412_wa -#endif - -#if ERRATA_A77_1925769 - mov x0, x18 - bl errata_a77_1925769_wa -#endif - -#if ERRATA_A77_1946167 - mov x0, x18 - bl errata_a77_1946167_wa -#endif - -#if ERRATA_A77_1791578 - mov x0, x18 - bl errata_a77_1791578_wa -#endif - -#if ERRATA_A77_2356587 - mov x0, x18 - bl errata_a77_2356587_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 /* * The Cortex-A77 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ adr x0, wa_cve_vbar_cortex_a77 msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a77, CVE(2022, 23960) -#if ERRATA_A77_1800714 - mov x0, x18 - bl errata_a77_1800714_wa -#endif +check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 - isb - ret x19 -endfunc cortex_a77_reset_func + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A77. Must follow AAPCS. + * ------------------------------------------------- + */ +cpu_reset_func_start cortex_a77 +cpu_reset_func_end cortex_a77 /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -351,48 +158,16 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_A77_CPUPWRCTLR_EL1, x0 -#if ERRATA_A77_2743100 - mov x15, x30 - bl cpu_get_rev_var - bl errata_a77_2743100_wa - mov x30, x15 -#endif /* ERRATA_A77_2743100 */ + sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \ + CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + + apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100 + isb ret endfunc cortex_a77_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex-A77. Must follow AAPCS. - */ -func cortex_a77_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A77_1508412, cortex_a77, 1508412 - report_errata ERRATA_A77_1791578, cortex_a77, 1791578 - report_errata ERRATA_A77_1800714, cortex_a77, 1800714 - report_errata ERRATA_A77_1925769, cortex_a77, 1925769 - report_errata ERRATA_A77_1946167, cortex_a77, 1946167 - report_errata ERRATA_A77_2356587, cortex_a77, 2356587 - report_errata ERRATA_A77_2743100, cortex_a77, 2743100 - report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a77_errata_report -#endif - - +errata_report_shim cortex_a77 /* --------------------------------------------- * This function provides Cortex-A77 specific * register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 69d7ab0..b5c24e1 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2023, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,77 +24,25 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for A78 Erratum 1688305. - * This applies to revision r0p0 and r1p0 of A78. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_1688305_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1688305 - cbz x0, 1f - mrs x1, CORTEX_A78_ACTLR2_EL1 - orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 - msr CORTEX_A78_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a78_1688305_wa +workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 + sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 +workaround_reset_end cortex_a78, ERRATUM(1688305) -func check_errata_1688305 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1688305 +check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) -/* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata #1941498. - * This applies to revisions r0p0, r1p0, and r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_1941498_wa - /* Compare x0 against revision <= r1p1 */ - mov x17, x30 - bl check_errata_1941498 - cbz x0, 1f +workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 + sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 +workaround_reset_end cortex_a78, ERRATUM(1821534) - /* Set bit 8 in ECTLR_EL1 */ - mrs x1, CORTEX_A78_CPUECTLR_EL1 - orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 - msr CORTEX_A78_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_a78_1941498_wa +check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) -func check_errata_1941498 - /* Check for revision <= r1p1, might need to be updated later. */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_1941498 +workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 + sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 +workaround_reset_end cortex_a78, ERRATUM(1941498) -/* -------------------------------------------------- - * Errata Workaround for A78 Erratum 1951500. - * This applies to revisions r1p0 and r1p1 of A78. - * The issue also exists in r0p0 but there is no fix - * in that revision. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_1951500_wa - /* Compare x0 against revisions r1p0 - r1p1 */ - mov x17, x30 - bl check_errata_1951500 - cbz x0, 1f +check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) +workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 msr S3_6_c15_c8_0, xzr ldr x0, =0x10E3900002 msr S3_6_c15_c8_2, x0 @@ -120,60 +68,11 @@ msr S3_6_c15_c8_3, x0 ldr x0, =0x2001003FF msr S3_6_c15_c8_1, x0 +workaround_reset_end cortex_a78, ERRATUM(1951500) - isb -1: - ret x17 -endfunc errata_a78_1951500_wa +check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) -func check_errata_1951500 - /* Applies to revisions r1p0 and r1p1. */ - mov x1, #CPU_REV(1, 0) - mov x2, #CPU_REV(1, 1) - b cpu_rev_var_range -endfunc check_errata_1951500 - -/* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata #1821534. - * This applies to revisions r0p0 and r1p0. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_1821534_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_1821534 - cbz x0, 1f - - /* Set bit 2 in ACTLR2_EL1 */ - mrs x1, CORTEX_A78_ACTLR2_EL1 - orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 - msr CORTEX_A78_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_a78_1821534_wa - -func check_errata_1821534 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1821534 - -/* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata 1952683. - * This applies to revision r0p0. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_1952683_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_1952683 - cbz x0, 1f - +workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 ldr x0,=0x5 msr S3_6_c15_c8_0,x0 ldr x0,=0xEEE10A10 @@ -194,61 +93,21 @@ msr S3_6_c15_c8_3,x0 ldr x0,=0x40000080023ff msr S3_6_c15_c8_1,x0 - isb -1: - ret x17 -endfunc errata_a78_1952683_wa +workaround_reset_end cortex_a78, ERRATUM(1952683) -func check_errata_1952683 - /* Applies to r0p0 only */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_1952683 +check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata 2132060. - * This applies to revisions r0p0, r1p0, r1p1, and r1p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_a78_2132060_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2132060 - cbz x0, 1f - +workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 /* Apply the workaround. */ mrs x1, CORTEX_A78_CPUECTLR_EL1 mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH msr CORTEX_A78_CPUECTLR_EL1, x1 -1: - ret x17 -endfunc errata_a78_2132060_wa +workaround_reset_end cortex_a78, ERRATUM(2132060) -func check_errata_2132060 - /* Applies to r0p0, r0p1, r1p1, and r1p2 */ - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_2132060 +check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) -/* -------------------------------------------------------------------- - * Errata Workaround for A78 Erratum 2242635. - * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78 - * processor and is still open. - * The issue also exists in r0p0 but there is no fix in that revision. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------------------------- - */ -func errata_a78_2242635_wa - /* Compare x0 against revisions r1p0 - r1p2 */ - mov x17, x30 - bl check_errata_2242635 - cbz x0, 1f - +workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 ldr x0, =0x5 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ ldr x0, =0x10F600E000 @@ -257,242 +116,64 @@ msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ ldr x0, =0x80000000003FF msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ +workaround_reset_end cortex_a78, ERRATUM(2242635) - isb -1: - ret x17 -endfunc errata_a78_2242635_wa +check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) -func check_errata_2242635 - /* Applies to revisions r1p0 through r1p2. */ - mov x1, #CPU_REV(1, 0) - mov x2, #CPU_REV(1, 2) - b cpu_rev_var_range -endfunc check_errata_2242635 +workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 + sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) +workaround_reset_end cortex_a78, ERRATUM(2376745) -/* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata 2376745. - * This applies to revisions r0p0, r1p0, r1p1, and r1p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_a78_2376745_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2376745 - cbz x0, 1f +check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) - /* Apply the workaround. */ - mrs x1, CORTEX_A78_ACTLR2_EL1 - orr x1, x1, #BIT(0) - msr CORTEX_A78_ACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a78_2376745_wa +workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 + sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) +workaround_reset_end cortex_a78, ERRATUM(2395406) -func check_errata_2376745 - /* Applies to r0p0, r0p1, r1p1, and r1p2 */ - mov x1, #CPU_REV(1, 2) - b cpu_rev_var_ls -endfunc check_errata_2376745 +check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) -/* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata 2395406. - * This applies to revisions r0p0, r1p0, r1p1, and r1p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_a78_2395406_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2395406 - cbz x0, 1f - - /* Apply the workaround. */ - mrs x1, CORTEX_A78_ACTLR2_EL1 - orr x1, x1, #BIT(40) - msr CORTEX_A78_ACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a78_2395406_wa - -func check_errata_2395406 - /* Applies to r0p0, r0p1, r1p1, and r1p2 */ - mov x1, #CPU_REV(1, 2) - b cpu_rev_var_ls -endfunc check_errata_2395406 - -/* ---------------------------------------------------- - * Errata Workaround for Cortex A78 Errata 2742426. - * This applies to revisions r0p0, r1p0, r1p1 and r1p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ---------------------------------------------------- - */ -func errata_a78_2742426_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2742426 - cbz x0, 1f - +workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 /* Apply the workaround */ mrs x1, CORTEX_A78_ACTLR5_EL1 bic x1, x1, #BIT(56) orr x1, x1, #BIT(55) msr CORTEX_A78_ACTLR5_EL1, x1 +workaround_reset_end cortex_a78, ERRATUM(2742426) -1: - ret x17 -endfunc errata_a78_2742426_wa +check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) -func check_errata_2742426 - /* Applies to r0p0, r1p0, r1p1, r1p2 */ - mov x1, #CPU_REV(1, 2) - b cpu_rev_var_ls -endfunc check_errata_2742426 - -/* ---------------------------------------------------- - * Errata Workaround for Cortex-A78 Errata 2772019 - * This applies to revisions <= r1p2 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_a78_2772019_wa - mov x17, x30 - bl check_errata_2772019 - cbz x0, 1f - - +workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_a78_2772019_wa +workaround_runtime_end cortex_a78, ERRATUM(2772019) -func check_errata_2772019 - /* Applies to all revisions <= r1p2 */ - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_2772019 +check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) -/* ---------------------------------------------------- - * Errata Workaround for Cortex A78 Errata 2779479. - * This applies to revisions r0p0, r1p0, r1p1, and r1p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ---------------------------------------------------- - */ -func errata_a78_2779479_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2779479 - cbz x0, 1f +workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 + sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47) +workaround_reset_end cortex_a78, ERRATUM(2779479) - /* Apply the workaround */ - mrs x1, CORTEX_A78_ACTLR3_EL1 - orr x1, x1, #BIT(47) - msr CORTEX_A78_ACTLR3_EL1, x1 +check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) -1: - ret x17 -endfunc errata_a78_2779479_wa - -func check_errata_2779479 - /* Applies to r0p0, r1p0, r1p1, r1p2 */ - mov x1, #CPU_REV(1, 2) - b cpu_rev_var_ls -endfunc check_errata_2779479 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A78 - * ------------------------------------------------- +workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Cortex-X1 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. */ -func cortex_a78_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 + override_vector_table wa_cve_vbar_cortex_a78 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a78, CVE(2022, 23960) -#if ERRATA_A78_1688305 - mov x0, x18 - bl errata_a78_1688305_wa -#endif +check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if ERRATA_A78_1941498 - mov x0, x18 - bl errata_a78_1941498_wa -#endif - -#if ERRATA_A78_1951500 - mov x0, x18 - bl errata_a78_1951500_wa -#endif - -#if ERRATA_A78_1821534 - mov x0, x18 - bl errata_a78_1821534_wa -#endif - -#if ERRATA_A78_1952683 - mov x0, x18 - bl errata_a78_1952683_wa -#endif - -#if ERRATA_A78_2132060 - mov x0, x18 - bl errata_a78_2132060_wa -#endif - -#if ERRATA_A78_2242635 - mov x0, x18 - bl errata_a78_2242635_wa -#endif - -#if ERRATA_A78_2376745 - mov x0, x18 - bl errata_a78_2376745_wa -#endif - -#if ERRATA_A78_2395406 - mov x0, x18 - bl errata_a78_2395406_wa -#endif - -#if ERRATA_A78_2742426 - mov x0, x18 - bl errata_a78_2742426_wa -#endif - -#if ERRATA_A78_2779479 - mov x0, x18 - bl errata_a78_2779479_wa -#endif - +cpu_reset_func_start cortex_a78 #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT - msr actlr_el3, x0 + sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT - msr actlr_el2, x0 + sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT /* Enable group0 counters */ mov x0, #CORTEX_A78_AMU_GROUP0_MASK @@ -502,74 +183,22 @@ mov x0, #CORTEX_A78_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 #endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex-A78 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_a78 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc cortex_a78_reset_func +cpu_reset_func_end cortex_a78 /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- */ func cortex_a78_core_pwr_dwn - /* --------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------- - */ - mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT - msr CORTEX_A78_CPUPWRCTLR_EL1, x0 -#if ERRATA_A78_2772019 - mov x15, x30 - bl cpu_get_rev_var - bl errata_a78_2772019_wa - mov x30, x15 -#endif /* ERRATA_A78_2772019 */ + sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + + apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 + isb ret endfunc cortex_a78_core_pwr_dwn - /* - * Errata printing function for cortex_a78. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_a78_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A78_1688305, cortex_a78, 1688305 - report_errata ERRATA_A78_1941498, cortex_a78, 1941498 - report_errata ERRATA_A78_1951500, cortex_a78, 1951500 - report_errata ERRATA_A78_1821534, cortex_a78, 1821534 - report_errata ERRATA_A78_1952683, cortex_a78, 1952683 - report_errata ERRATA_A78_2132060, cortex_a78, 2132060 - report_errata ERRATA_A78_2242635, cortex_a78, 2242635 - report_errata ERRATA_A78_2376745, cortex_a78, 2376745 - report_errata ERRATA_A78_2395406, cortex_a78, 2395406 - report_errata ERRATA_A78_2742426, cortex_a78, 2742426 - report_errata ERRATA_A78_2772019, cortex_a78, 2772019 - report_errata ERRATA_A78_2779479, cortex_a78, 2779479 - report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a78_errata_report -#endif +errata_report_shim cortex_a78 /* --------------------------------------------- * This function provides cortex_a78 specific
diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index d56f835..d3a3e5d 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -1,6 +1,6 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. - * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,50 +22,13 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for A78 AE Erratum 1941500. - * This applies to revisions r0p0 and r0p1 of A78 AE. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_ae_1941500_wa - /* Compare x0 against revisions r0p0 - r0p1 */ - mov x17, x30 - bl check_errata_1941500 - cbz x0, 1f +workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500 + sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 +workaround_reset_end cortex_a78_ae, ERRATUM(1941500) - /* Set bit 8 in ECTLR_EL1 */ - mrs x0, CORTEX_A78_AE_CPUECTLR_EL1 - bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 - msr CORTEX_A78_AE_CPUECTLR_EL1, x0 - isb -1: - ret x17 -endfunc errata_a78_ae_1941500_wa +check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1) -func check_errata_1941500 - /* Applies to revisions r0p0 and r0p1. */ - mov x1, #CPU_REV(0, 0) - mov x2, #CPU_REV(0, 1) - b cpu_rev_var_range -endfunc check_errata_1941500 - -/* -------------------------------------------------- - * Errata Workaround for A78 AE Erratum 1951502. - * This applies to revisions r0p0 and r0p1 of A78 AE. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_ae_1951502_wa - /* Compare x0 against revisions r0p0 - r0p1 */ - mov x17, x30 - bl check_errata_1951502 - cbz x0, 1f - +workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502 msr S3_6_c15_c8_0, xzr ldr x0, =0x10E3900002 msr S3_6_c15_c8_2, x0 @@ -91,33 +54,11 @@ msr S3_6_c15_c8_3, x0 ldr x0, =0x2001003FF msr S3_6_c15_c8_1, x0 +workaround_reset_end cortex_a78_ae, ERRATUM(1951502) - isb -1: - ret x17 -endfunc errata_a78_ae_1951502_wa +check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1) -func check_errata_1951502 - /* Applies to revisions r0p0 and r0p1. */ - mov x1, #CPU_REV(0, 0) - mov x2, #CPU_REV(0, 1) - b cpu_rev_var_range -endfunc check_errata_1951502 - -/* -------------------------------------------------- - * Errata Workaround for A78 AE Erratum 2376748. - * This applies to revisions r0p0 and r0p1 of A78 AE. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_ae_2376748_wa - /* Compare x0 against revisions r0p0 - r0p1 */ - mov x17, x30 - bl check_errata_2376748 - cbz x0, 1f - +workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748 /* ------------------------------------------------------- * Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to * behave like PLD/PRFM LD and not cause invalidations to @@ -126,104 +67,42 @@ * that share data. * ------------------------------------------------------- */ - mrs x0, CORTEX_A78_AE_ACTLR2_EL1 - orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0 - msr CORTEX_A78_AE_ACTLR2_EL1, x0 - isb -1: - ret x17 -endfunc errata_a78_ae_2376748_wa + sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0 +workaround_reset_end cortex_a78_ae, ERRATUM(2376748) -func check_errata_2376748 - /* Applies to revisions r0p0 and r0p1. */ - mov x1, #CPU_REV(0, 0) - mov x2, #CPU_REV(0, 1) - b cpu_rev_var_range -endfunc check_errata_2376748 +check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 2) -/* -------------------------------------------------- - * Errata Workaround for A78 AE Erratum 2395408. - * This applies to revisions r0p0 and r0p1 of A78 AE. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78_ae_2395408_wa - /* Compare x0 against revisions r0p0 - r0p1 */ - mov x17, x30 - bl check_errata_2395408 - cbz x0, 1f - +workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408 /* -------------------------------------------------------- * Disable folding of demand requests into older prefetches * with L2 miss requests outstanding by setting the * CPUACTLR2_EL1[40] to 1. * -------------------------------------------------------- */ - mrs x0, CORTEX_A78_AE_ACTLR2_EL1 - orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40 - msr CORTEX_A78_AE_ACTLR2_EL1, x0 - isb -1: - ret x17 -endfunc errata_a78_ae_2395408_wa + sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40 +workaround_reset_end cortex_a78_ae, ERRATUM(2395408) -func check_errata_2395408 - /* Applies to revisions r0p0 and r0p1. */ - mov x1, #CPU_REV(0, 0) - mov x2, #CPU_REV(0, 1) - b cpu_rev_var_range -endfunc check_errata_2395408 +check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1) -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A78-AE - * ------------------------------------------------- +workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Cortex-A78AE generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. */ -func cortex_a78_ae_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 + override_vector_table wa_cve_vbar_cortex_a78_ae +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a78_ae, CVE(2022, 23960) -#if ERRATA_A78_AE_1941500 - mov x0, x18 - bl errata_a78_ae_1941500_wa -#endif +check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -#if ERRATA_A78_AE_1951502 - mov x0, x18 - bl errata_a78_ae_1951502_wa -#endif - -#if ERRATA_A78_AE_2376748 - mov x0, x18 - bl errata_a78_ae_2376748_wa -#endif - -#if ERRATA_A78_AE_2395408 - mov x0, x18 - bl errata_a78_ae_2395408_wa -#endif - +cpu_reset_func_start cortex_a78_ae #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT - msr actlr_el3, x0 + sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT - msr actlr_el2, x0 + sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT /* Enable group0 counters */ mov x0, #CORTEX_A78_AMU_GROUP0_MASK @@ -233,19 +112,7 @@ mov x0, #CORTEX_A78_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 #endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex-A78AE generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_a78_ae - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc cortex_a78_ae_reset_func +cpu_reset_func_end cortex_a78_ae /* ------------------------------------------------------- * HW will do the cache maintenance while powering down @@ -256,37 +123,12 @@ * Enable CPU power down bit in power control register * ------------------------------------------------------- */ - mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT - msr CORTEX_A78_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT isb ret endfunc cortex_a78_ae_core_pwr_dwn - /* - * Errata printing function for cortex_a78_ae. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_a78_ae_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500 - report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 - report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748 - report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408 - report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a78_ae_errata_report -#endif +errata_report_shim cortex_a78_ae /* ------------------------------------------------------- * This function provides cortex_a78_ae specific
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index fddd24f..d19c693 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -17,174 +17,37 @@ #error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" #endif -/* -------------------------------------------------- - * Errata Workaround for A78C Erratum 1827430. - * This applies to revision r0p0 of the Cortex A78C - * processor and is fixed in r0p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78c_1827430_wa - mov x17, x30 - bl check_errata_1827430 - cbz x0, 1f - - /* Disable allocation of splintered pages in the L2 TLB */ - mrs x1, CORTEX_A78C_CPUECTLR_EL1 - orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN - msr CORTEX_A78C_CPUECTLR_EL1, x1 -1: - ret x17 -endfunc errata_a78c_1827430_wa - -func check_errata_1827430 - /* Applies to revision r0p0 only */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_1827430 - -/* -------------------------------------------------- - * Errata Workaround for A78C Erratum 1827440. - * This applies to revision r0p0 of the Cortex A78C - * processor and is fixed in r0p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78c_1827440_wa - mov x17, x30 - bl check_errata_1827440 - cbz x0, 1f - - /* Force Atomic Store to WB memory be done in L1 data cache */ - mrs x1, CORTEX_A78C_CPUACTLR2_EL1 - orr x1, x1, #BIT(2) - msr CORTEX_A78C_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a78c_1827440_wa - -func check_errata_1827440 - /* Applies to revision r0p0 only */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_1827440 - -/* -------------------------------------------------- - * Errata Workaround for Cortex A78C Erratum 2376749. - * This applies to revision r0p1 and r0p2 of the A78C - * and is currently open. It is a Cat B erratum. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x4, x17 - * -------------------------------------------------- - */ -func errata_a78c_2376749_wa - /* Check revision */ - mov x17, x30 - bl check_errata_2376749 - cbz x0, 1f - /* Set CPUACTLR2_EL1[0] to 1. */ - mrs x1, CORTEX_A78C_CPUACTLR2_EL1 - orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 - msr CORTEX_A78C_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a78c_2376749_wa - -func check_errata_2376749 - /* Applies to r0p1 and r0p2*/ - mov x1, #0x01 - mov x2, #0x02 - b cpu_rev_var_range -endfunc check_errata_2376749 - -/* -------------------------------------------------- - * Errata Workaround for Cortex A78C Erratum 2395411. - * This applies to revision r0p1 and r0p2 of the A78C - * and is currently open. It is a Cat B erratum. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x4, x17 - * -------------------------------------------------- - */ -func errata_a78c_2395411_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2395411 - cbz x0, 1f - - /* Set CPUACTRL2_EL1[40] to 1. */ - mrs x1, CORTEX_A78C_CPUACTLR2_EL1 - orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 - msr CORTEX_A78C_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_a78c_2395411_wa - -func check_errata_2395411 - /* Applies to r0p1 and r0p2 */ - mov x1, #0x01 - mov x2, #0x02 - b cpu_rev_var_range -endfunc check_errata_2395411 - #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for A78C Erratum 2132064. - * This applies to revisions r0p1 and r0p2 of A78C - * and is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_a78c_2132064_wa - /* Compare x0 against revisions r0p0 - r0p1 */ - mov x17, x30 - bl check_errata_2132064 - cbz x0, 1f +workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 + /* Disable allocation of splintered pages in the L2 TLB */ + sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN +workaround_reset_end cortex_a78c, ERRATUM(1827430) +check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) + +workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 + /* Force Atomic Store to WB memory be done in L1 data cache */ + sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) +workaround_reset_end cortex_a78c, ERRATUM(1827440) + +check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) + +workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 /* -------------------------------------------------------- * Place the data prefetcher in the most conservative mode * to reduce prefetches by writing the following bits to * the value indicated: ecltr[7:6], PF_MODE = 2'b11 * -------------------------------------------------------- */ - mrs x0, CORTEX_A78C_CPUECTLR_EL1 - orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 - orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 - msr CORTEX_A78C_CPUECTLR_EL1, x0 - isb -1: - ret x17 -endfunc errata_a78c_2132064_wa + sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) +workaround_reset_end cortex_a78c, ERRATUM(2132064) -func check_errata_2132064 - /* Applies to revisions r0p1 and r0p2. */ - mov x1, #CPU_REV(0, 1) - mov x2, #CPU_REV(0, 2) - b cpu_rev_var_range -endfunc check_errata_2132064 +check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) -/* ---------------------------------------------------------- - * Errata Workaround for A78C Erratum 2242638. - * This applies to revisions r0p1 and r0p2 of the Cortex A78C - * processor and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------------- - */ -func errata_a78c_2242638_wa - /* Compare x0 against revisions r0p1 - r0p2 */ - mov x17, x30 - bl check_errata_2242638 - cbz x0, 1f - +workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 ldr x0, =0x5 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 ldr x0, =0x10F600E000 @@ -193,139 +56,51 @@ msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 ldr x0, =0x80000000003FF msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 +workaround_reset_end cortex_a78c, ERRATUM(2242638) - isb -1: - ret x17 -endfunc errata_a78c_2242638_wa +check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) -func check_errata_2242638 - /* Applies to revisions r0p1-r0p2. */ - mov x1, #CPU_REV(0, 1) - mov x2, #CPU_REV(0, 2) - b cpu_rev_var_range -endfunc check_errata_2242638 +workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 + sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 +workaround_reset_end cortex_a78c, ERRATUM(2376749) -/* ---------------------------------------------------------------- - * Errata Workaround for A78C Erratum 2772121. - * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C - * processor and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------------------- - */ -func errata_a78c_2772121_wa - mov x17, x30 - bl check_errata_2772121 - cbz x0, 1f +check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) +workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 + sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 +workaround_reset_end cortex_a78c, ERRATUM(2395411) + +check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) + +workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_a78c_2772121_wa +workaround_runtime_end cortex_a78c, ERRATUM(2772121) -func check_errata_2772121 - /* Applies to all revisions <= r0p2 */ - mov x1, #0x02 - b cpu_rev_var_ls -endfunc check_errata_2772121 +check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) -/* -------------------------------------------------- - * Errata Workaround for Cortex A78C Errata 2779484. - * This applies to revisions r0p1 and r0p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_a78c_2779484_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2779484 - cbz x0, 1f +workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 + sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) +workaround_reset_end cortex_a78c, ERRATUM(2779484) - /* Apply the workaround */ - mrs x1, CORTEX_A78C_ACTLR3_EL1 - orr x1, x1, #BIT(47) - msr CORTEX_A78C_ACTLR3_EL1, x1 +check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) -1: - ret x17 -endfunc errata_a78c_2779484_wa +check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -func check_errata_2779484 - /* Applies to r0p1 and r0p2*/ - mov x1, #0x01 - mov x2, #0x02 - b cpu_rev_var_range -endfunc check_errata_2779484 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-A78C - * ------------------------------------------------- - */ -func cortex_a78c_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_A78C_1827430 - mov x0, x18 - bl errata_a78c_1827430_wa -#endif - -#if ERRATA_A78C_1827440 - mov x0, x18 - bl errata_a78c_1827440_wa -#endif - -#if ERRATA_A78C_2132064 - mov x0, x18 - bl errata_a78c_2132064_wa -#endif - -#if ERRATA_A78C_2242638 - mov x0, x18 - bl errata_a78c_2242638_wa -#endif - -#if ERRATA_A78C_2376749 - mov x0, x18 - bl errata_a78c_2376749_wa -#endif - -#if ERRATA_A78C_2395411 - mov x0, x18 - bl errata_a78c_2395411_wa -#endif - -#if ERRATA_A78C_2779484 - mov x0, x18 - bl errata_a78c_2779484_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 /* * The Cortex-A78c generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_cortex_a78c - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + override_vector_table wa_cve_vbar_cortex_a78c +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_a78c, CVE(2022, 23960) - isb - ret x19 -endfunc cortex_a78c_reset_func +cpu_reset_func_start cortex_a78c +cpu_reset_func_end cortex_a78c + +errata_report_shim cortex_a78c /* ---------------------------------------------------- * HW will do the cache maintenance while powering down @@ -336,48 +111,14 @@ * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT - msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 -#if ERRATA_A78C_2772121 - mov x15, x30 - bl cpu_get_rev_var - bl errata_a78c_2772121_wa - mov x30, x15 -#endif /* ERRATA_A78C_2772121 */ + sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + + apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 + isb ret endfunc cortex_a78c_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex A78C. Must follow AAPCS. - */ -func cortex_a78c_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430 - report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440 - report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 - report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 - report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 - report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 - report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121 - report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484 - report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_a78c_errata_report -#endif - /* --------------------------------------------- * This function provides cortex_a78c specific * register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_blackhawk.S b/lib/cpus/aarch64/cortex_blackhawk.S index 8dac4e9..b7b7a2d 100644 --- a/lib/cpus/aarch64/cortex_blackhawk.S +++ b/lib/cpus/aarch64/cortex_blackhawk.S
@@ -21,12 +21,10 @@ #error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -func cortex_blackhawk_reset_func +cpu_reset_func_start cortex_blackhawk /* Disable speculative loads */ msr SSBS, xzr - isb - ret -endfunc cortex_blackhawk_reset_func +cpu_reset_func_end cortex_blackhawk /* ---------------------------------------------------- * HW will do the cache maintenance while powering down @@ -37,21 +35,12 @@ * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT isb ret endfunc cortex_blackhawk_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Blackhawk. Must follow AAPCS. - */ -func cortex_blackhawk_errata_report - ret -endfunc cortex_blackhawk_errata_report -#endif +errata_report_shim cortex_blackhawk /* --------------------------------------------- * This function provides Cortex Blackhawk specific
diff --git a/lib/cpus/aarch64/cortex_chaberton.S b/lib/cpus/aarch64/cortex_chaberton.S index 2c47bd3..596fe4a 100644 --- a/lib/cpus/aarch64/cortex_chaberton.S +++ b/lib/cpus/aarch64/cortex_chaberton.S
@@ -21,12 +21,10 @@ #error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif -func cortex_chaberton_reset_func +cpu_reset_func_start cortex_chaberton /* Disable speculative loads */ msr SSBS, xzr - isb - ret -endfunc cortex_chaberton_reset_func +cpu_reset_func_end cortex_chaberton /* ---------------------------------------------------- * HW will do the cache maintenance while powering down @@ -37,21 +35,12 @@ * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_CHABERTON_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_CHABERTON_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT isb ret endfunc cortex_chaberton_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Chaberton. Must follow AAPCS. - */ -func cortex_chaberton_errata_report - ret -endfunc cortex_chaberton_errata_report -#endif +errata_report_shim cortex_chaberton /* --------------------------------------------- * This function provides Cortex Chaberton specific
diff --git a/lib/cpus/aarch64/cortex_gelas.S b/lib/cpus/aarch64/cortex_gelas.S new file mode 100644 index 0000000..dc704f2 --- /dev/null +++ b/lib/cpus/aarch64/cortex_gelas.S
@@ -0,0 +1,84 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_gelas.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Gelas must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +cpu_reset_func_start cortex_gelas + /* ---------------------------------------------------- + * Disable speculative loads + * ---------------------------------------------------- + */ + msr SSBS, xzr +cpu_reset_func_end cortex_gelas + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_gelas_core_pwr_dwn +#if ENABLE_SME_FOR_NS + /* --------------------------------------------------- + * Disable SME if enabled and supported + * --------------------------------------------------- + */ + mrs x0, ID_AA64PFR1_EL1 + ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ + #ID_AA64PFR1_EL1_SME_WIDTH + cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED + b.eq 1f + msr CORTEX_GELAS_SVCRSM, xzr + msr CORTEX_GELAS_SVCRZA, xzr +1: +#endif + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set CORTEX_GELAS_CPUPWRCTLR_EL1, \ + CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb + ret +endfunc cortex_gelas_core_pwr_dwn + +errata_report_shim cortex_gelas + + /* --------------------------------------------- + * This function provides Gelas specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_gelas_regs, "aS" +cortex_gelas_regs: /* The ASCII list of register names to be reported */ + .asciz "imp_cpuectlr_el1", "" + +func cortex_gelas_cpu_reg_dump + adr x6, cortex_gelas_regs + mrs x8, CORTEX_GELAS_IMP_CPUECTLR_EL1 + ret +endfunc cortex_gelas_cpu_reg_dump + +declare_cpu_ops cortex_gelas, CORTEX_GELAS_MIDR, \ + cortex_gelas_reset_func, \ + cortex_gelas_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hayes.S b/lib/cpus/aarch64/cortex_hayes.S deleted file mode 100644 index 445a691..0000000 --- a/lib/cpus/aarch64/cortex_hayes.S +++ /dev/null
@@ -1,77 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> -#include <common/bl_common.h> -#include <cortex_hayes.h> -#include <cpu_macros.S> -#include <plat_macros.S> - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Hayes must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Hayes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_hayes_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_HAYES_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_HAYES_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_hayes_core_pwr_dwn - - /* - * Errata printing function for Cortex Hayes. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_hayes_errata_report - ret -endfunc cortex_hayes_errata_report -#endif - -func cortex_hayes_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - isb - ret -endfunc cortex_hayes_reset_func - - /* --------------------------------------------- - * This function provides Cortex Hayes specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_hayes_regs, "aS" -cortex_hayes_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_hayes_cpu_reg_dump - adr x6, cortex_hayes_regs - mrs x8, CORTEX_HAYES_CPUECTLR_EL1 - ret -endfunc cortex_hayes_cpu_reg_dump - -declare_cpu_ops cortex_hayes, CORTEX_HAYES_MIDR, \ - cortex_hayes_reset_func, \ - cortex_hayes_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hunter.S b/lib/cpus/aarch64/cortex_hunter.S deleted file mode 100644 index 973637e..0000000 --- a/lib/cpus/aarch64/cortex_hunter.S +++ /dev/null
@@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> -#include <common/bl_common.h> -#include <cortex_hunter.h> -#include <cpu_macros.S> -#include <plat_macros.S> -#include "wa_cve_2022_23960_bhb_vector.S" - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - -#if WORKAROUND_CVE_2022_23960 - wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_BHB_LOOP_COUNT, cortex_hunter -#endif /* WORKAROUND_CVE_2022_23960 */ - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func cortex_hunter_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex Hunter generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_hunter - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret -endfunc cortex_hunter_reset_func - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_hunter_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_hunter_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Hunter. Must follow AAPCS. - */ -func cortex_hunter_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, cortex_hunter, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_hunter_errata_report -#endif - - /* --------------------------------------------- - * This function provides Cortex Hunter-specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_hunter_regs, "aS" -cortex_hunter_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_hunter_cpu_reg_dump - adr x6, cortex_hunter_regs - mrs x8, CORTEX_HUNTER_CPUECTLR_EL1 - ret -endfunc cortex_hunter_cpu_reg_dump - -declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \ - cortex_hunter_reset_func, \ - cortex_hunter_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_hunter_elp_arm.S b/lib/cpus/aarch64/cortex_hunter_elp_arm.S deleted file mode 100644 index 5f86d4e..0000000 --- a/lib/cpus/aarch64/cortex_hunter_elp_arm.S +++ /dev/null
@@ -1,113 +0,0 @@ -/* - * Copyright (c) 2022, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> -#include <common/bl_common.h> -#include <cortex_hunter_elp_arm.h> -#include <cpu_macros.S> -#include <plat_macros.S> -#include "wa_cve_2022_23960_bhb_vector.S" - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Hunter ELP must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Hunter ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - -#if WORKAROUND_CVE_2022_23960 - wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_ELP_ARM_BHB_LOOP_COUNT, cortex_hunter_elp_arm -#endif /* WORKAROUND_CVE_2022_23960 */ - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func cortex_hunter_elp_arm_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex Hunter ELP generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_hunter_elp_arm - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret -endfunc cortex_hunter_elp_arm_reset_func - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_hunter_elp_arm_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_HUNTER_ELP_ARM_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_hunter_elp_arm_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Hunter ELP. Must follow AAPCS. - */ -func cortex_hunter_elp_arm_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, cortex_hunter_elp_arm, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_hunter_elp_arm_errata_report -#endif - - /* --------------------------------------------- - * This function provides Cortex Hunter ELP-specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_hunter_elp_arm_regs, "aS" -cortex_hunter_elp_arm_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_hunter_elp_arm_cpu_reg_dump - adr x6, cortex_hunter_elp_arm_regs - mrs x8, CORTEX_HUNTER_ELP_ARM_CPUECTLR_EL1 - ret -endfunc cortex_hunter_elp_arm_cpu_reg_dump - -declare_cpu_ops cortex_hunter_elp_arm, CORTEX_HUNTER_ELP_ARM_MIDR, \ - cortex_hunter_elp_arm_reset_func, \ - cortex_hunter_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S index de65365..42634f1 100644 --- a/lib/cpus/aarch64/cortex_x1.S +++ b/lib/cpus/aarch64/cortex_x1.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Google LLC. All rights reserved. + * Copyright (c) 2022-2023, Google LLC. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,175 +23,50 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1 #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for X1 Erratum 1821534. - * This applies to revision r0p0 and r1p0 of X1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_x1_1821534_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1821534 - cbz x0, 1f - mrs x1, CORTEX_X1_ACTLR2_EL1 - orr x1, x1, #BIT(2) - msr CORTEX_X1_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_x1_1821534_wa +workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305 + sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1) +workaround_reset_end cortex_x1, ERRATUM(1688305) -func check_errata_1821534 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1821534 +check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0) -/* -------------------------------------------------- - * Errata Workaround for X1 Erratum 1688305. - * This applies to revision r0p0 and r1p0 of X1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_x1_1688305_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1688305 - cbz x0, 1f - mrs x0, CORTEX_X1_ACTLR2_EL1 - orr x0, x0, #BIT(1) - msr CORTEX_X1_ACTLR2_EL1, x0 - isb +workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534 + sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2) +workaround_reset_end cortex_x1, ERRATUM(1821534) -1: - ret x17 -endfunc errata_x1_1688305_wa +check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0) -func check_errata_1688305 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1688305 +workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429 + sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53) +workaround_reset_end cortex_x1, ERRATUM(1827429) -/* -------------------------------------------------- - * Errata Workaround for X1 Erratum 1827429. - * This applies to revision r0p0 and r1p0 of X1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_x1_1827429_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1827429 - cbz x0, 1f - mrs x0, CORTEX_X1_CPUECTLR_EL1 - orr x0, x0, #BIT(53) - msr CORTEX_X1_CPUECTLR_EL1, x0 - isb +check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0) -1: - ret x17 -endfunc errata_x1_1827429_wa +check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 -func check_errata_1827429 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1827429 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - - /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-X1. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func cortex_x1_reset_func - mov x19, x30 - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_X1_1821534 - mov x0, x18 - bl errata_x1_1821534_wa -#endif - -#if ERRATA_X1_1688305 - mov x0, x18 - bl errata_x1_1688305_wa -#endif - -#if ERRATA_X1_1827429 - mov x0, x18 - bl errata_x1_1827429_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 +workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 /* * The Cortex-X1 generic vectors are overridden to apply errata * mitigation on exception entry from lower ELs. */ - adr x0, wa_cve_vbar_cortex_x1 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ + override_vector_table wa_cve_vbar_cortex_x1 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_x1, CVE(2022, 23960) - isb - ret x19 -endfunc cortex_x1_reset_func +cpu_reset_func_start cortex_x1 +cpu_reset_func_end cortex_x1 /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- */ func cortex_x1_core_pwr_dwn - /* --------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------- - */ - mrs x0, CORTEX_X1_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK - msr CORTEX_X1_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK isb ret endfunc cortex_x1_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Cortex X1. Must follow AAPCS. - */ -func cortex_x1_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_X1_1821534, cortex_x1, 1821534 - report_errata ERRATA_X1_1688305, cortex_x1, 1688305 - report_errata ERRATA_X1_1827429, cortex_x1, 1827429 - report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_x1_errata_report -#endif +errata_report_shim cortex_x1 /* --------------------------------------------- * This function provides Cortex X1 specific
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 497bd52..258288c 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S
@@ -26,20 +26,7 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2 #endif /* WORKAROUND_CVE_2022_23960 */ - /* -------------------------------------------------- - * Errata Workaround for Cortex X2 Errata #2002765. - * This applies to revisions r0p0, r1p0, and r2p0 and - * is open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_x2_2002765_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2002765 - cbz x0, 1f - +workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765 ldr x0, =0x6 msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ ldr x0, =0xF3A08002 @@ -48,119 +35,24 @@ msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ ldr x0, =0x40000001003ff msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ - isb +workaround_reset_end cortex_x2, ERRATUM(2002765) -1: - ret x17 -endfunc errata_cortex_x2_2002765_wa +check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0) -func check_errata_2002765 - /* Applies to r0p0 - r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2002765 +workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096 + sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT +workaround_reset_end cortex_x2, ERRATUM(2017096) - /* -------------------------------------------------- - * Errata Workaround for Cortex X2 Errata #2058056. - * This applies to revisions r0p0, r1p0, and r2p0 and - * is open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_cortex_x2_2058056_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2058056 - cbz x0, 1f +check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0) - mrs x1, CORTEX_X2_CPUECTLR2_EL1 - mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV - bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH - msr CORTEX_X2_CPUECTLR2_EL1, x1 +workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056 + sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end cortex_x2, ERRATUM(2058056) -1: - ret x17 -endfunc errata_cortex_x2_2058056_wa +check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1) -func check_errata_2058056 - /* Applies to r0p0 - r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2058056 - - /* -------------------------------------------------- - * Errata Workaround for Cortex X2 Errata #2083908. - * This applies to revision r2p0 and is open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x2, x17 - * -------------------------------------------------- - */ -func errata_cortex_x2_2083908_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2083908 - cbz x0, 1f - - /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ - mrs x1, CORTEX_X2_CPUACTLR5_EL1 - orr x1, x1, #BIT(13) - msr CORTEX_X2_CPUACTLR5_EL1, x1 - -1: - ret x17 -endfunc errata_cortex_x2_2083908_wa - -func check_errata_2083908 - /* Applies to r2p0 */ - mov x1, #0x20 - mov x2, #0x20 - b cpu_rev_var_range -endfunc check_errata_2083908 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-X2 Errata 2017096. - * This applies only to revisions r0p0, r1p0 and r2p0 - * and is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_x2_2017096_wa - /* Compare x0 against revision r0p0 to r2p0 */ - mov x17, x30 - bl check_errata_2017096 - cbz x0, 1f - mrs x1, CORTEX_X2_CPUECTLR_EL1 - orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT - msr CORTEX_X2_CPUECTLR_EL1, x1 - -1: - ret x17 -endfunc errata_x2_2017096_wa - -func check_errata_2017096 - /* Applies to r0p0, r1p0, r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2017096 - - /* -------------------------------------------------- - * Errata Workaround for Cortex-X2 Errata 2081180. - * This applies to revision r0p0, r1p0 and r2p0 - * and is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_x2_2081180_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2081180 - cbz x0, 1f - +workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180 /* Apply instruction patching sequence */ ldr x0, =0x3 msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 @@ -178,34 +70,26 @@ msr CORTEX_X2_IMP_CPUPMR_EL3, x0 ldr x0, =0x10002001003F3 msr CORTEX_X2_IMP_CPUPCR_EL3, x0 - isb -1: - ret x17 -endfunc errata_x2_2081180_wa +workaround_reset_end cortex_x2, ERRATUM(2081180) -func check_errata_2081180 - /* Applies to r0p0, r1p0 and r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2081180 +check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0) - /* -------------------------------------------------- - * Errata Workaround for Cortex X2 Errata 2216384. - * This applies to revisions r0p0, r1p0, and r2p0 - * and is fixed in r2p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * -------------------------------------------------- - */ -func errata_x2_2216384_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2216384 - cbz x0, 1f +workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908 + /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ + sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13) +workaround_reset_end cortex_x2, ERRATUM(2083908) - mrs x1, CORTEX_X2_CPUACTLR5_EL1 - orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 - msr CORTEX_X2_CPUACTLR5_EL1, x1 +check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0) + +workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715 + /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ + sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22 +workaround_reset_end cortex_x2, ERRATUM(2147715) + +check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0) + +workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384 + sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 /* Apply instruction patching sequence */ ldr x0, =0x5 @@ -216,138 +100,60 @@ msr CORTEX_X2_IMP_CPUPMR_EL3, x0 ldr x0, =0x80000000003FF msr CORTEX_X2_IMP_CPUPCR_EL3, x0 - isb +workaround_reset_end cortex_x2, ERRATUM(2216384) -1: - ret x17 -endfunc errata_x2_2216384_wa +check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0) -func check_errata_2216384 - /* Applies to r0p0 - r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2216384 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - - /* --------------------------------------------------------- - * Errata Workaround for Cortex-X2 Errata 2147715. - * This applies only to revisions r2p0 and is fixed in r2p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * --------------------------------------------------------- - */ -func errata_x2_2147715_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_2147715 - cbz x0, 1f - - /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */ - mrs x1, CORTEX_X2_CPUACTLR_EL1 - orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22 - msr CORTEX_X2_CPUACTLR_EL1, x1 - -1: - ret x17 -endfunc errata_x2_2147715_wa - -func check_errata_2147715 - /* Applies to r2p0 */ - mov x1, #0x20 - mov x2, #0x20 - b cpu_rev_var_range -endfunc check_errata_2147715 - - /* --------------------------------------------------------------- - * Errata Workaround for Cortex-X2 Erratum 2282622. - * This applies to revision r0p0, r1p0, r2p0 and r2p1. - * It is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1, x17 - * --------------------------------------------------------------- - */ -func errata_x2_2282622_wa - /* Compare x0 against revision r2p1 */ - mov x17, x30 - bl check_errata_2282622 - cbz x0, 1f - +workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622 /* Apply the workaround */ - mrs x1, CORTEX_X2_CPUACTLR2_EL1 - orr x1, x1, #BIT(0) - msr CORTEX_X2_CPUACTLR2_EL1, x1 + sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0) +workaround_reset_end cortex_x2, ERRATUM(2282622) -1: - ret x17 -endfunc errata_x2_2282622_wa +check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1) -func check_errata_2282622 - /* Applies to r0p0, r1p0, r2p0 and r2p1 */ - mov x1, #0x21 - b cpu_rev_var_ls -endfunc check_errata_2282622 - - /* ------------------------------------------------------- - * Errata Workaround for Cortex-X2 Erratum 2371105. - * This applies to revisions <= r2p0 and is fixed in r2p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ------------------------------------------------------- - */ -func errata_x2_2371105_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2371105 - cbz x0, 1f - +workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105 /* Set bit 40 in CPUACTLR2_EL1 */ - mrs x1, CORTEX_X2_CPUACTLR2_EL1 - orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40 - msr CORTEX_X2_CPUACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_x2_2371105_wa + sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40 +workaround_reset_end cortex_x2, ERRATUM(2371105) -func check_errata_2371105 - /* Applies to <= r2p0. */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_2371105 +check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0) - /* ---------------------------------------------------- - * Errata Workaround for Cortex-X2 Errata #2768515 - * This applies to revisions <= r2p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_x2_2768515_wa - mov x17, x30 - bl check_errata_2768515 - cbz x0, 1f +workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55) + sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56) +workaround_reset_end cortex_x2, ERRATUM(2742423) +check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1) + +workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_x2_2768515_wa +workaround_reset_end cortex_x2, ERRATUM(2768515) -func check_errata_2768515 - /* Applies to all revisions <= r2p1 */ - mov x1, #0x21 - b cpu_rev_var_ls -endfunc check_errata_2768515 +check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1) + +workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Cortex-X2 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_cortex_x2 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_x2, CVE(2022, 23960) + +check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + +/* + * ERRATA_DSU_2313941 : + * The errata is defined in dsu_helpers.S but applies to cortex_x2 + * as well. Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941 +.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa +add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET /* ---------------------------------------------------- * HW will do the cache maintenance while powering down @@ -358,122 +164,24 @@ * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_X2_CPUPWRCTLR_EL1, x0 + sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + #if ERRATA_X2_2768515 mov x15, x30 bl cpu_get_rev_var - bl errata_x2_2768515_wa + bl erratum_cortex_x2_2768515_wa mov x30, x15 #endif /* ERRATA_X2_2768515 */ isb ret endfunc cortex_x2_core_pwr_dwn - /* - * Errata printing function for Cortex X2. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_x2_errata_report - stp x8, x30, [sp, #-16]! +errata_report_shim cortex_x2 - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_X2_2002765, cortex_x2, 2002765 - report_errata ERRATA_X2_2017096, cortex_x2, 2017096 - report_errata ERRATA_X2_2058056, cortex_x2, 2058056 - report_errata ERRATA_X2_2081180, cortex_x2, 2081180 - report_errata ERRATA_X2_2083908, cortex_x2, 2083908 - report_errata ERRATA_X2_2147715, cortex_x2, 2147715 - report_errata ERRATA_X2_2216384, cortex_x2, 2216384 - report_errata ERRATA_X2_2282622, cortex_x2, 2282622 - report_errata ERRATA_X2_2371105, cortex_x2, 2371105 - report_errata ERRATA_X2_2768515, cortex_x2, 2768515 - report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 - report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941 - - ldp x8, x30, [sp], #16 - ret -endfunc cortex_x2_errata_report -#endif - -func cortex_x2_reset_func - mov x19, x30 - +cpu_reset_func_start cortex_x2 /* Disable speculative loads */ msr SSBS, xzr - - /* Get the CPU revision and stash it in x18. */ - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_DSU_2313941 - bl errata_dsu_2313941_wa -#endif - -#if ERRATA_X2_2002765 - mov x0, x18 - bl errata_cortex_x2_2002765_wa -#endif - -#if ERRATA_X2_2058056 - mov x0, x18 - bl errata_cortex_x2_2058056_wa -#endif - -#if ERRATA_X2_2083908 - mov x0, x18 - bl errata_cortex_x2_2083908_wa -#endif - -#if ERRATA_X2_2017096 - mov x0, x18 - bl errata_x2_2017096_wa -#endif - -#if ERRATA_X2_2081180 - mov x0, x18 - bl errata_x2_2081180_wa -#endif - -#if ERRATA_X2_2216384 - mov x0, x18 - bl errata_x2_2216384_wa -#endif - -#if ERRATA_X2_2147715 - mov x0, x18 - bl errata_x2_2147715_wa -#endif - -#if ERRATA_X2_2282622 - mov x0, x18 - bl errata_x2_2282622_wa -#endif - -#if ERRATA_X2_2371105 - mov x0, x18 - bl errata_x2_2371105_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex-X2 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_x2 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc cortex_x2_reset_func +cpu_reset_func_end cortex_x2 /* --------------------------------------------- * This function provides Cortex X2 specific
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S index f104b48..0cb3b97 100644 --- a/lib/cpus/aarch64/cortex_x3.S +++ b/lib/cpus/aarch64/cortex_x3.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,141 +26,66 @@ wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 #endif /* WORKAROUND_CVE_2022_23960 */ - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_x3_core_pwr_dwn -#if ERRATA_X3_2313909 - mov x15, x30 - bl cpu_get_rev_var - bl errata_cortex_x3_2313909_wa - mov x30, x15 -#endif /* ERRATA_X3_2313909 */ +workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 + sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end cortex_x3, ERRATUM(2070301) - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_X3_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_x3_core_pwr_dwn +check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 +workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 + sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 +workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB -func cortex_x3_reset_func - mov x19, x30 - /* Disable speculative loads */ - msr SSBS, xzr +check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Cortex-X3 generic vectors are overridden to apply - * errata mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_cortex_x3 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - bl cpu_get_rev_var - -#if ERRATA_X3_2615812 - bl errata_cortex_x3_2615812_wa -#endif /* ERRATA_X3_2615812 */ - - isb - ret x19 -endfunc cortex_x3_reset_func - -/* ---------------------------------------------------------------------- - * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request. - * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ---------------------------------------------------------------------- - */ -func errata_cortex_x3_2313909_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2313909 - cbz x0, 1f - - /* Set bit 36 in ACTLR2_EL1 */ - mrs x1, CORTEX_X3_CPUACTLR2_EL1 - orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36 - msr CORTEX_X3_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_cortex_x3_2313909_wa - -func check_errata_2313909 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_2313909 - -/* ---------------------------------------------------------------------- - * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on. - * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ---------------------------------------------------------------------- - */ -func errata_cortex_x3_2615812_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2615812 - cbz x0, 1f - +workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 /* Disable retention control for WFI and WFE. */ mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 -1: - ret x17 -endfunc errata_cortex_x3_2615812_wa +workaround_reset_end cortex_x3, ERRATUM(2615812) -func check_errata_2615812 - /* Applies to r1p1 and below. */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2615812 +check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) -#if REPORT_ERRATA - /* - * Errata printing function for Cortex-X3. Must follow AAPCS. +workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 + sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 +workaround_reset_end cortex_x3, ERRATUM(2742421) + +check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) + +workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + override_vector_table wa_cve_vbar_cortex_x3 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_x3, CVE(2022, 23960) + +check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + +cpu_reset_func_start cortex_x3 + /* Disable speculative loads */ + msr SSBS, xzr +cpu_reset_func_end cortex_x3 + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- */ -func cortex_x3_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. +func cortex_x3_core_pwr_dwn +apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- */ - report_errata ERRATA_X3_2313909, cortex_x3, 2313909 - report_errata ERRATA_X3_2615812, cortex_x3, 2615812 - report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960 - - ldp x8, x30, [sp], #16 + sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb ret -endfunc cortex_x3_errata_report -#endif +endfunc cortex_x3_core_pwr_dwn + +errata_report_shim cortex_x3 /* --------------------------------------------- * This function provides Cortex-X3-
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S new file mode 100644 index 0000000..7619f9c --- /dev/null +++ b/lib/cpus/aarch64/cortex_x4.S
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_x4.h> +#include <cpu_macros.S> +#include <plat_macros.S> +#include "wa_cve_2022_23960_bhb_vector.S" + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +#if WORKAROUND_CVE_2022_23960 + wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4 +#endif /* WORKAROUND_CVE_2022_23960 */ + +workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Cortex X4 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_cortex_x4 +#endif /* IMAGE_BL31 */ +workaround_reset_end cortex_x4, CVE(2022, 23960) + +check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + +cpu_reset_func_start cortex_x4 + /* Disable speculative loads */ + msr SSBS, xzr +cpu_reset_func_end cortex_x4 + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_x4_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb + ret +endfunc cortex_x4_core_pwr_dwn + +errata_report_shim cortex_x4 + + /* --------------------------------------------- + * This function provides Cortex X4-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_x4_regs, "aS" +cortex_x4_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_x4_cpu_reg_dump + adr x6, cortex_x4_regs + mrs x8, CORTEX_X4_CPUECTLR_EL1 + ret +endfunc cortex_x4_cpu_reg_dump + +declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \ + cortex_x4_reset_func, \ + cortex_x4_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 0a03e38..1ae3180 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -10,7 +10,8 @@ #include <common/bl_common.h> #include <common/debug.h> #include <cpu_macros.S> -#include <lib/cpus/errata_report.h> +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> #include <lib/el3_runtime/cpu_data.h> /* Reset fn is needed in BL at reset vector */ @@ -32,6 +33,15 @@ /* Get the matching cpu_ops pointer */ bl get_cpu_ops_ptr +#if ENABLE_ASSERTIONS + /* + * Assert if invalid cpu_ops obtained. If this is not valid, it may + * suggest that the proper CPU file hasn't been included. + */ + cmp x0, #0 + ASM_ASSERT(ne) +#endif + /* Get the cpu_ops reset handler */ ldr x2, [x0, #CPU_RESET_FUNC] mov x30, x19 @@ -279,72 +289,6 @@ ret endfunc cpu_rev_var_range -#if REPORT_ERRATA -/* - * void print_errata_status(void); - * - * Function to print errata status for CPUs of its class. Must be called only: - * - * - with MMU and data caches are enabled; - * - after cpu_ops have been initialized in per-CPU data. - */ - .globl print_errata_status -func print_errata_status -#ifdef IMAGE_BL1 - /* - * BL1 doesn't have per-CPU data. So retrieve the CPU operations - * directly. - */ - stp xzr, x30, [sp, #-16]! - bl get_cpu_ops_ptr - ldp xzr, x30, [sp], #16 - ldr x1, [x0, #CPU_ERRATA_FUNC] - cbnz x1, .Lprint -#else - /* - * Retrieve pointer to cpu_ops from per-CPU data, and further, the - * errata printing function. If it's non-NULL, jump to the function in - * turn. - */ - mrs x0, tpidr_el3 -#if ENABLE_ASSERTIONS - cmp x0, #0 - ASM_ASSERT(ne) -#endif - ldr x1, [x0, #CPU_DATA_CPU_OPS_PTR] -#if ENABLE_ASSERTIONS - cmp x1, #0 - ASM_ASSERT(ne) -#endif - ldr x0, [x1, #CPU_ERRATA_FUNC] - cbz x0, .Lnoprint - - /* - * Printing errata status requires atomically testing the printed flag. - */ - stp x19, x30, [sp, #-16]! - mov x19, x0 - - /* - * Load pointers to errata lock and printed flag. Call - * errata_needs_reporting to check whether this CPU needs to report - * errata status pertaining to its class. - */ - ldr x0, [x1, #CPU_ERRATA_LOCK] - ldr x1, [x1, #CPU_ERRATA_PRINTED] - bl errata_needs_reporting - mov x1, x19 - ldp x19, x30, [sp], #16 - cbnz x0, .Lprint -#endif -.Lnoprint: - ret -.Lprint: - /* Jump to errata reporting function for this CPU */ - br x1 -endfunc print_errata_status -#endif - /* * int check_wa_cve_2017_5715(void); *
diff --git a/lib/cpus/aarch64/cpuamu_helpers.S b/lib/cpus/aarch64/cpuamu_helpers.S index 5a77fc7..e71e345 100644 --- a/lib/cpus/aarch64/cpuamu_helpers.S +++ b/lib/cpus/aarch64/cpuamu_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 3c54a6f..884281d 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -207,7 +207,14 @@ 2: ret endfunc denver_disable_dco -func check_errata_cve_2017_5715 +workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 +#if IMAGE_BL31 + adr x1, workaround_bpflush_runtime_exceptions + msr vbar_el3, x1 +#endif +workaround_reset_end denver, CVE(2017, 5715) + +check_erratum_custom_start denver, CVE(2017, 5715) mov x0, #ERRATA_MISSING #if WORKAROUND_CVE_2017_5715 /* @@ -224,43 +231,9 @@ 1: #endif ret -endfunc check_errata_cve_2017_5715 +check_erratum_custom_end denver, CVE(2017, 5715) -func check_errata_cve_2018_3639 -#if WORKAROUND_CVE_2018_3639 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2018_3639 - - /* ------------------------------------------------- - * The CPU Ops reset function for Denver. - * ------------------------------------------------- - */ -func denver_reset_func - - mov x19, x30 - -#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 - /* - * Check if the CPU supports the special instruction - * required to flush the indirect branch predictor and - * RSB. Support for this operation can be determined by - * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. - */ - mrs x0, id_afr0_el1 - mov x1, #0x10000 - and x0, x0, x1 - cmp x0, #0 - adr x1, workaround_bpflush_runtime_exceptions - mrs x2, vbar_el3 - csel x0, x1, x2, ne - msr vbar_el3, x0 -#endif - -#if WORKAROUND_CVE_2018_3639 +workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 /* * Denver CPUs with DENVER_MIDR_PN3 or earlier, use different * bits in the ACTLR_EL3 register to disable speculative @@ -277,8 +250,11 @@ msr actlr_el3, x0 isb dsb sy -#endif +workaround_reset_end denver, CVE(2018, 3639) +check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 + +cpu_reset_func_start denver /* ---------------------------------------------------- * Reset ACTLR.PMSTATE to C1 state * ---------------------------------------------------- @@ -293,9 +269,7 @@ * ---------------------------------------------------- */ bl denver_enable_dco - - ret x19 -endfunc denver_reset_func +cpu_reset_func_end denver /* ---------------------------------------------------- * The CPU Ops core power down function for Denver. @@ -322,27 +296,7 @@ ret endfunc denver_cluster_pwr_dwn -#if REPORT_ERRATA - /* - * Errata printing function for Denver. Must follow AAPCS. - */ -func denver_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715 - report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639 - - ldp x8, x30, [sp], #16 - ret -endfunc denver_errata_report -#endif +errata_report_shim denver /* --------------------------------------------- * This function provides Denver specific @@ -367,7 +321,7 @@ .macro denver_cpu_ops_wa midr declare_cpu_ops_wa denver, \midr, \ denver_reset_func, \ - check_errata_cve_2017_5715, \ + check_erratum_denver_5715, \ CPU_NO_EXTRA2_FUNC, \ CPU_NO_EXTRA3_FUNC, \ denver_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S index 419b6ea..a34b9a6 100644 --- a/lib/cpus/aarch64/dsu_helpers.S +++ b/lib/cpus/aarch64/dsu_helpers.S
@@ -1,12 +1,12 @@ /* - * Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <asm_macros.S> #include <dsu_def.h> -#include <lib/cpus/errata_report.h> +#include <lib/cpus/errata.h> /* ----------------------------------------------------------------------- * DSU erratum 798953 check function @@ -44,11 +44,11 @@ /* -------------------------------------------------- * Errata Workaround for DSU erratum #798953. * - * Can clobber only: x0-x17 + * Can clobber only: x0-x8 * -------------------------------------------------- */ func errata_dsu_798953_wa - mov x17, x30 + mov x8, x30 bl check_errata_dsu_798953 cbz x0, 1f @@ -58,7 +58,7 @@ msr CLUSTERACTLR_EL1, x0 isb 1: - ret x17 + ret x8 endfunc errata_dsu_798953_wa /* ----------------------------------------------------------------------- @@ -72,7 +72,7 @@ * This function is called from both assembly and C environment. So it * follows AAPCS. * - * Clobbers: x0-x15 + * Clobbers: x0-x4 * ----------------------------------------------------------------------- */ .globl check_errata_dsu_936184 @@ -83,7 +83,7 @@ * Default behaviour respresents SCU is always present with DSU. * CPUs can override this definition if required. * - * Can clobber only: x0-x14 + * Can clobber only: x0-x3 * -------------------------------------------------------------------- */ func is_scu_present_in_dsu @@ -92,7 +92,7 @@ endfunc is_scu_present_in_dsu func check_errata_dsu_936184 - mov x15, x30 + mov x4, x30 bl is_scu_present_in_dsu cmp x0, xzr /* Default error status */ @@ -116,17 +116,17 @@ b.hs 1f mov x0, #ERRATA_APPLIES 1: - ret x15 + ret x4 endfunc check_errata_dsu_936184 /* -------------------------------------------------- * Errata Workaround for DSU erratum #936184. * - * Can clobber only: x0-x17 + * Can clobber only: x0-x8 * -------------------------------------------------- */ func errata_dsu_936184_wa - mov x17, x30 + mov x8, x30 bl check_errata_dsu_936184 cbz x0, 1f @@ -137,7 +137,7 @@ msr CLUSTERACTLR_EL1, x0 isb 1: - ret x17 + ret x8 endfunc errata_dsu_936184_wa /* ----------------------------------------------------------------------- @@ -176,11 +176,11 @@ /* -------------------------------------------------- * Errata Workaround for DSU erratum #2313941. * - * Can clobber only: x0-x17 + * Can clobber only: x0-x8 * -------------------------------------------------- */ func errata_dsu_2313941_wa - mov x17, x30 + mov x8, x30 bl check_errata_dsu_2313941 cbz x0, 1f @@ -190,6 +190,5 @@ msr CLUSTERACTLR_EL1, x0 isb 1: - ret x17 + ret x8 endfunc errata_dsu_2313941_wa -
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S index 96b63cf..45bd8d3 100644 --- a/lib/cpus/aarch64/neoverse_e1.S +++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,20 +21,18 @@ #error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif - /* ------------------------------------------------- - * The CPU Ops reset function for Neoverse-E1. - * Shall clobber: x0-x19 - * ------------------------------------------------- - */ -func neoverse_e1_reset_func - mov x19, x30 +/* + * ERRATA_DSU_936184: + * The errata is defined in dsu_helpers.S and applies to neoverse_e1. + * Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. + */ +.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184 +.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa +add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif - - ret x19 -endfunc neoverse_e1_reset_func +cpu_reset_func_start neoverse_e1 +cpu_reset_func_end neoverse_e1 func neoverse_e1_cpu_pwr_dwn mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 @@ -44,27 +42,7 @@ ret endfunc neoverse_e1_cpu_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Neoverse N1. Must follow AAPCS. - */ -func neoverse_e1_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_e1_errata_report -#endif - +errata_report_shim neoverse_e1 .section .rodata.neoverse_e1_regs, "aS" neoverse_e1_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/neoverse_hermes.S b/lib/cpus/aarch64/neoverse_hermes.S new file mode 100644 index 0000000..cb90b71 --- /dev/null +++ b/lib/cpus/aarch64/neoverse_hermes.S
@@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <neoverse_hermes.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Neoverse Hermes must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Neoverse Hermes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +cpu_reset_func_start neoverse_hermes + /* Disable speculative loads */ + msr SSBS, xzr +cpu_reset_func_end neoverse_hermes + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func neoverse_hermes_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set NEOVERSE_HERMES_CPUPWRCTLR_EL1, NEOVERSE_HERMES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb + ret +endfunc neoverse_hermes_core_pwr_dwn + +errata_report_shim neoverse_hermes + + /* --------------------------------------------- + * This function provides Neoverse Hermes specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.neoverse_hermes_regs, "aS" +neoverse_hermes_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func neoverse_hermes_cpu_reg_dump + adr x6, neoverse_hermes_regs + mrs x8, NEOVERSE_HERMES_CPUECTLR_EL1 + ret +endfunc neoverse_hermes_cpu_reg_dump + +declare_cpu_ops neoverse_hermes, NEOVERSE_HERMES_MIDR, \ + neoverse_hermes_reset_func, \ + neoverse_hermes_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 2cf94c7..36a7ee7 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,20 +27,17 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1 #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Erratum 1043202. - * This applies to revision r0p0 and r1p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- +/* + * ERRATA_DSU_936184: + * The errata is defined in dsu_helpers.S and applies to Neoverse N1. + * Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. */ -func errata_n1_1043202_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1043202 - cbz x0, 1f +.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184 +.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa +add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET +workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202 /* Apply instruction patching sequence */ ldr x0, =0x0 msr CPUPSELR_EL3, x0 @@ -50,16 +47,140 @@ msr CPUPMR_EL3, x0 ldr x0, =0x800200071 msr CPUPCR_EL3, x0 - isb -1: - ret x17 -endfunc errata_n1_1043202_wa +workaround_reset_end neoverse_n1, ERRATUM(1043202) -func check_errata_1043202 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1043202 +check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348 + sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 +workaround_reset_end neoverse_n1, ERRATUM(1073348) + +check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799 + sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 +workaround_reset_end neoverse_n1, ERRATUM(1130799) + +check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347 + sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 + sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 +workaround_reset_end neoverse_n1, ERRATUM(1165347) + +check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823 + sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 +workaround_reset_end neoverse_n1, ERRATUM(1207823) + +check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197 + sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK +workaround_reset_end neoverse_n1, ERRATUM(1220197) + +check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314 + sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 +workaround_reset_end neoverse_n1, ERRATUM(1257314) + +check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606 + sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 +workaround_reset_end neoverse_n1, ERRATUM(1262606) + +check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888 + sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT +workaround_reset_end neoverse_n1, ERRATUM(1262888) + +check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112 + sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 +workaround_reset_end neoverse_n1, ERRATUM(1275112) + +check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703 + sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 +workaround_reset_end neoverse_n1, ERRATUM(1315703) + +check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419 + /* Apply instruction patching sequence */ + ldr x0, =0x0 + msr CPUPSELR_EL3, x0 + ldr x0, =0xEE670D35 + msr CPUPOR_EL3, x0 + ldr x0, =0xFFFF0FFF + msr CPUPMR_EL3, x0 + ldr x0, =0x08000020007D + msr CPUPCR_EL3, x0 + isb +workaround_reset_end neoverse_n1, ERRATUM(1542419) + +check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343 + sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 +workaround_reset_end neoverse_n1, ERRATUM(1868343) + +check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0) + +workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160 + mov x0, #3 + msr S3_6_C15_C8_0, x0 + ldr x0, =0x10E3900002 + msr S3_6_C15_C8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_C15_C8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_C15_C8_1, x0 + mov x0, #4 + msr S3_6_C15_C8_0, x0 + ldr x0, =0x10E3800082 + msr S3_6_C15_C8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_C15_C8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_C15_C8_1, x0 + mov x0, #5 + msr S3_6_C15_C8_0, x0 + ldr x0, =0x10E3800200 + msr S3_6_C15_C8_2, x0 + ldr x0, =0x10FFF003E0 + msr S3_6_C15_C8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_C15_C8_1, x0 + isb +workaround_reset_end neoverse_n1, ERRATUM(1946160) + +check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1) + +workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102 + /* dsb before isb of power down sequence */ + dsb sy +workaround_runtime_end neoverse_n1, ERRATUM(2743102) + +check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1) + +workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Neoverse-N1 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_neoverse_n1 +#endif /* IMAGE_BL31 */ +workaround_reset_end neoverse_n1, CVE(2022, 23960) + +check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 /* -------------------------------------------------- * Disable speculative loads if Neoverse N1 supports @@ -81,521 +202,18 @@ ret endfunc neoverse_n1_disable_speculative_loads -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1073348 - * This applies to revision r0p0 and r1p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1073348_wa - /* Compare x0 against revision r1p0 */ - mov x17, x30 - bl check_errata_1073348 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6 - msr NEOVERSE_N1_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_n1_1073348_wa - -func check_errata_1073348 - /* Applies to r0p0 and r1p0 */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1073348 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1130799 - * This applies to revision <=r2p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1130799_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_1130799 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 - msr NEOVERSE_N1_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_n1_1130799_wa - -func check_errata_1130799 - /* Applies to <=r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1130799 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1165347 - * This applies to revision <=r2p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1165347_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_1165347 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 - orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 - msr NEOVERSE_N1_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_n1_1165347_wa - -func check_errata_1165347 - /* Applies to <=r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1165347 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1207823 - * This applies to revision <=r2p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1207823_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_1207823 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR2_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 - msr NEOVERSE_N1_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_n1_1207823_wa - -func check_errata_1207823 - /* Applies to <=r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1207823 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1220197 - * This applies to revision <=r2p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1220197_wa - /* Compare x0 against revision r2p0 */ - mov x17, x30 - bl check_errata_1220197 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUECTLR_EL1 - orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK - msr NEOVERSE_N1_CPUECTLR_EL1, x1 -1: - ret x17 -endfunc errata_n1_1220197_wa - -func check_errata_1220197 - /* Applies to <=r2p0 */ - mov x1, #0x20 - b cpu_rev_var_ls -endfunc check_errata_1220197 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1257314 - * This applies to revision <=r3p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1257314_wa - /* Compare x0 against revision r3p0 */ - mov x17, x30 - bl check_errata_1257314 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR3_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 - msr NEOVERSE_N1_CPUACTLR3_EL1, x1 -1: - ret x17 -endfunc errata_n1_1257314_wa - -func check_errata_1257314 - /* Applies to <=r3p0 */ - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1257314 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1262606 - * This applies to revision <=r3p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1262606_wa - /* Compare x0 against revision r3p0 */ - mov x17, x30 - bl check_errata_1262606 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 - msr NEOVERSE_N1_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_n1_1262606_wa - -func check_errata_1262606 - /* Applies to <=r3p0 */ - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1262606 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1262888 - * This applies to revision <=r3p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1262888_wa - /* Compare x0 against revision r3p0 */ - mov x17, x30 - bl check_errata_1262888 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUECTLR_EL1 - orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT - msr NEOVERSE_N1_CPUECTLR_EL1, x1 -1: - ret x17 -endfunc errata_n1_1262888_wa - -func check_errata_1262888 - /* Applies to <=r3p0 */ - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1262888 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1275112 - * This applies to revision <=r3p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1275112_wa - /* Compare x0 against revision r3p0 */ - mov x17, x30 - bl check_errata_1275112 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 - msr NEOVERSE_N1_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_n1_1275112_wa - -func check_errata_1275112 - /* Applies to <=r3p0 */ - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1275112 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Erratum 1315703. - * This applies to revision <= r3p0 of Neoverse N1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1315703_wa - /* Compare x0 against revision r3p1 */ - mov x17, x30 - bl check_errata_1315703 - cbz x0, 1f - - mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 - orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 - msr NEOVERSE_N1_CPUACTLR2_EL1, x0 - -1: - ret x17 -endfunc errata_n1_1315703_wa - -func check_errata_1315703 - /* Applies to everything <= r3p0. */ - mov x1, #0x30 - b cpu_rev_var_ls -endfunc check_errata_1315703 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Erratum 1542419. - * This applies to revisions r3p0 - r4p0 of Neoverse N1 - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1542419_wa - /* Compare x0 against revision r3p0 and r4p0 */ - mov x17, x30 - bl check_errata_1542419 - cbz x0, 1f - - /* Apply instruction patching sequence */ - ldr x0, =0x0 - msr CPUPSELR_EL3, x0 - ldr x0, =0xEE670D35 - msr CPUPOR_EL3, x0 - ldr x0, =0xFFFF0FFF - msr CPUPMR_EL3, x0 - ldr x0, =0x08000020007D - msr CPUPCR_EL3, x0 - isb -1: - ret x17 -endfunc errata_n1_1542419_wa - -func check_errata_1542419 - /* Applies to everything r3p0 - r4p0. */ - mov x1, #0x30 - mov x2, #0x40 - b cpu_rev_var_range -endfunc check_errata_1542419 - - /* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1868343. - * This applies to revision <= r4p0 of Neoverse N1. - * This workaround is the same as the workaround for - * errata 1262606 and 1275112 but applies to a wider - * revision range. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1868343_wa - /* - * Compare x0 against revision r4p0 - */ - mov x17, x30 - bl check_errata_1868343 - cbz x0, 1f - mrs x1, NEOVERSE_N1_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13 - msr NEOVERSE_N1_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_n1_1868343_wa - -func check_errata_1868343 - /* Applies to everything <= r4p0 */ - mov x1, #0x40 - b cpu_rev_var_ls -endfunc check_errata_1868343 - - /* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1946160. - * This applies to revisions r3p0, r3p1, r4p0, and - * r4p1 of Neoverse N1. It also exists in r0p0, r1p0, - * and r2p0 but there is no fix in these revisions. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n1_1946160_wa - /* - * Compare x0 against r3p0 - r4p1 - */ - mov x17, x30 - bl check_errata_1946160 - cbz x0, 1f - - mov x0, #3 - msr S3_6_C15_C8_0, x0 - ldr x0, =0x10E3900002 - msr S3_6_C15_C8_2, x0 - ldr x0, =0x10FFF00083 - msr S3_6_C15_C8_3, x0 - ldr x0, =0x2001003FF - msr S3_6_C15_C8_1, x0 - - mov x0, #4 - msr S3_6_C15_C8_0, x0 - ldr x0, =0x10E3800082 - msr S3_6_C15_C8_2, x0 - ldr x0, =0x10FFF00083 - msr S3_6_C15_C8_3, x0 - ldr x0, =0x2001003FF - msr S3_6_C15_C8_1, x0 - - mov x0, #5 - msr S3_6_C15_C8_0, x0 - ldr x0, =0x10E3800200 - msr S3_6_C15_C8_2, x0 - ldr x0, =0x10FFF003E0 - msr S3_6_C15_C8_3, x0 - ldr x0, =0x2001003FF - msr S3_6_C15_C8_1, x0 - - isb -1: - ret x17 -endfunc errata_n1_1946160_wa - -func check_errata_1946160 - /* Applies to r3p0 - r4p1. */ - mov x1, #0x30 - mov x2, #0x41 - b cpu_rev_var_range -endfunc check_errata_1946160 - - /* ---------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #2743102 - * This applies to revisions <= r4p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_n1_2743102_wa - mov x17, x30 - bl check_errata_2743102 - cbz x0, 1f - - /* dsb before isb of power down sequence */ - dsb sy -1: - ret x17 -endfunc errata_n1_2743102_wa - -func check_errata_2743102 - /* Applies to all revisions <= r4p1 */ - mov x1, #0x41 - b cpu_rev_var_ls -endfunc check_errata_2743102 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func neoverse_n1_reset_func - mov x19, x30 - +cpu_reset_func_start neoverse_n1 bl neoverse_n1_disable_speculative_loads /* Forces all cacheable atomic instructions to be near */ - mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 - orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 - msr NEOVERSE_N1_CPUACTLR2_EL1, x0 + sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 isb - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_N1_1043202 - mov x0, x18 - bl errata_n1_1043202_wa -#endif - -#if ERRATA_N1_1073348 - mov x0, x18 - bl errata_n1_1073348_wa -#endif - -#if ERRATA_N1_1130799 - mov x0, x18 - bl errata_n1_1130799_wa -#endif - -#if ERRATA_N1_1165347 - mov x0, x18 - bl errata_n1_1165347_wa -#endif - -#if ERRATA_N1_1207823 - mov x0, x18 - bl errata_n1_1207823_wa -#endif - -#if ERRATA_N1_1220197 - mov x0, x18 - bl errata_n1_1220197_wa -#endif - -#if ERRATA_N1_1257314 - mov x0, x18 - bl errata_n1_1257314_wa -#endif - -#if ERRATA_N1_1262606 - mov x0, x18 - bl errata_n1_1262606_wa -#endif - -#if ERRATA_N1_1262888 - mov x0, x18 - bl errata_n1_1262888_wa -#endif - -#if ERRATA_N1_1275112 - mov x0, x18 - bl errata_n1_1275112_wa -#endif - -#if ERRATA_N1_1315703 - mov x0, x18 - bl errata_n1_1315703_wa -#endif - -#if ERRATA_N1_1542419 - mov x0, x18 - bl errata_n1_1542419_wa -#endif - -#if ERRATA_N1_1868343 - mov x0, x18 - bl errata_n1_1868343_wa -#endif - -#if ERRATA_N1_1946160 - mov x0, x18 - bl errata_n1_1946160_wa -#endif - #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT - msr actlr_el3, x0 - + sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT - msr actlr_el2, x0 - + sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT /* Enable group0 counters */ mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK msr CPUAMCNTENSET_EL0, x0 @@ -603,27 +221,9 @@ #if NEOVERSE_Nx_EXTERNAL_LLC /* Some system may have External LLC, core needs to be made aware */ - mrs x0, NEOVERSE_N1_CPUECTLR_EL1 - orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT - msr NEOVERSE_N1_CPUECTLR_EL1, x0 + sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT #endif - -#if ERRATA_DSU_936184 - bl errata_dsu_936184_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Neoverse-N1 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_neoverse_n1 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc neoverse_n1_reset_func +cpu_reset_func_end neoverse_n1 /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -634,55 +234,15 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK - msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 -#if ERRATA_N1_2743102 - mov x15, x30 - bl cpu_get_rev_var - bl errata_n1_2743102_wa - mov x30, x15 -#endif /* ERRATA_N1_2743102 */ + sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK + + apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102 + isb ret endfunc neoverse_n1_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Neoverse N1. Must follow AAPCS. - */ -func neoverse_n1_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 - report_errata ERRATA_N1_1073348, neoverse_n1, 1073348 - report_errata ERRATA_N1_1130799, neoverse_n1, 1130799 - report_errata ERRATA_N1_1165347, neoverse_n1, 1165347 - report_errata ERRATA_N1_1207823, neoverse_n1, 1207823 - report_errata ERRATA_N1_1220197, neoverse_n1, 1220197 - report_errata ERRATA_N1_1257314, neoverse_n1, 1257314 - report_errata ERRATA_N1_1262606, neoverse_n1, 1262606 - report_errata ERRATA_N1_1262888, neoverse_n1, 1262888 - report_errata ERRATA_N1_1275112, neoverse_n1, 1275112 - report_errata ERRATA_N1_1315703, neoverse_n1, 1315703 - report_errata ERRATA_N1_1542419, neoverse_n1, 1542419 - report_errata ERRATA_N1_1868343, neoverse_n1, 1868343 - report_errata ERRATA_N1_1946160, neoverse_n1, 1946160 - report_errata ERRATA_N1_2743102, neoverse_n1, 2743102 - report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184 - report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_n1_errata_report -#endif +errata_report_shim neoverse_n1 /* * Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
diff --git a/lib/cpus/aarch64/neoverse_n1_pubsub.c b/lib/cpus/aarch64/neoverse_n1_pubsub.c index b1b7bb8..ecfb501 100644 --- a/lib/cpus/aarch64/neoverse_n1_pubsub.c +++ b/lib/cpus/aarch64/neoverse_n1_pubsub.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 60d322f..477522f 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,20 +24,17 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2 #endif /* WORKAROUND_CVE_2022_23960 */ -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2002655. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- +/* + * ERRATA_DSU_2313941: + * The errata is defined in dsu_helpers.S and applies to Neoverse N2. + * Henceforth creating symbolic names to the already existing errata + * workaround functions to get them registered under the Errata Framework. */ -func errata_n2_2002655_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2002655 - cbz x0, 1f +.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941 +.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa +add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET +workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655 /* Apply instruction patching sequence */ ldr x0,=0x6 msr S3_6_c15_c8_0,x0 @@ -55,111 +52,49 @@ msr S3_6_c15_c8_3,x0 ldr x0,=0x40000001003f3 msr S3_6_c15_c8_1,x0 - isb -1: - ret x17 -endfunc errata_n2_2002655_wa +workaround_reset_end neoverse_n2, ERRATUM(2002655) -func check_errata_2002655 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2002655 +check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0) -/* --------------------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2067956. - * This applies to revision r0p0 of Neoverse N2 and is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------- - */ -func errata_n2_2067956_wa - /* Compare x0 against revision r0p0 */ - mov x17, x30 - bl check_errata_2067956 - cbz x0, 1f - mrs x1, NEOVERSE_N2_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 - msr NEOVERSE_N2_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_n2_2067956_wa +workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414 + sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT +workaround_reset_end neoverse_n2, ERRATUM(2025414) -func check_errata_2067956 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2067956 +check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0) -/* --------------------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2025414. - * This applies to revision r0p0 of Neoverse N2 and is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------- - */ -func errata_n2_2025414_wa - /* Compare x0 against revision r0p0 */ - mov x17, x30 - bl check_errata_2025414 - cbz x0, 1f - mrs x1, NEOVERSE_N2_CPUECTLR_EL1 - orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT - msr NEOVERSE_N2_CPUECTLR_EL1, x1 +workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956 + sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 +workaround_reset_end neoverse_n2, ERRATUM(2067956) -1: - ret x17 -endfunc errata_n2_2025414_wa +check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0) -func check_errata_2025414 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2025414 +workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 + /* Stash ERRSELR_EL1 in x2 */ + mrs x2, ERRSELR_EL1 -/* --------------------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2189731. - * This applies to revision r0p0 of Neoverse N2 and is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * --------------------------------------------------------------- - */ -func errata_n2_2189731_wa - /* Compare x0 against revision r0p0 */ - mov x17, x30 - bl check_errata_2189731 - cbz x0, 1f - mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 - msr NEOVERSE_N2_CPUACTLR5_EL1, x1 + /* Select error record 0 and clear ED bit */ + msr ERRSELR_EL1, xzr + mrs x1, ERXCTLR_EL1 + bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 + msr ERXCTLR_EL1, x1 -1: - ret x17 -endfunc errata_n2_2189731_wa + /* Restore ERRSELR_EL1 from x2 */ + msr ERRSELR_EL1, x2 +workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB -func check_errata_2189731 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2189731 +check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2138956. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_n2_2138956_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2138956 - cbz x0, 1f +workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953 + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 + mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH + msr NEOVERSE_N2_CPUECTLR2_EL1, x1 +workaround_reset_end neoverse_n2, ERRATUM(2138953) +check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3) + +workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956 /* Apply instruction patching sequence */ ldr x0,=0x3 msr S3_6_c15_c8_0,x0 @@ -177,120 +112,27 @@ msr S3_6_c15_c8_3,x0 ldr x0,=0x10002001003F3 msr S3_6_c15_c8_1,x0 - isb -1: - ret x17 -endfunc errata_n2_2138956_wa +workaround_reset_end neoverse_n2, ERRATUM(2138956) -func check_errata_2138956 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2138956 +check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2242415. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2242415_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2242415 - cbz x0, 1f +workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958 /* Apply instruction patching sequence */ - mrs x1, NEOVERSE_N2_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 - msr NEOVERSE_N2_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_n2_2242415_wa + sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 +workaround_reset_end neoverse_n2, ERRATUM(2138958) -func check_errata_2242415 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2242415 +check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2138953. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2138953_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2138953 - cbz x0, 1f +workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731 + sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 +workaround_reset_end neoverse_n2, ERRATUM(2189731) +check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0) + +workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400 /* Apply instruction patching sequence */ - mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 - mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV - bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH - msr NEOVERSE_N2_CPUECTLR2_EL1, x1 -1: - ret x17 -endfunc errata_n2_2138953_wa - -func check_errata_2138953 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2138953 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2138958. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2138958_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2138958 - cbz x0, 1f - - /* Apply instruction patching sequence */ - mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 - msr NEOVERSE_N2_CPUACTLR5_EL1, x1 -1: - ret x17 -endfunc errata_n2_2138958_wa - -func check_errata_2138958 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2138958 - -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2242400. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2242400_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2242400 - cbz x0, 1f - - /* Apply instruction patching sequence */ - mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 - msr NEOVERSE_N2_CPUACTLR5_EL1, x1 + sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 ldr x0, =0x2 msr S3_6_c15_c8_0, x0 ldr x0, =0x10F600E000 @@ -299,174 +141,103 @@ msr S3_6_c15_c8_3, x0 ldr x0, =0x80000000003FF msr S3_6_c15_c8_1, x0 - isb -1: - ret x17 -endfunc errata_n2_2242400_wa +workaround_reset_end neoverse_n2, ERRATUM(2242400) -func check_errata_2242400 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2242400 +check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2280757. - * This applies to revision r0p0 of Neoverse N2. it is still open. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2280757_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2280757 - cbz x0, 1f +workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415 + sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 +workaround_reset_end neoverse_n2, ERRATUM(2242415) +check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0) + +workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757 /* Apply instruction patching sequence */ - mrs x1, NEOVERSE_N2_CPUACTLR_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 - msr NEOVERSE_N2_CPUACTLR_EL1, x1 -1: - ret x17 -endfunc errata_n2_2280757_wa + sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 +workaround_reset_end neoverse_n2, ERRATUM(2280757) -func check_errata_2280757 - /* Applies to r0p0 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2280757 +check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2326639. - * This applies to revision r0p0 of Neoverse N2, - * fixed in r0p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2326639_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2326639 - cbz x0, 1f - +workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639 /* Set bit 36 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 - orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 - msr NEOVERSE_N2_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_n2_2326639_wa + sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 +workaround_runtime_end neoverse_n2, ERRATUM(2326639) -func check_errata_2326639 - /* Applies to r0p0, fixed in r0p1 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2326639 +check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2376738. - * This applies to revision r0p0 of Neoverse N2, - * fixed in r0p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current CPU. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2376738_wa - mov x17, x30 - bl check_errata_2376738 - cbz x0, 1f +workaround_runtime_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933 + /* Set bit 61 in CPUACTLR5_EL1 */ + sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61) +workaround_runtime_end neoverse_n2, ERRATUM(2340933) +check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0) + +workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952 + /* Set TXREQ to STATIC and full L2 TQ size */ + mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 + mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL + bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH + msr NEOVERSE_N2_CPUECTLR2_EL1, x1 +workaround_runtime_end neoverse_n2, ERRATUM(2346952) + +check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2) + +workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM * ST to behave like PLD/PFRM LD and not cause * invalidations to other PE caches. */ - mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 - orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 - msr NEOVERSE_N2_CPUACTLR2_EL1, x1 -1: - ret x17 -endfunc errata_n2_2376738_wa + sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 +workaround_reset_end neoverse_n2, ERRATUM(2376738) -func check_errata_2376738 - /* Applies to r0p0, fixed in r0p1 */ - mov x1, 0x00 - b cpu_rev_var_ls -endfunc check_errata_2376738 +check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3) -/* -------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2388450. - * This applies to revision r0p0 of Neoverse N2, - * fixed in r0p1. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_n2_2388450_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2388450 - cbz x0, 1f - +workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450 /*Set bit 40 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_N2_CPUACTLR2_EL1 - orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 - msr NEOVERSE_N2_CPUACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_n2_2388450_wa + sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 +workaround_reset_end neoverse_n2, ERRATUM(2388450) -func check_errata_2388450 - /* Applies to r0p0, fixed in r0p1 */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_2388450 +check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0) -/* ------------------------------------------------------- - * Errata Workaround for Neoverse N2 Erratum 2743089. - * This applies to revisions <= r0p2 and is fixed in r0p3. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ------------------------------------------------------- - */ -func errata_n2_2743089_wa - mov x17, x30 - bl check_errata_2743089 - cbz x0, 1f +workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014 + /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ + sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 + sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 +workaround_reset_end neoverse_n2, ERRATUM(2743014) +check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2) + +workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_n2_2743089_wa +workaround_runtime_end neoverse_n2, ERRATUM(2743089) -func check_errata_2743089 - /* Applies to all revisions <= r0p2 */ - mov x1, #0x02 - b cpu_rev_var_ls -endfunc check_errata_2743089 +check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2) -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 +workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511 + /* Set bit 47 in ACTLR3_EL1 */ + sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 +workaround_reset_end neoverse_n2, ERRATUM(2779511) + +check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2) + +workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Neoverse-N2 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_neoverse_n2 +#endif /* IMAGE_BL31 */ +workaround_reset_end neoverse_n2, CVE(2022,23960) + +check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- */ -func neoverse_n2_reset_func - mov x19, x30 +cpu_reset_func_start neoverse_n2 /* Check if the PE implements SSBS */ mrs x0, id_aa64pfr1_el1 @@ -477,174 +248,41 @@ msr SSBS, xzr 1: /* Force all cacheable atomic instructions to be near */ - mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 - orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 - msr NEOVERSE_N2_CPUACTLR2_EL1, x0 - - /* Get the CPU revision and stash it in x18. */ - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_DSU_2313941 - bl errata_dsu_2313941_wa -#endif - -#if ERRATA_N2_2067956 - mov x0, x18 - bl errata_n2_2067956_wa -#endif - -#if ERRATA_N2_2025414 - mov x0, x18 - bl errata_n2_2025414_wa -#endif - -#if ERRATA_N2_2189731 - mov x0, x18 - bl errata_n2_2189731_wa -#endif - - -#if ERRATA_N2_2138956 - mov x0, x18 - bl errata_n2_2138956_wa -#endif - -#if ERRATA_N2_2138953 - mov x0, x18 - bl errata_n2_2138953_wa -#endif - -#if ERRATA_N2_2242415 - mov x0, x18 - bl errata_n2_2242415_wa -#endif - -#if ERRATA_N2_2138958 - mov x0, x18 - bl errata_n2_2138958_wa -#endif - -#if ERRATA_N2_2242400 - mov x0, x18 - bl errata_n2_2242400_wa -#endif - -#if ERRATA_N2_2280757 - mov x0, x18 - bl errata_n2_2280757_wa -#endif - -#if ERRATA_N2_2376738 - mov x0, x18 - bl errata_n2_2376738_wa -#endif - -#if ERRATA_N2_2388450 - mov x0, x18 - bl errata_n2_2388450_wa -#endif + sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, cptr_el3 - orr x0, x0, #TAM_BIT - msr cptr_el3, x0 - + sysreg_bit_set cptr_el3, TAM_BIT /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ - mrs x0, cptr_el2 - orr x0, x0, #TAM_BIT - msr cptr_el2, x0 - + sysreg_bit_set cptr_el2, TAM_BIT /* No need to enable the counters as this would be done at el3 exit */ #endif #if NEOVERSE_Nx_EXTERNAL_LLC /* Some systems may have External LLC, core needs to be made aware */ - mrs x0, NEOVERSE_N2_CPUECTLR_EL1 - orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT - msr NEOVERSE_N2_CPUECTLR_EL1, x0 + sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT #endif - -#if ERRATA_N2_2002655 - mov x0, x18 - bl errata_n2_2002655_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Neoverse-N2 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_neoverse_n2 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc neoverse_n2_reset_func +cpu_reset_func_end neoverse_n2 func neoverse_n2_core_pwr_dwn -#if ERRATA_N2_2326639 - mov x15, x30 - bl cpu_get_rev_var - bl errata_n2_2326639_wa - mov x30, x15 -#endif /* ERRATA_N2_2326639 */ + + apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478 + apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV /* --------------------------------------------------- * Enable CPU power down bit in power control register * No need to do cache maintenance here. * --------------------------------------------------- */ - mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT - msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 -#if ERRATA_N2_2743089 - mov x15, x30 - bl cpu_get_rev_var - bl errata_n2_2743089_wa - mov x30, x15 -#endif /* ERRATA_N2_2743089 */ + sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT + + apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089 + isb ret endfunc neoverse_n2_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Neoverse N2 cores. Must follow AAPCS. - */ -func neoverse_n2_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 - report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 - report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 - report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 - report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 - report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 - report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 - report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 - report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 - report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 - report_errata ERRATA_N2_2326639, neoverse_n2, 2326639 - report_errata ERRATA_N2_2376738, neoverse_n2, 2376738 - report_errata ERRATA_N2_2388450, neoverse_n2, 2388450 - report_errata ERRATA_N2_2743089, neoverse_n2, 2743089 - report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960 - report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_n2_errata_report -#endif +errata_report_shim neoverse_n2 /* --------------------------------------------- * This function provides Neoverse N2 specific
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S index 030293d..3b3245d 100644 --- a/lib/cpus/aarch64/neoverse_poseidon.S +++ b/lib/cpus/aarch64/neoverse_poseidon.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,19 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon #endif /* WORKAROUND_CVE_2022_23960 */ +workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Neoverse-poseidon generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_neoverse_poseidon + +#endif /* IMAGE_BL31 */ +workaround_reset_end neoverse_poseidon, CVE(2022,23960) + +check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -35,59 +48,19 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0 + sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \ + NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + isb ret endfunc neoverse_poseidon_core_pwr_dwn -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func neoverse_poseidon_reset_func +cpu_reset_func_start neoverse_poseidon /* Disable speculative loads */ msr SSBS, xzr +cpu_reset_func_end neoverse_poseidon -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Neoverse Poseidon generic vectors are overridden to apply - * errata mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_neoverse_poseidon - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret -endfunc neoverse_poseidon_reset_func - -#if REPORT_ERRATA - /* - * Errata printing function for Neoverse Poseidon. Must follow AAPCS. - */ -func neoverse_poseidon_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, neoverse_poseidon, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_poseidon_errata_report -#endif +errata_report_shim neoverse_poseidon /* --------------------------------------------- * This function provides Neoverse-Poseidon specific
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 363c2e6..2a49134 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -26,20 +26,7 @@ wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 #endif /* WORKAROUND_CVE_2022_23960 */ - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #1618635. - * This applies to revision r0p0 and is fixed in - * r1p0. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1618635_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1618635 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635 /* Inserts a DMB SY before and after MRS PAR_EL1 */ ldr x0, =0x0 msr NEOVERSE_V1_CPUPSELR_EL3, x0 @@ -90,146 +77,39 @@ ldr x0, = 0x4004027FF msr NEOVERSE_V1_CPUPCR_EL3, x0 - /* Synchronize to enable patches */ - isb -1: - ret x17 -endfunc errata_neoverse_v1_1618635_wa +workaround_reset_end neoverse_v1, ERRATUM(1618635) -func check_errata_1618635 - /* Applies to revision r0p0. */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_1618635 +check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #1774420. - * This applies to revisions r0p0 and r1p0, fixed in r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1774420_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1774420 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420 /* Set bit 53 in CPUECTLR_EL1 */ - mrs x1, NEOVERSE_V1_CPUECTLR_EL1 - orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 - msr NEOVERSE_V1_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_neoverse_v1_1774420_wa + sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 +workaround_reset_end neoverse_v1, ERRATUM(1774420) -func check_errata_1774420 - /* Applies to r0p0 and r1p0. */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1774420 +check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #1791573. - * This applies to revisions r0p0 and r1p0, fixed in r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1791573_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1791573 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573 /* Set bit 2 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 - msr NEOVERSE_V1_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_neoverse_v1_1791573_wa + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 +workaround_reset_end neoverse_v1, ERRATUM(1791573) -func check_errata_1791573 - /* Applies to r0p0 and r1p0. */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1791573 +check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #1852267. - * This applies to revisions r0p0 and r1p0, fixed in r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1852267_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1852267 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267 /* Set bit 28 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 - msr NEOVERSE_V1_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_neoverse_v1_1852267_wa + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 +workaround_reset_end neoverse_v1, ERRATUM(1852267) -func check_errata_1852267 - /* Applies to r0p0 and r1p0. */ - mov x1, #0x10 - b cpu_rev_var_ls -endfunc check_errata_1852267 +check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #1925756. - * This applies to revisions <= r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1925756_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1925756 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756 /* Set bit 8 in CPUECTLR_EL1 */ - mrs x1, NEOVERSE_V1_CPUECTLR_EL1 - orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 - msr NEOVERSE_V1_CPUECTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_neoverse_v1_1925756_wa + sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8 +workaround_reset_end neoverse_v1, ERRATUM(1925756) -func check_errata_1925756 - /* Applies to <= r1p1. */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_1925756 +check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Erratum #1940577 - * This applies to revisions r1p0 - r1p1 and is open. - * It also exists in r0p0 but there is no fix in that - * revision. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1940577_wa - /* Compare x0 against revisions r1p0 - r1p1 */ - mov x17, x30 - bl check_errata_1940577 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577 mov x0, #0 msr S3_6_C15_C8_0, x0 ldr x0, =0x10E3900002 @@ -257,34 +137,11 @@ ldr x0, =0x2001003FF msr S3_6_C15_C8_1, x0 - isb -1: - ret x17 -endfunc errata_neoverse_v1_1940577_wa +workaround_reset_end neoverse_v1, ERRATUM(1940577) -func check_errata_1940577 - /* Applies to revisions r1p0 - r1p1. */ - mov x1, #0x10 - mov x2, #0x11 - b cpu_rev_var_range -endfunc check_errata_1940577 +check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #1966096 - * This applies to revisions r1p0 - r1p1 and is open. - * It also exists in r0p0 but there is no workaround - * for that revision. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_1966096_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_1966096 - cbz x0, 1f - - /* Apply the workaround. */ +workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096 mov x0, #0x3 msr S3_6_C15_C8_0, x0 ldr x0, =0xEE010F12 @@ -293,33 +150,20 @@ msr S3_6_C15_C8_3, x0 ldr x0, =0x80000000003FF msr S3_6_C15_C8_1, x0 - isb +workaround_reset_end neoverse_v1, ERRATUM(1966096) -1: - ret x17 -endfunc errata_neoverse_v1_1966096_wa +check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1) -func check_errata_1966096 - mov x1, #0x10 - mov x2, #0x11 - b cpu_rev_var_range -endfunc check_errata_1966096 +workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267 + mrs x1, NEOVERSE_V1_CPUECTLR_EL1 + mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH + msr NEOVERSE_V1_CPUECTLR_EL1, x1 +workaround_reset_end neoverse_v1, ERRATUM(2108267) - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2139242. - * This applies to revisions r0p0, r1p0, and r1p1, it - * is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_2139242_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2139242 - cbz x0, 1f +check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2) - /* Apply the workaround. */ +workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242 mov x0, #0x3 msr S3_6_C15_C8_0, x0 ldr x0, =0xEE720F14 @@ -328,63 +172,11 @@ msr S3_6_C15_C8_3, x0 ldr x0, =0x40000005003FF msr S3_6_C15_C8_1, x0 - isb +workaround_reset_end neoverse_v1, ERRATUM(2139242) -1: - ret x17 -endfunc errata_neoverse_v1_2139242_wa +check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1) -func check_errata_2139242 - /* Applies to r0p0, r1p0, r1p1 */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2139242 - - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2108267. - * This applies to revisions r0p0, r1p0, and r1p1, it - * is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_2108267_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2108267 - cbz x0, 1f - - /* Apply the workaround. */ - mrs x1, NEOVERSE_V1_CPUECTLR_EL1 - mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV - bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH - msr NEOVERSE_V1_CPUECTLR_EL1, x1 -1: - ret x17 -endfunc errata_neoverse_v1_2108267_wa - -func check_errata_2108267 - /* Applies to r0p0, r1p0, r1p1 */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2108267 - - /* -------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2216392. - * This applies to revisions r1p0 and r1p1 and is - * still open. - * This issue is also present in r0p0 but there is no - * workaround in that revision. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ -func errata_neoverse_v1_2216392_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2216392 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392 ldr x0, =0x5 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ ldr x0, =0x10F600E000 @@ -393,167 +185,56 @@ msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ ldr x0, =0x80000000003FF msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ +workaround_reset_end neoverse_v1, ERRATUM(2216392) - isb -1: - ret x17 -endfunc errata_neoverse_v1_2216392_wa +check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1) -func check_errata_2216392 - /* Applies to revisions r1p0 and r1p1. */ - mov x1, #CPU_REV(1, 0) - mov x2, #CPU_REV(1, 1) - b cpu_rev_var_range -endfunc check_errata_2216392 - - /* ----------------------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2294912. - * This applies to revisions r0p0, r1p0, and r1p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ----------------------------------------------------------------- - */ -func errata_neoverse_v1_2294912_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2294912 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912 /* Set bit 0 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0 - msr NEOVERSE_V1_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_neoverse_v1_2294912_wa + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0 +workaround_reset_end neoverse_v1, ERRATUM(2294912) -func check_errata_2294912 - /* Applies to r0p0, r1p0, and r1p1 right now */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2294912 +check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2) - /* --------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2372203. - * This applies to revisions <= r1p1 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_neoverse_v1_2372203_wa - /* Check workaround compatibility. */ - mov x17, x30 - bl check_errata_2372203 - cbz x0, 1f - +workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203 /* Set bit 40 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 - orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40 - msr NEOVERSE_V1_ACTLR2_EL1, x1 - isb -1: - ret x17 -endfunc errata_neoverse_v1_2372203_wa + sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40 +workaround_reset_end neoverse_v1, ERRATUM(2372203) -func check_errata_2372203 - /* Applies to <= r1p1. */ - mov x1, #0x11 - b cpu_rev_var_ls -endfunc check_errata_2372203 +check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1) - /* ---------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2743093. - * This applies to revisions <= r1p2 and is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * ---------------------------------------------------- - */ -func errata_neoverse_v1_2743093_wa - mov x17, x30 - bl check_errata_2743093 - cbz x0, 1f - +workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 /* dsb before isb of power down sequence */ dsb sy -1: - ret x17 -endfunc errata_neoverse_v1_2743093_wa +workaround_runtime_end neoverse_v1, ERRATUM(2743093) -func check_errata_2743093 - /* Applies to all revisions <= r1p2 */ - mov x1, #0x12 - b cpu_rev_var_ls -endfunc check_errata_2743093 +check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2) - /* --------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2743233. - * This applies to revisions r0p0, r1p0, r1p1 and r1p2. - * It is still open. - * x0: variant[4:7] and revisions[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * --------------------------------------------------- +workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233 + sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56 + sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55 +workaround_reset_end neoverse_v1, ERRATUM(2743233) + +check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2) + +workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461 + sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47 +workaround_reset_end neoverse_v1, ERRATUM(2779461) + +check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2) + + +workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Neoverse-V1 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. */ -func errata_neoverse_v1_2743233_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2743233 - cbz x0, 1f + override_vector_table wa_cve_vbar_neoverse_v1 +#endif /* IMAGE_BL31 */ +workaround_reset_end neoverse_v1, CVE(2022,23960) - /* Apply the workaround */ - mrs x1, NEOVERSE_V1_ACTLR5_EL1 - bic x1, x1, #BIT(56) - orr x1, x1, #BIT(55) - msr NEOVERSE_V1_ACTLR5_EL1, x1 - -1: - ret x17 -endfunc errata_neoverse_v1_2743233_wa - -func check_errata_2743233 - /* Applies to r0p0, r1p0, r1p1 and r1p2 */ - mov x1, #CPU_REV(1,2) - b cpu_rev_var_ls -endfunc check_errata_2743233 - - - /* ---------------------------------------------------- - * Errata Workaround for Neoverse V1 Errata #2779461. - * This applies to revisions r0p0, r1p0, r1p1, and r1p2. - * It is still open. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x1, x17 - * ---------------------------------------------------- - */ -func errata_neoverse_v1_2779461_wa - /* Check revision. */ - mov x17, x30 - bl check_errata_2779461 - cbz x0, 1f - - /* Apply the workaround */ - mrs x1, NEOVERSE_V1_ACTLR3_EL1 - orr x1, x1, #BIT(47) - msr NEOVERSE_V1_ACTLR3_EL1, x1 - -1: - ret x17 -endfunc errata_neoverse_v1_2779461_wa - -func check_errata_2779461 - /* Applies to r0p0, r1p0, r1p1, r1p2 */ - mov x1, #CPU_REV(1, 2) - b cpu_rev_var_ls -endfunc check_errata_2779461 - -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 +check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -564,148 +245,19 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 -#if ERRATA_V1_2743093 - mov x15, x30 - bl cpu_get_rev_var - bl errata_neoverse_v1_2743093_wa - mov x30, x15 -#endif /* ERRATA_V1_2743093 */ + sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 + isb ret endfunc neoverse_v1_core_pwr_dwn - /* - * Errata printing function for Neoverse V1. Must follow AAPCS. - */ -#if REPORT_ERRATA -func neoverse_v1_errata_report - stp x8, x30, [sp, #-16]! +errata_report_shim neoverse_v1 - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_V1_1618635, neoverse_v1, 1618635 - report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 - report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 - report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 - report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 - report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 - report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 - report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 - report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 - report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 - report_errata ERRATA_V1_2294912, neoverse_v1, 2294912 - report_errata ERRATA_V1_2372203, neoverse_v1, 2372203 - report_errata ERRATA_V1_2743093, neoverse_v1, 2743093 - report_errata ERRATA_V1_2743233, neoverse_v1, 2743233 - report_errata ERRATA_V1_2779461, neoverse_v1, 2779461 - report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_v1_errata_report -#endif - -func neoverse_v1_reset_func - mov x19, x30 - +cpu_reset_func_start neoverse_v1 /* Disable speculative loads */ msr SSBS, xzr - isb - - /* Get the CPU revision and stash it in x18. */ - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_V1_1618635 - mov x0, x18 - bl errata_neoverse_v1_1618635_wa -#endif - -#if ERRATA_V1_1774420 - mov x0, x18 - bl errata_neoverse_v1_1774420_wa -#endif - -#if ERRATA_V1_1791573 - mov x0, x18 - bl errata_neoverse_v1_1791573_wa -#endif - -#if ERRATA_V1_1852267 - mov x0, x18 - bl errata_neoverse_v1_1852267_wa -#endif - -#if ERRATA_V1_1925756 - mov x0, x18 - bl errata_neoverse_v1_1925756_wa -#endif - -#if ERRATA_V1_1940577 - mov x0, x18 - bl errata_neoverse_v1_1940577_wa -#endif - -#if ERRATA_V1_1966096 - mov x0, x18 - bl errata_neoverse_v1_1966096_wa -#endif - -#if ERRATA_V1_2139242 - mov x0, x18 - bl errata_neoverse_v1_2139242_wa -#endif - -#if ERRATA_V1_2108267 - mov x0, x18 - bl errata_neoverse_v1_2108267_wa -#endif - -#if ERRATA_V1_2216392 - mov x0, x18 - bl errata_neoverse_v1_2216392_wa -#endif - -#if ERRATA_V1_2294912 - mov x0, x18 - bl errata_neoverse_v1_2294912_wa -#endif - -#if ERRATA_V1_2372203 - mov x0, x18 - bl errata_neoverse_v1_2372203_wa -#endif - -#if ERRATA_V1_2743233 - mov x0, x18 - bl errata_neoverse_v1_2743233_wa -#endif - -#if ERRATA_V1_2779461 - mov x0, x18 - bl errata_neoverse_v1_2779461_wa -#endif - -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Neoverse-V1 generic vectors are overridden to apply errata - * mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_neoverse_v1 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - - isb - ret x19 -endfunc neoverse_v1_reset_func +cpu_reset_func_end neoverse_v1 /* --------------------------------------------- * This function provides Neoverse-V1 specific
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S index 4ea887f..bfd088d 100644 --- a/lib/cpus/aarch64/neoverse_v2.S +++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,51 @@ #error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132 + sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \ + NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH +workaround_reset_end neoverse_v2, ERRATUM(2331132) + +check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2) + +workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105 + sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0 +workaround_reset_end neoverse_v2, ERRATUM(2719105) + +check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1) + +workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011 + sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55 + sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56 +workaround_reset_end neoverse_v2, ERRATUM(2743011) + +check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1) + +workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510 + sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47 +workaround_reset_end neoverse_v2, ERRATUM(2779510) + +check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1) + +workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 + /* dsb before isb of power down sequence */ + dsb sy +workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 + +check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1) + +workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960 +#if IMAGE_BL31 + /* + * The Neoverse-V2 generic vectors are overridden to apply errata + * mitigation on exception entry from lower ELs. + */ + override_vector_table wa_cve_vbar_neoverse_v2 +#endif /* IMAGE_BL31 */ +workaround_reset_end neoverse_v2, CVE(2022,23960) + +check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -35,59 +80,19 @@ * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 + sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372 + isb ret endfunc neoverse_v2_core_pwr_dwn -func check_errata_cve_2022_23960 -#if WORKAROUND_CVE_2022_23960 - mov x0, #ERRATA_APPLIES -#else - mov x0, #ERRATA_MISSING -#endif - ret -endfunc check_errata_cve_2022_23960 - -func neoverse_v2_reset_func +cpu_reset_func_start neoverse_v2 /* Disable speculative loads */ msr SSBS, xzr +cpu_reset_func_end neoverse_v2 -#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 - /* - * The Neoverse V2 vectors are overridden to apply - * errata mitigation on exception entry from lower ELs. - */ - adr x0, wa_cve_vbar_neoverse_v2 - msr vbar_el3, x0 -#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ - isb - ret -endfunc neoverse_v2_reset_func - -#if REPORT_ERRATA -/* - * Errata printing function for Neoverse V2. Must follow AAPCS. - */ -func neoverse_v2_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960 - - ldp x8, x30, [sp], #16 - ret -endfunc neoverse_v2_errata_report -#endif - +errata_report_shim neoverse_v2 /* --------------------------------------------- * This function provides Neoverse V2- * specific register information for crash
diff --git a/lib/cpus/aarch64/nevis.S b/lib/cpus/aarch64/nevis.S new file mode 100644 index 0000000..36830a9 --- /dev/null +++ b/lib/cpus/aarch64/nevis.S
@@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <nevis.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +cpu_reset_func_start nevis + /* ---------------------------------------------------- + * Disable speculative loads + * ---------------------------------------------------- + */ + msr SSBS, xzr +cpu_reset_func_end nevis + +func nevis_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \ + NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + isb + ret +endfunc nevis_core_pwr_dwn + +errata_report_shim nevis + +.section .rodata.nevis_regs, "aS" +nevis_regs: /* The ASCII list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func nevis_cpu_reg_dump + adr x6, nevis_regs + mrs x8, NEVIS_CPUECTLR_EL1 + ret +endfunc nevis_cpu_reg_dump + +declare_cpu_ops nevis, NEVIS_MIDR, \ + nevis_reset_func, \ + nevis_core_pwr_dwn
diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S index 8948fda..00963bc 100644 --- a/lib/cpus/aarch64/qemu_max.S +++ b/lib/cpus/aarch64/qemu_max.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,14 +47,7 @@ b dcsw_op_all endfunc qemu_max_cluster_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for QEMU "max". Must follow AAPCS. - */ -func qemu_max_errata_report - ret -endfunc qemu_max_errata_report -#endif +errata_report_shim qemu_max /* --------------------------------------------- * This function provides cpu specific
diff --git a/lib/cpus/aarch64/rainier.S b/lib/cpus/aarch64/rainier.S index 3b7b8b2..c770f54 100644 --- a/lib/cpus/aarch64/rainier.S +++ b/lib/cpus/aarch64/rainier.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,78 +41,30 @@ ret endfunc rainier_disable_speculative_loads - /* -------------------------------------------------- - * Errata Workaround for Neoverse N1 Errata #1868343. - * This applies to revision <= r4p0 of Neoverse N1. - * This workaround is the same as the workaround for - * errata 1262606 and 1275112 but applies to a wider - * revision range. - * Rainier R0P0 is based on Neoverse N1 R4P0 so the - * workaround checks for r0p0 version of Rainier CPU. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0, x1 & x17 - * -------------------------------------------------- - */ -func errata_n1_1868343_wa - /* - * Compare x0 against revision r4p0 - */ - mov x17, x30 - bl check_errata_1868343 - cbz x0, 1f - mrs x1, RAINIER_CPUACTLR_EL1 - orr x1, x1, RAINIER_CPUACTLR_EL1_BIT_13 - msr RAINIER_CPUACTLR_EL1, x1 - isb -1: - ret x17 -endfunc errata_n1_1868343_wa + /* Rainier R0P0 is based on Neoverse N1 R4P0. */ +workaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343 + sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13 +workaround_reset_end rainier, ERRATUM(1868343) -func check_errata_1868343 - /* Applies to r0p0 of Rainier CPU */ - mov x1, #0x00 - b cpu_rev_var_ls -endfunc check_errata_1868343 +check_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0) -func rainier_reset_func - mov x19, x30 - +cpu_reset_func_start rainier bl rainier_disable_speculative_loads - /* Forces all cacheable atomic instructions to be near */ - mrs x0, RAINIER_CPUACTLR2_EL1 - orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2 - msr RAINIER_CPUACTLR2_EL1, x0 - isb - - bl cpu_get_rev_var - mov x18, x0 - -#if ERRATA_N1_1868343 - mov x0, x18 - bl errata_n1_1868343_wa -#endif + sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2 #if ENABLE_FEAT_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ - mrs x0, actlr_el3 - orr x0, x0, #RAINIER_ACTLR_AMEN_BIT - msr actlr_el3, x0 + sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ - mrs x0, actlr_el2 - orr x0, x0, #RAINIER_ACTLR_AMEN_BIT - msr actlr_el2, x0 + sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT /* Enable group0 counters */ mov x0, #RAINIER_AMU_GROUP0_MASK msr CPUAMCNTENSET_EL0, x0 #endif - - isb - ret x19 -endfunc rainier_reset_func +cpu_reset_func_end rainier /* --------------------------------------------- * HW will do the cache maintenance while powering down @@ -123,33 +75,12 @@ * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, RAINIER_CPUPWRCTLR_EL1 - orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK - msr RAINIER_CPUPWRCTLR_EL1, x0 + sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK isb ret endfunc rainier_core_pwr_dwn -#if REPORT_ERRATA -/* - * Errata printing function for Rainier. Must follow AAPCS. - */ -func rainier_errata_report - stp x8, x30, [sp, #-16]! - - bl cpu_get_rev_var - mov x8, x0 - - /* - * Report all errata. The revision-variant information is passed to - * checking functions of each errata. - */ - report_errata ERRATA_N1_1868343, rainier, 1868343 - - ldp x8, x30, [sp], #16 - ret -endfunc rainier_errata_report -#endif +errata_report_shim rainier /* --------------------------------------------- * This function provides Rainier specific
diff --git a/lib/cpus/aarch64/travis.S b/lib/cpus/aarch64/travis.S new file mode 100644 index 0000000..2abefe9 --- /dev/null +++ b/lib/cpus/aarch64/travis.S
@@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <travis.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Travis must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +cpu_reset_func_start travis + /* ---------------------------------------------------- + * Disable speculative loads + * ---------------------------------------------------- + */ + msr SSBS, xzr +cpu_reset_func_end travis + +func travis_core_pwr_dwn +#if ENABLE_SME_FOR_NS + /* --------------------------------------------------- + * Disable SME if enabled and supported + * --------------------------------------------------- + */ + mrs x0, ID_AA64PFR1_EL1 + ubfx x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \ + #ID_AA64PFR1_EL1_SME_WIDTH + cmp x0, #ID_AA64PFR1_EL1_SME_NOT_SUPPORTED + b.eq 1f + msr TRAVIS_SVCRSM, xzr + msr TRAVIS_SVCRZA, xzr +1: +#endif + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + sysreg_bit_set TRAVIS_IMP_CPUPWRCTLR_EL1, \ + TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + isb + ret +endfunc travis_core_pwr_dwn + +errata_report_shim travis + +.section .rodata.travis_regs, "aS" +travis_regs: /* The ASCII list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func travis_cpu_reg_dump + adr x6, travis_regs + mrs x8, TRAVIS_IMP_CPUECTLR_EL1 + ret +endfunc travis_cpu_reg_dump + +declare_cpu_ops travis, TRAVIS_MIDR, \ + travis_reset_func, \ + travis_core_pwr_dwn
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S index 0222818..8d9aa5e 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S index ed0a549..823f849 100644 --- a/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S +++ b/lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S index ceb93f1..bf26658 100644 --- a/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S +++ b/lib/cpus/aarch64/wa_cve_2022_23960_bhb.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e16c8e4..434ee08 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk
@@ -352,7 +352,7 @@ CPU_FLAG_LIST += ERRATA_A78_AE_1951502 # Flag to apply erratum 2376748 workaround during reset. This erratum applies -# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. +# to revisions r0p0, r0p1 and r0p2 of the A78 AE cpu. It is still open. CPU_FLAG_LIST += ERRATA_A78_AE_2376748 # Flag to apply erratum 2395408 workaround during reset. This erratum applies @@ -517,7 +517,7 @@ CPU_FLAG_LIST += ERRATA_V1_2216392 # Flag to apply erratum 2294912 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. +# to revisions r0p0, r1p0, and r1p1 and r1p2 of the Neoverse V1 cpu and is still open. CPU_FLAG_LIST += ERRATA_V1_2294912 # Flag to apply erratum 2372203 workaround during reset. This erratum applies @@ -557,7 +557,8 @@ CPU_FLAG_LIST += ERRATA_A710_2083908 # Flag to apply erratum 2058056 workaround during reset. This erratum applies -# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still +# open. CPU_FLAG_LIST += ERRATA_A710_2058056 # Flag to apply erratum 2055002 workaround during reset. This erratum applies @@ -606,57 +607,74 @@ # and is still open. CPU_FLAG_LIST += ERRATA_A710_2701952 +# Flag to apply erratum 2742423 workaround during reset. This erratum applies +# to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still +# open. +CPU_FLAG_LIST += ERRATA_A710_2742423 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is # still open. CPU_FLAG_LIST += ERRATA_A710_2768515 # Flag to apply erratum 2002655 workaround during reset. This erratum applies -# to revisions r0p0 of the Neoverse-N2 cpu, it is still open. +# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2002655 +# Flag to apply erratum 2009478 workaround during powerdown. This erratum +# applies to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1. +CPU_FLAG_LIST += ERRATA_N2_2009478 + # Flag to apply erratum 2067956 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2067956 # Flag to apply erratum 2025414 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2025414 # Flag to apply erratum 2189731 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2189731 # Flag to apply erratum 2138956 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2138956 # Flag to apply erratum 2138953 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open. CPU_FLAG_LIST += ERRATA_N2_2138953 # Flag to apply erratum 2242415 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2242415 # Flag to apply erratum 2138958 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2138958 # Flag to apply erratum 2242400 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2242400 # Flag to apply erratum 2280757 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu and is still open. +# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2280757 -# Flag to apply erraturm 2326639 workaroud during powerdown. This erratum +# Flag to apply erratum 2326639 workaroud during powerdown. This erratum # applies to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_N2_2326639 +# Flag to apply erratum 2340933 workaroud during reset. This erratum +# applies to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1. +CPU_FLAG_LIST += ERRATA_N2_2340933 + +# Flag to apply erratum 2346952 workaround during reset. This erratum applies +# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. +CPU_FLAG_LIST += ERRATA_N2_2346952 + # Flag to apply erratum 2376738 workaround during reset. This erratum applies -# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1. +# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open. CPU_FLAG_LIST += ERRATA_N2_2376738 # Flag to apply erratum 2388450 workaround during reset. This erratum applies @@ -668,16 +686,24 @@ # r0p3. CPU_FLAG_LIST += ERRATA_N2_2728475 +# Flag to apply erratum 2743014 workaround during reset. This erratum applies +# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. +CPU_FLAG_LIST += ERRATA_N2_2743014 + # Flag to apply erratum 2743089 workaround during during powerdown. This erratum # applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. CPU_FLAG_LIST += ERRATA_N2_2743089 +# Flag to apply erratum 2779511 workaround during reset. This erratum applies +# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3. +CPU_FLAG_LIST += ERRATA_N2_2779511 + # Flag to apply erratum 2002765 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_2002765 # Flag to apply erratum 2058056 workaround during reset. This erratum applies -# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open. +# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open. CPU_FLAG_LIST += ERRATA_X2_2058056 # Flag to apply erratum 2083908 workaround during reset. This erratum applies @@ -717,11 +743,20 @@ # and is still open. CPU_FLAG_LIST += ERRATA_X2_2701952 +# Flag to apply erratum 2742423 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open. +CPU_FLAG_LIST += ERRATA_X2_2742423 + # Flag to apply erratum 2768515 workaround during power down. This erratum # applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is # still open. CPU_FLAG_LIST += ERRATA_X2_2768515 +# Flag to apply erratum 2070301 workaround on reset. This erratum applies +# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is +# still open. +CPU_FLAG_LIST += ERRATA_X3_2070301 + # Flag to apply erratum 2313909 workaround on powerdown. This erratum applies # to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1. CPU_FLAG_LIST += ERRATA_X3_2313909 @@ -730,6 +765,10 @@ # to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open. CPU_FLAG_LIST += ERRATA_X3_2615812 +# Flag to apply erratum 2742421 workaround on reset. This erratum applies +# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2. +CPU_FLAG_LIST += ERRATA_X3_2742421 + # Flag to apply erratum 1922240 workaround during reset. This erratum applies # to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1. CPU_FLAG_LIST += ERRATA_A510_1922240 @@ -748,6 +787,11 @@ # present in r0p0 and r0p1 but there is no workaround for those revisions. CPU_FLAG_LIST += ERRATA_A510_2041909 +# Flag to aply erratum 2080326 workaround during reset. This erratum applies +# to revision r0p2 of the Cortex-A510 cpu and is fixed in r0p3. The issue is +# also present in r0p0 and r0p1 but there is no workaround for those revisions. +CPU_FLAG_LIST += ERRATA_A510_2080326 + # Flag to apply erratum 2250311 workaround during reset. This erratum applies # to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1. CPU_FLAG_LIST += ERRATA_A510_2250311 @@ -778,10 +822,30 @@ # Cortex-A510 cpu and is fixed in r1p3. CPU_FLAG_LIST += ERRATA_A510_2684597 +# Flag to apply erratum 2331132 workaround during reset. This erratum applies +# to revisions r0p0, r0p1 and r0p2. It is still open. +CPU_FLAG_LIST += ERRATA_V2_2331132 + # Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This # erratum applies to revisions r0p0, rop1. Fixed in r0p2. CPU_FLAG_LIST += ERRATA_V2_2719103 +# Flag to apply erratum 2719105 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1. It is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2719105 + +# Flag to apply erratum 2743011 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1. It is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2743011 + +# Flag to apply erratum 2779510 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1. It is fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2779510 + +# Flag to apply erratum 2801372 workaround for all configurations. +# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2. +CPU_FLAG_LIST += ERRATA_V2_2801372 + # Flag to apply erratum 2701951 workaround for non-arm interconnect ip. # This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2. CPU_FLAG_LIST += ERRATA_A715_2701951
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index 5f41aee..4e9bdfc 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,7 +11,8 @@ #include <arch_helpers.h> #include <common/debug.h> -#include <lib/cpus/errata_report.h> +#include <lib/cpus/cpu_ops.h> +#include <lib/cpus/errata.h> #include <lib/el3_runtime/cpu_data.h> #include <lib/spinlock.h> @@ -30,11 +31,106 @@ /* Errata format: BL stage, CPU, errata ID, message */ #define ERRATA_FORMAT "%s: %s: CPU workaround for %s was %s\n" +#define CVE_FORMAT "%s: %s: CPU workaround for CVE %u_%u was %s\n" +#define ERRATUM_FORMAT "%s: %s: CPU workaround for erratum %u was %s\n" + + +static __unused void print_status(int status, char *cpu_str, uint16_t cve, uint32_t id) +{ + if (status == ERRATA_MISSING) { + if (cve) { + WARN(CVE_FORMAT, BL_STRING, cpu_str, cve, id, "missing!"); + } else { + WARN(ERRATUM_FORMAT, BL_STRING, cpu_str, id, "missing!"); + } + } else if (status == ERRATA_APPLIES) { + if (cve) { + INFO(CVE_FORMAT, BL_STRING, cpu_str, cve, id, "applied"); + } else { + INFO(ERRATUM_FORMAT, BL_STRING, cpu_str, id, "applied"); + } + } else { + if (cve) { + VERBOSE(CVE_FORMAT, BL_STRING, cpu_str, cve, id, "not applied"); + } else { + VERBOSE(ERRATUM_FORMAT, BL_STRING, cpu_str, id, "not applied"); + } + } +} + +#if !REPORT_ERRATA +void print_errata_status(void) {} +#else /* !REPORT_ERRATA */ +/* + * New errata status message printer + * The order checking function is hidden behind the FEATURE_DETECTION flag to + * save space. This functionality is only useful on development and platform + * bringup builds, when FEATURE_DETECTION should be used anyway + */ +void __unused generic_errata_report(void) +{ + struct cpu_ops *cpu_ops = get_cpu_ops_ptr(); + struct erratum_entry *entry = cpu_ops->errata_list_start; + struct erratum_entry *end = cpu_ops->errata_list_end; + long rev_var = cpu_get_rev_var(); +#if FEATURE_DETECTION + uint32_t last_erratum_id = 0; + uint16_t last_cve_yr = 0; + bool check_cve = false; + bool failed = false; +#endif /* FEATURE_DETECTION */ + + for (; entry != end; entry += 1) { + uint64_t status = entry->check_func(rev_var); + + assert(entry->id != 0); + + /* + * Errata workaround has not been compiled in. If the errata + * would have applied had it been compiled in, print its status + * as missing. + */ + if (status == ERRATA_APPLIES && entry->chosen == 0) { + status = ERRATA_MISSING; + } + + print_status(status, cpu_ops->cpu_str, entry->cve, entry->id); + +#if FEATURE_DETECTION + if (entry->cve) { + if (last_cve_yr > entry->cve || + (last_cve_yr == entry->cve && last_erratum_id >= entry->id)) { + ERROR("CVE %u_%u was out of order!\n", + entry->cve, entry->id); + failed = true; + } + check_cve = true; + last_cve_yr = entry->cve; + } else { + if (last_erratum_id >= entry->id || check_cve) { + ERROR("Erratum %u was out of order!\n", + entry->id); + failed = true; + } + } + last_erratum_id = entry->id; +#endif /* FEATURE_DETECTION */ + } + +#if FEATURE_DETECTION + /* + * enforce errata and CVEs are in ascending order and that CVEs are + * after errata + */ + assert(!failed); +#endif /* FEATURE_DETECTION */ +} + /* * Returns whether errata needs to be reported. Passed arguments are private to * a CPU type. */ -int errata_needs_reporting(spinlock_t *lock, uint32_t *reported) +static __unused int errata_needs_reporting(spinlock_t *lock, uint32_t *reported) { bool report_now; @@ -56,14 +152,44 @@ } /* - * Print errata status message. - * - * Unknown: WARN - * Missing: WARN - * Applied: INFO - * Not applied: VERBOSE + * Function to print errata status for the calling CPU (and others of the same + * type). Must be called only: + * - when MMU and data caches are enabled; + * - after cpu_ops have been initialized in per-CPU data. */ -void errata_print_msg(unsigned int status, const char *cpu, const char *id) +void print_errata_status(void) +{ + struct cpu_ops *cpu_ops; +#ifdef IMAGE_BL1 + /* + * BL1 doesn't have per-CPU data. So retrieve the CPU operations + * directly. + */ + cpu_ops = get_cpu_ops_ptr(); + + if (cpu_ops->errata_func != NULL) { + cpu_ops->errata_func(); + } +#else /* IMAGE_BL1 */ + cpu_ops = (void *) get_cpu_data(cpu_ops_ptr); + + assert(cpu_ops != NULL); + + if (cpu_ops->errata_func == NULL) { + return; + } + + if (errata_needs_reporting(cpu_ops->errata_lock, cpu_ops->errata_reported)) { + cpu_ops->errata_func(); + } +#endif /* IMAGE_BL1 */ +} + +/* + * Old errata status message printer + * TODO: remove once all cpus have been converted to the new printing method + */ +void __unused errata_print_msg(unsigned int status, const char *cpu, const char *id) { /* Errata status strings */ static const char *const errata_status_str[] = { @@ -99,3 +225,4 @@ break; } } +#endif /* !REPORT_ERRATA */
diff --git a/lib/debugfs/debugfs.mk b/lib/debugfs/debugfs.mk index 138fc72..caa9fcf 100644 --- a/lib/debugfs/debugfs.mk +++ b/lib/debugfs/debugfs.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/debugfs/debugfs_smc.c b/lib/debugfs/debugfs_smc.c index 13ced3d..64c64f8 100644 --- a/lib/debugfs/debugfs_smc.c +++ b/lib/debugfs/debugfs_smc.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 62e30fc..b60b8e0 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,6 +17,7 @@ #include <context.h> #include <lib/el3_runtime/context_mgmt.h> #include <lib/extensions/amu.h> +#include <lib/extensions/pmuv3.h> #include <lib/extensions/sys_reg_trace.h> #include <lib/extensions/trf.h> #include <lib/utils.h> @@ -141,13 +142,19 @@ } if (is_feat_sys_reg_trace_supported()) { - sys_reg_trace_enable(); + sys_reg_trace_init_el3(); } if (is_feat_trf_supported()) { - trf_enable(); + trf_init_el3(); } -#endif + + /* + * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure + * state execution. This does not affect lower NS ELs. + */ + pmuv3_init_el3(); +#endif /* IMAGE_BL32 */ } /*******************************************************************************
diff --git a/lib/el3_runtime/aarch32/cpu_data.S b/lib/el3_runtime/aarch32/cpu_data.S index bdad2c1..e59b7fd 100644 --- a/lib/el3_runtime/aarch32/cpu_data.S +++ b/lib/el3_runtime/aarch32/cpu_data.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 9922fb1..631094f 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S
@@ -10,15 +10,6 @@ #include <context.h> #include <el3_common_macros.S> -#if CTX_INCLUDE_EL2_REGS - .global el2_sysregs_context_save_common - .global el2_sysregs_context_restore_common -#if CTX_INCLUDE_MTE_REGS - .global el2_sysregs_context_save_mte - .global el2_sysregs_context_restore_mte -#endif /* CTX_INCLUDE_MTE_REGS */ -#endif /* CTX_INCLUDE_EL2_REGS */ - .global el1_sysregs_context_save .global el1_sysregs_context_restore #if CTX_INCLUDE_FPREGS @@ -30,183 +21,6 @@ .global save_and_update_ptw_el1_sys_regs .global el3_exit -#if CTX_INCLUDE_EL2_REGS - -/* ----------------------------------------------------- - * The following functions strictly follow the AArch64 - * PCS to use x9-x16 (temporary caller-saved registers) - * to save/restore EL2 system register context. - * el2_sysregs_context_save/restore_common functions - * save and restore registers that are common to all - * configurations. The rest of the functions save and - * restore EL2 system registers that are present when a - * particular feature is enabled. All functions assume - * that 'x0' is pointing to a 'el2_sys_regs' structure - * where the register context will be saved/restored. - * - * The following registers are not added. - * AMEVCNTVOFF0<n>_EL2 - * AMEVCNTVOFF1<n>_EL2 - * ICH_AP0R<n>_EL2 - * ICH_AP1R<n>_EL2 - * ICH_LR<n>_EL2 - * ----------------------------------------------------- - */ -func el2_sysregs_context_save_common - mrs x9, actlr_el2 - mrs x10, afsr0_el2 - stp x9, x10, [x0, #CTX_ACTLR_EL2] - - mrs x11, afsr1_el2 - mrs x12, amair_el2 - stp x11, x12, [x0, #CTX_AFSR1_EL2] - - mrs x13, cnthctl_el2 - mrs x14, cntvoff_el2 - stp x13, x14, [x0, #CTX_CNTHCTL_EL2] - - mrs x15, cptr_el2 - str x15, [x0, #CTX_CPTR_EL2] - -#if CTX_INCLUDE_AARCH32_REGS - mrs x16, dbgvcr32_el2 - str x16, [x0, #CTX_DBGVCR32_EL2] -#endif /* CTX_INCLUDE_AARCH32_REGS */ - - mrs x9, elr_el2 - mrs x10, esr_el2 - stp x9, x10, [x0, #CTX_ELR_EL2] - - mrs x11, far_el2 - mrs x12, hacr_el2 - stp x11, x12, [x0, #CTX_FAR_EL2] - - mrs x13, hcr_el2 - mrs x14, hpfar_el2 - stp x13, x14, [x0, #CTX_HCR_EL2] - - mrs x15, hstr_el2 - mrs x16, ICC_SRE_EL2 - stp x15, x16, [x0, #CTX_HSTR_EL2] - - mrs x9, ICH_HCR_EL2 - mrs x10, ICH_VMCR_EL2 - stp x9, x10, [x0, #CTX_ICH_HCR_EL2] - - mrs x11, mair_el2 - mrs x12, mdcr_el2 - stp x11, x12, [x0, #CTX_MAIR_EL2] - - mrs x14, sctlr_el2 - str x14, [x0, #CTX_SCTLR_EL2] - - mrs x15, spsr_el2 - mrs x16, sp_el2 - stp x15, x16, [x0, #CTX_SPSR_EL2] - - mrs x9, tcr_el2 - mrs x10, tpidr_el2 - stp x9, x10, [x0, #CTX_TCR_EL2] - - mrs x11, ttbr0_el2 - mrs x12, vbar_el2 - stp x11, x12, [x0, #CTX_TTBR0_EL2] - - mrs x13, vmpidr_el2 - mrs x14, vpidr_el2 - stp x13, x14, [x0, #CTX_VMPIDR_EL2] - - mrs x15, vtcr_el2 - mrs x16, vttbr_el2 - stp x15, x16, [x0, #CTX_VTCR_EL2] - ret -endfunc el2_sysregs_context_save_common - -func el2_sysregs_context_restore_common - ldp x9, x10, [x0, #CTX_ACTLR_EL2] - msr actlr_el2, x9 - msr afsr0_el2, x10 - - ldp x11, x12, [x0, #CTX_AFSR1_EL2] - msr afsr1_el2, x11 - msr amair_el2, x12 - - ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] - msr cnthctl_el2, x13 - msr cntvoff_el2, x14 - - ldr x15, [x0, #CTX_CPTR_EL2] - msr cptr_el2, x15 - -#if CTX_INCLUDE_AARCH32_REGS - ldr x16, [x0, #CTX_DBGVCR32_EL2] - msr dbgvcr32_el2, x16 -#endif /* CTX_INCLUDE_AARCH32_REGS */ - - ldp x9, x10, [x0, #CTX_ELR_EL2] - msr elr_el2, x9 - msr esr_el2, x10 - - ldp x11, x12, [x0, #CTX_FAR_EL2] - msr far_el2, x11 - msr hacr_el2, x12 - - ldp x13, x14, [x0, #CTX_HCR_EL2] - msr hcr_el2, x13 - msr hpfar_el2, x14 - - ldp x15, x16, [x0, #CTX_HSTR_EL2] - msr hstr_el2, x15 - msr ICC_SRE_EL2, x16 - - ldp x9, x10, [x0, #CTX_ICH_HCR_EL2] - msr ICH_HCR_EL2, x9 - msr ICH_VMCR_EL2, x10 - - ldp x11, x12, [x0, #CTX_MAIR_EL2] - msr mair_el2, x11 - msr mdcr_el2, x12 - - ldr x14, [x0, #CTX_SCTLR_EL2] - msr sctlr_el2, x14 - - ldp x15, x16, [x0, #CTX_SPSR_EL2] - msr spsr_el2, x15 - msr sp_el2, x16 - - ldp x9, x10, [x0, #CTX_TCR_EL2] - msr tcr_el2, x9 - msr tpidr_el2, x10 - - ldp x11, x12, [x0, #CTX_TTBR0_EL2] - msr ttbr0_el2, x11 - msr vbar_el2, x12 - - ldp x13, x14, [x0, #CTX_VMPIDR_EL2] - msr vmpidr_el2, x13 - msr vpidr_el2, x14 - - ldp x15, x16, [x0, #CTX_VTCR_EL2] - msr vtcr_el2, x15 - msr vttbr_el2, x16 - ret -endfunc el2_sysregs_context_restore_common - -#if CTX_INCLUDE_MTE_REGS -func el2_sysregs_context_save_mte - mrs x9, TFSR_EL2 - str x9, [x0, #CTX_TFSR_EL2] - ret -endfunc el2_sysregs_context_save_mte - -func el2_sysregs_context_restore_mte - ldr x9, [x0, #CTX_TFSR_EL2] - msr TFSR_EL2, x9 - ret -endfunc el2_sysregs_context_restore_mte -#endif /* CTX_INCLUDE_MTE_REGS */ - -#endif /* CTX_INCLUDE_EL2_REGS */ /* ------------------------------------------------------------------ * The following function strictly follows the AArch64 PCS to use @@ -536,6 +350,43 @@ #endif /* ENABLE_FEAT_DIT */ .endm /* set_unset_pstate_bits */ +/*------------------------------------------------------------------------- + * This macro checks the ENABLE_FEAT_MPAM state, performs ID register + * check to see if the platform supports MPAM extension and restores MPAM3 + * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED. + * + * This is particularly more complicated because we can't check + * if the platform supports MPAM by looking for status of a particular bit + * in the MDCR_EL3 or CPTR_EL3 register like other extensions. + * ------------------------------------------------------------------------ + */ + + .macro restore_mpam3_el3 +#if ENABLE_FEAT_MPAM +#if ENABLE_FEAT_MPAM == 2 + + mrs x8, id_aa64pfr0_el1 + lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT) + and x8, x8, #(ID_AA64PFR0_MPAM_MASK) + mrs x7, id_aa64pfr1_el1 + lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT) + and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK) + orr x7, x7, x8 + cbz x7, no_mpam +#endif + /* ----------------------------------------------------------- + * Restore MPAM3_EL3 register as per context state + * Currently we only enable MPAM for NS world and trap to EL3 + * for MPAM access in lower ELs of Secure and Realm world + * ----------------------------------------------------------- + */ + ldr x17, [sp, #CTX_EL3STATE_OFFSET + CTX_MPAM3_EL3] + msr S3_6_C10_C5_0, x17 /* mpam3_el3 */ + +no_mpam: +#endif + .endm /* restore_mpam3_el3 */ + /* ------------------------------------------------------------------ * The following macro is used to save and restore all the general * purpose and ARMv8.3-PAuth (if enabled) registers. @@ -568,6 +419,8 @@ stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] mrs x18, sp_el0 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] + + /* PMUv3 is presumed to be always present */ mrs x9, pmcr_el0 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] /* Disable cycle counter when event counting is prohibited */ @@ -651,6 +504,8 @@ msr APGAKeyLo_EL1, x8 msr APGAKeyHi_EL1, x9 #endif /* CTX_INCLUDE_PAUTH_REGS */ + + /* PMUv3 is presumed to be always present */ ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] msr pmcr_el0, x0 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] @@ -715,6 +570,25 @@ ret endfunc save_and_update_ptw_el1_sys_regs +/* ----------------------------------------------------------------- +* The below macro returns the address of the per_world context for +* the security state, retrieved through "get_security_state" macro. +* The per_world context address is returned in the register argument. +* Clobbers: x9, x10 +* ------------------------------------------------------------------ +*/ + +.macro get_per_world_context _reg:req + ldr x10, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + get_security_state x9, x10 + mov_imm x10, (CTX_GLOBAL_EL3STATE_END - CTX_CPTR_EL3) + mul x9, x9, x10 + adrp x10, per_world_context + add x10, x10, :lo12:per_world_context + add x9, x9, x10 + mov \_reg, x9 +.endm + /* ------------------------------------------------------------------ * This routine assumes that the SP_EL3 is pointing to a valid * context structure from where the gp regs and other special @@ -739,22 +613,29 @@ msr spsel, #MODE_SP_ELX str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] -#if IMAGE_BL31 /* ---------------------------------------------------------- * Restore CPTR_EL3. * ZCR is only restored if SVE is supported and enabled. * Synchronization is required before zcr_el3 is addressed. * ---------------------------------------------------------- */ - ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3] + + /* The address of the per_world context is stored in x9 */ + get_per_world_context x9 + + ldp x19, x20, [x9, #CTX_CPTR_EL3] msr cptr_el3, x19 +#if IMAGE_BL31 ands x19, x19, #CPTR_EZ_BIT beq sve_not_enabled isb msr S3_6_C1_C2_0, x20 /* zcr_el3 */ sve_not_enabled: + + restore_mpam3_el3 + #endif /* IMAGE_BL31 */ #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 @@ -768,23 +649,9 @@ 1: #endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */ -/* - * This is a hot path, so we don't want to do some actual FEAT_RAS runtime - * detection here. The "esb" is a cheaper variant, so using "dsb" in the - * ENABLE_FEAT_RAS==2 case is not ideal, but won't hurt. - */ -#if IMAGE_BL31 && ENABLE_FEAT_RAS == 1 - /* ---------------------------------------------------------- - * Issue Error Synchronization Barrier to synchronize SErrors - * before exiting EL3. We're running with EAs unmasked, so - * any synchronized errors would be taken immediately; - * therefore no need to inspect DISR_EL1 register. - * ---------------------------------------------------------- - */ - esb -#else - dsb sy -#endif /* IMAGE_BL31 && ENABLE_FEAT_RAS */ +#if IMAGE_BL31 + synchronize_errors +#endif /* IMAGE_BL31 */ /* ---------------------------------------------------------- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET @@ -808,7 +675,8 @@ ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] #ifdef IMAGE_BL31 - str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3] + /* Clear the EL3 flag as we are exiting el3 */ + str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG] #endif /* IMAGE_BL31 */ exception_return
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 3760b8f..fdd1388 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -20,10 +20,12 @@ #include <context.h> #include <drivers/arm/gicv3.h> #include <lib/el3_runtime/context_mgmt.h> +#include <lib/el3_runtime/cpu_data.h> #include <lib/el3_runtime/pubsub_events.h> #include <lib/extensions/amu.h> #include <lib/extensions/brbe.h> #include <lib/extensions/mpam.h> +#include <lib/extensions/pmuv3.h> #include <lib/extensions/sme.h> #include <lib/extensions/spe.h> #include <lib/extensions/sve.h> @@ -37,7 +39,12 @@ CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); #endif /* ENABLE_FEAT_TWED */ +per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; +static bool has_secure_perworld_init; + +static void manage_extensions_nonsecure(cpu_context_t *ctx); static void manage_extensions_secure(cpu_context_t *ctx); +static void manage_extensions_secure_per_world(void); static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) { @@ -133,16 +140,6 @@ } #endif /* CTX_INCLUDE_MTE_REGS */ - /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ - if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { - if (GET_RW(ep->spsr) != MODE_RW_64) { - ERROR("S-EL2 can not be used in AArch32\n."); - panic(); - } - - scr_el3 |= SCR_EEL2_BIT; - } - write_ctx_reg(state, CTX_SCR_EL3, scr_el3); /* @@ -154,6 +151,18 @@ #endif manage_extensions_secure(ctx); + + /** + * manage_extensions_secure_per_world api has to be executed once, + * as the registers getting initialised, maintain constant value across + * all the cpus for the secure world. + * Henceforth, this check ensures that the registers are initialised once + * and avoids re-initialization from multiple cores. + */ + if (!has_secure_perworld_init) { + manage_extensions_secure_per_world(); + } + } #if ENABLE_RME @@ -195,22 +204,34 @@ /* SCR_NS: Set the NS bit */ scr_el3 |= SCR_NS_BIT; -#if !CTX_INCLUDE_PAUTH_REGS - /* - * If the pointer authentication registers aren't saved during world - * switches the value of the registers can be leaked from the Secure to - * the Non-secure world. To prevent this, rather than enabling pointer - * authentication everywhere, we only enable it in the Non-secure world. - * - * If the Secure world wants to use pointer authentication, - * CTX_INCLUDE_PAUTH_REGS must be set to 1. - */ - scr_el3 |= SCR_API_BIT | SCR_APK_BIT; -#endif /* !CTX_INCLUDE_PAUTH_REGS */ - /* Allow access to Allocation Tags when MTE is implemented. */ scr_el3 |= SCR_ATA_BIT; +#if !CTX_INCLUDE_PAUTH_REGS + /* + * Pointer Authentication feature, if present, is always enabled by default + * for Non secure lower exception levels. We do not have an explicit + * flag to set it. + * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower + * exception levels of secure and realm worlds. + * + * To prevent the leakage between the worlds during world switch, + * we enable it only for the non-secure world. + * + * If the Secure/realm world wants to use pointer authentication, + * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case + * it will be enabled globally for all the contexts. + * + * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs + * other than EL3 + * + * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other + * than EL3 + */ + scr_el3 |= SCR_API_BIT | SCR_APK_BIT; + +#endif /* CTX_INCLUDE_PAUTH_REGS */ + #if HANDLE_EA_EL3_FIRST_NS /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ scr_el3 |= SCR_EA_BIT; @@ -256,25 +277,6 @@ write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, sctlr_el2); - /* - * Program the ICC_SRE_EL2 to make sure the correct bits are set - * when restoring NS context. - */ - u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | - ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; - write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, - icc_sre_el2); - - /* - * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't - * throw anyone off who expects this to be sensible. - * TODO: A similar thing happens in cm_prepare_el3_exit. They should be - * unified with the proper PMU implementation - */ - u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & - PMCR_EL0_N_MASK); - write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); - if (is_feat_hcx_supported()) { /* * Initialize register HCRX_EL2 with its init value. @@ -287,7 +289,23 @@ write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, HCRX_EL2_INIT_VAL); } + + if (is_feat_fgt_supported()) { + /* + * Initialize HFG*_EL2 registers with a default value so legacy + * systems unaware of FEAT_FGT do not get trapped due to their lack + * of initialization for this feature. + */ + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, + HFGITR_EL2_INIT_VAL); + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, + HFGRTR_EL2_INIT_VAL); + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, + HFGWTR_EL2_INIT_VAL); + } #endif /* CTX_INCLUDE_EL2_REGS */ + + manage_extensions_nonsecure(ctx); } /******************************************************************************* @@ -304,21 +322,48 @@ el3_state_t *state; gp_regs_t *gp_regs; + state = get_el3state_ctx(ctx); + /* Clear any residual register values from the context */ zeromem(ctx, sizeof(*ctx)); /* - * SCR_EL3 was initialised during reset sequence in macro - * el3_arch_init_common. This code modifies the SCR_EL3 fields that - * affect the next EL. - * - * The following fields are initially set to zero and then updated to - * the required value depending on the state of the SPSR_EL3 and the - * Security state and entrypoint attributes of the next EL. + * The lower-EL context is zeroed so that no stale values leak to a world. + * It is assumed that an all-zero lower-EL context is good enough for it + * to boot correctly. However, there are very few registers where this + * is not true and some values need to be recreated. */ - scr_el3 = read_scr(); - scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | - SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); +#if CTX_INCLUDE_EL2_REGS + el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); + + /* + * These bits are set in the gicv3 driver. Losing them (especially the + * SRE bit) is problematic for all worlds. Henceforth recreate them. + */ + u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | + ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; + write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); +#endif /* CTX_INCLUDE_EL2_REGS */ + + /* Start with a clean SCR_EL3 copy as all relevant values are set */ + scr_el3 = SCR_RESET_VAL; + + /* + * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at + * EL2, EL1 and EL0 are not trapped to EL3. + * + * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at + * EL2, EL1 and EL0 are not trapped to EL3. + * + * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from + * both Security states and both Execution states. + * + * SCR_EL3.SIF: Set to one to disable secure instruction execution from + * Non-secure memory. + */ + scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); + + scr_el3 |= SCR_SIF_BIT; /* * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next @@ -360,6 +405,19 @@ scr_el3 |= SCR_FIEN_BIT; #endif +#if CTX_INCLUDE_PAUTH_REGS + /* + * Enable Pointer Authentication globally for all the worlds. + * + * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs + * other than EL3 + * + * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other + * than EL3 + */ + scr_el3 |= SCR_API_BIT | SCR_APK_BIT; +#endif /* CTX_INCLUDE_PAUTH_REGS */ + /* * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. */ @@ -383,12 +441,6 @@ } /* - * CPTR_EL3 was initialized out of reset, copy that value to the - * context register. - */ - write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); - - /* * SCR_EL3.HCE: Enable HVC instructions if next execution state is * AArch64 and next EL is EL2, or if next execution state is AArch32 and * next mode is Hyp. @@ -424,11 +476,22 @@ scr_el3 |= SCR_TWEDEn_BIT; } +#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 + /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ + if (is_feat_sel2_supported()) { + scr_el3 |= SCR_EEL2_BIT; + } +#endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ + + if (is_feat_mpam_supported()) { + write_ctx_reg(get_el3state_ctx(ctx), CTX_MPAM3_EL3, \ + MPAM3_EL3_RESET_VAL); + } + /* * Populate EL3 state so that we've the right context * before doing ERET */ - state = get_el3state_ctx(ctx); write_ctx_reg(state, CTX_SCR_EL3, scr_el3); write_ctx_reg(state, CTX_ELR_EL3, ep->pc); write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); @@ -502,24 +565,125 @@ } /******************************************************************************* - * Enable architecture extensions on first entry to Non-secure world. - * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise - * it is zero. + * Enable architecture extensions for EL3 execution. This function only updates + * registers in-place which are expected to either never change or be + * overwritten by el3_exit. ******************************************************************************/ -static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) -{ #if IMAGE_BL31 +void cm_manage_extensions_el3(void) +{ if (is_feat_spe_supported()) { - spe_enable(el2_unused); + spe_init_el3(); } if (is_feat_amu_supported()) { - amu_enable(el2_unused, ctx); + amu_init_el3(); } - /* Enable SVE and FPU/SIMD */ + if (is_feat_sme_supported()) { + sme_init_el3(); + } + + if (is_feat_trbe_supported()) { + trbe_init_el3(); + } + + if (is_feat_brbe_supported()) { + brbe_init_el3(); + } + + if (is_feat_trf_supported()) { + trf_init_el3(); + } + + pmuv3_init_el3(); +} +#endif /* IMAGE_BL31 */ + +/******************************************************************************* + * Initialise per_world_context for Non-Secure world. + * This function enables the architecture extensions, which have same value + * across the cores for the non-secure world. + ******************************************************************************/ +#if IMAGE_BL31 +void manage_extensions_nonsecure_per_world(void) +{ + if (is_feat_sme_supported()) { + sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); + } + if (is_feat_sve_supported()) { - sve_enable(ctx); + sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); + } + + if (is_feat_amu_supported()) { + amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); + } + + if (is_feat_sys_reg_trace_supported()) { + sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); + } +} +#endif /* IMAGE_BL31 */ + +/******************************************************************************* + * Initialise per_world_context for Secure world. + * This function enables the architecture extensions, which have same value + * across the cores for the secure world. + ******************************************************************************/ + +static void manage_extensions_secure_per_world(void) +{ +#if IMAGE_BL31 + if (is_feat_sme_supported()) { + + if (ENABLE_SME_FOR_SWD) { + /* + * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure + * SME, SVE, and FPU/SIMD context properly managed. + */ + sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); + } else { + /* + * Disable SME, SVE, FPU/SIMD in secure context so non-secure + * world can safely use the associated registers. + */ + sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); + } + } + if (is_feat_sve_supported()) { + if (ENABLE_SVE_FOR_SWD) { + /* + * Enable SVE and FPU in secure context, SPM must ensure + * that the SVE and FPU register contexts are properly managed. + */ + sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); + } else { + /* + * Disable SVE and FPU in secure context so non-secure world + * can safely use them. + */ + sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); + } + } + + /* NS can access this but Secure shouldn't */ + if (is_feat_sys_reg_trace_supported()) { + sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); + } + + has_secure_perworld_init = true; +#endif /* IMAGE_BL31 */ +} + +/******************************************************************************* + * Enable architecture extensions on first entry to Non-secure world. + ******************************************************************************/ +static void manage_extensions_nonsecure(cpu_context_t *ctx) +{ +#if IMAGE_BL31 + if (is_feat_amu_supported()) { + amu_enable(ctx); } if (is_feat_sme_supported()) { @@ -527,26 +691,74 @@ } if (is_feat_mpam_supported()) { - mpam_enable(el2_unused); + mpam_enable(ctx); + } + pmuv3_enable(ctx); +#endif /* IMAGE_BL31 */ +} + +/* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ +static __unused void enable_pauth_el2(void) +{ + u_register_t hcr_el2 = read_hcr_el2(); + /* + * For Armv8.3 pointer authentication feature, disable traps to EL2 when + * accessing key registers or using pointer authentication instructions + * from lower ELs. + */ + hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); + + write_hcr_el2(hcr_el2); +} + +#if INIT_UNUSED_NS_EL2 +/******************************************************************************* + * Enable architecture extensions in-place at EL2 on first entry to Non-secure + * world when EL2 is empty and unused. + ******************************************************************************/ +static void manage_extensions_nonsecure_el2_unused(void) +{ +#if IMAGE_BL31 + if (is_feat_spe_supported()) { + spe_init_el2_unused(); + } + + if (is_feat_amu_supported()) { + amu_init_el2_unused(); + } + + if (is_feat_mpam_supported()) { + mpam_init_el2_unused(); } if (is_feat_trbe_supported()) { - trbe_enable(); - } - - if (is_feat_brbe_supported()) { - brbe_enable(); + trbe_init_el2_unused(); } if (is_feat_sys_reg_trace_supported()) { - sys_reg_trace_enable(ctx); + sys_reg_trace_init_el2_unused(); } if (is_feat_trf_supported()) { - trf_enable(); + trf_init_el2_unused(); } -#endif + + pmuv3_init_el2_unused(); + + if (is_feat_sve_supported()) { + sve_init_el2_unused(); + } + + if (is_feat_sme_supported()) { + sme_init_el2_unused(); + } + +#if ENABLE_PAUTH + enable_pauth_el2(); +#endif /* ENABLE_PAUTH */ +#endif /* IMAGE_BL31 */ } +#endif /* INIT_UNUSED_NS_EL2 */ /******************************************************************************* * Enable architecture extensions on first entry to Secure world. @@ -554,29 +766,13 @@ static void manage_extensions_secure(cpu_context_t *ctx) { #if IMAGE_BL31 - if (is_feat_sve_supported()) { - if (ENABLE_SVE_FOR_SWD) { - /* - * Enable SVE and FPU in secure context, secure manager must - * ensure that the SVE and FPU register contexts are properly - * managed. - */ - sve_enable(ctx); - } else { - /* - * Disable SVE and FPU in secure context so non-secure world - * can safely use them. - */ - sve_disable(ctx); - } - } - if (is_feat_sme_supported()) { if (ENABLE_SME_FOR_SWD) { /* * Enable SME, SVE, FPU/SIMD in secure context, secure manager * must ensure SME, SVE, and FPU/SIMD context properly managed. */ + sme_init_el3(); sme_enable(ctx); } else { /* @@ -614,6 +810,111 @@ cm_setup_context(ctx, ep); } +/* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ +static void init_nonsecure_el2_unused(cpu_context_t *ctx) +{ +#if INIT_UNUSED_NS_EL2 + u_register_t hcr_el2 = HCR_RESET_VAL; + u_register_t mdcr_el2; + u_register_t scr_el3; + + scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); + + /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ + if ((scr_el3 & SCR_RW_BIT) != 0U) { + hcr_el2 |= HCR_RW_BIT; + } + + write_hcr_el2(hcr_el2); + + /* + * Initialise CPTR_EL2 setting all fields rather than relying on the hw. + * All fields have architecturally UNKNOWN reset values. + */ + write_cptr_el2(CPTR_EL2_RESET_VAL); + + /* + * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on + * reset and are set to zero except for field(s) listed below. + * + * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of + * Non-secure EL0 and EL1 accesses to the physical timer registers. + * + * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of + * Non-secure EL0 and EL1 accesses to the physical counter registers. + */ + write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); + + /* + * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally + * UNKNOWN value. + */ + write_cntvoff_el2(0); + + /* + * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 + * respectively. + */ + write_vpidr_el2(read_midr_el1()); + write_vmpidr_el2(read_mpidr_el1()); + + /* + * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. + * + * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address + * translation is disabled, cache maintenance operations depend on the + * VMID. + * + * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is + * disabled. + */ + write_vttbr_el2(VTTBR_RESET_VAL & + ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | + (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); + + /* + * Initialise MDCR_EL2, setting all fields rather than relying on hw. + * Some fields are architecturally UNKNOWN on reset. + * + * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System + * register accesses to the Debug ROM registers are not trapped to EL2. + * + * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register + * accesses to the powerdown debug registers are not trapped to EL2. + * + * MDCR_EL2.TDA: Set to zero so that System register accesses to the + * debug registers do not trap to EL2. + * + * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to + * EL2. + */ + mdcr_el2 = MDCR_EL2_RESET_VAL & + ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | + MDCR_EL2_TDE_BIT); + + write_mdcr_el2(mdcr_el2); + + /* + * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. + * + * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or + * EL1 accesses to System registers do not trap to EL2. + */ + write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); + + /* + * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on + * reset. + * + * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer + * and prevent timer interrupts. + */ + write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); + + manage_extensions_nonsecure_el2_unused(); +#endif /* INIT_UNUSED_NS_EL2 */ +} + /******************************************************************************* * Prepare the CPU system registers for first entry into realm, secure, or * normal world. @@ -625,10 +926,8 @@ ******************************************************************************/ void cm_prepare_el3_exit(uint32_t security_state) { - u_register_t sctlr_elx, scr_el3, mdcr_el2; + u_register_t sctlr_elx, scr_el3; cpu_context_t *ctx = cm_get_context(security_state); - bool el2_unused = false; - uint64_t hcr_el2 = 0U; assert(ctx != NULL); @@ -647,8 +946,27 @@ if (is_feat_hcx_supported()) { write_hcrx_el2(HCRX_EL2_INIT_VAL); } + + /* + * Initialize Fine-grained trap registers introduced + * by FEAT_FGT so all traps are initially disabled when + * switching to EL2 or a lower EL, preventing undesired + * behavior. + */ + if (is_feat_fgt_supported()) { + /* + * Initialize HFG*_EL2 registers with a default + * value so legacy systems unaware of FEAT_FGT + * do not get trapped due to their lack of + * initialization for this feature. + */ + write_hfgitr_el2(HFGITR_EL2_INIT_VAL); + write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); + write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); + } } + if ((scr_el3 & SCR_HCE_BIT) != 0U) { /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), @@ -665,188 +983,8 @@ #endif write_sctlr_el2(sctlr_elx); } else if (el2_implemented != EL_IMPL_NONE) { - el2_unused = true; - - /* - * EL2 present but unused, need to disable safely. - * SCTLR_EL2 can be ignored in this case. - * - * Set EL2 register width appropriately: Set HCR_EL2 - * field to match SCR_EL3.RW. - */ - if ((scr_el3 & SCR_RW_BIT) != 0U) - hcr_el2 |= HCR_RW_BIT; - - /* - * For Armv8.3 pointer authentication feature, disable - * traps to EL2 when accessing key registers or using - * pointer authentication instructions from lower ELs. - */ - hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); - - write_hcr_el2(hcr_el2); - - /* - * Initialise CPTR_EL2 setting all fields rather than - * relying on the hw. All fields have architecturally - * UNKNOWN reset values. - * - * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 - * accesses to the CPACR_EL1 or CPACR from both - * Execution states do not trap to EL2. - * - * CPTR_EL2.TTA: Set to zero so that Non-secure System - * register accesses to the trace registers from both - * Execution states do not trap to EL2. - * If PE trace unit System registers are not implemented - * then this bit is reserved, and must be set to zero. - * - * CPTR_EL2.TFP: Set to zero so that Non-secure accesses - * to SIMD and floating-point functionality from both - * Execution states do not trap to EL2. - */ - write_cptr_el2(CPTR_EL2_RESET_VAL & - ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT - | CPTR_EL2_TFP_BIT)); - - /* - * Initialise CNTHCTL_EL2. All fields are - * architecturally UNKNOWN on reset and are set to zero - * except for field(s) listed below. - * - * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to - * Hyp mode of Non-secure EL0 and EL1 accesses to the - * physical timer registers. - * - * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to - * Hyp mode of Non-secure EL0 and EL1 accesses to the - * physical counter registers. - */ - write_cnthctl_el2(CNTHCTL_RESET_VAL | - EL1PCEN_BIT | EL1PCTEN_BIT); - - /* - * Initialise CNTVOFF_EL2 to zero as it resets to an - * architecturally UNKNOWN value. - */ - write_cntvoff_el2(0); - - /* - * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and - * MPIDR_EL1 respectively. - */ - write_vpidr_el2(read_midr_el1()); - write_vmpidr_el2(read_mpidr_el1()); - - /* - * Initialise VTTBR_EL2. All fields are architecturally - * UNKNOWN on reset. - * - * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage - * 2 address translation is disabled, cache maintenance - * operations depend on the VMID. - * - * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address - * translation is disabled. - */ - write_vttbr_el2(VTTBR_RESET_VAL & - ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) - | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); - - /* - * Initialise MDCR_EL2, setting all fields rather than - * relying on hw. Some fields are architecturally - * UNKNOWN on reset. - * - * MDCR_EL2.HLP: Set to one so that event counter - * overflow, that is recorded in PMOVSCLR_EL0[0-30], - * occurs on the increment that changes - * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is - * implemented. This bit is RES0 in versions of the - * architecture earlier than ARMv8.5, setting it to 1 - * doesn't have any effect on them. - * - * MDCR_EL2.TTRF: Set to zero so that access to Trace - * Filter Control register TRFCR_EL1 at EL1 is not - * trapped to EL2. This bit is RES0 in versions of - * the architecture earlier than ARMv8.4. - * - * MDCR_EL2.HPMD: Set to one so that event counting is - * prohibited at EL2. This bit is RES0 in versions of - * the architecture earlier than ARMv8.1, setting it - * to 1 doesn't have any effect on them. - * - * MDCR_EL2.TPMS: Set to zero so that accesses to - * Statistical Profiling control registers from EL1 - * do not trap to EL2. This bit is RES0 when SPE is - * not implemented. - * - * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and - * EL1 System register accesses to the Debug ROM - * registers are not trapped to EL2. - * - * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 - * System register accesses to the powerdown debug - * registers are not trapped to EL2. - * - * MDCR_EL2.TDA: Set to zero so that System register - * accesses to the debug registers do not trap to EL2. - * - * MDCR_EL2.TDE: Set to zero so that debug exceptions - * are not routed to EL2. - * - * MDCR_EL2.HPME: Set to zero to disable EL2 Performance - * Monitors. - * - * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and - * EL1 accesses to all Performance Monitors registers - * are not trapped to EL2. - * - * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 - * and EL1 accesses to the PMCR_EL0 or PMCR are not - * trapped to EL2. - * - * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the - * architecturally-defined reset value. - * - * MDCR_EL2.E2TB: Set to zero so that the trace Buffer - * owning exception level is NS-EL1 and, tracing is - * prohibited at NS-EL2. These bits are RES0 when - * FEAT_TRBE is not implemented. - */ - mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | - MDCR_EL2_HPMD) | - ((read_pmcr_el0() & PMCR_EL0_N_BITS) - >> PMCR_EL0_N_SHIFT)) & - ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | - MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | - MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | - MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | - MDCR_EL2_TPMCR_BIT | - MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); - - write_mdcr_el2(mdcr_el2); - - /* - * Initialise HSTR_EL2. All fields are architecturally - * UNKNOWN on reset. - * - * HSTR_EL2.T<n>: Set all these fields to zero so that - * Non-secure EL0 or EL1 accesses to System registers - * do not trap to EL2. - */ - write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); - /* - * Initialise CNTHP_CTL_EL2. All fields are - * architecturally UNKNOWN on reset. - * - * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 - * physical timer and prevent timer interrupts. - */ - write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & - ~(CNTHP_CTL_ENABLE_BIT)); + init_nonsecure_el2_unused(ctx); } - manage_extensions_nonsecure(el2_unused, ctx); } cm_el1_sysregs_context_restore(security_state); @@ -969,92 +1107,185 @@ } } +/* ----------------------------------------------------- + * The following registers are not added: + * AMEVCNTVOFF0<n>_EL2 + * AMEVCNTVOFF1<n>_EL2 + * ICH_AP0R<n>_EL2 + * ICH_AP1R<n>_EL2 + * ICH_LR<n>_EL2 + * ----------------------------------------------------- + */ +static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) +{ + write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); + write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); + write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); + write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); + write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); + write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); + write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); + if (CTX_INCLUDE_AARCH32_REGS) { + write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); + } + write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); + write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); + write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); + write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); + write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); + write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); + write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); + + /* + * Set the NS bit to be able to access the ICC_SRE_EL2 register + * TODO: remove with root context + */ + u_register_t scr_el3 = read_scr_el3(); + + write_scr_el3(scr_el3 | SCR_NS_BIT); + isb(); + write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); + + write_scr_el3(scr_el3); + isb(); + + write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); + write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); + write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); + write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); + write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); + write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); + write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); + write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); + write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); + write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); + write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); + write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); + write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); + write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); + write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); +} + +static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) +{ + write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); + write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); + write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); + write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); + write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); + write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); + write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); + if (CTX_INCLUDE_AARCH32_REGS) { + write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); + } + write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); + write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); + write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); + write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); + write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); + write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); + write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); + + /* + * Set the NS bit to be able to access the ICC_SRE_EL2 register + * TODO: remove with root context + */ + u_register_t scr_el3 = read_scr_el3(); + + write_scr_el3(scr_el3 | SCR_NS_BIT); + isb(); + write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); + + write_scr_el3(scr_el3); + isb(); + + write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); + write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); + write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); + write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); + write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); + write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); + write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); + write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); + write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); + write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); + write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); + write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); + write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); + write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); + write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); +} + /******************************************************************************* * Save EL2 sysreg context ******************************************************************************/ void cm_el2_sysregs_context_save(uint32_t security_state) { - u_register_t scr_el3 = read_scr(); + cpu_context_t *ctx; + el2_sysregs_t *el2_sysregs_ctx; - /* - * Always save the non-secure and realm EL2 context, only save the - * S-EL2 context if S-EL2 is enabled. - */ - if ((security_state != SECURE) || - ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { - cpu_context_t *ctx; - el2_sysregs_t *el2_sysregs_ctx; + ctx = cm_get_context(security_state); + assert(ctx != NULL); - ctx = cm_get_context(security_state); - assert(ctx != NULL); + el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); - el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); - - el2_sysregs_context_save_common(el2_sysregs_ctx); + el2_sysregs_context_save_common(el2_sysregs_ctx); #if CTX_INCLUDE_MTE_REGS - el2_sysregs_context_save_mte(el2_sysregs_ctx); + write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); #endif - if (is_feat_mpam_supported()) { - el2_sysregs_context_save_mpam(el2_sysregs_ctx); - } + if (is_feat_mpam_supported()) { + el2_sysregs_context_save_mpam(el2_sysregs_ctx); + } - if (is_feat_fgt_supported()) { - el2_sysregs_context_save_fgt(el2_sysregs_ctx); - } + if (is_feat_fgt_supported()) { + el2_sysregs_context_save_fgt(el2_sysregs_ctx); + } - if (is_feat_ecv_v2_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, - read_cntpoff_el2()); - } + if (is_feat_ecv_v2_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2()); + } - if (is_feat_vhe_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, - read_contextidr_el2()); - write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, - read_ttbr1_el2()); - } + if (is_feat_vhe_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); + } - if (is_feat_ras_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, - read_vdisr_el2()); - write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, - read_vsesr_el2()); - } + if (is_feat_ras_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2()); + } - if (is_feat_nv2_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, - read_vncr_el2()); - } + if (is_feat_nv2_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2()); + } - if (is_feat_trf_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); - } + if (is_feat_trf_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); + } - if (is_feat_csv2_2_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, - read_scxtnum_el2()); - } + if (is_feat_csv2_2_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2()); + } - if (is_feat_hcx_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); - } - if (is_feat_tcr2_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); - } - if (is_feat_sxpie_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); - write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); - } - if (is_feat_s2pie_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); - } - if (is_feat_sxpoe_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); - } - if (is_feat_gcs_supported()) { - write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); - write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); - } + if (is_feat_hcx_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); + } + if (is_feat_tcr2_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); + } + if (is_feat_sxpie_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); + } + if (is_feat_s2pie_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); + } + if (is_feat_sxpoe_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); + } + if (is_feat_gcs_supported()) { + write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); + write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); } } @@ -1063,81 +1294,70 @@ ******************************************************************************/ void cm_el2_sysregs_context_restore(uint32_t security_state) { - u_register_t scr_el3 = read_scr(); + cpu_context_t *ctx; + el2_sysregs_t *el2_sysregs_ctx; - /* - * Always restore the non-secure and realm EL2 context, only restore the - * S-EL2 context if S-EL2 is enabled. - */ - if ((security_state != SECURE) || - ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { - cpu_context_t *ctx; - el2_sysregs_t *el2_sysregs_ctx; + ctx = cm_get_context(security_state); + assert(ctx != NULL); - ctx = cm_get_context(security_state); - assert(ctx != NULL); + el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); - el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); - - el2_sysregs_context_restore_common(el2_sysregs_ctx); + el2_sysregs_context_restore_common(el2_sysregs_ctx); #if CTX_INCLUDE_MTE_REGS - el2_sysregs_context_restore_mte(el2_sysregs_ctx); + write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); #endif - if (is_feat_mpam_supported()) { - el2_sysregs_context_restore_mpam(el2_sysregs_ctx); - } + if (is_feat_mpam_supported()) { + el2_sysregs_context_restore_mpam(el2_sysregs_ctx); + } - if (is_feat_fgt_supported()) { - el2_sysregs_context_restore_fgt(el2_sysregs_ctx); - } + if (is_feat_fgt_supported()) { + el2_sysregs_context_restore_fgt(el2_sysregs_ctx); + } - if (is_feat_ecv_v2_supported()) { - write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, - CTX_CNTPOFF_EL2)); - } + if (is_feat_ecv_v2_supported()) { + write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2)); + } - if (is_feat_vhe_supported()) { - write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); - write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); - } + if (is_feat_vhe_supported()) { + write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); + write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); + } - if (is_feat_ras_supported()) { - write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); - write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); - } + if (is_feat_ras_supported()) { + write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); + write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); + } - if (is_feat_nv2_supported()) { - write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); - } - if (is_feat_trf_supported()) { - write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); - } + if (is_feat_nv2_supported()) { + write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); + } + if (is_feat_trf_supported()) { + write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); + } - if (is_feat_csv2_2_supported()) { - write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, - CTX_SCXTNUM_EL2)); - } + if (is_feat_csv2_2_supported()) { + write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2)); + } - if (is_feat_hcx_supported()) { - write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); - } - if (is_feat_tcr2_supported()) { - write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); - } - if (is_feat_sxpie_supported()) { - write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); - write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); - } - if (is_feat_s2pie_supported()) { - write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); - } - if (is_feat_sxpoe_supported()) { - write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); - } - if (is_feat_gcs_supported()) { - write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); - write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); - } + if (is_feat_hcx_supported()) { + write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); + } + if (is_feat_tcr2_supported()) { + write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); + } + if (is_feat_sxpie_supported()) { + write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); + write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); + } + if (is_feat_s2pie_supported()) { + write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); + } + if (is_feat_sxpoe_supported()) { + write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); + } + if (is_feat_gcs_supported()) { + write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); + write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); } } #endif /* CTX_INCLUDE_EL2_REGS */ @@ -1151,35 +1371,15 @@ void cm_prepare_el3_exit_ns(void) { #if CTX_INCLUDE_EL2_REGS +#if ENABLE_ASSERTIONS cpu_context_t *ctx = cm_get_context(NON_SECURE); assert(ctx != NULL); /* Assert that EL2 is used. */ -#if ENABLE_ASSERTIONS - el3_state_t *state = get_el3state_ctx(ctx); - u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); -#endif + u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && (el_implemented(2U) != EL_IMPL_NONE)); - - /* - * Currently some extensions are configured using - * direct register updates. Therefore, do this here - * instead of when setting up context. - */ - manage_extensions_nonsecure(0, ctx); - - /* - * Set the NS bit to be able to access the ICC_SRE_EL2 - * register when restoring context. - */ - write_scr_el3(read_scr_el3() | SCR_NS_BIT); - - /* - * Ensure the NS bit change is committed before the EL2/EL1 - * state restoration. - */ - isb(); +#endif /* ENABLE_ASSERTIONS */ /* Restore EL2 and EL1 sysreg contexts */ cm_el2_sysregs_context_restore(NON_SECURE);
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S index 2392d6b..313f882 100644 --- a/lib/el3_runtime/aarch64/cpu_data.S +++ b/lib/el3_runtime/aarch64/cpu_data.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/el3_runtime/cpu_data_array.c b/lib/el3_runtime/cpu_data_array.c index 13d464c..2056182 100644 --- a/lib/el3_runtime/cpu_data_array.c +++ b/lib/el3_runtime/cpu_data_array.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c index 03186d6..351a552 100644 --- a/lib/extensions/amu/aarch32/amu.c +++ b/lib/extensions/amu/aarch32/amu.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S index 8ac7678..7090b2d 100644 --- a/lib/extensions/amu/aarch32/amu_helpers.S +++ b/lib/extensions/amu/aarch32/amu_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c index c650629..cb9a0f2 100644 --- a/lib/extensions/amu/aarch64/amu.c +++ b/lib/extensions/amu/aarch64/amu.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,16 +69,6 @@ ((value << CPTR_EL2_TAM_SHIFT) & CPTR_EL2_TAM_BIT)); } -static inline __unused void ctx_write_cptr_el3_tam(cpu_context_t *ctx, uint64_t tam) -{ - uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); - - value &= ~TAM_BIT; - value |= (tam << TAM_SHIFT) & TAM_BIT; - - write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, value); -} - static inline __unused void ctx_write_scr_el3_amvoffen(cpu_context_t *ctx, uint64_t amvoffen) { uint64_t value = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); @@ -188,95 +178,72 @@ * Enable counters. This function is meant to be invoked by the context * management library before exiting from EL3. */ -void amu_enable(bool el2_unused, cpu_context_t *ctx) +void amu_enable(cpu_context_t *ctx) { - uint64_t amcfgr_el0_ncg; /* Number of counter groups */ - uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */ - - uint64_t amcntenset0_el0_px = 0x0; /* Group 0 enable mask */ - uint64_t amcntenset1_el0_px = 0x0; /* Group 1 enable mask */ - - if (el2_unused) { + /* Initialize FEAT_AMUv1p1 features if present. */ + if (is_feat_amuv1p1_supported()) { /* - * CPTR_EL2.TAM: Set to zero so any accesses to the Activity - * Monitor registers do not trap to EL2. + * Set SCR_EL3.AMVOFFEN to one so that accesses to virtual + * offset registers at EL2 do not trap to EL3 */ - write_cptr_el2_tam(0U); + ctx_write_scr_el3_amvoffen(ctx, 1U); } +} +void amu_enable_per_world(per_world_context_t *per_world_ctx) +{ /* - * Retrieve and update the CPTR_EL3 value from the context mentioned - * in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to - * the Activity Monitor registers do not trap to EL3. + * Set CPTR_EL3.TAM to zero so that any accesses to the Activity Monitor + * registers do not trap to EL3. */ - ctx_write_cptr_el3_tam(ctx, 0U); + uint64_t cptr_el3 = per_world_ctx->ctx_cptr_el3; - /* - * Retrieve the number of architected counters. All of these counters - * are enabled by default. - */ + cptr_el3 &= ~TAM_BIT; + per_world_ctx->ctx_cptr_el3 = cptr_el3; +} - amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc(); - amcntenset0_el0_px = (UINT64_C(1) << (amcgcr_el0_cg0nc)) - 1U; +void amu_init_el3(void) +{ + uint64_t group0_impl_ctr = read_amcgcr_el0_cg0nc(); + uint64_t group0_en_mask = (1 << (group0_impl_ctr)) - 1U; + uint64_t num_ctr_groups = read_amcfgr_el0_ncg(); - assert(amcgcr_el0_cg0nc <= AMU_AMCGCR_CG0NC_MAX); - - /* - * The platform may opt to enable specific auxiliary counters. This can - * be done via the common FCONF getter, or via the platform-implemented - * function. - */ + /* Enable all architected counters by default */ + write_amcntenset0_el0_px(group0_en_mask); #if ENABLE_AMU_AUXILIARY_COUNTERS - const struct amu_topology *topology; + if (num_ctr_groups > 0U) { + uint64_t amcntenset1_el0_px = 0x0; /* Group 1 enable mask */ + const struct amu_topology *topology; + /* + * The platform may opt to enable specific auxiliary counters. + * This can be done via the common FCONF getter, or via the + * platform-implemented function. + */ #if ENABLE_AMU_FCONF - topology = FCONF_GET_PROPERTY(amu, config, topology); + topology = FCONF_GET_PROPERTY(amu, config, topology); #else - topology = plat_amu_topology(); + topology = plat_amu_topology(); #endif /* ENABLE_AMU_FCONF */ - if (topology != NULL) { - unsigned int core_pos = plat_my_core_pos(); + if (topology != NULL) { + unsigned int core_pos = plat_my_core_pos(); - amcntenset1_el0_px = topology->cores[core_pos].enable; - } else { - ERROR("AMU: failed to generate AMU topology\n"); + amcntenset1_el0_px = topology->cores[core_pos].enable; + } else { + ERROR("AMU: failed to generate AMU topology\n"); + } + + write_amcntenset1_el0_px(amcntenset1_el0_px); + } +#else /* ENABLE_AMU_AUXILIARY_COUNTERS */ + if (num_ctr_groups > 0U) { + VERBOSE("AMU: auxiliary counters detected but support is disabled\n"); } #endif /* ENABLE_AMU_AUXILIARY_COUNTERS */ - /* - * Enable the requested counters. - */ - - write_amcntenset0_el0_px(amcntenset0_el0_px); - - amcfgr_el0_ncg = read_amcfgr_el0_ncg(); - if (amcfgr_el0_ncg > 0U) { - write_amcntenset1_el0_px(amcntenset1_el0_px); - -#if !ENABLE_AMU_AUXILIARY_COUNTERS - VERBOSE("AMU: auxiliary counters detected but support is disabled\n"); -#endif - } - - /* Initialize FEAT_AMUv1p1 features if present. */ if (is_feat_amuv1p1_supported()) { - if (el2_unused) { - /* - * Make sure virtual offsets are disabled if EL2 not - * used. - */ - write_hcr_el2_amvoffen(0U); - } else { - /* - * Virtual offset registers are only accessible from EL3 - * and EL2, when clear, this bit traps accesses from EL2 - * so we set it to 1 when EL2 is present. - */ - ctx_write_scr_el3_amvoffen(ctx, 1U); - } - #if AMU_RESTRICT_COUNTERS /* * FEAT_AMUv1p1 adds a register field to restrict access to @@ -297,6 +264,21 @@ #endif } +void amu_init_el2_unused(void) +{ + /* + * CPTR_EL2.TAM: Set to zero so any accesses to the Activity Monitor + * registers do not trap to EL2. + */ + write_cptr_el2_tam(0U); + + /* Initialize FEAT_AMUv1p1 features if present. */ + if (is_feat_amuv1p1_supported()) { + /* Make sure virtual offsets are disabled if EL2 not used. */ + write_hcr_el2_amvoffen(0U); + } +} + /* Read the group 0 counter identified by the given `idx`. */ static uint64_t amu_group0_cnt_read(unsigned int idx) { @@ -526,10 +508,10 @@ uint64_t hcr_el2_amvoffen = 0; /* AMU virtual offsets enabled */ - uint64_t amcfgr_el0_ncg; /* Number of counter groups */ uint64_t amcgcr_el0_cg0nc; /* Number of group 0 counters */ #if ENABLE_AMU_AUXILIARY_COUNTERS + uint64_t amcfgr_el0_ncg; /* Number of counter groups */ uint64_t amcgcr_el0_cg1nc; /* Number of group 1 counters */ uint64_t amcg1idr_el0_voff; /* Auxiliary counters with virtual offsets */ #endif @@ -541,7 +523,6 @@ core_pos = plat_my_core_pos(); ctx = &amu_ctxs_[core_pos]; - amcfgr_el0_ncg = read_amcfgr_el0_ncg(); amcgcr_el0_cg0nc = read_amcgcr_el0_cg0nc(); if (is_feat_amuv1p1_supported()) { @@ -549,22 +530,12 @@ } #if ENABLE_AMU_AUXILIARY_COUNTERS + amcfgr_el0_ncg = read_amcfgr_el0_ncg(); amcgcr_el0_cg1nc = (amcfgr_el0_ncg > 0U) ? read_amcgcr_el0_cg1nc() : 0U; amcg1idr_el0_voff = (hcr_el2_amvoffen != 0U) ? read_amcg1idr_el0_voff() : 0U; #endif /* - * Sanity check that all counters were disabled when the context was - * previously saved. - */ - - assert(read_amcntenset0_el0_px() == 0U); - - if (amcfgr_el0_ncg > 0U) { - assert(read_amcntenset1_el0_px() == 0U); - } - - /* * Restore the counter values from the local context. */
diff --git a/lib/extensions/amu/aarch64/amu_helpers.S b/lib/extensions/amu/aarch64/amu_helpers.S index 0f6d799..95d4ad6 100644 --- a/lib/extensions/amu/aarch64/amu_helpers.S +++ b/lib/extensions/amu/aarch64/amu_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/extensions/amu/amu_private.h b/lib/extensions/amu/amu_private.h index eb7ff0e..a3b6845 100644 --- a/lib/extensions/amu/amu_private.h +++ b/lib/extensions/amu/amu_private.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c index 329cf98..37bd834 100644 --- a/lib/extensions/brbe/brbe.c +++ b/lib/extensions/brbe/brbe.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +7,9 @@ #include <arch.h> #include <arch_features.h> #include <arch_helpers.h> +#include <lib/extensions/brbe.h> -void brbe_enable(void) +void brbe_init_el3(void) { uint64_t val;
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c index 62533fc..875ad9c 100644 --- a/lib/extensions/mpam/mpam.c +++ b/lib/extensions/mpam/mpam.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,23 +11,31 @@ #include <arch_helpers.h> #include <lib/extensions/mpam.h> -void mpam_enable(bool el2_unused) +void mpam_enable(cpu_context_t *context) { + u_register_t mpam3_el3; + + mpam3_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3); + /* * Enable MPAM, and disable trapping to EL3 when lower ELs access their - * own MPAM registers. + * own MPAM registers */ - write_mpam3_el3(MPAM3_EL3_MPAMEN_BIT); + mpam3_el3 = (mpam3_el3 | MPAM3_EL3_MPAMEN_BIT) & + ~(MPAM3_EL3_TRAPLOWER_BIT); + write_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3, mpam3_el3); +} - /* - * If EL2 is implemented but unused, disable trapping to EL2 when lower - * ELs access their own MPAM registers. - */ - if (el2_unused) { - write_mpam2_el2(0ULL); +/* + * If EL2 is implemented but unused, disable trapping to EL2 when lower ELs + * access their own MPAM registers. + */ +void mpam_init_el2_unused(void) +{ + write_mpam2_el2(0ULL); - if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) { - write_mpamhcr_el2(0ULL); - } + if ((read_mpamidr_el1() & MPAMIDR_HAS_HCR_BIT) != 0U) { + write_mpamhcr_el2(0ULL); } + }
diff --git a/lib/extensions/mtpmu/aarch32/mtpmu.S b/lib/extensions/mtpmu/aarch32/mtpmu.S deleted file mode 100644 index 834cee3..0000000 --- a/lib/extensions/mtpmu/aarch32/mtpmu.S +++ /dev/null
@@ -1,105 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> - - .global mtpmu_disable - -/* ------------------------------------------------------------- - * The functions in this file are called at entrypoint, before - * the CPU has decided whether this is a cold or a warm boot. - * Therefore there are no stack yet to rely on for a C function - * call. - * ------------------------------------------------------------- - */ - -/* - * bool mtpmu_supported(void) - * - * Return a boolean indicating whether FEAT_MTPMU is supported or not. - * - * Trash registers: r0. - */ -func mtpmu_supported - ldcopr r0, ID_DFR1 - and r0, r0, #(ID_DFR1_MTPMU_MASK >> ID_DFR1_MTPMU_SHIFT) - cmp r0, #ID_DFR1_MTPMU_SUPPORTED - mov r0, #0 - addeq r0, r0, #1 - bx lr -endfunc mtpmu_supported - -/* - * bool el_implemented(unsigned int el) - * - * Return a boolean indicating if the specified EL (2 or 3) is implemented. - * - * Trash registers: r0 - */ -func el_implemented - cmp r0, #3 - ldcopr r0, ID_PFR1 - lsreq r0, r0, #ID_PFR1_SEC_SHIFT - lsrne r0, r0, #ID_PFR1_VIRTEXT_SHIFT - /* - * ID_PFR1_VIRTEXT_MASK is the same as ID_PFR1_SEC_MASK - * so use any one of them - */ - and r0, r0, #ID_PFR1_VIRTEXT_MASK - cmp r0, #ID_PFR1_ELx_ENABLED - mov r0, #0 - addeq r0, r0, #1 - bx lr -endfunc el_implemented - -/* - * void mtpmu_disable(void) - * - * Disable mtpmu feature if supported. - * - * Trash register: r0, r1, r2 - */ -func mtpmu_disable - mov r2, lr - bl mtpmu_supported - cmp r0, #0 - bxeq r2 /* FEAT_MTPMU not supported */ - - /* FEAT_MTMPU Supported */ - mov r0, #3 - bl el_implemented - cmp r0, #0 - beq 1f - - /* EL3 implemented */ - ldcopr r0, SDCR - ldr r1, =SDCR_MTPME_BIT - bic r0, r0, r1 - stcopr r0, SDCR - - /* - * If EL3 is implemented, HDCR.MTPME is implemented as Res0 and - * FEAT_MTPMU is controlled only from EL3, so no need to perform - * any operations for EL2. - */ - isb - bx r2 -1: - /* EL3 not implemented */ - mov r0, #2 - bl el_implemented - cmp r0, #0 - bxeq r2 /* No EL2 or EL3 implemented */ - - /* EL2 implemented */ - ldcopr r0, HDCR - ldr r1, =HDCR_MTPME_BIT - orr r0, r0, r1 - stcopr r0, HDCR - isb - bx r2 -endfunc mtpmu_disable
diff --git a/lib/extensions/mtpmu/aarch64/mtpmu.S b/lib/extensions/mtpmu/aarch64/mtpmu.S deleted file mode 100644 index 0a1d57b..0000000 --- a/lib/extensions/mtpmu/aarch64/mtpmu.S +++ /dev/null
@@ -1,96 +0,0 @@ -/* - * Copyright (c) 2020, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> - - .global mtpmu_disable - -/* ------------------------------------------------------------- - * The functions in this file are called at entrypoint, before - * the CPU has decided whether this is a cold or a warm boot. - * Therefore there are no stack yet to rely on for a C function - * call. - * ------------------------------------------------------------- - */ - -/* - * bool mtpmu_supported(void) - * - * Return a boolean indicating whether FEAT_MTPMU is supported or not. - * - * Trash registers: x0, x1 - */ -func mtpmu_supported - mrs x0, id_aa64dfr0_el1 - mov_imm x1, ID_AA64DFR0_MTPMU_MASK - and x0, x1, x0, LSR #ID_AA64DFR0_MTPMU_SHIFT - cmp x0, ID_AA64DFR0_MTPMU_SUPPORTED - cset x0, eq - ret -endfunc mtpmu_supported - -/* - * bool el_implemented(unsigned int el_shift) - * - * Return a boolean indicating if the specified EL is implemented. - * The EL is represented as the bitmask shift on id_aa64pfr0_el1 register. - * - * Trash registers: x0, x1 - */ -func el_implemented - mrs x1, id_aa64pfr0_el1 - lsr x1, x1, x0 - cmp x1, #ID_AA64PFR0_ELX_MASK - cset x0, eq - ret -endfunc el_implemented - -/* - * void mtpmu_disable(void) - * - * Disable mtpmu feature if supported. - * - * Trash register: x0, x1, x30 - */ -func mtpmu_disable - mov x10, x30 - bl mtpmu_supported - cbz x0, exit_disable - - /* FEAT_MTMPU Supported */ - mov_imm x0, ID_AA64PFR0_EL3_SHIFT - bl el_implemented - cbz x0, 1f - - /* EL3 implemented */ - mrs x0, mdcr_el3 - mov_imm x1, MDCR_MTPME_BIT - bic x0, x0, x1 - msr mdcr_el3, x0 - - /* - * If EL3 is implemented, MDCR_EL2.MTPME is implemented as Res0 and - * FEAT_MTPMU is controlled only from EL3, so no need to perform - * any operations for EL2. - */ - isb -exit_disable: - ret x10 -1: - /* EL3 not implemented */ - mov_imm x0, ID_AA64PFR0_EL2_SHIFT - bl el_implemented - cbz x0, exit_disable - - /* EL2 implemented */ - mrs x0, mdcr_el2 - mov_imm x1, MDCR_EL2_MTPME - bic x0, x0, x1 - msr mdcr_el2, x0 - isb - ret x10 -endfunc mtpmu_disable
diff --git a/lib/extensions/pauth/pauth_helpers.S b/lib/extensions/pauth/pauth_helpers.S index d483c7df..fb5fa97 100644 --- a/lib/extensions/pauth/pauth_helpers.S +++ b/lib/extensions/pauth/pauth_helpers.S
@@ -45,7 +45,7 @@ endfunc pauth_init_enable_el1 /* ------------------------------------------------------------- - * Disable pointer authentication in EL3 + * Disable pointer authentication in EL1 * ------------------------------------------------------------- */ func pauth_disable_el1
diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c new file mode 100644 index 0000000..effb7e0 --- /dev/null +++ b/lib/extensions/pmuv3/aarch32/pmuv3.c
@@ -0,0 +1,72 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_features.h> +#include <arch_helpers.h> +#include <lib/extensions/pmuv3.h> + +static u_register_t mtpmu_disable_el3(u_register_t sdcr) +{ + if (!is_feat_mtpmu_supported()) { + return sdcr; + } + + /* + * SDCR.MTPME = 0 + * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is + * zero. + */ + sdcr &= ~SDCR_MTPME_BIT; + + return sdcr; +} + +/* + * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and + * to not clash with platforms which reuse the PMU name + */ +void pmuv3_init_el3(void) +{ + u_register_t sdcr = read_sdcr(); + + /* --------------------------------------------------------------------- + * Initialise SDCR, setting all the fields rather than relying on hw. + * + * SDCR.SCCD: Set to one so that cycle counting by PMCCNTR is prohibited + * in Secure state. This bit is RES0 in versions of the architecture + * earlier than ARMv8.5 + * + * SDCR.SPME: Set to zero so that event counting is prohibited in Secure + * state (and explicitly EL3 with later revisions). If ARMv8.2 Debug is + * not implemented this bit does not have any effect on the counters + * unless there is support for the implementation defined + * authentication interface ExternalSecureNoninvasiveDebugEnabled(). + * --------------------------------------------------------------------- + */ + sdcr = (sdcr | SDCR_SCCD_BIT) & ~SDCR_SPME_BIT; + sdcr = mtpmu_disable_el3(sdcr); + write_sdcr(sdcr); + + /* --------------------------------------------------------------------- + * Initialise PMCR, setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR.DP: Set to one to prohibit cycle counting whilst in Secure mode. + * + * PMCR.X: Set to zero to disable export of events. + * + * PMCR.C: Set to one to reset PMCCNTR. + * + * PMCR.P: Set to one to reset each event counter PMEVCNTR<n> to zero. + * + * PMCR.E: Set to zero to disable cycle and event counters. + * --------------------------------------------------------------------- + */ + + write_pmcr(read_pmcr() | PMCR_DP_BIT | PMCR_C_BIT | PMCR_P_BIT | + ~(PMCR_X_BIT | PMCR_E_BIT)); +}
diff --git a/lib/extensions/pmuv3/aarch64/pmuv3.c b/lib/extensions/pmuv3/aarch64/pmuv3.c new file mode 100644 index 0000000..61fc47d --- /dev/null +++ b/lib/extensions/pmuv3/aarch64/pmuv3.c
@@ -0,0 +1,173 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_features.h> +#include <arch_helpers.h> +#include <lib/extensions/pmuv3.h> + +static u_register_t init_mdcr_el2_hpmn(u_register_t mdcr_el2) +{ + /* + * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't + * throw anyone off who expects this to be sensible. + */ + mdcr_el2 &= ~MDCR_EL2_HPMN_MASK; + mdcr_el2 |= ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & PMCR_EL0_N_MASK); + + return mdcr_el2; +} + +void pmuv3_enable(cpu_context_t *ctx) +{ +#if CTX_INCLUDE_EL2_REGS + u_register_t mdcr_el2; + + mdcr_el2 = read_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2); + mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); + write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); +#endif /* CTX_INCLUDE_EL2_REGS */ +} + +static u_register_t mtpmu_disable_el3(u_register_t mdcr_el3) +{ + if (!is_feat_mtpmu_supported()) { + return mdcr_el3; + } + + /* + * MDCR_EL3.MTPME = 0 + * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is + * zero. + */ + mdcr_el3 &= ~MDCR_MTPME_BIT; + + return mdcr_el3; +} + +void pmuv3_init_el3(void) +{ + u_register_t mdcr_el3 = read_mdcr_el3(); + + /* --------------------------------------------------------------------- + * Initialise MDCR_EL3, setting all fields rather than relying on hw. + * Some fields are architecturally UNKNOWN on reset. + * + * MDCR_EL3.MPMX: Set to zero to not affect event counters (when + * SPME = 0). + * + * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is + * prohibited in EL3. This bit is RES0 in versions of the + * architecture with FEAT_PMUv3p7 not implemented. + * + * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is + * prohibited in Secure state. This bit is RES0 in versions of the + * architecture with FEAT_PMUv3p5 not implemented. + * + * MDCR_EL3.SPME: Set to zero so that event counting is prohibited in + * Secure state (and explicitly EL3 with later revisions). If ARMv8.2 + * Debug is not implemented this bit does not have any effect on the + * counters unless there is support for the implementation defined + * authentication interface ExternalSecureNoninvasiveDebugEnabled(). + * + * The SPME/MPMX combination is a little tricky. Below is a small + * summary if another combination is ever needed: + * SPME | MPMX | secure world | EL3 + * ------------------------------------- + * 0 | 0 | disabled | disabled + * 1 | 0 | enabled | enabled + * 0 | 1 | enabled | disabled + * 1 | 1 | enabled | disabled only for counters 0 to + * MDCR_EL2.HPMN - 1. Enabled for the rest + * + * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register + * accesses to all Performance Monitors registers do not trap to EL3. + */ + mdcr_el3 = (mdcr_el3 | MDCR_SCCD_BIT | MDCR_MCCD_BIT) & + ~(MDCR_MPMX_BIT | MDCR_SPME_BIT | MDCR_TPM_BIT); + mdcr_el3 = mtpmu_disable_el3(mdcr_el3); + write_mdcr_el3(mdcr_el3); + + /* --------------------------------------------------------------------- + * Initialise PMCR_EL0 setting all fields rather than relying + * on hw. Some fields are architecturally UNKNOWN on reset. + * + * PMCR_EL0.DP: Set to one so that the cycle counter, + * PMCCNTR_EL0 does not count when event counting is prohibited. + * Necessary on PMUv3 <= p7 where MDCR_EL3.{SCCD,MCCD} are not + * available + * + * PMCR_EL0.X: Set to zero to disable export of events. + * + * PMCR_EL0.C: Set to one to reset PMCCNTR_EL0 to zero. + * + * PMCR_EL0.P: Set to one to reset each event counter PMEVCNTR<n>_EL0 to + * zero. + * + * PMCR_EL0.E: Set to zero to disable cycle and event counters. + * --------------------------------------------------------------------- + */ + write_pmcr_el0((read_pmcr_el0() | PMCR_EL0_DP_BIT | PMCR_EL0_C_BIT | + PMCR_EL0_P_BIT) & ~(PMCR_EL0_X_BIT | PMCR_EL0_E_BIT)); +} + +static u_register_t mtpmu_disable_el2(u_register_t mdcr_el2) +{ + if (!is_feat_mtpmu_supported()) { + return mdcr_el2; + } + + /* + * MDCR_EL2.MTPME = 0 + * FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>_EL0.MT is + * zero. + */ + mdcr_el2 &= ~MDCR_EL2_MTPME; + + return mdcr_el2; +} + +void pmuv3_init_el2_unused(void) +{ + u_register_t mdcr_el2 = read_mdcr_el2(); + + /* + * Initialise MDCR_EL2, setting all fields rather than + * relying on hw. Some fields are architecturally + * UNKNOWN on reset. + * + * MDCR_EL2.HLP: Set to one so that event counter overflow, that is + * recorded in PMOVSCLR_EL0[0-30], occurs on the increment that changes + * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is implemented. + * This bit is RES0 in versions of the architecture earlier than + * ARMv8.5, setting it to 1 doesn't have any effect on them. + * + * MDCR_EL2.HCCD: Set to one to prohibit cycle counting at EL2. This bit + * is RES0 in versions of the architecture with FEAT_PMUv3p5 not + * implemented. + * + * MDCR_EL2.HPMD: Set to one so that event counting is + * prohibited at EL2 for counter n < MDCR_EL2.HPMN. This bit is RES0 + * in versions of the architecture with FEAT_PMUv3p1 not implemented. + * + * MDCR_EL2.HPME: Set to zero to disable event counters for counters + * n >= MDCR_EL2.HPMN. + * + * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and + * EL1 accesses to all Performance Monitors registers + * are not trapped to EL2. + * + * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 + * and EL1 accesses to the PMCR_EL0 or PMCR are not + * trapped to EL2. + */ + mdcr_el2 = (mdcr_el2 | MDCR_EL2_HLP_BIT | MDCR_EL2_HPMD_BIT | + MDCR_EL2_HCCD_BIT) & + ~(MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | MDCR_EL2_TPMCR_BIT); + mdcr_el2 = init_mdcr_el2_hpmn(mdcr_el2); + mdcr_el2 = mtpmu_disable_el2(mdcr_el2); + write_mdcr_el2(mdcr_el2); +}
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c index 622879e..50f3727 100644 --- a/lib/extensions/ras/ras_common.c +++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/extensions/ras/std_err_record.c b/lib/extensions/ras/std_err_record.c index c03fbbe..6c1dc9f 100644 --- a/lib/extensions/ras/std_err_record.c +++ b/lib/extensions/ras/std_err_record.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c index 3423dba..b1409b9 100644 --- a/lib/extensions/sme/sme.c +++ b/lib/extensions/sme/sme.c
@@ -17,37 +17,45 @@ void sme_enable(cpu_context_t *context) { u_register_t reg; - u_register_t cptr_el3; el3_state_t *state; /* Get the context state. */ state = get_el3state_ctx(context); - /* Enable SME in CPTR_EL3. */ - reg = read_ctx_reg(state, CTX_CPTR_EL3); - reg |= ESM_BIT; - write_ctx_reg(state, CTX_CPTR_EL3, reg); - /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */ reg = read_ctx_reg(state, CTX_SCR_EL3); reg |= SCR_ENTP2_BIT; write_ctx_reg(state, CTX_SCR_EL3, reg); +} - /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */ - cptr_el3 = read_cptr_el3(); +void sme_enable_per_world(per_world_context_t *per_world_ctx) +{ + u_register_t reg; + + /* Enable SME in CPTR_EL3. */ + reg = per_world_ctx->ctx_cptr_el3; + reg |= ESM_BIT; + per_world_ctx->ctx_cptr_el3 = reg; +} + +void sme_init_el3(void) +{ + u_register_t cptr_el3 = read_cptr_el3(); + u_register_t smcr_el3; + + /* Set CPTR_EL3.ESM bit so we can access SMCR_EL3 without trapping. */ write_cptr_el3(cptr_el3 | ESM_BIT); isb(); /* - * Set the max LEN value and FA64 bit. This register is set up globally + * Set the max LEN value and FA64 bit. This register is set up per_world * to be the least restrictive, then lower ELs can restrict as needed * using SMCR_EL2 and SMCR_EL1. */ - reg = SMCR_ELX_LEN_MAX; - + smcr_el3 = SMCR_ELX_LEN_MAX; if (read_feat_sme_fa64_id_field() != 0U) { VERBOSE("[SME] FA64 enabled\n"); - reg |= SMCR_ELX_FA64_BIT; + smcr_el3 |= SMCR_ELX_FA64_BIT; } /* @@ -58,15 +66,24 @@ */ if (is_feat_sme2_supported()) { VERBOSE("SME2 enabled\n"); - reg |= SMCR_ELX_EZT0_BIT; + smcr_el3 |= SMCR_ELX_EZT0_BIT; } - write_smcr_el3(reg); + write_smcr_el3(smcr_el3); /* Reset CPTR_EL3 value. */ write_cptr_el3(cptr_el3); isb(); } +void sme_init_el2_unused(void) +{ + /* + * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 accesses to the + * CPACR_EL1 or CPACR from both Execution states do not trap to EL2. + */ + write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TCPAC_BIT); +} + void sme_disable(cpu_context_t *context) { u_register_t reg; @@ -75,15 +92,20 @@ /* Get the context state. */ state = get_el3state_ctx(context); - /* Disable SME, SVE, and FPU since they all share registers. */ - reg = read_ctx_reg(state, CTX_CPTR_EL3); - reg &= ~ESM_BIT; /* Trap SME */ - reg &= ~CPTR_EZ_BIT; /* Trap SVE */ - reg |= TFP_BIT; /* Trap FPU/SIMD */ - write_ctx_reg(state, CTX_CPTR_EL3, reg); - /* Disable access to TPIDR2_EL0. */ reg = read_ctx_reg(state, CTX_SCR_EL3); reg &= ~SCR_ENTP2_BIT; write_ctx_reg(state, CTX_SCR_EL3, reg); } + +void sme_disable_per_world(per_world_context_t *per_world_ctx) +{ + u_register_t reg; + + /* Disable SME, SVE, and FPU since they all share registers. */ + reg = per_world_ctx->ctx_cptr_el3; + reg &= ~ESM_BIT; /* Trap SME */ + reg &= ~CPTR_EZ_BIT; /* Trap SVE */ + reg |= TFP_BIT; /* Trap FPU/SIMD */ + per_world_ctx->ctx_cptr_el3 = reg; +}
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c index b1fe39f..2c25a9d 100644 --- a/lib/extensions/spe/spe.c +++ b/lib/extensions/spe/spe.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,30 +21,18 @@ __asm__ volatile("hint #17"); } -void spe_enable(bool el2_unused) +void spe_init_el3(void) { uint64_t v; - if (el2_unused) { - /* - * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical - * profiling controls to EL2. - * - * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure - * state. Accesses to profiling buffer controls at - * Non-secure EL1 are not trapped to EL2. - */ - v = read_mdcr_el2(); - v &= ~MDCR_EL2_TPMS; - v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); - write_mdcr_el2(v); - } - /* - * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state + * MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state * and disabled in secure state. Accesses to SPE registers at * S-EL1 generate trap exceptions to EL3. * + * MDCR_EL3.NSPBE: Profiling Buffer uses Non-secure Virtual Addresses. + * When FEAT_RME is not implemented, this field is RES0. + * * MDCR_EL3.EnPMSN (ARM v8.7): Do not trap access to PMSNEVFR_EL1 * register at NS-EL1 or NS-EL2 to EL3 if FEAT_SPEv1p2 is implemented. * Setting this bit to 1 doesn't have any effect on it when @@ -52,9 +40,28 @@ */ v = read_mdcr_el3(); v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT; + v &= ~(MDCR_NSPBE_BIT); write_mdcr_el3(v); } +void spe_init_el2_unused(void) +{ + uint64_t v; + + /* + * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical + * profiling controls to EL2. + * + * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure + * state. Accesses to profiling buffer controls at + * Non-secure EL1 are not trapped to EL2. + */ + v = read_mdcr_el2(); + v &= ~MDCR_EL2_TPMS; + v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); + write_mdcr_el2(v); +} + void spe_disable(void) { uint64_t v;
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index f551ca7..143717e 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,32 +22,36 @@ */ #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) -void sve_enable(cpu_context_t *context) +void sve_enable_per_world(per_world_context_t *per_world_ctx) { u_register_t cptr_el3; - cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); - /* Enable access to SVE functionality for all ELs. */ + cptr_el3 = per_world_ctx->ctx_cptr_el3; cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); - write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); + per_world_ctx->ctx_cptr_el3 = cptr_el3; /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */ - write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, - (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN))); + per_world_ctx->ctx_zcr_el3 = (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)); } -void sve_disable(cpu_context_t *context) +void sve_init_el2_unused(void) +{ + /* + * CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced + * SIMD and floating-point functionality from both Execution states do + * not trap to EL2. + */ + write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT); +} + +void sve_disable_per_world(per_world_context_t *per_world_ctx) { u_register_t reg; - el3_state_t *state; - - /* Get the context state. */ - state = get_el3state_ctx(context); /* Disable SVE and FPU since they share registers. */ - reg = read_ctx_reg(state, CTX_CPTR_EL3); + reg = per_world_ctx->ctx_cptr_el3; reg &= ~CPTR_EZ_BIT; /* Trap SVE */ reg |= TFP_BIT; /* Trap FPU/SIMD */ - write_ctx_reg(state, CTX_CPTR_EL3, reg); + per_world_ctx->ctx_cptr_el3 = reg; }
diff --git a/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c index b3f44b7..6da504e 100644 --- a/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c +++ b/lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,7 +10,7 @@ #include <arch_helpers.h> #include <lib/extensions/sys_reg_trace.h> -void sys_reg_trace_enable(void) +void sys_reg_trace_init_el3(void) { uint32_t val;
diff --git a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c index e61cb90..2170763 100644 --- a/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c +++ b/lib/extensions/sys_reg_trace/aarch64/sys_reg_trace.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,17 +10,36 @@ #include <arch_helpers.h> #include <lib/extensions/sys_reg_trace.h> -void sys_reg_trace_enable(cpu_context_t *ctx) +void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx) { - uint64_t val; - - /* Retrieve CPTR_EL3 value from the given context 'ctx', - * and update CPTR_EL3.TTA bit to 0. - * This function is called while switching context to NS to - * allow system trace register access to NS-EL2 and NS-EL1 - * when NS-EL2 is implemented but not used. + /* + * CPTR_EL3.TTA: Set to zero so that System register accesses to the + * trace registers do not trap to EL3. */ - val = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); - val &= ~TTA_BIT; - write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, val); + uint64_t val = per_world_ctx->ctx_cptr_el3; + val &= ~(TTA_BIT); + per_world_ctx->ctx_cptr_el3 = val; +} + +void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx) +{ + /* + * CPTR_EL3.TTA: Set to one so that System register accesses to the + * trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS, + * CPACR_EL1.TTA, or CPTR_EL2.TTA + */ + uint64_t val = per_world_ctx->ctx_cptr_el3; + val |= TTA_BIT; + per_world_ctx->ctx_cptr_el3 = val; +} + +void sys_reg_trace_init_el2_unused(void) +{ + /* + * CPTR_EL2.TTA: Set to zero so that Non-secure System register accesses + * to the trace registers from both Execution states do not trap to + * EL2. If PE trace unit System registers are not implemented then this + * bit is reserved, and must be set to zero. + */ + write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TTA_BIT); }
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c index fa139ca..d4fbdfb 100644 --- a/lib/extensions/trbe/trbe.c +++ b/lib/extensions/trbe/trbe.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,21 +19,37 @@ __asm__ volatile("hint #18"); } -void trbe_enable(void) +void trbe_init_el3(void) { - uint64_t val; + u_register_t val; /* + * MDCR_EL3.NSTBE = 0b0 + * Trace Buffer owning Security state is Non-secure state. If FEAT_RME + * is not implemented, this field is RES0. + * * MDCR_EL3.NSTB = 0b11 - * Allow access of trace buffer control registers from NS-EL1 - * and NS-EL2, tracing is prohibited in Secure and Realm state - * (if implemented). + * Allow access of trace buffer control registers from NS-EL1 and + * NS-EL2, tracing is prohibited in Secure and Realm state (if + * implemented). */ val = read_mdcr_el3(); val |= MDCR_NSTB(MDCR_NSTB_EL1); + val &= ~(MDCR_NSTBE_BIT); write_mdcr_el3(val); } +void trbe_init_el2_unused(void) +{ + /* + * MDCR_EL2.E2TB: Set to zero so that the trace Buffer + * owning exception level is NS-EL1 and, tracing is + * prohibited at NS-EL2. These bits are RES0 when + * FEAT_TRBE is not implemented. + */ + write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); +} + static void *trbe_drain_trace_buffers_hook(const void *arg __unused) { if (is_feat_trbe_supported()) {
diff --git a/lib/extensions/trf/aarch32/trf.c b/lib/extensions/trf/aarch32/trf.c index 0c63efa..321c089 100644 --- a/lib/extensions/trf/aarch32/trf.c +++ b/lib/extensions/trf/aarch32/trf.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,15 +10,15 @@ #include <arch_helpers.h> #include <lib/extensions/trf.h> -void trf_enable(void) +void trf_init_el3(void) { uint32_t val; /* * Allow access of trace filter control registers from - * non-monitor mode + * non-monitor mode. */ val = read_sdcr(); - val &= ~SDCR_TTRF_BIT; + val &= ~(SDCR_TTRF_BIT); write_sdcr(val); }
diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c index 941692b..83fbf85 100644 --- a/lib/extensions/trf/aarch64/trf.c +++ b/lib/extensions/trf/aarch64/trf.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,16 +9,32 @@ #include <arch_helpers.h> #include <lib/extensions/trf.h> -void trf_enable(void) +void trf_init_el3(void) { - uint64_t val; + u_register_t val; /* + * MDCR_EL3.STE = b0 + * Trace prohibited in Secure state unless overridden by the + * IMPLEMENTATION DEFINED authentication interface. + * * MDCR_EL3.TTRF = b0 * Allow access of trace filter control registers from NS-EL2 * and NS-EL1 when NS-EL2 is implemented but not used */ val = read_mdcr_el3(); - val &= ~MDCR_TTRF_BIT; + val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT); write_mdcr_el3(val); } + +void trf_init_el2_unused(void) +{ + /* + * MDCR_EL2.TTRF: Set to zero so that access to Trace + * Filter Control register TRFCR_EL1 at EL1 is not + * trapped to EL2. This bit is RES0 in versions of + * the architecture earlier than ARMv8.4. + * + */ + write_mdcr_el2(read_mdcr_el2() & ~MDCR_EL2_TTRF); +}
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c index b1d6eaa..136e056 100644 --- a/lib/fconf/fconf.c +++ b/lib/fconf/fconf.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/fconf/fconf.mk b/lib/fconf/fconf.mk index fb88910..ff781aa 100644 --- a/lib/fconf/fconf.mk +++ b/lib/fconf/fconf.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) 2019-2021, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/fconf/fconf_dyn_cfg_getter.c b/lib/fconf/fconf_dyn_cfg_getter.c index 13081b0..58956d6 100644 --- a/lib/fconf/fconf_dyn_cfg_getter.c +++ b/lib/fconf/fconf_dyn_cfg_getter.c
@@ -83,7 +83,7 @@ /* * In case of BL1, fw_config dtb information is already - * populated in global dtb_infos array by 'set_fw_config_info' + * populated in global dtb_infos array by 'set_config_info' * function, Below check is present to avoid re-population of * fw_config information. *
diff --git a/lib/libc/aarch64/setjmp.S b/lib/libc/aarch64/setjmp.S index 9d9eb49..9cb31ea 100644 --- a/lib/libc/aarch64/setjmp.S +++ b/lib/libc/aarch64/setjmp.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/abort.c b/lib/libc/abort.c index 432b1d0..ac27f62 100644 --- a/lib/libc/abort.c +++ b/lib/libc/abort.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/assert.c b/lib/libc/assert.c index 8973ed5..301d142 100644 --- a/lib/libc/assert.c +++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/exit.c b/lib/libc/exit.c index f4ffe27..6de2e93 100644 --- a/lib/libc/exit.c +++ b/lib/libc/exit.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/libc.mk b/lib/libc/libc.mk index b75d09c..95da68c 100644 --- a/lib/libc/libc.mk +++ b/lib/libc/libc.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -11,6 +11,7 @@ memchr.c \ memcmp.c \ memcpy.c \ + memcpy_s.c \ memmove.c \ memrchr.c \ memset.c \
diff --git a/lib/libc/memchr.c b/lib/libc/memchr.c index 8cbb715..66d7ba1 100644 --- a/lib/libc/memchr.c +++ b/lib/libc/memchr.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/memcmp.c b/lib/libc/memcmp.c index cd5f0df..db2701b 100644 --- a/lib/libc/memcmp.c +++ b/lib/libc/memcmp.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c index 158df9b..af9ed45 100644 --- a/lib/libc/memcpy.c +++ b/lib/libc/memcpy.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/memcpy_s.c b/lib/libc/memcpy_s.c new file mode 100644 index 0000000..26953bf --- /dev/null +++ b/lib/libc/memcpy_s.c
@@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> +#include <stddef.h> +#include <string.h> + +int memcpy_s(void *dst, size_t dsize, void *src, size_t ssize) +{ + unsigned int *s = (unsigned int *)src; + unsigned int *d = (unsigned int *)dst; + + /* + * Check source and destination size is NULL + */ + if ((dst == NULL) || (src == NULL)) { + return -ENOMEM; + } + + /* + * Check source and destination size validity + */ + if ((dsize == 0) || (ssize == 0)) { + return -ERANGE; + } + + /* + * Check both source and destination size range + */ + if ((ssize > dsize) || (dsize > ssize)) { + return -EINVAL; + } + + /* + * Check both source and destination address overlapping + * When (s > d < s + ssize) + * Or (d > s < d + dsize) + */ + + if (d > s) { + if ((d) < (s + ssize)) { + return -EOPNOTSUPP; + } + } + + if (s > d) { + if ((s) < (d + dsize)) { + return -EOPNOTSUPP; + } + } + + /* + * Start copy process when there is no error + */ + while (ssize--) { + d[ssize] = s[ssize]; + } + + return 0; +}
diff --git a/lib/libc/memmove.c b/lib/libc/memmove.c index 63acf26..5c2b661 100644 --- a/lib/libc/memmove.c +++ b/lib/libc/memmove.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/memset.c b/lib/libc/memset.c index 17f798c..c5bac8d 100644 --- a/lib/libc/memset.c +++ b/lib/libc/memset.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/printf.c b/lib/libc/printf.c index faccfdf..6931a7e 100644 --- a/lib/libc/printf.c +++ b/lib/libc/printf.c
@@ -36,7 +36,7 @@ } static int unsigned_num_print(unsigned long long int unum, unsigned int radix, - char padc, int padn) + char padc, int padn, bool uppercase) { /* Just need enough space to store 64 bit decimal integer */ char num_buf[20]; @@ -51,10 +51,13 @@ do { rem = unum % radix; - if (rem < 0xa) + if (rem < 0xa) { num_buf[i] = '0' + rem; - else + } else if (uppercase) { + num_buf[i] = 'A' + (rem - 0xa); + } else { num_buf[i] = 'a' + (rem - 0xa); + } i++; unum /= radix; } while (unum > 0U); @@ -105,8 +108,10 @@ char padc = '\0'; /* Padding character */ int padn; /* Number of characters to pad */ int count = 0; /* Number of printed characters */ + bool uppercase; /* Print characters in uppercase */ while (*fmt != '\0') { + uppercase = false; l_count = 0; padn = 0; @@ -129,7 +134,7 @@ unum = (unsigned long long int)num; count += unsigned_num_print(unum, 10, - padc, padn); + padc, padn, uppercase); break; case 'c': (void)putchar(va_arg(args, int)); @@ -147,12 +152,15 @@ } count += unsigned_num_print(unum, 16, - padc, padn); + padc, padn, uppercase); break; + case 'X': + uppercase = true; + // fall through case 'x': unum = get_unum_va_args(args, l_count); count += unsigned_num_print(unum, 16, - padc, padn); + padc, padn, uppercase); break; case 'z': if (sizeof(size_t) == 8U) @@ -167,7 +175,7 @@ case 'u': unum = get_unum_va_args(args, l_count); count += unsigned_num_print(unum, 10, - padc, padn); + padc, padn, uppercase); break; case '0': padc = '0';
diff --git a/lib/libc/putchar.c b/lib/libc/putchar.c index 340bdd8..1f919d1 100644 --- a/lib/libc/putchar.c +++ b/lib/libc/putchar.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/puts.c b/lib/libc/puts.c index 2a0ca11..f57fc98 100644 --- a/lib/libc/puts.c +++ b/lib/libc/puts.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/strchr.c b/lib/libc/strchr.c index d94bb9e..1cd03ca 100644 --- a/lib/libc/strchr.c +++ b/lib/libc/strchr.c
@@ -30,7 +30,7 @@ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/lib/libc/strcmp.c b/lib/libc/strcmp.c index b742f9b..290db4c 100644 --- a/lib/libc/strcmp.c +++ b/lib/libc/strcmp.c
@@ -33,7 +33,7 @@ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/lib/libc/strlen.c b/lib/libc/strlen.c index 3c27630..e4b79d9 100644 --- a/lib/libc/strlen.c +++ b/lib/libc/strlen.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/libc/strncmp.c b/lib/libc/strncmp.c index ce9e5ed..f0bbadc 100644 --- a/lib/libc/strncmp.c +++ b/lib/libc/strncmp.c
@@ -30,7 +30,7 @@ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/lib/libc/strnlen.c b/lib/libc/strnlen.c index b944e95..49e9f7a 100644 --- a/lib/libc/strnlen.c +++ b/lib/libc/strnlen.c
@@ -27,7 +27,7 @@ */ /* - * Portions copyright (c) 2018, ARM Limited and Contributors. + * Portions copyright (c) 2018, Arm Limited and Contributors. * All rights reserved. */
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk index 1cbbd78..812057d 100644 --- a/lib/libfdt/libfdt.mk +++ b/lib/libfdt/libfdt.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c index 748eedd..bcd89ef 100644 --- a/lib/locks/bakery/bakery_lock_coherent.c +++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c index 3c03ae6..9f27322 100644 --- a/lib/locks/bakery/bakery_lock_normal.c +++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/locks/exclusive/aarch32/spinlock.S b/lib/locks/exclusive/aarch32/spinlock.S index 9492cc0..853d096 100644 --- a/lib/locks/exclusive/aarch32/spinlock.S +++ b/lib/locks/exclusive/aarch32/spinlock.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S index e941b8a..5144bf7 100644 --- a/lib/locks/exclusive/aarch64/spinlock.S +++ b/lib/locks/exclusive/aarch64/spinlock.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c index 6641db9..14f5533 100644 --- a/lib/optee/optee_utils.c +++ b/lib/optee/optee_utils.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/pmf/pmf_main.c b/lib/pmf/pmf_main.c index ce2f0d9..b33f49c 100644 --- a/lib/pmf/pmf_main.c +++ b/lib/pmf/pmf_main.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -165,7 +165,7 @@ /* Search for registered service. */ svc_desc = get_service(tid); - if ((svc_desc == NULL) || (plat_core_pos_by_mpidr(mpidr) < 0)) { + if (svc_desc == NULL) { *ts_value = 0; return -EINVAL; } else {
diff --git a/lib/pmf/pmf_smc.c b/lib/pmf/pmf_smc.c index 6d79502..f3dd112 100644 --- a/lib/pmf/pmf_smc.c +++ b/lib/pmf/pmf_smc.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,6 +26,10 @@ int rc; unsigned long long ts_value; + /* Determine if the cpu exists of not */ + if (!is_valid_mpidr(x2)) + return PSCI_E_INVALID_PARAMS; + if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { x1 = (uint32_t)x1;
diff --git a/lib/psa/delegated_attestation.c b/lib/psa/delegated_attestation.c index a813e84..81e2621 100644 --- a/lib/psa/delegated_attestation.c +++ b/lib/psa/delegated_attestation.c
@@ -5,13 +5,10 @@ * */ -#include <string.h> - #include <delegated_attestation.h> #include <psa/client.h> #include <psa_manifest/sid.h> -#if !PLAT_RSS_NOT_SUPPORTED psa_status_t rss_delegated_attest_get_delegated_key(uint8_t ecc_curve, uint32_t key_bits, @@ -74,143 +71,3 @@ return status; } - - -#else /* !PLAT_RSS_NOT_SUPPORTED */ - -static const uint8_t delegated_key[] = { - 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E, - 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6, - 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E, - 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7, - 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68 -}; - -static const uint8_t platform_token[] = { - 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0, - 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78, - 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F, - 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F, - 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F, - 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20, - 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5, - 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69, - 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD, - 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA, - 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C, - 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00, - 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, - 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, - 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, - 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, - 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21, - 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, - 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, - 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, - 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, - 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19, - 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32, - 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01, - 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06, - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, - 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, - 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, - 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, - 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20, - 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, - 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, - 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, - 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, - 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53, - 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D, - 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01, - 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06, - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, - 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, - 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, - 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63, - 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, - 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, - 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, - 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01, - 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06, - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, - 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, - 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, - 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, - 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20, - 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, - 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, - 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, - 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, - 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20, - 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, - 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, - 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, - 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, - 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06, - 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, - 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, - 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, - 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, - 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76, - 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60, - 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67, - 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA, - 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02, - 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5, - 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E, - 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1, - 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59, - 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98, - 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4, - 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0, - 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C, - 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30 -}; - -psa_status_t -rss_delegated_attest_get_delegated_key(uint8_t ecc_curve, - uint32_t key_bits, - uint8_t *key_buf, - size_t key_buf_size, - size_t *key_size, - uint32_t hash_algo) -{ - (void)ecc_curve; - (void)key_bits; - (void)hash_algo; - - if (key_buf_size < sizeof(delegated_key)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - (void)memcpy(key_buf, delegated_key, sizeof(delegated_key)); - *key_size = sizeof(delegated_key); - - return PSA_SUCCESS; -} -psa_status_t -rss_delegated_attest_get_token(const uint8_t *dak_pub_hash, - size_t dak_pub_hash_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size) -{ - (void)dak_pub_hash; - (void)dak_pub_hash_size; - - if (token_buf_size < sizeof(platform_token)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - (void)memcpy(token_buf, platform_token, sizeof(platform_token)); - *token_size = sizeof(platform_token); - - return PSA_SUCCESS; -} -#endif /* !PLAT_RSS_NOT_SUPPORTED */
diff --git a/lib/psa/measured_boot.c b/lib/psa/measured_boot.c index 10c43f1..c359e9f 100644 --- a/lib/psa/measured_boot.c +++ b/lib/psa/measured_boot.c
@@ -80,16 +80,23 @@ .lock_measurement = lock_measurement, .measurement_algo = measurement_algo, .sw_type = {0}, - /* Removing \0 */ - .sw_type_size = (sw_type_size > 0) ? (sw_type_size - 1) : 0, + .sw_type_size = sw_type_size, }; + if (version_size > VERSION_MAX_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + + if (version_size > 0 && version[version_size - 1] == '\0') { + version_size--; + } + psa_invec in_vec[] = { {.base = &extend_iov, .len = sizeof(struct measured_boot_extend_iovec_t)}, {.base = signer_id, .len = signer_id_size}, - {.base = version, - .len = (version_size > 0) ? (version_size - 1) : 0}, + {.base = version, .len = version_size }, {.base = measurement_value, .len = measurement_value_size} }; @@ -97,6 +104,9 @@ if (extend_iov.sw_type_size > SW_TYPE_MAX_SIZE) { return PSA_ERROR_INVALID_ARGUMENT; } + if (sw_type_size > 0 && sw_type[sw_type_size - 1] == '\0') { + extend_iov.sw_type_size--; + } memcpy(extend_iov.sw_type, sw_type, extend_iov.sw_type_size); }
diff --git a/lib/psa/rss_platform.c b/lib/psa/rss_platform.c index 359f894..7d90bfc 100644 --- a/lib/psa/rss_platform.c +++ b/lib/psa/rss_platform.c
@@ -5,10 +5,9 @@ * */ -#include <stdint.h> - #include <psa/client.h> #include <psa_manifest/sid.h> +#include <rss_crypto_defs.h> #include <rss_platform_api.h> psa_status_t @@ -41,3 +40,30 @@ RSS_PLATFORM_API_ID_NV_READ, in_vec, 1, out_vec, 1); } + +psa_status_t +rss_platform_key_read(enum rss_key_id_builtin_t key, uint8_t *data, + size_t data_size, size_t *data_length) +{ + psa_status_t status; + + struct rss_crypto_pack_iovec iov = { + .function_id = RSS_CRYPTO_EXPORT_PUBLIC_KEY_SID, + .key_id = key, + }; + + psa_invec in_vec[] = { + {.base = &iov, .len = sizeof(struct rss_crypto_pack_iovec)}, + }; + psa_outvec out_vec[] = { + {.base = data, .len = data_size} + }; + + status = psa_call(RSS_CRYPTO_HANDLE, PSA_IPC_CALL, + in_vec, IOVEC_LEN(in_vec), + out_vec, IOVEC_LEN(out_vec)); + + *data_length = out_vec[0].len; + + return status; +}
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S index d28d469..4e1013c 100644 --- a/lib/psci/aarch32/psci_helpers.S +++ b/lib/psci/aarch32/psci_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S index 61f31e5..3b77ab2 100644 --- a/lib/psci/aarch64/psci_helpers.S +++ b/lib/psci/aarch64/psci_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S index 8d46691..89e3e12 100644 --- a/lib/psci/aarch64/runtime_errata.S +++ b/lib/psci/aarch64/runtime_errata.S
@@ -20,7 +20,7 @@ mov x18, x0 #if ERRATA_A510_2684597 - bl errata_cortex_a510_2684597_wa + bl erratum_cortex_a510_2684597_wa #endif ret x19
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index c893476..f9de432 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -451,8 +451,8 @@ * enter. This function will be called after coordination of requested power * states has been done for each power level. *****************************************************************************/ -static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, - const psci_power_state_t *target_state) +void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, + const psci_power_state_t *target_state) { unsigned int parent_idx, lvl; const plat_local_state_t *pd_state = target_state->pwr_domain_state; @@ -474,7 +474,6 @@ } } - /******************************************************************************* * PSCI helper function to get the parent nodes corresponding to a cpu_index. ******************************************************************************/ @@ -595,9 +594,6 @@ state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; } - - /* Update the target state in the power domain nodes */ - psci_set_target_local_pwr_states(end_pwrlvl, state_info); } #if PSCI_OS_INIT_MODE @@ -684,9 +680,6 @@ return rc; } - /* Update the target state in the power domain nodes */ - psci_set_target_local_pwr_states(end_pwrlvl, state_info); - return rc; } #endif @@ -825,20 +818,6 @@ } /******************************************************************************* - * Simple routine to determine whether a mpidr is valid or not. - ******************************************************************************/ -int psci_validate_mpidr(u_register_t mpidr) -{ - int pos = plat_core_pos_by_mpidr(mpidr); - - if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) { - return PSCI_E_INVALID_PARAMS; - } - - return PSCI_E_SUCCESS; -} - -/******************************************************************************* * This function determines the full entrypoint information for the requested * PSCI entrypoint on power on/resume and returns it. ******************************************************************************/ @@ -992,6 +971,9 @@ unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; + /* Init registers that never change for the lifetime of TF-A */ + cm_manage_extensions_el3(); + /* * Verify that we have been explicitly turned ON or resumed from * suspend. @@ -1041,6 +1023,13 @@ psci_cpu_suspend_finish(cpu_idx, &state_info); /* + * Generic management: Now we just need to retrieve the + * information that we had stashed away during the cpu_on + * call to set this cpu on its way. + */ + cm_prepare_el3_exit_ns(); + + /* * Set the requested and target state of this CPU and all the higher * power domains which are ancestors of this CPU to run. */
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 326f125..a015531 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c
@@ -29,9 +29,8 @@ int rc; entry_point_info_t ep; - /* Determine if the cpu exists of not */ - rc = psci_validate_mpidr(target_cpu); - if (rc != PSCI_E_SUCCESS) + /* Validate the target CPU */ + if (!is_valid_mpidr(target_cpu)) return PSCI_E_INVALID_PARAMS; /* Validate the entry point and get the entry_point_info */ @@ -245,19 +244,18 @@ int psci_affinity_info(u_register_t target_affinity, unsigned int lowest_affinity_level) { - int ret; unsigned int target_idx; + /* Validate the target affinity */ + if (!is_valid_mpidr(target_affinity)) + return PSCI_E_INVALID_PARAMS; + /* We dont support level higher than PSCI_CPU_PWR_LVL */ if (lowest_affinity_level > PSCI_CPU_PWR_LVL) return PSCI_E_INVALID_PARAMS; /* Calculate the cpu index of the target */ - ret = plat_core_pos_by_mpidr(target_affinity); - if (ret == -1) { - return PSCI_E_INVALID_PARAMS; - } - target_idx = (unsigned int)ret; + target_idx = (unsigned int) plat_core_pos_by_mpidr(target_affinity); /* * Generic management: @@ -285,6 +283,10 @@ int rc; u_register_t resident_cpu_mpidr; + /* Validate the target cpu */ + if (!is_valid_mpidr(target_cpu)) + return PSCI_E_INVALID_PARAMS; + rc = psci_spd_migrate_info(&resident_cpu_mpidr); if (rc != PSCI_TOS_UP_MIG_CAP) return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? @@ -298,8 +300,7 @@ return PSCI_E_NOT_PRESENT; /* Check the validity of the specified target cpu */ - rc = psci_validate_mpidr(target_cpu); - if (rc != PSCI_E_SUCCESS) + if (!is_valid_mpidr(target_cpu)) return PSCI_E_INVALID_PARAMS; assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL)); @@ -339,8 +340,7 @@ int rc; /* Validate target_cpu */ - rc = psci_validate_mpidr(target_cpu); - if (rc != PSCI_E_SUCCESS) + if (!is_valid_mpidr(target_cpu)) return PSCI_E_INVALID_PARAMS; /* Validate power_level against PLAT_MAX_PWR_LVL */
diff --git a/lib/psci/psci_mem_protect.c b/lib/psci/psci_mem_protect.c index 481051f..385dcd2 100644 --- a/lib/psci/psci_mem_protect.c +++ b/lib/psci/psci_mem_protect.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index 9f36ac7..f83753f 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c
@@ -104,6 +104,9 @@ */ psci_do_state_coordination(end_pwrlvl, &state_info); + /* Update the target state in the power domain nodes */ + psci_set_target_local_pwr_states(end_pwrlvl, &state_info); + #if ENABLE_PSCI_STAT /* Update the last cpu for each level till end_pwrlvl */ psci_stats_update_pwr_down(end_pwrlvl, &state_info);
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c index 76eb50c..b279774 100644 --- a/lib/psci/psci_on.c +++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -61,15 +61,7 @@ { int rc; aff_info_state_t target_aff_state; - int ret = plat_core_pos_by_mpidr(target_cpu); - unsigned int target_idx; - - /* Calling function must supply valid input arguments */ - assert(ret >= 0); - assert((unsigned int)ret < PLATFORM_CORE_COUNT); - assert(ep != NULL); - - target_idx = (unsigned int)ret; + unsigned int target_idx = (unsigned int)plat_core_pos_by_mpidr(target_cpu); /* * This function must only be called on platforms where the @@ -225,11 +217,4 @@ /* Populate the mpidr field within the cpu node array */ /* This needs to be done only once */ psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; - - /* - * Generic management: Now we just need to retrieve the - * information that we had stashed away during the cpu_on - * call to set this cpu on its way. - */ - cm_prepare_el3_exit_ns(); }
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h index b9987fe..2eb4a9b 100644 --- a/lib/psci/psci_private.h +++ b/lib/psci/psci_private.h
@@ -286,7 +286,6 @@ int psci_validate_power_state(unsigned int power_state, psci_power_state_t *state_info); void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); -int psci_validate_mpidr(u_register_t mpidr); void psci_init_req_local_pwr_states(void); #if PSCI_OS_INIT_MODE void psci_update_req_local_pwr_states(unsigned int end_pwrlvl, @@ -298,6 +297,8 @@ #endif void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, psci_power_state_t *target_state); +void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, + const psci_power_state_t *target_state); int psci_validate_entry_point(entry_point_info_t *ep, uintptr_t entrypoint, u_register_t context_id); void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c index 16d6e45..6bf1ff4 100644 --- a/lib/psci/psci_setup.c +++ b/lib/psci/psci_setup.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +11,8 @@ #include <arch_helpers.h> #include <common/bl_common.h> #include <context.h> +#include <lib/cpus/errata.h> #include <lib/el3_runtime/context_mgmt.h> -#include <lib/cpus/errata_report.h> #include <plat/common/platform.h> #include "psci_private.h"
diff --git a/lib/psci/psci_stat.c b/lib/psci/psci_stat.c index ecef95a..bedb816d 100644 --- a/lib/psci/psci_stat.c +++ b/lib/psci/psci_stat.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -181,10 +181,8 @@ psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; plat_local_state_t local_state; - /* Validate the target_cpu parameter and determine the cpu index */ + /* Determine the cpu index */ target_idx = (unsigned int) plat_core_pos_by_mpidr(target_cpu); - if (target_idx == (unsigned int) -1) - return PSCI_E_INVALID_PARAMS; /* Validate the power_state parameter */ if (psci_plat_pm_ops->translate_power_state_by_mpidr == NULL) @@ -228,6 +226,11 @@ unsigned int power_state) { psci_stat_t psci_stat; + + /* Validate the target cpu */ + if (!is_valid_mpidr(target_cpu)) + return 0; + int rc = psci_get_stat(target_cpu, power_state, &psci_stat); if (rc == PSCI_E_SUCCESS) @@ -241,6 +244,11 @@ unsigned int power_state) { psci_stat_t psci_stat; + + /* Validate the target cpu */ + if (!is_valid_mpidr(target_cpu)) + return 0; + int rc = psci_get_stat(target_cpu, power_state, &psci_stat); if (rc == PSCI_E_SUCCESS)
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c index 861b875..cb12b83 100644 --- a/lib/psci/psci_suspend.c +++ b/lib/psci/psci_suspend.c
@@ -219,6 +219,19 @@ } #endif +#if PSCI_OS_INIT_MODE + if (psci_plat_pm_ops->pwr_domain_validate_suspend != NULL) { + rc = psci_plat_pm_ops->pwr_domain_validate_suspend(state_info); + if (rc != PSCI_E_SUCCESS) { + skip_wfi = true; + goto exit; + } + } +#endif + + /* Update the target state in the power domain nodes */ + psci_set_target_local_pwr_states(end_pwrlvl, state_info); + #if ENABLE_PSCI_STAT /* Update the last cpu for each level till end_pwrlvl */ psci_stats_update_pwr_down(end_pwrlvl, state_info); @@ -234,15 +247,7 @@ * program the power controller etc. */ -#if PSCI_OS_INIT_MODE - rc = psci_plat_pm_ops->pwr_domain_suspend(state_info); - if (rc != PSCI_E_SUCCESS) { - skip_wfi = true; - goto exit; - } -#else psci_plat_pm_ops->pwr_domain_suspend(state_info); -#endif #if ENABLE_PSCI_STAT plat_psci_stat_accounting_start(state_info); @@ -362,11 +367,4 @@ psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); PUBLISH_EVENT(psci_suspend_pwrdown_finish); - - /* - * Generic management: Now we just need to retrieve the - * information that we had stashed away during the suspend - * call to set this cpu on its way. - */ - cm_prepare_el3_exit_ns(); }
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile index 2ff480b..c3ddc5a 100644 --- a/lib/romlib/Makefile +++ b/lib/romlib/Makefile
@@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/romlib/gen_combined_bl1_romlib.sh b/lib/romlib/gen_combined_bl1_romlib.sh index 1e3f73a..3941467 100755 --- a/lib/romlib/gen_combined_bl1_romlib.sh +++ b/lib/romlib/gen_combined_bl1_romlib.sh
@@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause
diff --git a/lib/romlib/init.s b/lib/romlib/init.s index 7d97e4d..2bea15b 100644 --- a/lib/romlib/init.s +++ b/lib/romlib/init.s
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i index 33710f5..44751a2 100644 --- a/lib/romlib/jmptbl.i +++ b/lib/romlib/jmptbl.i
@@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/romlib/romlib.ld.S b/lib/romlib/romlib.ld.S index d54a684..0d076b4 100644 --- a/lib/romlib/romlib.ld.S +++ b/lib/romlib/romlib.ld.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/semihosting/aarch32/semihosting_call.S b/lib/semihosting/aarch32/semihosting_call.S index aced3d1..42d4718 100644 --- a/lib/semihosting/aarch32/semihosting_call.S +++ b/lib/semihosting/aarch32/semihosting_call.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/semihosting/aarch64/semihosting_call.S b/lib/semihosting/aarch64/semihosting_call.S index 97d2bca..6f60f3e 100644 --- a/lib/semihosting/aarch64/semihosting_call.S +++ b/lib/semihosting/aarch64/semihosting_call.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2014, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c index 163a82d..adc6b78 100644 --- a/lib/semihosting/semihosting.c +++ b/lib/semihosting/semihosting.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/stack_protector/aarch32/asm_stack_protector.S b/lib/stack_protector/aarch32/asm_stack_protector.S index 19b7525..0ffcf8a 100644 --- a/lib/stack_protector/aarch32/asm_stack_protector.S +++ b/lib/stack_protector/aarch32/asm_stack_protector.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/stack_protector/aarch64/asm_stack_protector.S b/lib/stack_protector/aarch64/asm_stack_protector.S index c2245d3..a002617 100644 --- a/lib/stack_protector/aarch64/asm_stack_protector.S +++ b/lib/stack_protector/aarch64/asm_stack_protector.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/stack_protector/stack_protector.c b/lib/stack_protector/stack_protector.c index 3ff74fc..d0f2400 100644 --- a/lib/stack_protector/stack_protector.c +++ b/lib/stack_protector/stack_protector.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/stack_protector/stack_protector.mk b/lib/stack_protector/stack_protector.mk index b5aba15..4f13bc3 100644 --- a/lib/stack_protector/stack_protector.mk +++ b/lib/stack_protector/stack_protector.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/transfer_list/transfer_list.c b/lib/transfer_list/transfer_list.c new file mode 100644 index 0000000..e38bf74 --- /dev/null +++ b/lib/transfer_list/transfer_list.c
@@ -0,0 +1,474 @@ +/* + * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <inttypes.h> +#include <string.h> + +#include <common/debug.h> +#include <lib/transfer_list.h> +#include <lib/utils_def.h> + +void transfer_list_dump(struct transfer_list_header *tl) +{ + struct transfer_list_entry *te = NULL; + int i = 0; + + if (!tl) { + return; + } + NOTICE("Dump transfer list:\n"); + NOTICE("signature 0x%x\n", tl->signature); + NOTICE("checksum 0x%x\n", tl->checksum); + NOTICE("version 0x%x\n", tl->version); + NOTICE("hdr_size 0x%x\n", tl->hdr_size); + NOTICE("alignment 0x%x\n", tl->alignment); + NOTICE("size 0x%x\n", tl->size); + NOTICE("max_size 0x%x\n", tl->max_size); + while (true) { + te = transfer_list_next(tl, te); + if (!te) { + break; + } + NOTICE("Entry %d:\n", i++); + NOTICE("tag_id 0x%x\n", te->tag_id); + NOTICE("hdr_size 0x%x\n", te->hdr_size); + NOTICE("data_size 0x%x\n", te->data_size); + NOTICE("data_addr 0x%lx\n", + (unsigned long)transfer_list_entry_data(te)); + } +} + +/******************************************************************************* + * Creating a transfer list in a reserved memory region specified + * Compliant to 2.4.5 of Firmware handoff specification (v0.9) + * Return pointer to the created transfer list or NULL on error + ******************************************************************************/ +struct transfer_list_header *transfer_list_init(void *addr, size_t max_size) +{ + struct transfer_list_header *tl = addr; + + if (!addr || max_size == 0) { + return NULL; + } + + if (!is_aligned((uintptr_t)addr, 1 << TRANSFER_LIST_INIT_MAX_ALIGN) || + !is_aligned(max_size, 1 << TRANSFER_LIST_INIT_MAX_ALIGN) || + max_size < sizeof(*tl)) { + return NULL; + } + + memset(tl, 0, max_size); + tl->signature = TRANSFER_LIST_SIGNATURE; + tl->version = TRANSFER_LIST_VERSION; + tl->hdr_size = sizeof(*tl); + tl->alignment = TRANSFER_LIST_INIT_MAX_ALIGN; // initial max align + tl->size = sizeof(*tl); // initial size is the size of header + tl->max_size = max_size; + + transfer_list_update_checksum(tl); + + return tl; +} + +/******************************************************************************* + * Relocating a transfer list to a reserved memory region specified + * Compliant to 2.4.6 of Firmware handoff specification (v0.9) + * Return true on success or false on error + ******************************************************************************/ +struct transfer_list_header *transfer_list_relocate( + struct transfer_list_header *tl, + void *addr, size_t max_size) +{ + uintptr_t new_addr, align_mask, align_off; + struct transfer_list_header *new_tl; + uint32_t new_max_size; + + if (!tl || !addr || max_size == 0) { + return NULL; + } + + align_mask = (1 << tl->alignment) - 1; + align_off = (uintptr_t)tl & align_mask; + new_addr = ((uintptr_t)addr & ~align_mask) + align_off; + + if (new_addr < (uintptr_t)addr) { + new_addr += (1 << tl->alignment); + } + + new_max_size = max_size - (new_addr - (uintptr_t)addr); + + // the new space is not sufficient for the tl + if (tl->size > new_max_size) { + return NULL; + } + + new_tl = (struct transfer_list_header *)new_addr; + memmove(new_tl, tl, tl->size); + new_tl->max_size = new_max_size; + + transfer_list_update_checksum(new_tl); + + return new_tl; +} + +/******************************************************************************* + * Verifying the header of a transfer list + * Compliant to 2.4.1 of Firmware handoff specification (v0.9) + * Return transfer list operation status code + ******************************************************************************/ +enum transfer_list_ops transfer_list_check_header( + const struct transfer_list_header *tl) +{ + if (!tl) { + return TL_OPS_NON; + } + + if (tl->signature != TRANSFER_LIST_SIGNATURE) { + ERROR("Bad transfer list signature %#"PRIx32"\n", + tl->signature); + return TL_OPS_NON; + } + + if (!tl->max_size) { + ERROR("Bad transfer list max size %#"PRIx32"\n", + tl->max_size); + return TL_OPS_NON; + } + + if (tl->size > tl->max_size) { + ERROR("Bad transfer list size %#"PRIx32"\n", tl->size); + return TL_OPS_NON; + } + + if (tl->hdr_size != sizeof(struct transfer_list_header)) { + ERROR("Bad transfer list header size %#"PRIx32"\n", tl->hdr_size); + return TL_OPS_NON; + } + + if (!transfer_list_verify_checksum(tl)) { + ERROR("Bad transfer list checksum %#"PRIx32"\n", tl->checksum); + return TL_OPS_NON; + } + + if (tl->version == 0) { + ERROR("Transfer list version is invalid\n"); + return TL_OPS_NON; + } else if (tl->version == TRANSFER_LIST_VERSION) { + INFO("Transfer list version is valid for all operations\n"); + return TL_OPS_ALL; + } else if (tl->version > TRANSFER_LIST_VERSION) { + INFO("Transfer list version is valid for read-only\n"); + return TL_OPS_RO; + } + + INFO("Old transfer list version is detected\n"); + return TL_OPS_CUS; +} + +/******************************************************************************* + * Enumerate the next transfer entry + * Return pointer to the next transfer entry or NULL on error + ******************************************************************************/ +struct transfer_list_entry *transfer_list_next(struct transfer_list_header *tl, + struct transfer_list_entry *last) +{ + struct transfer_list_entry *te = NULL; + uintptr_t tl_ev = 0; + uintptr_t va = 0; + uintptr_t ev = 0; + size_t sz = 0; + + if (!tl) { + return NULL; + } + + tl_ev = (uintptr_t)tl + tl->size; + + if (last) { + va = (uintptr_t)last; + // check if the total size overflow + if (add_overflow(last->hdr_size, + last->data_size, &sz)) { + return NULL; + } + // roundup to the next entry + if (add_with_round_up_overflow(va, sz, + TRANSFER_LIST_GRANULE, &va)) { + return NULL; + } + } else { + va = (uintptr_t)tl + tl->hdr_size; + } + + te = (struct transfer_list_entry *)va; + + if (va + sizeof(*te) > tl_ev || te->hdr_size < sizeof(*te) || + add_overflow(te->hdr_size, te->data_size, &sz) || + add_overflow(va, sz, &ev) || + ev > tl_ev) { + return NULL; + } + + return te; +} + +/******************************************************************************* + * Calculate the byte sum of a transfer list + * Return byte sum of the transfer list + ******************************************************************************/ +static uint8_t calc_byte_sum(const struct transfer_list_header *tl) +{ + uint8_t *b = (uint8_t *)tl; + uint8_t cs = 0; + size_t n = 0; + + if (!tl) { + return 0; + } + + for (n = 0; n < tl->size; n++) { + cs += b[n]; + } + + return cs; +} + +/******************************************************************************* + * Update the checksum of a transfer list + * Return updated checksum of the transfer list + ******************************************************************************/ +void transfer_list_update_checksum(struct transfer_list_header *tl) +{ + uint8_t cs; + + if (!tl) { + return; + } + + cs = calc_byte_sum(tl); + cs -= tl->checksum; + cs = 256 - cs; + tl->checksum = cs; + assert(transfer_list_verify_checksum(tl)); +} + +/******************************************************************************* + * Verify the checksum of a transfer list + * Return true if verified or false if not + ******************************************************************************/ +bool transfer_list_verify_checksum(const struct transfer_list_header *tl) +{ + return !calc_byte_sum(tl); +} + +/******************************************************************************* + * Update the data size of a transfer entry + * Return true on success or false on error + ******************************************************************************/ +bool transfer_list_set_data_size(struct transfer_list_header *tl, + struct transfer_list_entry *te, + uint32_t new_data_size) +{ + uintptr_t tl_old_ev, new_ev = 0, old_ev = 0, ru_new_ev; + struct transfer_list_entry *dummy_te = NULL; + size_t gap = 0; + size_t mov_dis = 0; + size_t sz = 0; + + if (!tl || !te) { + return false; + } + tl_old_ev = (uintptr_t)tl + tl->size; + + // calculate the old and new end of TE + // both must be roundup to align with TRANSFER_LIST_GRANULE + if (add_overflow(te->hdr_size, te->data_size, &sz) || + add_with_round_up_overflow((uintptr_t)te, sz, + TRANSFER_LIST_GRANULE, &old_ev)) { + return false; + } + if (add_overflow(te->hdr_size, new_data_size, &sz) || + add_with_round_up_overflow((uintptr_t)te, sz, + TRANSFER_LIST_GRANULE, &new_ev)) { + return false; + } + + if (new_ev > old_ev) { + // move distance should be roundup + // to meet the requirement of TE data max alignment + // ensure that the increased size doesn't exceed + // the max size of TL + mov_dis = new_ev - old_ev; + if (round_up_overflow(mov_dis, 1 << tl->alignment, + &mov_dis) || tl->size + mov_dis > tl->max_size) { + return false; + } + ru_new_ev = old_ev + mov_dis; + memmove((void *)ru_new_ev, (void *)old_ev, tl_old_ev - old_ev); + tl->size += mov_dis; + gap = ru_new_ev - new_ev; + } else { + gap = old_ev - new_ev; + } + + if (gap >= sizeof(*dummy_te)) { + // create a dummy TE to fill up the gap + dummy_te = (struct transfer_list_entry *)new_ev; + dummy_te->tag_id = TL_TAG_EMPTY; + dummy_te->reserved0 = 0; + dummy_te->hdr_size = sizeof(*dummy_te); + dummy_te->data_size = gap - sizeof(*dummy_te); + } + + te->data_size = new_data_size; + + transfer_list_update_checksum(tl); + return true; +} + +/******************************************************************************* + * Remove a specified transfer entry from a transfer list + * Return true on success or false on error + ******************************************************************************/ +bool transfer_list_rem(struct transfer_list_header *tl, + struct transfer_list_entry *te) +{ + if (!tl || !te || (uintptr_t)te > (uintptr_t)tl + tl->size) { + return false; + } + te->tag_id = TL_TAG_EMPTY; + te->reserved0 = 0; + transfer_list_update_checksum(tl); + return true; +} + +/******************************************************************************* + * Add a new transfer entry into a transfer list + * Compliant to 2.4.3 of Firmware handoff specification (v0.9) + * Return pointer to the added transfer entry or NULL on error + ******************************************************************************/ +struct transfer_list_entry *transfer_list_add(struct transfer_list_header *tl, + uint16_t tag_id, + uint32_t data_size, + const void *data) +{ + uintptr_t max_tl_ev, tl_ev, ev; + struct transfer_list_entry *te = NULL; + uint8_t *te_data = NULL; + size_t sz = 0; + + if (!tl) { + return NULL; + } + + max_tl_ev = (uintptr_t)tl + tl->max_size; + tl_ev = (uintptr_t)tl + tl->size; + ev = tl_ev; + + // skip the step 1 (optional step) + // new TE will be added into the tail + if (add_overflow(sizeof(*te), data_size, &sz) || + add_with_round_up_overflow(ev, sz, + TRANSFER_LIST_GRANULE, &ev) || ev > max_tl_ev) { + return NULL; + } + + te = (struct transfer_list_entry *)tl_ev; + te->tag_id = tag_id; + te->reserved0 = 0; + te->hdr_size = sizeof(*te); + te->data_size = data_size; + tl->size += ev - tl_ev; + + if (data) { + // get TE data pointer + te_data = transfer_list_entry_data(te); + if (!te_data) { + return NULL; + } + memmove(te_data, data, data_size); + } + + transfer_list_update_checksum(tl); + + return te; +} + +/******************************************************************************* + * Add a new transfer entry into a transfer list with specified new data + * alignment requirement + * Compliant to 2.4.4 of Firmware handoff specification (v0.9) + * Return pointer to the added transfer entry or NULL on error + ******************************************************************************/ +struct transfer_list_entry *transfer_list_add_with_align( + struct transfer_list_header *tl, + uint16_t tag_id, uint32_t data_size, + const void *data, uint8_t alignment) +{ + struct transfer_list_entry *te = NULL; + uintptr_t tl_ev, ev, new_tl_ev; + size_t dummy_te_data_sz = 0; + + if (!tl) { + return NULL; + } + + tl_ev = (uintptr_t)tl + tl->size; + ev = tl_ev + sizeof(struct transfer_list_entry); + + if (!is_aligned(ev, 1 << alignment)) { + // TE data address is not aligned to the new alignment + // fill the gap with an empty TE as a placeholder before + // adding the desire TE + new_tl_ev = round_up(ev, 1 << alignment) - + sizeof(struct transfer_list_entry); + dummy_te_data_sz = new_tl_ev - tl_ev - + sizeof(struct transfer_list_entry); + if (!transfer_list_add(tl, TL_TAG_EMPTY, dummy_te_data_sz, + NULL)) { + return NULL; + } + } + + te = transfer_list_add(tl, tag_id, data_size, data); + + if (alignment > tl->alignment) { + tl->alignment = alignment; + transfer_list_update_checksum(tl); + } + + return te; +} + +/******************************************************************************* + * Search for an existing transfer entry with the specified tag id from a + * transfer list + * Return pointer to the found transfer entry or NULL on error + ******************************************************************************/ +struct transfer_list_entry *transfer_list_find(struct transfer_list_header *tl, + uint16_t tag_id) +{ + struct transfer_list_entry *te = NULL; + + do { + te = transfer_list_next(tl, te); + } while (te && (te->tag_id != tag_id || te->reserved0 != 0)); + + return te; +} + +/******************************************************************************* + * Retrieve the data pointer of a specified transfer entry + * Return pointer to the transfer entry data or NULL on error + ******************************************************************************/ +void *transfer_list_entry_data(struct transfer_list_entry *entry) +{ + if (!entry) { + return NULL; + } + return (uint8_t *)entry + entry->hdr_size; +}
diff --git a/lib/transfer_list/transfer_list.mk b/lib/transfer_list/transfer_list.mk new file mode 100644 index 0000000..42574e8 --- /dev/null +++ b/lib/transfer_list/transfer_list.mk
@@ -0,0 +1,20 @@ +# +# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +ifeq (${TRANSFER_LIST},1) + +ifeq (${ARCH},aarch32) +$(eval $(call add_define,TRANSFER_LIST_AARCH32)) +endif + +TRANSFER_LIST_SOURCES += $(addprefix lib/transfer_list/, \ + transfer_list.c) + +BL31_SOURCES += $(TRANSFER_LIST_SOURCES) +BL2_SOURCES += $(TRANSFER_LIST_SOURCES) + +endif # TRANSFER_LIST +
diff --git a/lib/utils/mem_region.c b/lib/utils/mem_region.c index fec086b..e9f0a12 100644 --- a/lib/utils/mem_region.c +++ b/lib/utils/mem_region.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S index 3791f2d..0dda979 100644 --- a/lib/xlat_mpu/aarch64/enable_mpu.S +++ b/lib/xlat_mpu/aarch64/enable_mpu.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c index 5068eb8..5a2120b 100644 --- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c +++ b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_mpu/ro_xlat_mpu.mk b/lib/xlat_mpu/ro_xlat_mpu.mk index 23f1d46..d3af3bd 100644 --- a/lib/xlat_mpu/ro_xlat_mpu.mk +++ b/lib/xlat_mpu/ro_xlat_mpu.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2021, ARM Limited. All rights reserved. +# Copyright (c) 2021, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/xlat_mpu/xlat_mpu.mk b/lib/xlat_mpu/xlat_mpu.mk index 041b91c..31bef04 100644 --- a/lib/xlat_mpu/xlat_mpu.mk +++ b/lib/xlat_mpu/xlat_mpu.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/xlat_mpu/xlat_mpu_context.c b/lib/xlat_mpu/xlat_mpu_context.c index 28c463b..783f21d 100644 --- a/lib/xlat_mpu/xlat_mpu_context.c +++ b/lib/xlat_mpu/xlat_mpu_context.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_mpu/xlat_mpu_core.c b/lib/xlat_mpu/xlat_mpu_core.c index 6b4b0c2..33f381d 100644 --- a/lib/xlat_mpu/xlat_mpu_core.c +++ b/lib/xlat_mpu/xlat_mpu_core.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_mpu/xlat_mpu_private.h b/lib/xlat_mpu/xlat_mpu_private.h index e0e479d..14800e9 100644 --- a/lib/xlat_mpu/xlat_mpu_private.h +++ b/lib/xlat_mpu/xlat_mpu_private.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c index 5400875..dc5f956 100644 --- a/lib/xlat_mpu/xlat_mpu_utils.c +++ b/lib/xlat_mpu/xlat_mpu_utils.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c index 4b01b9b..6d098be 100644 --- a/lib/xlat_tables/aarch32/xlat_tables.c +++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index dc167e3..4dbfc11 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c index e2c8370..8b44df2 100644 --- a/lib/xlat_tables/xlat_tables_common.c +++ b/lib/xlat_tables/xlat_tables_common.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h index 82bc70c..cfecc39 100644 --- a/lib/xlat_tables/xlat_tables_private.h +++ b/lib/xlat_tables/xlat_tables_private.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables_v2/aarch32/enable_mmu.S b/lib/xlat_tables_v2/aarch32/enable_mmu.S index f2fff36..22c2876 100644 --- a/lib/xlat_tables_v2/aarch32/enable_mmu.S +++ b/lib/xlat_tables_v2/aarch32/enable_mmu.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index a1a44af..920754b 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables_v2/aarch64/enable_mmu.S b/lib/xlat_tables_v2/aarch64/enable_mmu.S index 9f075e4..247a796 100644 --- a/lib/xlat_tables_v2/aarch64/enable_mmu.S +++ b/lib/xlat_tables_v2/aarch64/enable_mmu.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index 719110a..bb6a35c 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,22 +22,21 @@ */ bool xlat_arch_is_granule_size_supported(size_t size) { - u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); + unsigned int tgranx; if (size == PAGE_SIZE_4KB) { - return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & - ID_AA64MMFR0_EL1_TGRAN4_MASK) == - ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; + tgranx = read_id_aa64mmfr0_el0_tgran4_field(); + /* MSB of TGRAN4 field will be '1' for unsupported feature */ + return (tgranx < 8U); } else if (size == PAGE_SIZE_16KB) { - return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & - ID_AA64MMFR0_EL1_TGRAN16_MASK) == - ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; + tgranx = read_id_aa64mmfr0_el0_tgran16_field(); + return (tgranx >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED); } else if (size == PAGE_SIZE_64KB) { - return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & - ID_AA64MMFR0_EL1_TGRAN64_MASK) == - ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; + tgranx = read_id_aa64mmfr0_el0_tgran64_field(); + /* MSB of TGRAN64 field will be '1' for unsupported feature */ + return (tgranx < 8U); } else { - return 0; + return false; } }
diff --git a/lib/xlat_tables_v2/ro_xlat_tables.mk b/lib/xlat_tables_v2/ro_xlat_tables.mk index fb8a426..20bb015 100644 --- a/lib/xlat_tables_v2/ro_xlat_tables.mk +++ b/lib/xlat_tables_v2/ro_xlat_tables.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2020-2022, ARM Limited. All rights reserved. +# Copyright (c) 2020-2022, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/xlat_tables_v2/xlat_tables.mk b/lib/xlat_tables_v2/xlat_tables.mk index bcc3e68..b4ad34b 100644 --- a/lib/xlat_tables_v2/xlat_tables.mk +++ b/lib/xlat_tables_v2/xlat_tables.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c index 95dae88..ae9244a 100644 --- a/lib/xlat_tables_v2/xlat_tables_context.c +++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -200,7 +200,7 @@ * region. Therefore, in this case we have to assume that the whole address * space size might be mapped. */ -#ifdef PLAT_XLAT_TABLES_DYNAMIC +#if PLAT_XLAT_TABLES_DYNAMIC #define MAX_PHYS_ADDR tf_xlat_ctx.pa_max_address #else #define MAX_PHYS_ADDR tf_xlat_ctx.max_pa
diff --git a/lib/zlib/adler32.c b/lib/zlib/adler32.c index d0be438..04b81d2 100644 --- a/lib/zlib/adler32.c +++ b/lib/zlib/adler32.c
@@ -7,8 +7,6 @@ #include "zutil.h" -local uLong adler32_combine_ OF((uLong adler1, uLong adler2, z_off64_t len2)); - #define BASE 65521U /* largest prime smaller than 65536 */ #define NMAX 5552 /* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */ @@ -60,11 +58,7 @@ #endif /* ========================================================================= */ -uLong ZEXPORT adler32_z(adler, buf, len) - uLong adler; - const Bytef *buf; - z_size_t len; -{ +uLong ZEXPORT adler32_z(uLong adler, const Bytef *buf, z_size_t len) { unsigned long sum2; unsigned n; @@ -131,20 +125,12 @@ } /* ========================================================================= */ -uLong ZEXPORT adler32(adler, buf, len) - uLong adler; - const Bytef *buf; - uInt len; -{ +uLong ZEXPORT adler32(uLong adler, const Bytef *buf, uInt len) { return adler32_z(adler, buf, len); } /* ========================================================================= */ -local uLong adler32_combine_(adler1, adler2, len2) - uLong adler1; - uLong adler2; - z_off64_t len2; -{ +local uLong adler32_combine_(uLong adler1, uLong adler2, z_off64_t len2) { unsigned long sum1; unsigned long sum2; unsigned rem; @@ -169,18 +155,10 @@ } /* ========================================================================= */ -uLong ZEXPORT adler32_combine(adler1, adler2, len2) - uLong adler1; - uLong adler2; - z_off_t len2; -{ +uLong ZEXPORT adler32_combine(uLong adler1, uLong adler2, z_off_t len2) { return adler32_combine_(adler1, adler2, len2); } -uLong ZEXPORT adler32_combine64(adler1, adler2, len2) - uLong adler1; - uLong adler2; - z_off64_t len2; -{ +uLong ZEXPORT adler32_combine64(uLong adler1, uLong adler2, z_off64_t len2) { return adler32_combine_(adler1, adler2, len2); }
diff --git a/lib/zlib/crc32.c b/lib/zlib/crc32.c index 21a69a8..6c38f5c 100644 --- a/lib/zlib/crc32.c +++ b/lib/zlib/crc32.c
@@ -103,19 +103,6 @@ # define ARMCRC32 #endif -/* Local functions. */ -local z_crc_t multmodp OF((z_crc_t a, z_crc_t b)); -local z_crc_t x2nmodp OF((z_off64_t n, unsigned k)); - -#if defined(W) && (!defined(ARMCRC32) || defined(DYNAMIC_CRC_TABLE)) - local z_word_t byte_swap OF((z_word_t word)); -#endif - -#if defined(W) && !defined(ARMCRC32) - local z_crc_t crc_word OF((z_word_t data)); - local z_word_t crc_word_big OF((z_word_t data)); -#endif - #if defined(W) && (!defined(ARMCRC32) || defined(DYNAMIC_CRC_TABLE)) /* Swap the bytes in a z_word_t to convert between little and big endian. Any @@ -123,9 +110,7 @@ instruction, if one is available. This assumes that word_t is either 32 bits or 64 bits. */ -local z_word_t byte_swap(word) - z_word_t word; -{ +local z_word_t byte_swap(z_word_t word) { # if W == 8 return (word & 0xff00000000000000) >> 56 | @@ -146,24 +131,77 @@ } #endif +#ifdef DYNAMIC_CRC_TABLE +/* ========================================================================= + * Table of powers of x for combining CRC-32s, filled in by make_crc_table() + * below. + */ + local z_crc_t FAR x2n_table[32]; +#else +/* ========================================================================= + * Tables for byte-wise and braided CRC-32 calculations, and a table of powers + * of x for combining CRC-32s, all made by make_crc_table(). + */ +# include "crc32.h" +#endif + /* CRC polynomial. */ #define POLY 0xedb88320 /* p(x) reflected, with x^32 implied */ -#ifdef DYNAMIC_CRC_TABLE +/* + Return a(x) multiplied by b(x) modulo p(x), where p(x) is the CRC polynomial, + reflected. For speed, this requires that a not be zero. + */ +local z_crc_t multmodp(z_crc_t a, z_crc_t b) { + z_crc_t m, p; + m = (z_crc_t)1 << 31; + p = 0; + for (;;) { + if (a & m) { + p ^= b; + if ((a & (m - 1)) == 0) + break; + } + m >>= 1; + b = b & 1 ? (b >> 1) ^ POLY : b >> 1; + } + return p; +} + +/* + Return x^(n * 2^k) modulo p(x). Requires that x2n_table[] has been + initialized. + */ +local z_crc_t x2nmodp(z_off64_t n, unsigned k) { + z_crc_t p; + + p = (z_crc_t)1 << 31; /* x^0 == 1 */ + while (n) { + if (n & 1) + p = multmodp(x2n_table[k & 31], p); + n >>= 1; + k++; + } + return p; +} + +#ifdef DYNAMIC_CRC_TABLE +/* ========================================================================= + * Build the tables for byte-wise and braided CRC-32 calculations, and a table + * of powers of x for combining CRC-32s. + */ local z_crc_t FAR crc_table[256]; -local z_crc_t FAR x2n_table[32]; -local void make_crc_table OF((void)); #ifdef W local z_word_t FAR crc_big_table[256]; local z_crc_t FAR crc_braid_table[W][256]; local z_word_t FAR crc_braid_big_table[W][256]; - local void braid OF((z_crc_t [][256], z_word_t [][256], int, int)); + local void braid(z_crc_t [][256], z_word_t [][256], int, int); #endif #ifdef MAKECRCH - local void write_table OF((FILE *, const z_crc_t FAR *, int)); - local void write_table32hi OF((FILE *, const z_word_t FAR *, int)); - local void write_table64 OF((FILE *, const z_word_t FAR *, int)); + local void write_table(FILE *, const z_crc_t FAR *, int); + local void write_table32hi(FILE *, const z_word_t FAR *, int); + local void write_table64(FILE *, const z_word_t FAR *, int); #endif /* MAKECRCH */ /* @@ -176,7 +214,6 @@ /* Definition of once functionality. */ typedef struct once_s once_t; -local void once OF((once_t *, void (*)(void))); /* Check for the availability of atomics. */ #if defined(__STDC__) && __STDC_VERSION__ >= 201112L && \ @@ -196,10 +233,7 @@ invoke once() at the same time. The state must be a once_t initialized with ONCE_INIT. */ -local void once(state, init) - once_t *state; - void (*init)(void); -{ +local void once(once_t *state, void (*init)(void)) { if (!atomic_load(&state->done)) { if (atomic_flag_test_and_set(&state->begun)) while (!atomic_load(&state->done)) @@ -222,10 +256,7 @@ /* Test and set. Alas, not atomic, but tries to minimize the period of vulnerability. */ -local int test_and_set OF((int volatile *)); -local int test_and_set(flag) - int volatile *flag; -{ +local int test_and_set(int volatile *flag) { int was; was = *flag; @@ -234,10 +265,7 @@ } /* Run the provided init() function once. This is not thread-safe. */ -local void once(state, init) - once_t *state; - void (*init)(void); -{ +local void once(once_t *state, void (*init)(void)) { if (!state->done) { if (test_and_set(&state->begun)) while (!state->done) @@ -279,8 +307,7 @@ combinations of CRC register values and incoming bytes. */ -local void make_crc_table(void) -{ +local void make_crc_table(void) { unsigned i, j, n; z_crc_t p; @@ -447,11 +474,7 @@ Write the 32-bit values in table[0..k-1] to out, five per line in hexadecimal separated by commas. */ -local void write_table(out, table, k) - FILE *out; - const z_crc_t FAR *table; - int k; -{ +local void write_table(FILE *out, const z_crc_t FAR *table, int k) { int n; for (n = 0; n < k; n++) @@ -464,11 +487,7 @@ Write the high 32-bits of each value in table[0..k-1] to out, five per line in hexadecimal separated by commas. */ -local void write_table32hi(out, table, k) -FILE *out; -const z_word_t FAR *table; -int k; -{ +local void write_table32hi(FILE *out, const z_word_t FAR *table, int k) { int n; for (n = 0; n < k; n++) @@ -484,11 +503,7 @@ bits. If not, then the type cast and format string can be adjusted accordingly. */ -local void write_table64(out, table, k) - FILE *out; - const z_word_t FAR *table; - int k; -{ +local void write_table64(FILE *out, const z_word_t FAR *table, int k) { int n; for (n = 0; n < k; n++) @@ -498,8 +513,7 @@ } /* Actually do the deed. */ -int main(void) -{ +int main(void) { make_crc_table(); return 0; } @@ -511,12 +525,7 @@ Generate the little and big-endian braid tables for the given n and z_word_t size w. Each array must have room for w blocks of 256 elements. */ -local void braid(ltl, big, n, w) - z_crc_t ltl[][256]; - z_word_t big[][256]; - int n; - int w; -{ +local void braid(z_crc_t ltl[][256], z_word_t big[][256], int n, int w) { int k; z_crc_t i, p, q; for (k = 0; k < w; k++) { @@ -531,69 +540,13 @@ } #endif -#else /* !DYNAMIC_CRC_TABLE */ -/* ======================================================================== - * Tables for byte-wise and braided CRC-32 calculations, and a table of powers - * of x for combining CRC-32s, all made by make_crc_table(). - */ -#include "crc32.h" #endif /* DYNAMIC_CRC_TABLE */ -/* ======================================================================== - * Routines used for CRC calculation. Some are also required for the table - * generation above. - */ - -/* - Return a(x) multiplied by b(x) modulo p(x), where p(x) is the CRC polynomial, - reflected. For speed, this requires that a not be zero. - */ -local z_crc_t multmodp(a, b) - z_crc_t a; - z_crc_t b; -{ - z_crc_t m, p; - - m = (z_crc_t)1 << 31; - p = 0; - for (;;) { - if (a & m) { - p ^= b; - if ((a & (m - 1)) == 0) - break; - } - m >>= 1; - b = b & 1 ? (b >> 1) ^ POLY : b >> 1; - } - return p; -} - -/* - Return x^(n * 2^k) modulo p(x). Requires that x2n_table[] has been - initialized. - */ -local z_crc_t x2nmodp(n, k) - z_off64_t n; - unsigned k; -{ - z_crc_t p; - - p = (z_crc_t)1 << 31; /* x^0 == 1 */ - while (n) { - if (n & 1) - p = multmodp(x2n_table[k & 31], p); - n >>= 1; - k++; - } - return p; -} - /* ========================================================================= * This function can be used by asm versions of crc32(), and to force the * generation of the CRC tables in a threaded application. */ -const z_crc_t FAR * ZEXPORT get_crc_table() -{ +const z_crc_t FAR * ZEXPORT get_crc_table(void) { #ifdef DYNAMIC_CRC_TABLE once(&made, make_crc_table); #endif /* DYNAMIC_CRC_TABLE */ @@ -619,11 +572,8 @@ #define Z_BATCH_ZEROS 0xa10d3d0c /* computed from Z_BATCH = 3990 */ #define Z_BATCH_MIN 800 /* fewest words in a final batch */ -unsigned long ZEXPORT crc32_z(crc, buf, len) - unsigned long crc; - const unsigned char FAR *buf; - z_size_t len; -{ +unsigned long ZEXPORT crc32_z(unsigned long crc, const unsigned char FAR *buf, + z_size_t len) { z_crc_t val; z_word_t crc1, crc2; const z_word_t *word; @@ -723,18 +673,14 @@ least-significant byte of the word as the first byte of data, without any pre or post conditioning. This is used to combine the CRCs of each braid. */ -local z_crc_t crc_word(data) - z_word_t data; -{ +local z_crc_t crc_word(z_word_t data) { int k; for (k = 0; k < W; k++) data = (data >> 8) ^ crc_table[data & 0xff]; return (z_crc_t)data; } -local z_word_t crc_word_big(data) - z_word_t data; -{ +local z_word_t crc_word_big(z_word_t data) { int k; for (k = 0; k < W; k++) data = (data << 8) ^ @@ -745,11 +691,8 @@ #endif /* ========================================================================= */ -unsigned long ZEXPORT crc32_z(crc, buf, len) - unsigned long crc; - const unsigned char FAR *buf; - z_size_t len; -{ +unsigned long ZEXPORT crc32_z(unsigned long crc, const unsigned char FAR *buf, + z_size_t len) { /* Return initial CRC, if requested. */ if (buf == Z_NULL) return 0; @@ -781,8 +724,8 @@ words = (z_word_t const *)buf; /* Do endian check at execution time instead of compile time, since ARM - processors can change the endianess at execution time. If the - compiler knows what the endianess will be, it can optimize out the + processors can change the endianness at execution time. If the + compiler knows what the endianness will be, it can optimize out the check and the unused branch. */ endian = 1; if (*(unsigned char *)&endian) { @@ -1069,20 +1012,13 @@ #endif /* ========================================================================= */ -unsigned long ZEXPORT crc32(crc, buf, len) - unsigned long crc; - const unsigned char FAR *buf; - uInt len; -{ +unsigned long ZEXPORT crc32(unsigned long crc, const unsigned char FAR *buf, + uInt len) { return crc32_z(crc, buf, len); } /* ========================================================================= */ -uLong ZEXPORT crc32_combine64(crc1, crc2, len2) - uLong crc1; - uLong crc2; - z_off64_t len2; -{ +uLong ZEXPORT crc32_combine64(uLong crc1, uLong crc2, z_off64_t len2) { #ifdef DYNAMIC_CRC_TABLE once(&made, make_crc_table); #endif /* DYNAMIC_CRC_TABLE */ @@ -1090,18 +1026,12 @@ } /* ========================================================================= */ -uLong ZEXPORT crc32_combine(crc1, crc2, len2) - uLong crc1; - uLong crc2; - z_off_t len2; -{ +uLong ZEXPORT crc32_combine(uLong crc1, uLong crc2, z_off_t len2) { return crc32_combine64(crc1, crc2, (z_off64_t)len2); } /* ========================================================================= */ -uLong ZEXPORT crc32_combine_gen64(len2) - z_off64_t len2; -{ +uLong ZEXPORT crc32_combine_gen64(z_off64_t len2) { #ifdef DYNAMIC_CRC_TABLE once(&made, make_crc_table); #endif /* DYNAMIC_CRC_TABLE */ @@ -1109,17 +1039,11 @@ } /* ========================================================================= */ -uLong ZEXPORT crc32_combine_gen(len2) - z_off_t len2; -{ +uLong ZEXPORT crc32_combine_gen(z_off_t len2) { return crc32_combine_gen64((z_off64_t)len2); } /* ========================================================================= */ -uLong ZEXPORT crc32_combine_op(crc1, crc2, op) - uLong crc1; - uLong crc2; - uLong op; -{ +uLong ZEXPORT crc32_combine_op(uLong crc1, uLong crc2, uLong op) { return multmodp(op, crc1) ^ (crc2 & 0xffffffff); }
diff --git a/lib/zlib/inffast.c b/lib/zlib/inffast.c index 1fec7f3..9354676 100644 --- a/lib/zlib/inffast.c +++ b/lib/zlib/inffast.c
@@ -47,10 +47,7 @@ requires strm->avail_out >= 258 for each loop to avoid checking for output space. */ -void ZLIB_INTERNAL inflate_fast(strm, start) -z_streamp strm; -unsigned start; /* inflate()'s starting value for strm->avail_out */ -{ +void ZLIB_INTERNAL inflate_fast(z_streamp strm, unsigned start) { struct inflate_state FAR *state; z_const unsigned char FAR *in; /* local strm->next_in */ z_const unsigned char FAR *last; /* have enough input while in < last */
diff --git a/lib/zlib/inffast.h b/lib/zlib/inffast.h index e5c1aa4..49c6d15 100644 --- a/lib/zlib/inffast.h +++ b/lib/zlib/inffast.h
@@ -8,4 +8,4 @@ subject to change. Applications should only use zlib.h. */ -void ZLIB_INTERNAL inflate_fast OF((z_streamp strm, unsigned start)); +void ZLIB_INTERNAL inflate_fast(z_streamp strm, unsigned start);
diff --git a/lib/zlib/inflate.c b/lib/zlib/inflate.c index aa25e61..b0757a9 100644 --- a/lib/zlib/inflate.c +++ b/lib/zlib/inflate.c
@@ -91,20 +91,7 @@ # endif #endif -/* function prototypes */ -local int inflateStateCheck OF((z_streamp strm)); -local void fixedtables OF((struct inflate_state FAR *state)); -local int updatewindow OF((z_streamp strm, const unsigned char FAR *end, - unsigned copy)); -#ifdef BUILDFIXED - void makefixed OF((void)); -#endif -local unsigned syncsearch OF((unsigned FAR *have, const unsigned char FAR *buf, - unsigned len)); - -local int inflateStateCheck(strm) -z_streamp strm; -{ +local int inflateStateCheck(z_streamp strm) { struct inflate_state FAR *state; if (strm == Z_NULL || strm->zalloc == (alloc_func)0 || strm->zfree == (free_func)0) @@ -116,9 +103,7 @@ return 0; } -int ZEXPORT inflateResetKeep(strm) -z_streamp strm; -{ +int ZEXPORT inflateResetKeep(z_streamp strm) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; @@ -142,9 +127,7 @@ return Z_OK; } -int ZEXPORT inflateReset(strm) -z_streamp strm; -{ +int ZEXPORT inflateReset(z_streamp strm) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; @@ -155,10 +138,7 @@ return inflateResetKeep(strm); } -int ZEXPORT inflateReset2(strm, windowBits) -z_streamp strm; -int windowBits; -{ +int ZEXPORT inflateReset2(z_streamp strm, int windowBits) { int wrap; struct inflate_state FAR *state; @@ -195,12 +175,8 @@ return inflateReset(strm); } -int ZEXPORT inflateInit2_(strm, windowBits, version, stream_size) -z_streamp strm; -int windowBits; -const char *version; -int stream_size; -{ +int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, + const char *version, int stream_size) { int ret; struct inflate_state FAR *state; @@ -239,22 +215,17 @@ return ret; } -int ZEXPORT inflateInit_(strm, version, stream_size) -z_streamp strm; -const char *version; -int stream_size; -{ +int ZEXPORT inflateInit_(z_streamp strm, const char *version, + int stream_size) { return inflateInit2_(strm, DEF_WBITS, version, stream_size); } -int ZEXPORT inflatePrime(strm, bits, value) -z_streamp strm; -int bits; -int value; -{ +int ZEXPORT inflatePrime(z_streamp strm, int bits, int value) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; + if (bits == 0) + return Z_OK; state = (struct inflate_state FAR *)strm->state; if (bits < 0) { state->hold = 0; @@ -278,9 +249,7 @@ used for threaded applications, since the rewriting of the tables and virgin may not be thread-safe. */ -local void fixedtables(state) -struct inflate_state FAR *state; -{ +local void fixedtables(struct inflate_state FAR *state) { #ifdef BUILDFIXED static int virgin = 1; static code *lenfix, *distfix; @@ -396,11 +365,7 @@ output will fall in the output data, making match copies simpler and faster. The advantage may be dependent on the size of the processor's data caches. */ -local int updatewindow(strm, end, copy) -z_streamp strm; -const Bytef *end; -unsigned copy; -{ +local int updatewindow(z_streamp strm, const Bytef *end, unsigned copy) { struct inflate_state FAR *state; unsigned dist; @@ -622,10 +587,7 @@ will return Z_BUF_ERROR if it has not reached the end of the stream. */ -int ZEXPORT inflate(strm, flush) -z_streamp strm; -int flush; -{ +int ZEXPORT inflate(z_streamp strm, int flush) { struct inflate_state FAR *state; z_const unsigned char FAR *next; /* next input */ unsigned char FAR *put; /* next output */ @@ -1301,9 +1263,7 @@ return ret; } -int ZEXPORT inflateEnd(strm) -z_streamp strm; -{ +int ZEXPORT inflateEnd(z_streamp strm) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; @@ -1315,11 +1275,8 @@ return Z_OK; } -int ZEXPORT inflateGetDictionary(strm, dictionary, dictLength) -z_streamp strm; -Bytef *dictionary; -uInt *dictLength; -{ +int ZEXPORT inflateGetDictionary(z_streamp strm, Bytef *dictionary, + uInt *dictLength) { struct inflate_state FAR *state; /* check state */ @@ -1338,11 +1295,8 @@ return Z_OK; } -int ZEXPORT inflateSetDictionary(strm, dictionary, dictLength) -z_streamp strm; -const Bytef *dictionary; -uInt dictLength; -{ +int ZEXPORT inflateSetDictionary(z_streamp strm, const Bytef *dictionary, + uInt dictLength) { struct inflate_state FAR *state; unsigned long dictid; int ret; @@ -1373,10 +1327,7 @@ return Z_OK; } -int ZEXPORT inflateGetHeader(strm, head) -z_streamp strm; -gz_headerp head; -{ +int ZEXPORT inflateGetHeader(z_streamp strm, gz_headerp head) { struct inflate_state FAR *state; /* check state */ @@ -1401,11 +1352,8 @@ called again with more data and the *have state. *have is initialized to zero for the first call. */ -local unsigned syncsearch(have, buf, len) -unsigned FAR *have; -const unsigned char FAR *buf; -unsigned len; -{ +local unsigned syncsearch(unsigned FAR *have, const unsigned char FAR *buf, + unsigned len) { unsigned got; unsigned next; @@ -1424,9 +1372,7 @@ return next; } -int ZEXPORT inflateSync(strm) -z_streamp strm; -{ +int ZEXPORT inflateSync(z_streamp strm) { unsigned len; /* number of bytes to look at or looked at */ int flags; /* temporary to save header status */ unsigned long in, out; /* temporary to save total_in and total_out */ @@ -1482,9 +1428,7 @@ block. When decompressing, PPP checks that at the end of input packet, inflate is waiting for these length bytes. */ -int ZEXPORT inflateSyncPoint(strm) -z_streamp strm; -{ +int ZEXPORT inflateSyncPoint(z_streamp strm) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; @@ -1492,10 +1436,7 @@ return state->mode == STORED && state->bits == 0; } -int ZEXPORT inflateCopy(dest, source) -z_streamp dest; -z_streamp source; -{ +int ZEXPORT inflateCopy(z_streamp dest, z_streamp source) { struct inflate_state FAR *state; struct inflate_state FAR *copy; unsigned char FAR *window; @@ -1539,10 +1480,7 @@ return Z_OK; } -int ZEXPORT inflateUndermine(strm, subvert) -z_streamp strm; -int subvert; -{ +int ZEXPORT inflateUndermine(z_streamp strm, int subvert) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; @@ -1557,10 +1495,7 @@ #endif } -int ZEXPORT inflateValidate(strm, check) -z_streamp strm; -int check; -{ +int ZEXPORT inflateValidate(z_streamp strm, int check) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return Z_STREAM_ERROR; @@ -1572,9 +1507,7 @@ return Z_OK; } -long ZEXPORT inflateMark(strm) -z_streamp strm; -{ +long ZEXPORT inflateMark(z_streamp strm) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) @@ -1585,9 +1518,7 @@ (state->mode == MATCH ? state->was - state->length : 0)); } -unsigned long ZEXPORT inflateCodesUsed(strm) -z_streamp strm; -{ +unsigned long ZEXPORT inflateCodesUsed(z_streamp strm) { struct inflate_state FAR *state; if (inflateStateCheck(strm)) return (unsigned long)-1; state = (struct inflate_state FAR *)strm->state;
diff --git a/lib/zlib/inftrees.c b/lib/zlib/inftrees.c index 57d2793..8a208c2 100644 --- a/lib/zlib/inftrees.c +++ b/lib/zlib/inftrees.c
@@ -1,5 +1,5 @@ /* inftrees.c -- generate Huffman trees for efficient decoding - * Copyright (C) 1995-2022 Mark Adler + * Copyright (C) 1995-2023 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h */ @@ -9,7 +9,7 @@ #define MAXBITS 15 const char inflate_copyright[] = - " inflate 1.2.13 Copyright 1995-2022 Mark Adler "; + " inflate 1.3 Copyright 1995-2023 Mark Adler "; /* If you use the zlib library in a product, an acknowledgment is welcome in the documentation of your product. If for some reason you cannot @@ -29,14 +29,9 @@ table index bits. It will differ if the request is greater than the longest code or if it is less than the shortest code. */ -int ZLIB_INTERNAL inflate_table(type, lens, codes, table, bits, work) -codetype type; -unsigned short FAR *lens; -unsigned codes; -code FAR * FAR *table; -unsigned FAR *bits; -unsigned short FAR *work; -{ +int ZLIB_INTERNAL inflate_table(codetype type, unsigned short FAR *lens, + unsigned codes, code FAR * FAR *table, + unsigned FAR *bits, unsigned short FAR *work) { unsigned len; /* a code's length in bits */ unsigned sym; /* index of code symbols */ unsigned min, max; /* minimum and maximum code lengths */ @@ -62,7 +57,7 @@ 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258, 0, 0}; static const unsigned short lext[31] = { /* Length codes 257..285 extra */ 16, 16, 16, 16, 16, 16, 16, 16, 17, 17, 17, 17, 18, 18, 18, 18, - 19, 19, 19, 19, 20, 20, 20, 20, 21, 21, 21, 21, 16, 194, 65}; + 19, 19, 19, 19, 20, 20, 20, 20, 21, 21, 21, 21, 16, 198, 203}; static const unsigned short dbase[32] = { /* Distance codes 0..29 base */ 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145,
diff --git a/lib/zlib/inftrees.h b/lib/zlib/inftrees.h index f536653..a10712d 100644 --- a/lib/zlib/inftrees.h +++ b/lib/zlib/inftrees.h
@@ -57,6 +57,6 @@ DISTS } codetype; -int ZLIB_INTERNAL inflate_table OF((codetype type, unsigned short FAR *lens, - unsigned codes, code FAR * FAR *table, - unsigned FAR *bits, unsigned short FAR *work)); +int ZLIB_INTERNAL inflate_table(codetype type, unsigned short FAR *lens, + unsigned codes, code FAR * FAR *table, + unsigned FAR *bits, unsigned short FAR *work);
diff --git a/lib/zlib/tf_gunzip.c b/lib/zlib/tf_gunzip.c index 3ac80bc..8b8d14d 100644 --- a/lib/zlib/tf_gunzip.c +++ b/lib/zlib/tf_gunzip.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */
diff --git a/lib/zlib/zconf.h b/lib/zlib/zconf.h index bf977d3..fb76ffe 100644 --- a/lib/zlib/zconf.h +++ b/lib/zlib/zconf.h
@@ -241,7 +241,11 @@ #endif #ifdef Z_SOLO - typedef unsigned long z_size_t; +# ifdef _WIN64 + typedef unsigned long long z_size_t; +# else + typedef unsigned long z_size_t; +# endif #else # define z_longlong long long # if defined(NO_SIZE_T) @@ -520,7 +524,7 @@ #if !defined(_WIN32) && defined(Z_LARGE64) # define z_off64_t off64_t #else -# if defined(_WIN32) && !defined(__GNUC__) && !defined(Z_SOLO) +# if defined(_WIN32) && !defined(__GNUC__) # define z_off64_t __int64 # else # define z_off64_t z_off_t
diff --git a/lib/zlib/zlib.h b/lib/zlib/zlib.h index 953cb50..6b7244f 100644 --- a/lib/zlib/zlib.h +++ b/lib/zlib/zlib.h
@@ -1,7 +1,7 @@ /* zlib.h -- interface of the 'zlib' general purpose compression library - version 1.2.13, October 13th, 2022 + version 1.3, August 18th, 2023 - Copyright (C) 1995-2022 Jean-loup Gailly and Mark Adler + Copyright (C) 1995-2023 Jean-loup Gailly and Mark Adler This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages @@ -37,11 +37,11 @@ extern "C" { #endif -#define ZLIB_VERSION "1.2.13" -#define ZLIB_VERNUM 0x12d0 +#define ZLIB_VERSION "1.3" +#define ZLIB_VERNUM 0x1300 #define ZLIB_VER_MAJOR 1 -#define ZLIB_VER_MINOR 2 -#define ZLIB_VER_REVISION 13 +#define ZLIB_VER_MINOR 3 +#define ZLIB_VER_REVISION 0 #define ZLIB_VER_SUBREVISION 0 /* @@ -78,8 +78,8 @@ even in the case of corrupted input. */ -typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size)); -typedef void (*free_func) OF((voidpf opaque, voidpf address)); +typedef voidpf (*alloc_func)(voidpf opaque, uInt items, uInt size); +typedef void (*free_func)(voidpf opaque, voidpf address); struct internal_state; @@ -217,7 +217,7 @@ /* basic functions */ -ZEXTERN const char * ZEXPORT zlibVersion OF((void)); +ZEXTERN const char * ZEXPORT zlibVersion(void); /* The application can compare zlibVersion and ZLIB_VERSION for consistency. If the first character differs, the library code actually used is not compatible with the zlib.h header file used by the application. This check @@ -225,12 +225,12 @@ */ /* -ZEXTERN int ZEXPORT deflateInit OF((z_streamp strm, int level)); +ZEXTERN int ZEXPORT deflateInit(z_streamp strm, int level); Initializes the internal stream state for compression. The fields zalloc, zfree and opaque must be initialized before by the caller. If zalloc and zfree are set to Z_NULL, deflateInit updates them to use default - allocation functions. + allocation functions. total_in, total_out, adler, and msg are initialized. The compression level must be Z_DEFAULT_COMPRESSION, or between 0 and 9: 1 gives best speed, 9 gives best compression, 0 gives no compression at all @@ -247,7 +247,7 @@ */ -ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush)); +ZEXTERN int ZEXPORT deflate(z_streamp strm, int flush); /* deflate compresses as much data as possible, and stops when the input buffer becomes empty or the output buffer becomes full. It may introduce @@ -320,8 +320,8 @@ with the same value of the flush parameter and more output space (updated avail_out), until the flush is complete (deflate returns with non-zero avail_out). In the case of a Z_FULL_FLUSH or Z_SYNC_FLUSH, make sure that - avail_out is greater than six to avoid repeated flush markers due to - avail_out == 0 on return. + avail_out is greater than six when the flush marker begins, in order to avoid + repeated flush markers upon calling deflate() again when avail_out == 0. If the parameter flush is set to Z_FINISH, pending input is processed, pending output is flushed and deflate returns with Z_STREAM_END if there was @@ -360,7 +360,7 @@ */ -ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm)); +ZEXTERN int ZEXPORT deflateEnd(z_streamp strm); /* All dynamically allocated data structures for this stream are freed. This function discards any unprocessed input and does not flush any pending @@ -375,7 +375,7 @@ /* -ZEXTERN int ZEXPORT inflateInit OF((z_streamp strm)); +ZEXTERN int ZEXPORT inflateInit(z_streamp strm); Initializes the internal stream state for decompression. The fields next_in, avail_in, zalloc, zfree and opaque must be initialized before by @@ -383,7 +383,8 @@ read or consumed. The allocation of a sliding window will be deferred to the first call of inflate (if the decompression does not complete on the first call). If zalloc and zfree are set to Z_NULL, inflateInit updates - them to use default allocation functions. + them to use default allocation functions. total_in, total_out, adler, and + msg are initialized. inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not enough memory, Z_VERSION_ERROR if the zlib library version is incompatible with the @@ -397,7 +398,7 @@ */ -ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush)); +ZEXTERN int ZEXPORT inflate(z_streamp strm, int flush); /* inflate decompresses as much data as possible, and stops when the input buffer becomes empty or the output buffer becomes full. It may introduce @@ -517,7 +518,7 @@ */ -ZEXTERN int ZEXPORT inflateEnd OF((z_streamp strm)); +ZEXTERN int ZEXPORT inflateEnd(z_streamp strm); /* All dynamically allocated data structures for this stream are freed. This function discards any unprocessed input and does not flush any pending @@ -535,12 +536,12 @@ */ /* -ZEXTERN int ZEXPORT deflateInit2 OF((z_streamp strm, - int level, - int method, - int windowBits, - int memLevel, - int strategy)); +ZEXTERN int ZEXPORT deflateInit2(z_streamp strm, + int level, + int method, + int windowBits, + int memLevel, + int strategy); This is another version of deflateInit with more compression options. The fields zalloc, zfree and opaque must be initialized before by the caller. @@ -607,9 +608,9 @@ compression: this will be done by deflate(). */ -ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm, - const Bytef *dictionary, - uInt dictLength)); +ZEXTERN int ZEXPORT deflateSetDictionary(z_streamp strm, + const Bytef *dictionary, + uInt dictLength); /* Initializes the compression dictionary from the given byte sequence without producing any compressed output. When using the zlib format, this @@ -651,9 +652,9 @@ not perform any compression: this will be done by deflate(). */ -ZEXTERN int ZEXPORT deflateGetDictionary OF((z_streamp strm, - Bytef *dictionary, - uInt *dictLength)); +ZEXTERN int ZEXPORT deflateGetDictionary(z_streamp strm, + Bytef *dictionary, + uInt *dictLength); /* Returns the sliding dictionary being maintained by deflate. dictLength is set to the number of bytes in the dictionary, and that many bytes are copied @@ -673,8 +674,8 @@ stream state is inconsistent. */ -ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest, - z_streamp source)); +ZEXTERN int ZEXPORT deflateCopy(z_streamp dest, + z_streamp source); /* Sets the destination stream as a complete copy of the source stream. @@ -691,20 +692,20 @@ destination. */ -ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm)); +ZEXTERN int ZEXPORT deflateReset(z_streamp strm); /* This function is equivalent to deflateEnd followed by deflateInit, but does not free and reallocate the internal compression state. The stream will leave the compression level and any other attributes that may have been - set unchanged. + set unchanged. total_in, total_out, adler, and msg are initialized. deflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source stream state was inconsistent (such as zalloc or state being Z_NULL). */ -ZEXTERN int ZEXPORT deflateParams OF((z_streamp strm, - int level, - int strategy)); +ZEXTERN int ZEXPORT deflateParams(z_streamp strm, + int level, + int strategy); /* Dynamically update the compression level and compression strategy. The interpretation of level and strategy is as in deflateInit2(). This can be @@ -729,7 +730,7 @@ Then no more input data should be provided before the deflateParams() call. If this is done, the old level and strategy will be applied to the data compressed before deflateParams(), and the new level and strategy will be - applied to the the data compressed after deflateParams(). + applied to the data compressed after deflateParams(). deflateParams returns Z_OK on success, Z_STREAM_ERROR if the source stream state was inconsistent or if a parameter was invalid, or Z_BUF_ERROR if @@ -740,11 +741,11 @@ retried with more output space. */ -ZEXTERN int ZEXPORT deflateTune OF((z_streamp strm, - int good_length, - int max_lazy, - int nice_length, - int max_chain)); +ZEXTERN int ZEXPORT deflateTune(z_streamp strm, + int good_length, + int max_lazy, + int nice_length, + int max_chain); /* Fine tune deflate's internal compression parameters. This should only be used by someone who understands the algorithm used by zlib's deflate for @@ -757,8 +758,8 @@ returns Z_OK on success, or Z_STREAM_ERROR for an invalid deflate stream. */ -ZEXTERN uLong ZEXPORT deflateBound OF((z_streamp strm, - uLong sourceLen)); +ZEXTERN uLong ZEXPORT deflateBound(z_streamp strm, + uLong sourceLen); /* deflateBound() returns an upper bound on the compressed size after deflation of sourceLen bytes. It must be called after deflateInit() or @@ -772,9 +773,9 @@ than Z_FINISH or Z_NO_FLUSH are used. */ -ZEXTERN int ZEXPORT deflatePending OF((z_streamp strm, - unsigned *pending, - int *bits)); +ZEXTERN int ZEXPORT deflatePending(z_streamp strm, + unsigned *pending, + int *bits); /* deflatePending() returns the number of bytes and bits of output that have been generated, but not yet provided in the available output. The bytes not @@ -787,9 +788,9 @@ stream state was inconsistent. */ -ZEXTERN int ZEXPORT deflatePrime OF((z_streamp strm, - int bits, - int value)); +ZEXTERN int ZEXPORT deflatePrime(z_streamp strm, + int bits, + int value); /* deflatePrime() inserts bits in the deflate output stream. The intent is that this function is used to start off the deflate output with the bits @@ -804,8 +805,8 @@ source stream state was inconsistent. */ -ZEXTERN int ZEXPORT deflateSetHeader OF((z_streamp strm, - gz_headerp head)); +ZEXTERN int ZEXPORT deflateSetHeader(z_streamp strm, + gz_headerp head); /* deflateSetHeader() provides gzip header information for when a gzip stream is requested by deflateInit2(). deflateSetHeader() may be called @@ -821,16 +822,17 @@ gzip file" and give up. If deflateSetHeader is not used, the default gzip header has text false, - the time set to zero, and os set to 255, with no extra, name, or comment - fields. The gzip header is returned to the default state by deflateReset(). + the time set to zero, and os set to the current operating system, with no + extra, name, or comment fields. The gzip header is returned to the default + state by deflateReset(). deflateSetHeader returns Z_OK if success, or Z_STREAM_ERROR if the source stream state was inconsistent. */ /* -ZEXTERN int ZEXPORT inflateInit2 OF((z_streamp strm, - int windowBits)); +ZEXTERN int ZEXPORT inflateInit2(z_streamp strm, + int windowBits); This is another version of inflateInit with an extra parameter. The fields next_in, avail_in, zalloc, zfree and opaque must be initialized @@ -883,9 +885,9 @@ deferred until inflate() is called. */ -ZEXTERN int ZEXPORT inflateSetDictionary OF((z_streamp strm, - const Bytef *dictionary, - uInt dictLength)); +ZEXTERN int ZEXPORT inflateSetDictionary(z_streamp strm, + const Bytef *dictionary, + uInt dictLength); /* Initializes the decompression dictionary from the given uncompressed byte sequence. This function must be called immediately after a call of inflate, @@ -906,9 +908,9 @@ inflate(). */ -ZEXTERN int ZEXPORT inflateGetDictionary OF((z_streamp strm, - Bytef *dictionary, - uInt *dictLength)); +ZEXTERN int ZEXPORT inflateGetDictionary(z_streamp strm, + Bytef *dictionary, + uInt *dictLength); /* Returns the sliding dictionary being maintained by inflate. dictLength is set to the number of bytes in the dictionary, and that many bytes are copied @@ -921,7 +923,7 @@ stream state is inconsistent. */ -ZEXTERN int ZEXPORT inflateSync OF((z_streamp strm)); +ZEXTERN int ZEXPORT inflateSync(z_streamp strm); /* Skips invalid compressed data until a possible full flush point (see above for the description of deflate with Z_FULL_FLUSH) can be found, or until all @@ -940,8 +942,8 @@ input each time, until success or end of the input data. */ -ZEXTERN int ZEXPORT inflateCopy OF((z_streamp dest, - z_streamp source)); +ZEXTERN int ZEXPORT inflateCopy(z_streamp dest, + z_streamp source); /* Sets the destination stream as a complete copy of the source stream. @@ -956,18 +958,19 @@ destination. */ -ZEXTERN int ZEXPORT inflateReset OF((z_streamp strm)); +ZEXTERN int ZEXPORT inflateReset(z_streamp strm); /* This function is equivalent to inflateEnd followed by inflateInit, but does not free and reallocate the internal decompression state. The stream will keep attributes that may have been set by inflateInit2. + total_in, total_out, adler, and msg are initialized. inflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source stream state was inconsistent (such as zalloc or state being Z_NULL). */ -ZEXTERN int ZEXPORT inflateReset2 OF((z_streamp strm, - int windowBits)); +ZEXTERN int ZEXPORT inflateReset2(z_streamp strm, + int windowBits); /* This function is the same as inflateReset, but it also permits changing the wrap and window size requests. The windowBits parameter is interpreted @@ -980,9 +983,9 @@ the windowBits parameter is invalid. */ -ZEXTERN int ZEXPORT inflatePrime OF((z_streamp strm, - int bits, - int value)); +ZEXTERN int ZEXPORT inflatePrime(z_streamp strm, + int bits, + int value); /* This function inserts bits in the inflate input stream. The intent is that this function is used to start inflating at a bit position in the @@ -1001,7 +1004,7 @@ stream state was inconsistent. */ -ZEXTERN long ZEXPORT inflateMark OF((z_streamp strm)); +ZEXTERN long ZEXPORT inflateMark(z_streamp strm); /* This function returns two values, one in the lower 16 bits of the return value, and the other in the remaining upper bits, obtained by shifting the @@ -1029,8 +1032,8 @@ source stream state was inconsistent. */ -ZEXTERN int ZEXPORT inflateGetHeader OF((z_streamp strm, - gz_headerp head)); +ZEXTERN int ZEXPORT inflateGetHeader(z_streamp strm, + gz_headerp head); /* inflateGetHeader() requests that gzip header information be stored in the provided gz_header structure. inflateGetHeader() may be called after @@ -1070,8 +1073,8 @@ */ /* -ZEXTERN int ZEXPORT inflateBackInit OF((z_streamp strm, int windowBits, - unsigned char FAR *window)); +ZEXTERN int ZEXPORT inflateBackInit(z_streamp strm, int windowBits, + unsigned char FAR *window); Initialize the internal stream state for decompression using inflateBack() calls. The fields zalloc, zfree and opaque in strm must be initialized @@ -1091,13 +1094,13 @@ the version of the header file. */ -typedef unsigned (*in_func) OF((void FAR *, - z_const unsigned char FAR * FAR *)); -typedef int (*out_func) OF((void FAR *, unsigned char FAR *, unsigned)); +typedef unsigned (*in_func)(void FAR *, + z_const unsigned char FAR * FAR *); +typedef int (*out_func)(void FAR *, unsigned char FAR *, unsigned); -ZEXTERN int ZEXPORT inflateBack OF((z_streamp strm, - in_func in, void FAR *in_desc, - out_func out, void FAR *out_desc)); +ZEXTERN int ZEXPORT inflateBack(z_streamp strm, + in_func in, void FAR *in_desc, + out_func out, void FAR *out_desc); /* inflateBack() does a raw inflate with a single call using a call-back interface for input and output. This is potentially more efficient than @@ -1165,7 +1168,7 @@ cannot return Z_OK. */ -ZEXTERN int ZEXPORT inflateBackEnd OF((z_streamp strm)); +ZEXTERN int ZEXPORT inflateBackEnd(z_streamp strm); /* All memory allocated by inflateBackInit() is freed. @@ -1173,7 +1176,7 @@ state was inconsistent. */ -ZEXTERN uLong ZEXPORT zlibCompileFlags OF((void)); +ZEXTERN uLong ZEXPORT zlibCompileFlags(void); /* Return flags indicating compile-time options. Type sizes, two bits each, 00 = 16 bits, 01 = 32, 10 = 64, 11 = other: @@ -1226,8 +1229,8 @@ you need special options. */ -ZEXTERN int ZEXPORT compress OF((Bytef *dest, uLongf *destLen, - const Bytef *source, uLong sourceLen)); +ZEXTERN int ZEXPORT compress(Bytef *dest, uLongf *destLen, + const Bytef *source, uLong sourceLen); /* Compresses the source buffer into the destination buffer. sourceLen is the byte length of the source buffer. Upon entry, destLen is the total size @@ -1241,9 +1244,9 @@ buffer. */ -ZEXTERN int ZEXPORT compress2 OF((Bytef *dest, uLongf *destLen, - const Bytef *source, uLong sourceLen, - int level)); +ZEXTERN int ZEXPORT compress2(Bytef *dest, uLongf *destLen, + const Bytef *source, uLong sourceLen, + int level); /* Compresses the source buffer into the destination buffer. The level parameter has the same meaning as in deflateInit. sourceLen is the byte @@ -1257,15 +1260,15 @@ Z_STREAM_ERROR if the level parameter is invalid. */ -ZEXTERN uLong ZEXPORT compressBound OF((uLong sourceLen)); +ZEXTERN uLong ZEXPORT compressBound(uLong sourceLen); /* compressBound() returns an upper bound on the compressed size after compress() or compress2() on sourceLen bytes. It would be used before a compress() or compress2() call to allocate the destination buffer. */ -ZEXTERN int ZEXPORT uncompress OF((Bytef *dest, uLongf *destLen, - const Bytef *source, uLong sourceLen)); +ZEXTERN int ZEXPORT uncompress(Bytef *dest, uLongf *destLen, + const Bytef *source, uLong sourceLen); /* Decompresses the source buffer into the destination buffer. sourceLen is the byte length of the source buffer. Upon entry, destLen is the total size @@ -1282,8 +1285,8 @@ buffer with the uncompressed data up to that point. */ -ZEXTERN int ZEXPORT uncompress2 OF((Bytef *dest, uLongf *destLen, - const Bytef *source, uLong *sourceLen)); +ZEXTERN int ZEXPORT uncompress2(Bytef *dest, uLongf *destLen, + const Bytef *source, uLong *sourceLen); /* Same as uncompress, except that sourceLen is a pointer, where the length of the source is *sourceLen. On return, *sourceLen is the number of @@ -1302,7 +1305,7 @@ typedef struct gzFile_s *gzFile; /* semi-opaque gzip file descriptor */ /* -ZEXTERN gzFile ZEXPORT gzopen OF((const char *path, const char *mode)); +ZEXTERN gzFile ZEXPORT gzopen(const char *path, const char *mode); Open the gzip (.gz) file at path for reading and decompressing, or compressing and writing. The mode parameter is as in fopen ("rb" or "wb") @@ -1339,7 +1342,7 @@ file could not be opened. */ -ZEXTERN gzFile ZEXPORT gzdopen OF((int fd, const char *mode)); +ZEXTERN gzFile ZEXPORT gzdopen(int fd, const char *mode); /* Associate a gzFile with the file descriptor fd. File descriptors are obtained from calls like open, dup, creat, pipe or fileno (if the file has @@ -1362,7 +1365,7 @@ will not detect if fd is invalid (unless fd is -1). */ -ZEXTERN int ZEXPORT gzbuffer OF((gzFile file, unsigned size)); +ZEXTERN int ZEXPORT gzbuffer(gzFile file, unsigned size); /* Set the internal buffer size used by this library's functions for file to size. The default buffer size is 8192 bytes. This function must be called @@ -1378,7 +1381,7 @@ too late. */ -ZEXTERN int ZEXPORT gzsetparams OF((gzFile file, int level, int strategy)); +ZEXTERN int ZEXPORT gzsetparams(gzFile file, int level, int strategy); /* Dynamically update the compression level and strategy for file. See the description of deflateInit2 for the meaning of these parameters. Previously @@ -1389,7 +1392,7 @@ or Z_MEM_ERROR if there is a memory allocation error. */ -ZEXTERN int ZEXPORT gzread OF((gzFile file, voidp buf, unsigned len)); +ZEXTERN int ZEXPORT gzread(gzFile file, voidp buf, unsigned len); /* Read and decompress up to len uncompressed bytes from file into buf. If the input file is not in gzip format, gzread copies the given number of @@ -1419,8 +1422,8 @@ Z_STREAM_ERROR. */ -ZEXTERN z_size_t ZEXPORT gzfread OF((voidp buf, z_size_t size, z_size_t nitems, - gzFile file)); +ZEXTERN z_size_t ZEXPORT gzfread(voidp buf, z_size_t size, z_size_t nitems, + gzFile file); /* Read and decompress up to nitems items of size size from file into buf, otherwise operating as gzread() does. This duplicates the interface of @@ -1445,14 +1448,14 @@ file, resetting and retrying on end-of-file, when size is not 1. */ -ZEXTERN int ZEXPORT gzwrite OF((gzFile file, voidpc buf, unsigned len)); +ZEXTERN int ZEXPORT gzwrite(gzFile file, voidpc buf, unsigned len); /* Compress and write the len uncompressed bytes at buf to file. gzwrite returns the number of uncompressed bytes written or 0 in case of error. */ -ZEXTERN z_size_t ZEXPORT gzfwrite OF((voidpc buf, z_size_t size, - z_size_t nitems, gzFile file)); +ZEXTERN z_size_t ZEXPORT gzfwrite(voidpc buf, z_size_t size, + z_size_t nitems, gzFile file); /* Compress and write nitems items of size size from buf to file, duplicating the interface of stdio's fwrite(), with size_t request and return types. If @@ -1465,7 +1468,7 @@ is returned, and the error state is set to Z_STREAM_ERROR. */ -ZEXTERN int ZEXPORTVA gzprintf Z_ARG((gzFile file, const char *format, ...)); +ZEXTERN int ZEXPORTVA gzprintf(gzFile file, const char *format, ...); /* Convert, format, compress, and write the arguments (...) to file under control of the string format, as in fprintf. gzprintf returns the number of @@ -1480,7 +1483,7 @@ This can be determined using zlibCompileFlags(). */ -ZEXTERN int ZEXPORT gzputs OF((gzFile file, const char *s)); +ZEXTERN int ZEXPORT gzputs(gzFile file, const char *s); /* Compress and write the given null-terminated string s to file, excluding the terminating null character. @@ -1488,7 +1491,7 @@ gzputs returns the number of characters written, or -1 in case of error. */ -ZEXTERN char * ZEXPORT gzgets OF((gzFile file, char *buf, int len)); +ZEXTERN char * ZEXPORT gzgets(gzFile file, char *buf, int len); /* Read and decompress bytes from file into buf, until len-1 characters are read, or until a newline character is read and transferred to buf, or an @@ -1502,13 +1505,13 @@ buf are indeterminate. */ -ZEXTERN int ZEXPORT gzputc OF((gzFile file, int c)); +ZEXTERN int ZEXPORT gzputc(gzFile file, int c); /* Compress and write c, converted to an unsigned char, into file. gzputc returns the value that was written, or -1 in case of error. */ -ZEXTERN int ZEXPORT gzgetc OF((gzFile file)); +ZEXTERN int ZEXPORT gzgetc(gzFile file); /* Read and decompress one byte from file. gzgetc returns this byte or -1 in case of end of file or error. This is implemented as a macro for speed. @@ -1517,7 +1520,7 @@ points to has been clobbered or not. */ -ZEXTERN int ZEXPORT gzungetc OF((int c, gzFile file)); +ZEXTERN int ZEXPORT gzungetc(int c, gzFile file); /* Push c back onto the stream for file to be read as the first character on the next read. At least one character of push-back is always allowed. @@ -1529,7 +1532,7 @@ gzseek() or gzrewind(). */ -ZEXTERN int ZEXPORT gzflush OF((gzFile file, int flush)); +ZEXTERN int ZEXPORT gzflush(gzFile file, int flush); /* Flush all pending output to file. The parameter flush is as in the deflate() function. The return value is the zlib error number (see function @@ -1545,8 +1548,8 @@ */ /* -ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile file, - z_off_t offset, int whence)); +ZEXTERN z_off_t ZEXPORT gzseek(gzFile file, + z_off_t offset, int whence); Set the starting position to offset relative to whence for the next gzread or gzwrite on file. The offset represents a number of bytes in the @@ -1564,7 +1567,7 @@ would be before the current position. */ -ZEXTERN int ZEXPORT gzrewind OF((gzFile file)); +ZEXTERN int ZEXPORT gzrewind(gzFile file); /* Rewind file. This function is supported only for reading. @@ -1572,7 +1575,7 @@ */ /* -ZEXTERN z_off_t ZEXPORT gztell OF((gzFile file)); +ZEXTERN z_off_t ZEXPORT gztell(gzFile file); Return the starting position for the next gzread or gzwrite on file. This position represents a number of bytes in the uncompressed data stream, @@ -1583,7 +1586,7 @@ */ /* -ZEXTERN z_off_t ZEXPORT gzoffset OF((gzFile file)); +ZEXTERN z_off_t ZEXPORT gzoffset(gzFile file); Return the current compressed (actual) read or write offset of file. This offset includes the count of bytes that precede the gzip stream, for example @@ -1592,7 +1595,7 @@ be used for a progress indicator. On error, gzoffset() returns -1. */ -ZEXTERN int ZEXPORT gzeof OF((gzFile file)); +ZEXTERN int ZEXPORT gzeof(gzFile file); /* Return true (1) if the end-of-file indicator for file has been set while reading, false (0) otherwise. Note that the end-of-file indicator is set @@ -1607,7 +1610,7 @@ has grown since the previous end of file was detected. */ -ZEXTERN int ZEXPORT gzdirect OF((gzFile file)); +ZEXTERN int ZEXPORT gzdirect(gzFile file); /* Return true (1) if file is being copied directly while reading, or false (0) if file is a gzip stream being decompressed. @@ -1628,7 +1631,7 @@ gzip file reading and decompression, which may not be desired.) */ -ZEXTERN int ZEXPORT gzclose OF((gzFile file)); +ZEXTERN int ZEXPORT gzclose(gzFile file); /* Flush all pending output for file, if necessary, close file and deallocate the (de)compression state. Note that once file is closed, you @@ -1641,8 +1644,8 @@ last read ended in the middle of a gzip stream, or Z_OK on success. */ -ZEXTERN int ZEXPORT gzclose_r OF((gzFile file)); -ZEXTERN int ZEXPORT gzclose_w OF((gzFile file)); +ZEXTERN int ZEXPORT gzclose_r(gzFile file); +ZEXTERN int ZEXPORT gzclose_w(gzFile file); /* Same as gzclose(), but gzclose_r() is only for use when reading, and gzclose_w() is only for use when writing or appending. The advantage to @@ -1653,7 +1656,7 @@ zlib library. */ -ZEXTERN const char * ZEXPORT gzerror OF((gzFile file, int *errnum)); +ZEXTERN const char * ZEXPORT gzerror(gzFile file, int *errnum); /* Return the error message for the last error which occurred on file. errnum is set to zlib error number. If an error occurred in the file system @@ -1669,7 +1672,7 @@ functions above that do not distinguish those cases in their return values. */ -ZEXTERN void ZEXPORT gzclearerr OF((gzFile file)); +ZEXTERN void ZEXPORT gzclearerr(gzFile file); /* Clear the error and end-of-file flags for file. This is analogous to the clearerr() function in stdio. This is useful for continuing to read a gzip @@ -1686,7 +1689,7 @@ library. */ -ZEXTERN uLong ZEXPORT adler32 OF((uLong adler, const Bytef *buf, uInt len)); +ZEXTERN uLong ZEXPORT adler32(uLong adler, const Bytef *buf, uInt len); /* Update a running Adler-32 checksum with the bytes buf[0..len-1] and return the updated checksum. An Adler-32 value is in the range of a 32-bit @@ -1706,15 +1709,15 @@ if (adler != original_adler) error(); */ -ZEXTERN uLong ZEXPORT adler32_z OF((uLong adler, const Bytef *buf, - z_size_t len)); +ZEXTERN uLong ZEXPORT adler32_z(uLong adler, const Bytef *buf, + z_size_t len); /* Same as adler32(), but with a size_t length. */ /* -ZEXTERN uLong ZEXPORT adler32_combine OF((uLong adler1, uLong adler2, - z_off_t len2)); +ZEXTERN uLong ZEXPORT adler32_combine(uLong adler1, uLong adler2, + z_off_t len2); Combine two Adler-32 checksums into one. For two sequences of bytes, seq1 and seq2 with lengths len1 and len2, Adler-32 checksums were calculated for @@ -1724,7 +1727,7 @@ negative, the result has no meaning or utility. */ -ZEXTERN uLong ZEXPORT crc32 OF((uLong crc, const Bytef *buf, uInt len)); +ZEXTERN uLong ZEXPORT crc32(uLong crc, const Bytef *buf, uInt len); /* Update a running CRC-32 with the bytes buf[0..len-1] and return the updated CRC-32. A CRC-32 value is in the range of a 32-bit unsigned integer. @@ -1742,14 +1745,14 @@ if (crc != original_crc) error(); */ -ZEXTERN uLong ZEXPORT crc32_z OF((uLong crc, const Bytef *buf, - z_size_t len)); +ZEXTERN uLong ZEXPORT crc32_z(uLong crc, const Bytef *buf, + z_size_t len); /* Same as crc32(), but with a size_t length. */ /* -ZEXTERN uLong ZEXPORT crc32_combine OF((uLong crc1, uLong crc2, z_off_t len2)); +ZEXTERN uLong ZEXPORT crc32_combine(uLong crc1, uLong crc2, z_off_t len2); Combine two CRC-32 check values into one. For two sequences of bytes, seq1 and seq2 with lengths len1 and len2, CRC-32 check values were @@ -1759,13 +1762,13 @@ */ /* -ZEXTERN uLong ZEXPORT crc32_combine_gen OF((z_off_t len2)); +ZEXTERN uLong ZEXPORT crc32_combine_gen(z_off_t len2); Return the operator corresponding to length len2, to be used with crc32_combine_op(). */ -ZEXTERN uLong ZEXPORT crc32_combine_op OF((uLong crc1, uLong crc2, uLong op)); +ZEXTERN uLong ZEXPORT crc32_combine_op(uLong crc1, uLong crc2, uLong op); /* Give the same result as crc32_combine(), using op in place of len2. op is is generated from len2 by crc32_combine_gen(). This will be faster than @@ -1778,20 +1781,20 @@ /* deflateInit and inflateInit are macros to allow checking the zlib version * and the compiler's view of z_stream: */ -ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level, - const char *version, int stream_size)); -ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm, - const char *version, int stream_size)); -ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int level, int method, - int windowBits, int memLevel, - int strategy, const char *version, - int stream_size)); -ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int windowBits, - const char *version, int stream_size)); -ZEXTERN int ZEXPORT inflateBackInit_ OF((z_streamp strm, int windowBits, - unsigned char FAR *window, - const char *version, - int stream_size)); +ZEXTERN int ZEXPORT deflateInit_(z_streamp strm, int level, + const char *version, int stream_size); +ZEXTERN int ZEXPORT inflateInit_(z_streamp strm, + const char *version, int stream_size); +ZEXTERN int ZEXPORT deflateInit2_(z_streamp strm, int level, int method, + int windowBits, int memLevel, + int strategy, const char *version, + int stream_size); +ZEXTERN int ZEXPORT inflateInit2_(z_streamp strm, int windowBits, + const char *version, int stream_size); +ZEXTERN int ZEXPORT inflateBackInit_(z_streamp strm, int windowBits, + unsigned char FAR *window, + const char *version, + int stream_size); #ifdef Z_PREFIX_SET # define z_deflateInit(strm, level) \ deflateInit_((strm), (level), ZLIB_VERSION, (int)sizeof(z_stream)) @@ -1836,7 +1839,7 @@ unsigned char *next; z_off64_t pos; }; -ZEXTERN int ZEXPORT gzgetc_ OF((gzFile file)); /* backward compatibility */ +ZEXTERN int ZEXPORT gzgetc_(gzFile file); /* backward compatibility */ #ifdef Z_PREFIX_SET # undef z_gzgetc # define z_gzgetc(g) \ @@ -1853,13 +1856,13 @@ * without large file support, _LFS64_LARGEFILE must also be true */ #ifdef Z_LARGE64 - ZEXTERN gzFile ZEXPORT gzopen64 OF((const char *, const char *)); - ZEXTERN z_off64_t ZEXPORT gzseek64 OF((gzFile, z_off64_t, int)); - ZEXTERN z_off64_t ZEXPORT gztell64 OF((gzFile)); - ZEXTERN z_off64_t ZEXPORT gzoffset64 OF((gzFile)); - ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off64_t)); - ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off64_t)); - ZEXTERN uLong ZEXPORT crc32_combine_gen64 OF((z_off64_t)); + ZEXTERN gzFile ZEXPORT gzopen64(const char *, const char *); + ZEXTERN z_off64_t ZEXPORT gzseek64(gzFile, z_off64_t, int); + ZEXTERN z_off64_t ZEXPORT gztell64(gzFile); + ZEXTERN z_off64_t ZEXPORT gzoffset64(gzFile); + ZEXTERN uLong ZEXPORT adler32_combine64(uLong, uLong, z_off64_t); + ZEXTERN uLong ZEXPORT crc32_combine64(uLong, uLong, z_off64_t); + ZEXTERN uLong ZEXPORT crc32_combine_gen64(z_off64_t); #endif #if !defined(ZLIB_INTERNAL) && defined(Z_WANT64) @@ -1881,50 +1884,50 @@ # define crc32_combine_gen crc32_combine_gen64 # endif # ifndef Z_LARGE64 - ZEXTERN gzFile ZEXPORT gzopen64 OF((const char *, const char *)); - ZEXTERN z_off_t ZEXPORT gzseek64 OF((gzFile, z_off_t, int)); - ZEXTERN z_off_t ZEXPORT gztell64 OF((gzFile)); - ZEXTERN z_off_t ZEXPORT gzoffset64 OF((gzFile)); - ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine_gen64 OF((z_off_t)); + ZEXTERN gzFile ZEXPORT gzopen64(const char *, const char *); + ZEXTERN z_off_t ZEXPORT gzseek64(gzFile, z_off_t, int); + ZEXTERN z_off_t ZEXPORT gztell64(gzFile); + ZEXTERN z_off_t ZEXPORT gzoffset64(gzFile); + ZEXTERN uLong ZEXPORT adler32_combine64(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine64(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine_gen64(z_off_t); # endif #else - ZEXTERN gzFile ZEXPORT gzopen OF((const char *, const char *)); - ZEXTERN z_off_t ZEXPORT gzseek OF((gzFile, z_off_t, int)); - ZEXTERN z_off_t ZEXPORT gztell OF((gzFile)); - ZEXTERN z_off_t ZEXPORT gzoffset OF((gzFile)); - ZEXTERN uLong ZEXPORT adler32_combine OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine_gen OF((z_off_t)); + ZEXTERN gzFile ZEXPORT gzopen(const char *, const char *); + ZEXTERN z_off_t ZEXPORT gzseek(gzFile, z_off_t, int); + ZEXTERN z_off_t ZEXPORT gztell(gzFile); + ZEXTERN z_off_t ZEXPORT gzoffset(gzFile); + ZEXTERN uLong ZEXPORT adler32_combine(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine_gen(z_off_t); #endif #else /* Z_SOLO */ - ZEXTERN uLong ZEXPORT adler32_combine OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine_gen OF((z_off_t)); + ZEXTERN uLong ZEXPORT adler32_combine(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine_gen(z_off_t); #endif /* !Z_SOLO */ /* undocumented functions */ -ZEXTERN const char * ZEXPORT zError OF((int)); -ZEXTERN int ZEXPORT inflateSyncPoint OF((z_streamp)); -ZEXTERN const z_crc_t FAR * ZEXPORT get_crc_table OF((void)); -ZEXTERN int ZEXPORT inflateUndermine OF((z_streamp, int)); -ZEXTERN int ZEXPORT inflateValidate OF((z_streamp, int)); -ZEXTERN unsigned long ZEXPORT inflateCodesUsed OF((z_streamp)); -ZEXTERN int ZEXPORT inflateResetKeep OF((z_streamp)); -ZEXTERN int ZEXPORT deflateResetKeep OF((z_streamp)); +ZEXTERN const char * ZEXPORT zError(int); +ZEXTERN int ZEXPORT inflateSyncPoint(z_streamp); +ZEXTERN const z_crc_t FAR * ZEXPORT get_crc_table(void); +ZEXTERN int ZEXPORT inflateUndermine(z_streamp, int); +ZEXTERN int ZEXPORT inflateValidate(z_streamp, int); +ZEXTERN unsigned long ZEXPORT inflateCodesUsed(z_streamp); +ZEXTERN int ZEXPORT inflateResetKeep(z_streamp); +ZEXTERN int ZEXPORT deflateResetKeep(z_streamp); #if defined(_WIN32) && !defined(Z_SOLO) -ZEXTERN gzFile ZEXPORT gzopen_w OF((const wchar_t *path, - const char *mode)); +ZEXTERN gzFile ZEXPORT gzopen_w(const wchar_t *path, + const char *mode); #endif #if defined(STDC) || defined(Z_HAVE_STDARG_H) # ifndef Z_SOLO -ZEXTERN int ZEXPORTVA gzvprintf Z_ARG((gzFile file, - const char *format, - va_list va)); +ZEXTERN int ZEXPORTVA gzvprintf(gzFile file, + const char *format, + va_list va); # endif #endif
diff --git a/lib/zlib/zlib.mk b/lib/zlib/zlib.mk index 98d4efa..a8937a7 100644 --- a/lib/zlib/zlib.mk +++ b/lib/zlib/zlib.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause #
diff --git a/lib/zlib/zutil.c b/lib/zlib/zutil.c index 9543ae8..b1c5d2d 100644 --- a/lib/zlib/zutil.c +++ b/lib/zlib/zutil.c
@@ -24,13 +24,11 @@ }; -const char * ZEXPORT zlibVersion() -{ +const char * ZEXPORT zlibVersion(void) { return ZLIB_VERSION; } -uLong ZEXPORT zlibCompileFlags() -{ +uLong ZEXPORT zlibCompileFlags(void) { uLong flags; flags = 0; @@ -121,9 +119,7 @@ # endif int ZLIB_INTERNAL z_verbose = verbose; -void ZLIB_INTERNAL z_error(m) - char *m; -{ +void ZLIB_INTERNAL z_error(char *m) { fprintf(stderr, "%s\n", m); exit(1); } @@ -132,9 +128,7 @@ /* exported to allow conversion of error code to string for compress() and * uncompress() */ -const char * ZEXPORT zError(err) - int err; -{ +const char * ZEXPORT zError(int err) { return ERR_MSG(err); } @@ -148,22 +142,14 @@ #ifndef HAVE_MEMCPY -void ZLIB_INTERNAL zmemcpy(dest, source, len) - Bytef* dest; - const Bytef* source; - uInt len; -{ +void ZLIB_INTERNAL zmemcpy(Bytef* dest, const Bytef* source, uInt len) { if (len == 0) return; do { *dest++ = *source++; /* ??? to be unrolled */ } while (--len != 0); } -int ZLIB_INTERNAL zmemcmp(s1, s2, len) - const Bytef* s1; - const Bytef* s2; - uInt len; -{ +int ZLIB_INTERNAL zmemcmp(const Bytef* s1, const Bytef* s2, uInt len) { uInt j; for (j = 0; j < len; j++) { @@ -172,10 +158,7 @@ return 0; } -void ZLIB_INTERNAL zmemzero(dest, len) - Bytef* dest; - uInt len; -{ +void ZLIB_INTERNAL zmemzero(Bytef* dest, uInt len) { if (len == 0) return; do { *dest++ = 0; /* ??? to be unrolled */ @@ -216,8 +199,7 @@ * a protected system like OS/2. Use Microsoft C instead. */ -voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, unsigned size) -{ +voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, unsigned size) { voidpf buf; ulg bsize = (ulg)items*size; @@ -242,8 +224,7 @@ return buf; } -void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) -{ +void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) { int n; (void)opaque; @@ -279,14 +260,12 @@ # define _hfree hfree #endif -voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, uInt items, uInt size) -{ +voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, uInt items, uInt size) { (void)opaque; return _halloc((long)items, size); } -void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) -{ +void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) { (void)opaque; _hfree(ptr); } @@ -299,25 +278,18 @@ #ifndef MY_ZCALLOC /* Any system without a special alloc function */ #ifndef STDC -extern voidp malloc OF((uInt size)); -extern voidp calloc OF((uInt items, uInt size)); -extern void free OF((voidpf ptr)); +extern voidp malloc(uInt size); +extern voidp calloc(uInt items, uInt size); +extern void free(voidpf ptr); #endif -voidpf ZLIB_INTERNAL zcalloc(opaque, items, size) - voidpf opaque; - unsigned items; - unsigned size; -{ +voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, unsigned size) { (void)opaque; return sizeof(uInt) > 2 ? (voidpf)malloc(items * size) : (voidpf)calloc(items, size); } -void ZLIB_INTERNAL zcfree(opaque, ptr) - voidpf opaque; - voidpf ptr; -{ +void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr) { (void)opaque; free(ptr); }
diff --git a/lib/zlib/zutil.h b/lib/zlib/zutil.h index 0bc7f4e..902a304 100644 --- a/lib/zlib/zutil.h +++ b/lib/zlib/zutil.h
@@ -191,9 +191,9 @@ /* provide prototypes for these when building zlib without LFS */ #if !defined(_WIN32) && \ (!defined(_LARGEFILE64_SOURCE) || _LFS64_LARGEFILE-0 == 0) - ZEXTERN uLong ZEXPORT adler32_combine64 OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine64 OF((uLong, uLong, z_off_t)); - ZEXTERN uLong ZEXPORT crc32_combine_gen64 OF((z_off_t)); + ZEXTERN uLong ZEXPORT adler32_combine64(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine64(uLong, uLong, z_off_t); + ZEXTERN uLong ZEXPORT crc32_combine_gen64(z_off_t); #endif /* common defaults */ @@ -232,16 +232,16 @@ # define zmemzero(dest, len) memset(dest, 0, len) # endif #else - void ZLIB_INTERNAL zmemcpy OF((Bytef* dest, const Bytef* source, uInt len)); - int ZLIB_INTERNAL zmemcmp OF((const Bytef* s1, const Bytef* s2, uInt len)); - void ZLIB_INTERNAL zmemzero OF((Bytef* dest, uInt len)); + void ZLIB_INTERNAL zmemcpy(Bytef* dest, const Bytef* source, uInt len); + int ZLIB_INTERNAL zmemcmp(const Bytef* s1, const Bytef* s2, uInt len); + void ZLIB_INTERNAL zmemzero(Bytef* dest, uInt len); #endif /* Diagnostic functions */ #ifdef ZLIB_DEBUG # include <stdio.h> extern int ZLIB_INTERNAL z_verbose; - extern void ZLIB_INTERNAL z_error OF((char *m)); + extern void ZLIB_INTERNAL z_error(char *m); # define Assert(cond,msg) {if(!(cond)) z_error(msg);} # define Trace(x) {if (z_verbose>=0) fprintf x ;} # define Tracev(x) {if (z_verbose>0) fprintf x ;} @@ -258,9 +258,9 @@ #endif #ifndef Z_SOLO - voidpf ZLIB_INTERNAL zcalloc OF((voidpf opaque, unsigned items, - unsigned size)); - void ZLIB_INTERNAL zcfree OF((voidpf opaque, voidpf ptr)); + voidpf ZLIB_INTERNAL zcalloc(voidpf opaque, unsigned items, + unsigned size); + void ZLIB_INTERNAL zcfree(voidpf opaque, voidpf ptr); #endif #define ZALLOC(strm, items, size) \
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk index b799697..a337e76 100644 --- a/make_helpers/arch_features.mk +++ b/make_helpers/arch_features.mk
@@ -1,41 +1,333 @@ # -# Copyright (c) 2022, Arm Limited. All rights reserved. +# Copyright (c) 2022-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # -# This file lists all the checks related to the Architectural Feature -# Enablement flags, based on the Architectural version. +# This file lists all of the architectural features, and initializes +# and enables them based on the configured architecture version. + +# This file follows the following format: +# - Enable mandatory feature if applicable to an Arch Version. +# - By default disable any mandatory features if they have not been defined yet. +# - Disable or enable any optional feature this would be enabled/disabled if needed by platform. + +# +################################################################################ +# Enable Mandatory features based on Arch versions. +################################################################################ +# # Enable the features which are mandatory from ARCH version 8.1 and upwards. ifeq "8.1" "$(word 1, $(sort 8.1 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -ENABLE_FEAT_PAN = 1 -ENABLE_FEAT_VHE = 1 +ENABLE_FEAT_PAN := 1 +ENABLE_FEAT_VHE := 1 endif # Enable the features which are mandatory from ARCH version 8.2 and upwards. ifeq "8.2" "$(word 1, $(sort 8.2 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -ENABLE_FEAT_RAS = 1 +ENABLE_FEAT_RAS := 1 endif # Enable the features which are mandatory from ARCH version 8.4 and upwards. ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -ENABLE_FEAT_DIT = 1 -ENABLE_FEAT_SEL2 = 1 +ENABLE_FEAT_SEL2 := 1 +ENABLE_TRF_FOR_NS := 1 +ENABLE_FEAT_DIT := 1 endif # Enable the features which are mandatory from ARCH version 8.5 and upwards. ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -ENABLE_FEAT_SB = 1 +ENABLE_FEAT_RNG := 1 +ENABLE_FEAT_SB := 1 + +# Enable Memory tagging, Branch Target Identification for aarch64 only. +ifeq ($(ARCH), aarch64) + mem_tag_arch_support := yes +endif #(ARCH=aarch64) + endif # Enable the features which are mandatory from ARCH version 8.6 and upwards. ifeq "8.6" "$(word 1, $(sort 8.6 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -ENABLE_FEAT_FGT = 1 -ENABLE_FEAT_ECV = 1 +ENABLE_FEAT_ECV := 1 +ENABLE_FEAT_FGT := 1 endif # Enable the features which are mandatory from ARCH version 8.7 and upwards. ifeq "8.7" "$(word 1, $(sort 8.7 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" -ENABLE_FEAT_HCX = 1 +ENABLE_FEAT_HCX := 1 endif + +# Enable the features which are mandatory from ARCH version 8.9 and upwards. +ifeq "8.9" "$(word 1, $(sort 8.9 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))" +ENABLE_FEAT_TCR2 := 1 +endif + +# +################################################################################ +# Set mandatory features by default to zero. +################################################################################ +# + +#---- +# 8.1 +#---- + +# Flag to enable access to Privileged Access Never bit of PSTATE. +ENABLE_FEAT_PAN ?= 0 + +# Flag to enable Virtualization Host Extensions. +ENABLE_FEAT_VHE ?= 0 + +#---- +# 8.2 +#---- + +# Enable RAS Support. +ENABLE_FEAT_RAS ?= 0 + +#---- +# 8.3 +#---- + +# Flag to enable Pointer Authentication. Internal flag not meant for +# direct setting. Use BRANCH_PROTECTION to enable PAUTH. +ENABLE_PAUTH ?= 0 + +# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This +# must be set to 1 if the platform wants to use this feature in the Secure +# world. It is not necessary for use in the Non-secure world. +CTX_INCLUDE_PAUTH_REGS ?= 0 + + +#---- +# 8.4 +#---- + +# Flag to enable Secure EL-2 feature. +ENABLE_FEAT_SEL2 ?= 0 + +# By default, disable trace filter control register access to lower non-secure +# exception levels, i.e. NS-EL2, or NS-EL1 if NS-EL2 is implemented, but +# trace filter control register access is unused if FEAT_TRF is implemented. +ENABLE_TRF_FOR_NS ?= 0 + +# Flag to enable Data Independent Timing instructions. +ENABLE_FEAT_DIT ?= 0 + +#---- +# 8.5 +#---- + +# Flag to enable Branch Target Identification. +# Internal flag not meant for direct setting. +# Use BRANCH_PROTECTION to enable BTI. +ENABLE_BTI ?= 0 + +# Flag to enable access to the Random Number Generator registers. +ENABLE_FEAT_RNG ?= 0 + +# Flag to enable Speculation Barrier Instruction. +ENABLE_FEAT_SB ?= 0 + +#---- +# 8.6 +#---- + +# Flag to enable access to the CNTPOFF_EL2 register. +ENABLE_FEAT_ECV ?= 0 + +# Flag to enable access to the HDFGRTR_EL2 register. +ENABLE_FEAT_FGT ?= 0 + +#---- +# 8.7 +#---- + +# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. +ENABLE_FEAT_HCX ?= 0 + +#---- +# 8.9 +#---- + +# Flag to enable access to TCR2 (FEAT_TCR2). +ENABLE_FEAT_TCR2 ?= 0 + +# +################################################################################ +# Optional Features defaulted to 0 or 2, if they are not enabled from +# build option. Can also be disabled or enabled by platform if needed. +################################################################################ +# + +#---- +# 8.0 +#---- + +# Flag to enable CSV2_2 extension. +ENABLE_FEAT_CSV2_2 ?= 0 + +# By default, disable access of trace system registers from NS lower +# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if +# system register trace is implemented. This feature is available if +# trace unit such as ETMv4.x, This feature is OPTIONAL and is only +# permitted in Armv8 implementations. +ENABLE_SYS_REG_TRACE_FOR_NS ?= 0 + +#---- +# 8.2 +#---- + +# Build option to enable/disable the Statistical Profiling Extension, +# keep it enabled by default for AArch64. +ifeq (${ARCH},aarch64) + ENABLE_SPE_FOR_NS ?= 2 +else ifeq (${ARCH},aarch32) + ifneq ($(or $(ENABLE_SPE_FOR_NS),0),0) + $(error ENABLE_SPE_FOR_NS is not supported for AArch32) + else + ENABLE_SPE_FOR_NS := 0 + endif +endif + +# Enable SVE for non-secure world by default. +ifeq (${ARCH},aarch64) + ENABLE_SVE_FOR_NS ?= 2 +# SVE is only supported on AArch64 so disable it on AArch32. +else ifeq (${ARCH},aarch32) + ifneq ($(or $(ENABLE_SVE_FOR_NS),0),0) + $(error ENABLE_SVE_FOR_NS is not supported for AArch32) + else + ENABLE_SVE_FOR_NS := 0 + endif +endif + +#---- +# 8.4 +#---- + +# Feature flags for supporting Activity monitor extensions. +ENABLE_FEAT_AMU ?= 0 +ENABLE_AMU_AUXILIARY_COUNTERS ?= 0 +ENABLE_AMU_FCONF ?= 0 +AMU_RESTRICT_COUNTERS ?= 0 + +# Build option to enable MPAM for lower ELs. +# Enabling it by default +ifeq (${ARCH},aarch64) + ENABLE_FEAT_MPAM ?= 2 +else ifeq (${ARCH},aarch32) + ifneq ($(or $(ENABLE_FEAT_MPAM),0),0) + $(error ENABLE_FEAT_MPAM is not supported for AArch32) + else + ENABLE_FEAT_MPAM := 0 + endif +endif + +# Include nested virtualization control (Armv8.4-NV) registers in cpu context. +# This must be set to 1 if architecture implements Nested Virtualization +# Extension and platform wants to use this feature in the Secure world. +CTX_INCLUDE_NEVE_REGS ?= 0 + +#---- +# 8.5 +#---- + +# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS +# registers, by setting SCR_EL3.TRNDR. +ENABLE_FEAT_RNG_TRAP ?= 0 + +# Include Memory Tagging Extension registers in cpu context. This must be set +# to 1 if the platform wants to use this feature in the Secure world and MTE is +# enabled at ELX. +CTX_INCLUDE_MTE_REGS ?= 0 + +#---- +# 8.6 +#---- + +# Flag to enable AMUv1p1 extension. +ENABLE_FEAT_AMUv1p1 ?= 0 + +# Flag to enable delayed trapping of WFE instruction (FEAT_TWED). +ENABLE_FEAT_TWED ?= 0 + +# In v8.6+ platforms with delayed trapping of WFE being supported +# via FEAT_TWED, this flag takes the delay value to be set in the +# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented. +# By default it takes 0, and need to be updated by the platforms. +TWED_DELAY ?= 0 + +# Disable MTPMU if FEAT_MTPMU is supported. +DISABLE_MTPMU ?= 0 + +#---- +# 8.9 +#---- + +# Flag to enable NoTagAccess memory region attribute for stage 2 of translation. +ENABLE_FEAT_MTE_PERM ?= 0 + +# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE). +ENABLE_FEAT_S2PIE ?= 0 + +# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE). +ENABLE_FEAT_S1PIE ?= 0 + +# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE). +ENABLE_FEAT_S2POE ?= 0 + +# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE). +ENABLE_FEAT_S1POE ?= 0 + +#---- +# 9.0 +#---- + +# Flag to enable Realm Management Extension (FEAT_RME). +ENABLE_RME ?= 0 + +# Scalable Matrix Extension for non-secure world. +ENABLE_SME_FOR_NS ?= 0 + +# Scalable Vector Extension for secure world. +ENABLE_SVE_FOR_SWD ?= 0 + +# By default, disable access of trace buffer control registers from NS +# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused +# if FEAT_TRBE is implemented. +# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in +# AArch32. +ifeq (${ARCH},aarch64) + ENABLE_TRBE_FOR_NS ?= 0 +else ifeq (${ARCH},aarch32) + ifneq ($(or $(ENABLE_TRBE_FOR_NS),0),0) + $(error ENABLE_TRBE_FOR_NS is not supported for AArch32) + else + ENABLE_TRBE_FOR_NS := 0 + endif +endif + +#---- +# 9.2 +#---- + +# Scalable Matrix Extension version 2 for non-secure world. +ENABLE_SME2_FOR_NS ?= 0 + +# Scalable Matrix Extension for secure world. +ENABLE_SME_FOR_SWD ?= 0 + +# By default, disable access to branch record buffer control registers from NS +# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused +# if FEAT_BRBE is implemented. +ENABLE_BRBE_FOR_NS ?= 0 + +#---- +#9.4 +#---- + +# Flag to enable access to Guarded Control Stack (FEAT_GCS). +ENABLE_FEAT_GCS ?= 0
diff --git a/make_helpers/armv7-a-cpus.mk b/make_helpers/armv7-a-cpus.mk index eec85cc..a8e9d50 100644 --- a/make_helpers/armv7-a-cpus.mk +++ b/make_helpers/armv7-a-cpus.mk
@@ -15,9 +15,9 @@ # armClang requires -march=armv7-a for all ARMv7 Cortex-A. To comply with # all, just drop -march and supply only -mcpu. -# Platform can override march32-directive through MARCH32_DIRECTIVE -ifdef MARCH32_DIRECTIVE -march32-directive := $(MARCH32_DIRECTIVE) +# Platform can override march-directive through MARCH_DIRECTIVE +ifdef MARCH_DIRECTIVE +march-directive := $(MARCH_DIRECTIVE) else march32-set-${ARM_CORTEX_A5} := -mcpu=cortex-a5 march32-set-${ARM_CORTEX_A7} := -mcpu=cortex-a7 @@ -29,7 +29,7 @@ # default to -march=armv7-a as target directive march32-set-yes ?= -march=armv7-a -march32-directive := ${march32-set-yes} ${march32-neon-yes} +march-directive := ${march32-set-yes} ${march32-neon-yes} endif # Platform may override these extension support directives:
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 3bce3a5..71cf18b 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk
@@ -334,10 +334,10 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) -$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES)) -$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS)) -$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS))) -$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS)) +$(eval BL_DEFINES := IMAGE_$(call uppercase,$(3)) $($(call uppercase,$(3))_DEFINES) $(PLAT_BL_COMMON_DEFINES)) +$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)) +$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS)) +$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS) $(PLAT_BL_COMMON_CFLAGS)) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs $$(ECHO) " CC $$<" @@ -357,10 +357,10 @@ $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) $(eval DEP := $(patsubst %.o,%.d,$(OBJ))) -$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES)) -$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS)) -$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS))) -$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS)) +$(eval BL_DEFINES := IMAGE_$(call uppercase,$(3)) $($(call uppercase,$(3))_DEFINES) $(PLAT_BL_COMMON_DEFINES)) +$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)) +$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS)) +$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS) $(PLAT_BL_COMMON_ASFLAGS)) $(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs $$(ECHO) " AS $$<" @@ -379,9 +379,9 @@ $(eval DEP := $(1).d) -$(eval BL_DEFINES := $($(call uppercase,$(3))_DEFINES)) -$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS)) -$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) -DIMAGE_$(call uppercase,$(3)) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS))) +$(eval BL_DEFINES := IMAGE_$(call uppercase,$(3)) $($(call uppercase,$(3))_DEFINES) $(PLAT_BL_COMMON_DEFINES)) +$(eval BL_INCLUDE_DIRS := $($(call uppercase,$(3))_INCLUDE_DIRS) $(PLAT_BL_COMMON_INCLUDE_DIRS)) +$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS)) $(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs $$(ECHO) " PP $$<" @@ -504,7 +504,7 @@ define MAKE_BL $(eval BUILD_DIR := ${BUILD_PLAT}/$(1)) $(eval BL_SOURCES := $($(call uppercase,$(1))_SOURCES)) - $(eval SOURCES := $(BL_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES)) + $(eval SOURCES := $(sort $(BL_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES))) $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES)))) $(eval MAPFILE := $(call IMG_MAPFILE,$(1))) $(eval ELF := $(call IMG_ELF,$(1))) @@ -558,7 +558,7 @@ $(ELF): $(OBJS) $(DEFAULT_LINKER_SCRIPT) $(LINKER_SCRIPTS) | $(1)_dirs libraries $(BL_LIBS) $$(ECHO) " LD $$@" ifdef MAKE_BUILD_STRINGS - $(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o) + $(call MAKE_BUILD_STRINGS,$(BUILD_DIR)/build_message.o) else @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \ const char version_string[] = "${VERSION_STRING}"; \
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index f9077eb..f0f157c 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk
@@ -63,16 +63,6 @@ # Include FP registers in cpu context CTX_INCLUDE_FPREGS := 0 -# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This -# must be set to 1 if the platform wants to use this feature in the Secure -# world. It is not needed to use it in the Non-secure world. -CTX_INCLUDE_PAUTH_REGS := 0 - -# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. -# This must be set to 1 if architecture implements Nested Virtualization -# Extension and platform wants to use this feature in the Secure world -CTX_INCLUDE_NEVE_REGS := 0 - # Debug build DEBUG := 0 @@ -85,17 +75,10 @@ # Disable the generation of the binary image (ELF only). DISABLE_BIN_GENERATION := 0 -# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards -# compatibility. -DISABLE_MTPMU := 0 - # Enable capability to disable authentication dynamically. Only meant for # development platforms. DYN_DISABLE_AUTH := 0 -# Build option to enable MPAM for lower ELs -ENABLE_MPAM_FOR_LOWER_ELS := 0 - # Enable the Maximum Power Mitigation Mechanism on supporting cores. ENABLE_MPMM := 0 @@ -111,9 +94,6 @@ # Flag to enable PSCI STATs functionality ENABLE_PSCI_STAT := 0 -# Flag to enable Realm Management Extension (FEAT_RME) -ENABLE_RME := 0 - # Flag to enable runtime instrumentation using PMF ENABLE_RUNTIME_INSTRUMENTATION := 0 @@ -123,74 +103,6 @@ # Flag to enable exception handling in EL3 EL3_EXCEPTION_HANDLING := 0 -# Flag to enable Branch Target Identification. -# Internal flag not meant for direct setting. -# Use BRANCH_PROTECTION to enable BTI. -ENABLE_BTI := 0 - -# Flag to enable Pointer Authentication. -# Internal flag not meant for direct setting. -# Use BRANCH_PROTECTION to enable PAUTH. -ENABLE_PAUTH := 0 - -# Flag to enable AMUv1p1 extension. -ENABLE_FEAT_AMUv1p1 := 0 - -# Flag to enable CSV2_2 extension. -ENABLE_FEAT_CSV2_2 := 0 - -# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. -ENABLE_FEAT_HCX := 0 - -# Flag to enable access to the HDFGRTR_EL2 register -ENABLE_FEAT_FGT := 0 - -# Flag to enable access to the CNTPOFF_EL2 register -ENABLE_FEAT_ECV := 0 - -# Flag to enable use of the DIT feature. -ENABLE_FEAT_DIT := 0 - -# Flag to enable access to Privileged Access Never bit of PSTATE. -ENABLE_FEAT_PAN := 0 - -# Flag to enable access to the Random Number Generator registers -ENABLE_FEAT_RNG := 0 - -# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS -# registers, by setting SCR_EL3.TRNDR. -ENABLE_FEAT_RNG_TRAP := 0 - -# Flag to enable Speculation Barrier Instruction -ENABLE_FEAT_SB := 0 - -# Flag to enable Secure EL-2 feature. -ENABLE_FEAT_SEL2 := 0 - -# Flag to enable Virtualization Host Extensions -ENABLE_FEAT_VHE := 0 - -# Flag to enable delayed trapping of WFE instruction (FEAT_TWED) -ENABLE_FEAT_TWED := 0 - -# Flag to enable access to TCR2 (FEAT_TCR2) -ENABLE_FEAT_TCR2 := 0 - -# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE) -ENABLE_FEAT_S2PIE := 0 - -# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE) -ENABLE_FEAT_S1PIE := 0 - -# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE) -ENABLE_FEAT_S2POE := 0 - -# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE) -ENABLE_FEAT_S1POE := 0 - -# Flag to enable access to Guarded Control Stack (FEAT_GCS) -ENABLE_FEAT_GCS := 0 - # By default BL31 encryption disabled ENCRYPT_BL31 := 0 @@ -235,6 +147,9 @@ # by lower ELs. HANDLE_EA_EL3_FIRST_NS := 0 +# Enable Handoff protocol using transfer lists +TRANSFER_LIST := 0 + # Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. # The default value is sha256. HASH_ALG := sha256 @@ -276,10 +191,6 @@ # Enable PSCI OS-initiated mode support PSCI_OS_INIT_MODE := 0 -# Enable RAS Support -ENABLE_FEAT_RAS := 0 -RAS_FFH_SUPPORT := 0 - # By default, BL1 acts as the reset handler, not BL31 RESET_TO_BL31 := 0 @@ -326,6 +237,9 @@ # Use the FF-A SPMC implementation in EL3. SPMC_AT_EL3 := 0 +# Enable SEL0 SP when SPMC is enabled at EL3 +SPMC_AT_EL3_SEL0_SP :=0 + # Use SPM at S-EL2 as a default config for SPMD SPMD_SPM_AT_SEL2 := 1 @@ -376,40 +290,9 @@ # platforms). WARMBOOT_ENABLE_DCACHE_EARLY := 0 -# Build option to enable/disable the Statistical Profiling Extensions -ENABLE_SPE_FOR_NS := 2 - -# SPE is only supported on AArch64 so disable it on AArch32. -ifeq (${ARCH},aarch32) - override ENABLE_SPE_FOR_NS := 0 -endif - -# Include Memory Tagging Extension registers in cpu context. This must be set -# to 1 if the platform wants to use this feature in the Secure world and MTE is -# enabled at ELX. -CTX_INCLUDE_MTE_REGS := 0 - -ENABLE_FEAT_AMU := 0 -ENABLE_AMU_AUXILIARY_COUNTERS := 0 -ENABLE_AMU_FCONF := 0 -AMU_RESTRICT_COUNTERS := 0 - -# Enable SVE for non-secure world by default -ENABLE_SVE_FOR_NS := 2 -# SVE is only supported on AArch64 so disable it on AArch32. -ifeq (${ARCH},aarch32) - override ENABLE_SVE_FOR_NS := 0 -endif -ENABLE_SVE_FOR_SWD := 0 - # Default SVE vector length to maximum architected value SVE_VECTOR_LEN := 2048 -# SME defaults to disabled -ENABLE_SME_FOR_NS := 0 -ENABLE_SME_FOR_SWD := 0 -ENABLE_SME2_FOR_NS := 0 - SANITIZE_UB := off # For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock @@ -464,38 +347,6 @@ # Disable Firmware update support by default PSA_FWU_SUPPORT := 0 -# By default, disable access of trace buffer control registers from NS -# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused -# if FEAT_TRBE is implemented. -# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in -# AArch32. -ifneq (${ARCH},aarch32) - ENABLE_TRBE_FOR_NS := 0 -else - override ENABLE_TRBE_FOR_NS := 0 -endif - -# By default, disable access to branch record buffer control registers from NS -# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused -# if FEAT_BRBE is implemented. -ENABLE_BRBE_FOR_NS := 0 - -# By default, disable access of trace system registers from NS lower -# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if -# system register trace is implemented. -ENABLE_SYS_REG_TRACE_FOR_NS := 0 - -# By default, disable trace filter control registers access to NS -# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused -# if FEAT_TRF is implemented. -ENABLE_TRF_FOR_NS := 0 - -# In v8.6+ platforms with delayed trapping of WFE being supported -# via FEAT_TWED, this flag takes the delay value to be set in the -# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented. -# By default it takes 0, and need to be updated by the platforms. -TWED_DELAY := 0 - # By default, disable the mocking of RSS provided services PLAT_RSS_NOT_SUPPORTED := 0 @@ -505,3 +356,20 @@ # Check platform if cache management operations should be performed. # Disabled by default. CONDITIONAL_CMO := 0 + +# By default, disable SPMD Logical partitions +ENABLE_SPMD_LP := 0 + +# By default, disable PSA crypto (use MbedTLS legacy crypto API). +PSA_CRYPTO := 0 + +# getc() support from the console(s). +# Disabled by default because it constitutes an attack vector into TF-A. It +# should only be enabled if there is a use case for it. +ENABLE_CONSOLE_GETC := 0 + +# Build option to disable EL2 when it is not used. +# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 +# functions must be enabled by platforms if they require it. +# Disabled by default. +INIT_UNUSED_NS_EL2 := 0
diff --git a/make_helpers/march.mk b/make_helpers/march.mk new file mode 100644 index 0000000..2417709 --- /dev/null +++ b/make_helpers/march.mk
@@ -0,0 +1,85 @@ +# +# Copyright (c) 2023, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +# This build helper makefile is used to determine a suitable march build +# option to be used, based on platform provided ARM_ARCH_MAJOR/MINOR +# data and compiler supported march version. + +# Set the compiler's target architecture profile based on +# ARM_ARCH_MAJOR and ARM_ARCH_MINOR options. + + +# This is used to collect available march values from compiler. +# Example on a gcc-12.2 arm64 toolchain it will look like: +# [...] +#./aarch64-none-elf-gcc --target-help -march=foo +# cc1: error: unknown value 'foo' for '-march' +# cc1: note: valid arguments are: armv8-a armv8.1-a armv8.2-a armv8.3-a armv8.4-a armv8.5-a +# armv8.6-a armv8.7-a armv8.8-a armv8-r armv9-a +# [...] +# +GCC_MARCH_OUTPUT := $(shell $(CC) -march=foo -Q --help=target -v 2>&1) + +# This function is used to find the best march value supported by the given compiler. +# We try to use `GCC_MARCH_OUTPUT` which has verbose message with supported march values we filter that +# to find armvX.Y-a or armvX-a values, then filter the best supported arch based on ARM_ARCH_MAJOR. +# +# Example on a gcc-12.2 arm64 toolchain this will return armv9-a if platform requested for armv9.2-a +# Similarly on gcc 11.3 it would return armv8.6-a if platform requested armv8.8-a +define major_best_avail_march +$(1) := $(lastword $(filter armv$(ARM_ARCH_MAJOR)% ,$(filter armv%-a, $(GCC_MARCH_OUTPUT)))) +endef + +# This function is used to just return latest march value supported by the given compiler. +# +# Example: this would return armv8.6-a on a gcc-11.3 when platform requested for armv9.0-a +# +# Thus this function should be used in conjunction with major_best_avail_march, when best match +# is not found it should be ok to try with lastest known supported march value from the +# compiler. +define latest_match_march +$(1) := $(lastword $(filter armv%-a, $(GCC_MARCH_OUTPUT))) +endef + +ifdef MARCH_DIRECTIVE + march-directive := $(MARCH_DIRECTIVE) +else + +ifeq (${ARM_ARCH_MINOR},0) + provided-march = armv${ARM_ARCH_MAJOR}-a +else + provided-march = armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a +endif + +ifeq ($(findstring clang,$(notdir $(CC))),) + +# We expect from Platform to provide a correct Major/Minor value but expecting something +# from compiler with unsupported march means we shouldn't fail without trying anything, +# so here we try to find best supported march value and use that for compilation. +# If we don't support current march version from gcc compiler, try with lower arch based on +# availability. In TF-A there is no hard rule for need of higher version march for basic +# functionality, denying a build on only this fact doesn't look correct, so try with best +# or latest march values from whats available from compiler. +ifeq (,$(findstring $(provided-march), $(GCC_MARCH_OUTPUT))) + $(eval $(call major_best_avail_march, available-march)) + +ifeq (, $(available-march)) + $(eval $(call latest_match_march, available-march)) +endif + +# If we fail to come up with any available-march value so far, don't update +# provided-march and thus allow the build to fail using the provided-march +# which is derived based on arch_major and arch_minor values. +ifneq (,$(available-march)) + provided-march := ${available-march} +endif + +endif # provided-march supported +endif # not clang + +march-directive := -march=${provided-march} + +endif # MARCH_DIRECTIVE
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk index 8605bae..3a2c53f 100644 --- a/make_helpers/tbbr/tbbr_tools.mk +++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -43,10 +43,14 @@ # Default non-volatile counter values (overridable by the platform) TFW_NVCTR_VAL ?= 0 NTFW_NVCTR_VAL ?= 0 +CCAFW_NVCTR_VAL ?= 0 # Pass the non-volatile counters to the cert_create tool $(eval $(call CERT_ADD_CMD_OPT,${TFW_NVCTR_VAL},--tfw-nvctr)) $(eval $(call CERT_ADD_CMD_OPT,${NTFW_NVCTR_VAL},--ntfw-nvctr)) +ifeq (${COT},cca) +$(eval $(call CERT_ADD_CMD_OPT,${CCAFW_NVCTR_VAL},--ccafw-nvctr)) +endif # Add Trusted Key certificate to the fiptool and cert_create command line options ifneq (${COT},cca) @@ -114,8 +118,10 @@ ifeq (${NEED_BL32},yes) $(if ${BL32_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL32_KEY},--tos-fw-key))) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_content.crt,--tos-fw-cert)) +ifneq (${COT},cca) $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_key.crt,--tos-fw-key-cert)) endif +endif # Add the BL33 CoT (key cert + img cert) ifneq (${BL33},)
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk index b6d6f0b..ac0f940 100644 --- a/make_helpers/windows.mk +++ b/make_helpers/windows.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -83,8 +83,9 @@ VERSION_STRING_MESSAGE = const char version_string[] = "${VERSION_STRING}"; VERSION_MESSAGE = const char version[] = "${VERSION}"; define MAKE_BUILD_STRINGS + $$(file >$1.in,$$(TF_CFLAGS) $$(CFLAGS)) @echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) $$(VERSION_MESSAGE) | \ - $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -x c -c - -o $1 + $$(CC) @$1.in -x c -c - -o $1 endef MSVC_NMAKE := nmake.exe
diff --git a/package-lock.json b/package-lock.json index 89ebd51..e43fa65 100644 --- a/package-lock.json +++ b/package-lock.json
@@ -1,12 +1,12 @@ { "name": "trusted-firmware-a", - "version": "2.9.0", + "version": "2.10.0", "lockfileVersion": 2, "requires": true, "packages": { "": { "name": "trusted-firmware-a", - "version": "2.9.0", + "version": "2.10.0", "hasInstallScript": true, "license": "BSD-3-Clause", "devDependencies": { @@ -3894,9 +3894,9 @@ } }, "node_modules/word-wrap": { - "version": "1.2.3", - "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.3.tgz", - "integrity": "sha512-Hz/mrNwitNRh/HUAtM/VT/5VH+ygD6DV7mYKZAtHOrbs8U7lvPS6xf7EJKMF0uW1KJCl0H701g3ZGus+muE5vQ==", + "version": "1.2.4", + "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz", + "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==", "dev": true, "engines": { "node": ">=0.10.0" @@ -4022,7 +4022,7 @@ } }, "tools/conventional-changelog-tf-a": { - "version": "2.7.0", + "version": "2.9.0", "dev": true, "license": "BSD-3-Clause", "dependencies": { @@ -6978,9 +6978,9 @@ } }, "word-wrap": { - "version": "1.2.3", - "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.3.tgz", - "integrity": "sha512-Hz/mrNwitNRh/HUAtM/VT/5VH+ygD6DV7mYKZAtHOrbs8U7lvPS6xf7EJKMF0uW1KJCl0H701g3ZGus+muE5vQ==", + "version": "1.2.4", + "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz", + "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==", "dev": true }, "wordwrap": {
diff --git a/package.json b/package.json index 8b724dae..1c557fd 100644 --- a/package.json +++ b/package.json
@@ -1,6 +1,6 @@ { "name": "trusted-firmware-a", - "version": "2.9.0", + "version": "2.10.0", "license": "BSD-3-Clause", "private": true, "scripts": {
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c index 41dc563..6a0e967 100644 --- a/plat/allwinner/common/sunxi_scpi_pm.c +++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -125,6 +125,32 @@ psci_power_down_wfi(); } +static int sunxi_system_reset2(int is_vendor, int reset_type, u_register_t cookie) +{ + uint32_t ret; + + if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET)) + return PSCI_E_NOT_SUPPORTED; + + gicv2_cpuif_disable(); + + /* Send the system reset request to the SCP. */ + ret = scpi_sys_power_state(scpi_system_reset); + if (ret != SCP_OK) { + ERROR("PSCI: SCPI %s failed: %d\n", "reset", ret); + return PSCI_E_INVALID_PARAMS; + } + + psci_power_down_wfi(); + + /* + * Should not reach here. + * However sunxi_system_reset2 has to return some value + * according to PSCI v1.1 spec. + */ + return PSCI_E_SUCCESS; +} + static int sunxi_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { @@ -177,6 +203,7 @@ .pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish, .system_off = sunxi_system_off, .system_reset = sunxi_system_reset, + .system_reset2 = sunxi_system_reset2, .validate_power_state = sunxi_validate_power_state, .validate_ns_entrypoint = sunxi_validate_ns_entrypoint, .get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state,
diff --git a/plat/arm/board/a5ds/a5ds_bl2_setup.c b/plat/arm/board/a5ds/a5ds_bl2_setup.c index 1979c50..a0aa639 100644 --- a/plat/arm/board/a5ds/a5ds_bl2_setup.c +++ b/plat/arm/board/a5ds/a5ds_bl2_setup.c
@@ -16,3 +16,8 @@ { arm_bl2_platform_setup(); } + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return arm_bl2_plat_handle_post_image_load(image_id); +}
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk index 6fcf080..dd82a10 100644 --- a/plat/arm/board/a5ds/platform.mk +++ b/plat/arm/board/a5ds/platform.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2021, Arm Limited. All rights reserved. +# Copyright (c) 2019-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -98,7 +98,9 @@ NEED_BL32 := yes -MULTI_CONSOLE_API := 1 +ifeq (${AARCH32_SP},none) + $(error Variable AARCH32_SP has to be set for AArch32) +endif ARM_DISABLE_TRUSTED_WDOG := 1
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index f88eaa8..f44b37d 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk
@@ -33,7 +33,16 @@ FPGA_PRELOADED_CMD_LINE := 0x1000 $(eval $(call add_define,FPGA_PRELOADED_CMD_LINE)) -ENABLE_FEAT_AMU := 2 +ENABLE_BRBE_FOR_NS := 2 +ENABLE_TRBE_FOR_NS := 2 +ENABLE_FEAT_AMU := 2 +ENABLE_FEAT_AMUv1p1 := 2 +ENABLE_FEAT_CSV2_2 := 2 +ENABLE_FEAT_ECV := 2 +ENABLE_FEAT_FGT := 2 +ENABLE_FEAT_HCX := 2 +ENABLE_SYS_REG_TRACE_FOR_NS := 2 +ENABLE_TRF_FOR_NS := 2 # Treating this as a memory-constrained port for now USE_COHERENT_MEM := 0 @@ -58,18 +67,17 @@ lib/cpus/aarch64/cortex_a73.S else # AArch64-only cores - FPGA_CPU_LIBS +=lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_a715.S \ - lib/cpus/aarch64/cortex_x3.S \ + FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ + lib/cpus/aarch64/cortex_a520.S \ + lib/cpus/aarch64/cortex_a715.S \ + lib/cpus/aarch64/cortex_a720.S \ + lib/cpus/aarch64/cortex_x3.S \ + lib/cpus/aarch64/cortex_x4.S \ lib/cpus/aarch64/neoverse_n_common.S \ - lib/cpus/aarch64/neoverse_n1.S \ - lib/cpus/aarch64/neoverse_n2.S \ - lib/cpus/aarch64/neoverse_v1.S \ - lib/cpus/aarch64/cortex_hayes.S \ - lib/cpus/aarch64/cortex_hunter.S \ - lib/cpus/aarch64/cortex_hunter_elp_arm.S \ - lib/cpus/aarch64/cortex_chaberton.S \ + lib/cpus/aarch64/neoverse_n1.S \ + lib/cpus/aarch64/neoverse_n2.S \ + lib/cpus/aarch64/neoverse_v1.S \ + lib/cpus/aarch64/cortex_chaberton.S \ lib/cpus/aarch64/cortex_blackhawk.S # AArch64/AArch32 cores
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c index 24d88ee..655a4d2 100644 --- a/plat/arm/board/common/board_arm_trusted_boot.c +++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,7 +9,6 @@ #include <string.h> #include <common/debug.h> -#include <drivers/arm/cryptocell/cc_rotpk.h> #include <drivers/delay_timer.h> #include <lib/cassert.h> #include <lib/fconf/fconf.h> @@ -27,11 +26,9 @@ #include <plat/arm/common/plat_arm.h> #include <platform_def.h> -#if !ARM_CRYPTOCELL_INTEG #if !ARM_ROTPK_LOCATION_ID #error "ARM_ROTPK_LOCATION_ID not defined" #endif -#endif #if COT_DESC_IN_DTB && defined(IMAGE_BL2) uintptr_t nv_cntr_base_addr[MAX_NV_CTR_IDS]; @@ -50,7 +47,7 @@ extern unsigned char arm_rotpk_header[], arm_rotpk_key[], arm_rotpk_hash_end[], arm_rotpk_key_end[]; -#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) || ARM_CRYPTOCELL_INTEG +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) static unsigned char rotpk_hash_der[ARM_ROTPK_HEADER_LEN + ARM_ROTPK_HASH_LEN]; #endif @@ -94,43 +91,26 @@ #endif #if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ - (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ - (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, unsigned int *flags) { - if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) { - *key_ptr = arm_rotpk_key; - *key_len = arm_rotpk_key_end - arm_rotpk_key; - *flags = 0; - } else { - *key_ptr = arm_rotpk_header; - *key_len = arm_rotpk_hash_end - arm_rotpk_header; - *flags = ROTPK_IS_HASH; - } + *key_ptr = arm_rotpk_header; + *key_len = arm_rotpk_hash_end - arm_rotpk_header; + *flags = ROTPK_IS_HASH; return 0; } #endif -#if ARM_CRYPTOCELL_INTEG -/* - * Return ROTPK hash from CryptoCell. - */ -int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ + (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) +int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, unsigned int *flags) { - unsigned char *dst; - - assert(key_ptr != NULL); - assert(key_len != NULL); - assert(flags != NULL); - - /* Copy the DER header */ - memcpy(rotpk_hash_der, arm_rotpk_header, ARM_ROTPK_HEADER_LEN); - dst = &rotpk_hash_der[ARM_ROTPK_HEADER_LEN]; - *key_ptr = rotpk_hash_der; - *key_len = sizeof(rotpk_hash_der); - return cc_get_rotpk_hash(dst, ARM_ROTPK_HASH_LEN, flags); + *key_ptr = arm_rotpk_key; + *key_len = arm_rotpk_key_end - arm_rotpk_key; + *flags = 0; + return 0; } #endif @@ -140,20 +120,13 @@ static int get_rotpk_info(void **key_ptr, unsigned int *key_len, unsigned int *flags) { -#if ARM_CRYPTOCELL_INTEG - return arm_get_rotpk_info_cc(key_ptr, key_len, flags); -#else - -#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ - (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ - (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) +#if ARM_USE_DEVEL_ROTPK return arm_get_rotpk_info_dev(key_ptr, key_len, flags); #elif (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) return arm_get_rotpk_info_regs(key_ptr, key_len, flags); #else return 1; #endif -#endif /* ARM_CRYPTOCELL_INTEG */ } #if defined(ARM_COT_tbbr)
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk index d73c2e3..365a960 100644 --- a/plat/arm/board/common/board_common.mk +++ b/plat/arm/board/common/board_common.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -13,7 +13,7 @@ ifneq (${TRUSTED_BOARD_BOOT},0) ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_dev_rotpk.S -ifneq (${ARM_CRYPTOCELL_INTEG}, 1) + # ROTPK hash location ifeq (${ARM_ROTPK_LOCATION}, regs) ARM_ROTPK_LOCATION_ID = ARM_ROTPK_REGS_ID @@ -39,6 +39,16 @@ ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S $(warning Development keys support for FVP is deprecated. Use `regs` \ option instead) +else ifeq (${ARM_ROTPK_LOCATION}, devel_full_dev_ecdsa_key) + CRYPTO_ALG=ec + ARM_ROTPK_LOCATION_ID = ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID +ifeq (${KEY_SIZE},384) + ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p384_rotpk.S +else + ARM_ROTPK_S = plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p256_rotpk.S +endif +$(warning Development keys support for FVP is deprecated. Use `regs` \ +option instead) else $(error "Unsupported ARM_ROTPK_LOCATION value") endif @@ -52,8 +62,6 @@ # Force generation of the new hash if ROT_KEY is specified ifdef ROT_KEY HASH_PREREQUISITES = $(ROT_KEY) FORCE -else - HASH_PREREQUISITES = $(ROT_KEY) endif $(ARM_ROTPK_HASH) : $(HASH_PREREQUISITES) @@ -67,12 +75,11 @@ # ARM development platforms TFW_NVCTR_VAL ?= 31 NTFW_NVCTR_VAL ?= 223 -else -# Certificate NV-Counters when CryptoCell is integrated. For development -# platforms we set the counter to first valid value. -TFW_NVCTR_VAL ?= 0 -NTFW_NVCTR_VAL ?= 0 -endif +# The CCA Non-Volatile Counter only exists on some Arm development platforms. +# On others, we mock it by aliasing it to the Trusted Firmware Non-Volatile counter, +# hence we set both counters to the same default value. +CCAFW_NVCTR_VAL ?= 31 + BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c \ ${ARM_ROTPK_S} BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c \
diff --git a/plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p256_rotpk.S b/plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p256_rotpk.S new file mode 100644 index 0000000..690bdbc --- /dev/null +++ b/plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p256_rotpk.S
@@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global arm_rotpk_key + .global arm_rotpk_key_end + + .section .rodata.arm_rotpk_key, "a" + +/* Derived from arm_rotprivk_ecdsa.pem private key file. */ +arm_rotpk_key: + .byte 0x30, 0x59, 0x30, 0x13, 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D + .byte 0x02, 0x01, 0x06, 0x08, 0x2A, 0x86, 0x48, 0xCE, 0x3D, 0x03, 0x01 + .byte 0x07, 0x03, 0x42, 0x00, 0x04, 0x9B, 0xE6, 0x48, 0xBD, 0x34, 0x38 + .byte 0xE1, 0xA2, 0xA4, 0xF3, 0x70, 0xE1, 0x54, 0xBB, 0x2F, 0xB0, 0x5A + .byte 0x4A, 0x0C, 0xFF, 0xC2, 0x87, 0xDB, 0xC0, 0xFB, 0x81, 0xE9, 0xF9 + .byte 0xF9, 0x95, 0x7D, 0x7E, 0xA0, 0x0C, 0x7F, 0x0A, 0xD4, 0xE0, 0x62 + .byte 0x4A, 0x94, 0x5F, 0xEC, 0x52, 0x7D, 0x44, 0x63, 0xC8, 0x9F, 0x61 + .byte 0xFA, 0xC6, 0xCB, 0x7E, 0x6B, 0x53, 0xAD, 0x2C, 0xC5, 0x94, 0x0D + .byte 0x1A, 0x86, 0x91 +arm_rotpk_key_end:
diff --git a/plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p384_rotpk.S b/plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p384_rotpk.S new file mode 100644 index 0000000..eaf2de4 --- /dev/null +++ b/plat/arm/board/common/rotpk/arm_full_dev_ecdsa_p384_rotpk.S
@@ -0,0 +1,25 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global arm_rotpk_key + .global arm_rotpk_key_end + + .section .rodata.arm_rotpk_key, "a" + +/* Derived from arm_rotprivk_ecdsa_secp384r1.pem private key file. */ +arm_rotpk_key: + .byte 0x30, 0x76, 0x30, 0x10, 0x06, 0x07, 0x2A, 0x86, 0x48, 0xCE, 0x3D + .byte 0x02, 0x01, 0x06, 0x05, 0x2B, 0x81, 0x04, 0x00, 0x22, 0x03, 0x62 + .byte 0x00, 0x04, 0xB8, 0xB0, 0xC7, 0xC4, 0x57, 0x19, 0xB7, 0x5A, 0x06 + .byte 0x36, 0xC5, 0xD8, 0x3C, 0x4E, 0xC3, 0xB5, 0xE1, 0x15, 0x60, 0x0E + .byte 0x63, 0xD8, 0xAF, 0x22, 0x2C, 0x6D, 0x79, 0x29, 0xDF, 0x46, 0xA9 + .byte 0x30, 0x12, 0x16, 0x2D, 0x4F, 0x0F, 0x96, 0x6B, 0x1F, 0x87, 0x06 + .byte 0xDB, 0x8F, 0xD7, 0x08, 0x46, 0xE4, 0x4C, 0x22, 0xF3, 0xDE, 0xCE + .byte 0x0F, 0x72, 0x27, 0x00, 0xAA, 0xD8, 0xC3, 0x79, 0x80, 0x5E, 0xF1 + .byte 0x35, 0x1B, 0x33, 0xB6, 0x31, 0xC4, 0x59, 0xD4, 0xE9, 0x65, 0x91 + .byte 0x22, 0x58, 0x2F, 0x87, 0xF1, 0x6C, 0x27, 0xBE, 0x99, 0x6F, 0x5F + .byte 0x6C, 0x14, 0xC5, 0x37, 0x0C, 0x73, 0xB4, 0xE4, 0x8A, 0x63 +arm_rotpk_key_end:
diff --git a/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S b/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S index 4bb04dc..4532e53 100644 --- a/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S +++ b/plat/arm/board/common/rotpk/arm_full_dev_rsa_rotpk.S
@@ -1,32 +1,40 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -/* corstone1000 platform provides custom values for the macros defined in - * arm_def.h , so only platform_def.h needs to be included - */ -#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA) -#include "plat/arm/common/arm_def.h" -#else -#include <platform_def.h> -#endif - .global arm_rotpk_key .global arm_rotpk_key_end .section .rodata.arm_rotpk_key, "a" arm_rotpk_key: - .byte 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01 - .byte 0x05, 0x00, 0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01, 0x0A, 0x02, 0x82, 0x01, 0x01 - .byte 0x00, 0xCB, 0x2C, 0x60, 0xD5, 0x8D, 0x63, 0xD4, 0x07, 0x79, 0x7E, 0xC7, 0x16, 0x96, 0xBD, 0x4D, 0x24, 0x4E, 0xAC, 0x86, 0xE6, 0xB7, 0x71, 0xE3, 0xC5, 0x54, 0x0B, 0xE7, 0x14, 0x1C, 0xBD, 0x29, 0x1A, 0xC1, 0x3F, 0x7A, 0xB6, 0x02, 0xAA, 0xAB, 0x36, 0xC4, 0xD9, 0x36, 0x69, 0x6C, 0xE2, 0x65, 0xC3, 0x9B, 0xB1, 0xBF, 0x3D, 0xA8, 0x56, 0x26, 0xCB, 0xFD, 0x04, 0x01, 0xBA, 0xAC, 0x3E, 0x54, 0x32, 0xCA, 0x79, 0x5E, 0xBB, 0xB2, 0x05, 0xEA, 0x06, 0x58, 0xF2, 0x74, 0xBA, 0xE1, 0xF4, 0x87, 0xC0, 0x19, 0x0A, 0x1F, 0x66, 0x07, 0x77, 0x84, 0x83, 0xA1, 0x1C, 0xEF, 0xFF, 0x28, 0x59, 0xE7, 0xC3, 0x68, 0x7D, 0x26, 0x20, 0x43, 0xEB, 0x56, 0x63, 0xF3, 0x39, 0x31, 0xD8, 0x2B, 0x51, 0xA9, 0xBC, 0x4F, 0xD0, 0xF6, 0xDE, 0x95, 0xDC, 0x5F, 0x5B, 0xC1, 0xED, 0x90, 0x6F, 0xEC, 0x28, 0x91, 0x7E, 0x17, 0xED, 0x78, 0x90, 0xF4, 0x60, 0xA7, 0xC4, 0xC7, 0x4F, 0x50, 0xED, 0x5D, 0x13, 0x3A, 0x21, 0x2B, 0x70, 0xC5, 0x61, 0x7B, 0x08, 0x21, 0x65, 0x3A, 0xCD, 0x82, 0x56, 0x8C, 0x7A, 0x47, 0xAC, 0x89, 0xE8, 0xA5, 0x48, 0x48 - .byte 0x31, 0xD9, 0x1D, 0x46, 0xE5, 0x85, 0x86, 0x98, 0xA0, 0xE5, 0xC0, 0xA6, 0x6A, 0xBD, 0x07, 0xE4, 0x92, 0x57, 0x61, 0x07, 0x8F, 0x7D, 0x5A, 0x4D, 0xCA, 0xAE, 0x36, 0xB9, 0x56, 0x04, 0x10, 0xF2, 0x6C, 0xBE, 0xF6, 0x3B, 0x6C, 0x80, 0x3E, 0xBE , 0x0E, 0xA3, 0x4D , 0xC7 , 0xD4, 0x7E , 0xA7 , 0x49, 0xD4, 0xF2, 0xD2, 0xBC, 0xCF, 0x30, 0xA8, 0xE7, 0x74, 0x8F, 0x64, 0xDF, 0xBC, 0x5C, 0x47, 0x68, 0xCC, 0x40, 0x4C, 0xF8, 0x83, 0xCC, 0xCB, 0x40, 0x35, 0x04, 0x60, 0xCA, 0xB3, 0xA4, 0x17, 0x9F, 0x03, 0xCA, 0x1D, 0x5A, 0xFA, 0xD1, 0xAF, 0x21, 0x57, 0x10, 0xD3, 0x02, 0x03, 0x01, 0x00, 0x01 - + .byte 0x30, 0x82, 0x01, 0x22, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48 + .byte 0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 0x05, 0x00, 0x03, 0x82, 0x01 + .byte 0x0F, 0x00, 0x30, 0x82, 0x01, 0x0A, 0x02, 0x82, 0x01, 0x01, 0x00 + .byte 0xCB, 0x2C, 0x60, 0xD5, 0x8D, 0x63, 0xD4, 0x07, 0x79, 0x7E, 0xC7 + .byte 0x16, 0x96, 0xBD, 0x4D, 0x24, 0x4E, 0xAC, 0x86, 0xE6, 0xB7, 0x71 + .byte 0xE3, 0xC5, 0x54, 0x0B, 0xE7, 0x14, 0x1C, 0xBD, 0x29, 0x1A, 0xC1 + .byte 0x3F, 0x7A, 0xB6, 0x02, 0xAA, 0xAB, 0x36, 0xC4, 0xD9, 0x36, 0x69 + .byte 0x6C, 0xE2, 0x65, 0xC3, 0x9B, 0xB1, 0xBF, 0x3D, 0xA8, 0x56, 0x26 + .byte 0xCB, 0xFD, 0x04, 0x01, 0xBA, 0xAC, 0x3E, 0x54, 0x32, 0xCA, 0x79 + .byte 0x5E, 0xBB, 0xB2, 0x05, 0xEA, 0x06, 0x58, 0xF2, 0x74, 0xBA, 0xE1 + .byte 0xF4, 0x87, 0xC0, 0x19, 0x0A, 0x1F, 0x66, 0x07, 0x77, 0x84, 0x83 + .byte 0xA1, 0x1C, 0xEF, 0xFF, 0x28, 0x59, 0xE7, 0xC3, 0x68, 0x7D, 0x26 + .byte 0x20, 0x43, 0xEB, 0x56, 0x63, 0xF3, 0x39, 0x31, 0xD8, 0x2B, 0x51 + .byte 0xA9, 0xBC, 0x4F, 0xD0, 0xF6, 0xDE, 0x95, 0xDC, 0x5F, 0x5B, 0xC1 + .byte 0xED, 0x90, 0x6F, 0xEC, 0x28, 0x91, 0x7E, 0x17, 0xED, 0x78, 0x90 + .byte 0xF4, 0x60, 0xA7, 0xC4, 0xC7, 0x4F, 0x50, 0xED, 0x5D, 0x13, 0x3A + .byte 0x21, 0x2B, 0x70, 0xC5, 0x61, 0x7B, 0x08, 0x21, 0x65, 0x3A, 0xCD + .byte 0x82, 0x56, 0x8C, 0x7A, 0x47, 0xAC, 0x89, 0xE8, 0xA5, 0x48, 0x48 + .byte 0x31, 0xD9, 0x1D, 0x46, 0xE5, 0x85, 0x86, 0x98, 0xA0, 0xE5, 0xC0 + .byte 0xA6, 0x6A, 0xBD, 0x07, 0xE4, 0x92, 0x57, 0x61, 0x07, 0x8F, 0x7D + .byte 0x5A, 0x4D, 0xCA, 0xAE, 0x36, 0xB9, 0x56, 0x04, 0x10, 0xF2, 0x6C + .byte 0xBE, 0xF6, 0x3B, 0x6C, 0x80, 0x3E, 0xBE, 0x0E, 0xA3, 0x4D, 0xC7 + .byte 0xD4, 0x7E, 0xA7, 0x49, 0xD4, 0xF2, 0xD2, 0xBC, 0xCF, 0x30, 0xA8 + .byte 0xE7, 0x74, 0x8F, 0x64, 0xDF, 0xBC, 0x5C, 0x47, 0x68, 0xCC, 0x40 + .byte 0x4C, 0xF8, 0x83, 0xCC, 0xCB, 0x40, 0x35, 0x04, 0x60, 0xCA, 0xB3 + .byte 0xA4, 0x17, 0x9F, 0x03, 0xCA, 0x1D, 0x5A, 0xFA, 0xD1, 0xAF, 0x21 + .byte 0x57, 0x10, 0xD3, 0x02, 0x03, 0x01, 0x00, 0x01 arm_rotpk_key_end: - -.if ARM_ROTPK_KEY_LEN != arm_rotpk_key_end - arm_rotpk_key -.error "Invalid ROTPK length." -.endif -
diff --git a/plat/arm/board/common/rotpk/arm_rotprivk_ecdsa_secp384r1.pem b/plat/arm/board/common/rotpk/arm_rotprivk_ecdsa_secp384r1.pem new file mode 100644 index 0000000..d40fc05 --- /dev/null +++ b/plat/arm/board/common/rotpk/arm_rotprivk_ecdsa_secp384r1.pem
@@ -0,0 +1,6 @@ +-----BEGIN PRIVATE KEY----- +MIG2AgEAMBAGByqGSM49AgEGBSuBBAAiBIGeMIGbAgEBBDAWrGXulAoVCrH3oRMC +/AGvn2LA6+VI0xtd9eCWCzIcOSt+AC+/kULZnypuC8bdGJOhZANiAAS4sMfEVxm3 +WgY2xdg8TsO14RVgDmPYryIsbXkp30apMBIWLU8Plmsfhwbbj9cIRuRMIvPezg9y +JwCq2MN5gF7xNRsztjHEWdTpZZEiWC+H8WwnvplvX2wUxTcMc7TkimM= +-----END PRIVATE KEY-----
diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c index 0235f8b..ed3801c 100644 --- a/plat/arm/board/corstone1000/common/corstone1000_plat.c +++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,36 +33,16 @@ static void set_fip_image_source(void) { const struct plat_io_policy *policy; - /* - * metadata for firmware update is written at 0x0000 offset of the flash. - * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted. - * As per firmware update spec, at a given point of time, only one bank - * is active. This means, TF-A should boot from the same bank as TF-M. - */ - volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG); - - if (*boot_bank_flag > 1) { - VERBOSE("Boot_bank is set higher than possible values"); - } - - VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag); - policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID); assert(policy != NULL); assert(policy->image_spec != 0UL); + /* FIP Partition contains Signature area at the beginning which TF-A doesn't expect */ io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec; + spec->offset += FIP_SIGNATURE_AREA_SIZE; + spec->length -= FIP_SIGNATURE_AREA_SIZE; - if ((*boot_bank_flag) == 0) { - VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r", - PLAT_ARM_FIP_BASE_BANK0); - spec->offset = PLAT_ARM_FIP_BASE_BANK0; - } else { - VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r", - PLAT_ARM_FIP_BASE_BANK1); - spec->offset = PLAT_ARM_FIP_BASE_BANK1; - } } void bl2_platform_setup(void)
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h index 584d485..442d187 100644 --- a/plat/arm/board/corstone1000/common/include/platform_def.h +++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -173,16 +173,15 @@ /* NOR Flash */ -#define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000) -#define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000) -#define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000) -#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ - #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE #define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ - -#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0 +#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ +#define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000) #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE +#define PLAT_ARM_FIP_OFFSET_IN_GPT (0x86000) + +/* FIP Information */ +#define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */ /* * Some data must be aligned on the biggest cache line size in the platform.
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk index 3edffe0..dcd0df8 100644 --- a/plat/arm/board/corstone1000/platform.mk +++ b/plat/arm/board/corstone1000/platform.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -43,6 +43,7 @@ plat/arm/board/corstone1000/common/corstone1000_err.c \ plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \ lib/utils/mem_region.c \ + lib/cpus/aarch64/cpu_helpers.S \ plat/arm/board/corstone1000/common/corstone1000_helpers.S \ plat/arm/board/corstone1000/common/corstone1000_plat.c \ plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
diff --git a/plat/arm/board/corstone700/platform.mk b/plat/arm/board/corstone700/platform.mk index 75833f6..d6d3bef 100644 --- a/plat/arm/board/corstone700/platform.mk +++ b/plat/arm/board/corstone700/platform.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -25,6 +25,10 @@ NEED_BL32 := yes +ifeq (${AARCH32_SP},none) + $(error Variable AARCH32_SP has to be set for AArch32) +endif + # Include GICv2 driver files include drivers/arm/gic/v2/gicv2.mk
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts index 4f97339..e159248 100644 --- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts +++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -35,6 +35,11 @@ load_address = <0x7000000>; vcpu_count = <8>; mem_size = <1048576>; + /* + * Platform specific SiP SMC call handled at EL3. Used + * to pend an interrupt for testing purpose. + */ + smc_whitelist = <0x82000100>; }; vm2 { is_ffa_partition;
diff --git a/plat/arm/board/fvp/fvp_bl1_measured_boot.c b/plat/arm/board/fvp/fvp_bl1_measured_boot.c index 72fdfef..dc95ba1 100644 --- a/plat/arm/board/fvp/fvp_bl1_measured_boot.c +++ b/plat/arm/board/fvp/fvp_bl1_measured_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <drivers/measured_boot/event_log/event_log.h> #include <drivers/measured_boot/rss/rss_measured_boot.h> #include <plat/arm/common/plat_arm.h> +#include <tools_share/zero_oid.h> /* Event Log data */ static uint8_t event_log[PLAT_ARM_EVENT_LOG_MAX_SIZE]; @@ -31,18 +32,21 @@ .slot = U(6), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_FW_CONFIG_STRING, + .pk_oid = ZERO_OID, .lock_measurement = true }, { .id = TB_FW_CONFIG_ID, .slot = U(7), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING, + .pk_oid = ZERO_OID, .lock_measurement = true }, { .id = BL2_IMAGE_ID, .slot = U(8), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_BL2_STRING, + .pk_oid = ZERO_OID, .lock_measurement = true }, { @@ -54,7 +58,7 @@ event_log_init(event_log, event_log + sizeof(event_log)); event_log_write_header(); - rss_measured_boot_init(); + rss_measured_boot_init(fvp_rss_mboot_metadata); } void bl1_plat_mboot_finish(void)
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c index e6b9192..349e064 100644 --- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c +++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -9,7 +9,11 @@ #include <common/tbbr/tbbr_img_def.h> #include <drivers/measured_boot/event_log/event_log.h> #include <drivers/measured_boot/rss/rss_measured_boot.h> +#if defined(ARM_COT_cca) +#include <tools_share/cca_oid.h> +#else #include <tools_share/tbbr_oid.h> +#endif /* ARM_COT_cca */ #include <fvp_critical_data.h> #include <plat/arm/common/plat_arm.h> @@ -62,25 +66,31 @@ .slot = U(9), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_BL31_STRING, + .pk_oid = BL31_IMAGE_KEY_OID, .lock_measurement = true }, { .id = HW_CONFIG_ID, .slot = U(10), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_HW_CONFIG_STRING, + .pk_oid = HW_CONFIG_KEY_OID, .lock_measurement = true }, { .id = SOC_FW_CONFIG_ID, .slot = U(11), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING, + .pk_oid = SOC_FW_CONFIG_KEY_OID, .lock_measurement = true }, +#if ENABLE_RME { .id = RMM_IMAGE_ID, .slot = U(12), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_RMM_STRING, + .pk_oid = RMM_IMAGE_KEY_OID, .lock_measurement = true }, +#endif /* ENABLE_RME */ { .id = RSS_MBOOT_INVALID_ID } }; @@ -117,7 +127,7 @@ event_log_init((uint8_t *)event_log_start, event_log_finish); - rss_measured_boot_init(); + rss_measured_boot_init(fvp_rss_mboot_metadata); } int plat_mboot_measure_critical_data(unsigned int critical_data_id,
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c index b93922a..ebd5266 100644 --- a/plat/arm/board/fvp/fvp_bl2_setup.c +++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -11,6 +11,7 @@ #include <drivers/arm/sp804_delay_timer.h> #include <lib/fconf/fconf.h> #include <lib/fconf/fconf_dyn_cfg_getter.h> +#include <lib/transfer_list.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> @@ -18,6 +19,8 @@ #include "fvp_private.h" +static struct transfer_list_header *ns_tl __unused; + void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); @@ -30,6 +33,10 @@ { arm_bl2_platform_setup(); +#if TRANSFER_LIST + ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE); + assert(ns_tl != NULL); +#endif /* Initialize System level generic or SP804 timer */ fvp_timer_init(); } @@ -41,6 +48,7 @@ { struct bl_params *arm_bl_params; const struct dyn_cfg_dtb_info_t *hw_config_info __unused; + struct transfer_list_entry *te __unused; bl_mem_params_node_t *param_node __unused; arm_bl_params = arm_get_next_bl_params(); @@ -48,7 +56,6 @@ #if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE const struct dyn_cfg_dtb_info_t *fw_config_info; uintptr_t fw_config_base = 0UL; - entry_point_info_t *ep_info; #if __aarch64__ /* Get BL31 image node */ @@ -59,47 +66,75 @@ #endif /* __aarch64__ */ assert(param_node != NULL); - /* get fw_config load address */ + /* Update the next image's ep info with the FW config address */ fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID); assert(fw_config_info != NULL); fw_config_base = fw_config_info->config_addr; assert(fw_config_base != 0UL); - /* - * Get the entry point info of next executable image and override - * arg1 of entry point info with fw_config base address - */ - ep_info = ¶m_node->ep_info; - ep_info->args.arg1 = (uint32_t)fw_config_base; + param_node->ep_info.args.arg1 = (uint32_t)fw_config_base; - /* grab NS HW config address */ - hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); - assert(hw_config_info != NULL); - - /* To retrieve actual size of the HW_CONFIG */ - param_node = get_bl_mem_params_node(HW_CONFIG_ID); - assert(param_node != NULL); - - /* Copy HW config from Secure address to NS address */ - memcpy((void *)hw_config_info->secondary_config_addr, - (void *)hw_config_info->config_addr, - (size_t)param_node->image_info.image_size); - - /* - * Ensure HW-config device tree committed to memory, as there is - * a possibility to use HW-config without cache and MMU enabled - * at BL33 - */ - flush_dcache_range(hw_config_info->secondary_config_addr, - param_node->image_info.image_size); - + /* Update BL33's ep info with the NS HW config address */ param_node = get_bl_mem_params_node(BL33_IMAGE_ID); assert(param_node != NULL); +#if TRANSFER_LIST /* Update BL33's ep info with NS HW config address */ + te = transfer_list_find(ns_tl, TL_TAG_FDT); + assert(te != NULL); + + param_node->ep_info.args.arg1 = TRANSFER_LIST_SIGNATURE | + REGISTER_CONVENTION_VERSION_MASK; + param_node->ep_info.args.arg2 = 0; + param_node->ep_info.args.arg3 = (uintptr_t)ns_tl; + param_node->ep_info.args.arg0 = + te ? (uintptr_t)transfer_list_entry_data(te) : 0; +#else + hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); + assert(hw_config_info != NULL); + param_node->ep_info.args.arg1 = hw_config_info->secondary_config_addr; +#endif /* TRANSFER_LIST */ #endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */ return arm_bl_params; } + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ +#if !RESET_TO_BL2 && !EL3_PAYLOAD_BASE + if (image_id == HW_CONFIG_ID) { + const struct dyn_cfg_dtb_info_t *hw_config_info; + struct transfer_list_entry *te __unused; + + const bl_mem_params_node_t *param_node = + get_bl_mem_params_node(image_id); + assert(param_node != NULL); + + hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); + assert(hw_config_info != NULL); + +#if TRANSFER_LIST + /* Update BL33's ep info with NS HW config address */ + te = transfer_list_add(ns_tl, TL_TAG_FDT, + param_node->image_info.image_size, + (void *)hw_config_info->config_addr); + assert(te != NULL); +#else + memcpy((void *)hw_config_info->secondary_config_addr, + (void *)hw_config_info->config_addr, + (size_t)param_node->image_info.image_size); + + /* + * Ensure HW-config device tree is committed to memory, as the HW-Config + * might be used without cache and MMU enabled at BL33. + */ + flush_dcache_range(hw_config_info->secondary_config_addr, + param_node->image_info.image_size); +#endif /* TRANSFER_LIST */ + } +#endif /* !RESET_TO_BL2 && !EL3_PAYLOAD_BASE */ + + return arm_bl2_plat_handle_post_image_load(image_id); +}
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 283918b..c40a3ce 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c
@@ -71,6 +71,14 @@ DEVICE2_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +#if TRANSFER_LIST +#ifdef FW_NS_HANDOFF_BASE +#define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, \ + FW_HANDOFF_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) +#endif +#endif + /* * Table of memory regions for various BL stages to map using the MMU. * This doesn't include Trusted SRAM as setup_page_tables() already takes care @@ -183,6 +191,9 @@ ARM_MAP_GPT_L1_DRAM, ARM_MAP_EL3_RMM_SHARED_MEM, #endif +#ifdef MAP_FW_NS_HANDOFF + MAP_FW_NS_HANDOFF, +#endif {0} };
diff --git a/plat/arm/board/fvp/fvp_common_measured_boot.c b/plat/arm/board/fvp/fvp_common_measured_boot.c index b5b8f10..0c1d5e7 100644 --- a/plat/arm/board/fvp/fvp_common_measured_boot.c +++ b/plat/arm/board/fvp/fvp_common_measured_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,11 +16,6 @@ extern event_log_metadata_t fvp_event_log_metadata[]; extern struct rss_mboot_metadata fvp_rss_mboot_metadata[]; -struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void) -{ - return fvp_rss_mboot_metadata; -} - int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data) { int err; @@ -38,7 +33,8 @@ } /* Calculate image hash and record data in RSS */ - err = rss_mboot_measure_and_record(image_data->image_base, + err = rss_mboot_measure_and_record(fvp_rss_mboot_metadata, + image_data->image_base, image_data->image_size, image_id); if (err != 0) { @@ -49,3 +45,10 @@ return rc; } + +int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, + size_t pk_len) +{ + return rss_mboot_set_signer_id(fvp_rss_mboot_metadata, pk_oid, pk_ptr, + pk_len); +}
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk index 944571d..b8fa4ea 100644 --- a/plat/arm/board/fvp/fvp_cpu_errata.mk +++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -30,6 +30,7 @@ CORTEX_A77_H_INC := 1 CORTEX_A78_H_INC := 1 NEOVERSE_N1_H_INC := 1 +NEOVERSE_N2_H_INC := 1 NEOVERSE_V1_H_INC := 1 CORTEX_A78_AE_H_INC := 1 CORTEX_A510_H_INC := 1 @@ -41,6 +42,7 @@ $(eval $(call add_define, CORTEX_A77_H_INC)) $(eval $(call add_define, CORTEX_A78_H_INC)) $(eval $(call add_define, NEOVERSE_N1_H_INC)) +$(eval $(call add_define, NEOVERSE_N2_H_INC)) $(eval $(call add_define, NEOVERSE_V1_H_INC)) $(eval $(call add_define, CORTEX_A78_AE_H_INC)) $(eval $(call add_define, CORTEX_A510_H_INC))
diff --git a/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c b/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c index b9e4f86..72dfa30 100644 --- a/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c +++ b/plat/arm/board/fvp/fvp_el3_spmc_logical_sp.c
@@ -27,6 +27,7 @@ void *handle, uint64_t flags) { uint64_t ret; + uint32_t src_dst; /* Determine if we have a 64 or 32 direct request. */ if (smc_fid == FFA_MSG_SEND_DIRECT_REQ_SMC32) { @@ -36,18 +37,22 @@ } else { panic(); /* Unknown SMC. */ } + /* * Handle the incoming request. For testing purposes we echo the * incoming message. */ - INFO("Logical Partition: Received Direct Request from %s world!\n", - secure_origin ? "Secure" : "Normal"); + INFO("LSP: Received Direct Request from %s world (0x%x)\n", + secure_origin ? "Secure" : "Normal", ffa_endpoint_source(x1)); + /* Populate the source and destination IDs. */ + src_dst = (uint32_t) LP_PARTITION_ID << FFA_DIRECT_MSG_SOURCE_SHIFT | + ffa_endpoint_source(x1) << FFA_DIRECT_MSG_DESTINATION_SHIFT; /* * Logical SP's must always send a direct response so we can populate * our response directly. */ - SMC_RET8(handle, ret, 0, 0, x4, 0, 0, 0, 0); + SMC_RET8(handle, ret, src_dst, 0, x4, 0, 0, 0, 0); } /* Register logical partition */
diff --git a/plat/arm/board/fvp/fvp_plat_attest_token.c b/plat/arm/board/fvp/fvp_plat_attest_token.c index 5af2405..5fb3141 100644 --- a/plat/arm/board/fvp/fvp_plat_attest_token.c +++ b/plat/arm/board/fvp/fvp_plat_attest_token.c
@@ -4,23 +4,115 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <delegated_attestation.h> -#include <psa/error.h> +#include <errno.h> +#include <string.h> + +#include <plat/common/platform.h> + +static const uint8_t sample_platform_token[] = { + 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0, + 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78, + 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F, + 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F, + 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F, + 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20, + 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5, + 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69, + 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD, + 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA, + 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C, + 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00, + 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, + 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, + 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, + 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, + 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21, + 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, + 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, + 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, + 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, + 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19, + 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32, + 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01, + 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06, + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, + 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, + 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, + 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, + 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, + 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, + 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, + 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53, + 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D, + 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01, + 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06, + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, + 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, + 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, + 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63, + 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06, + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, + 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, + 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, + 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01, + 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06, + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, + 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, + 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, + 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65, + 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, + 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, + 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, + 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, + 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, + 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, + 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, + 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06, + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E, + 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16, + 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E, + 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09, + 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76, + 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60, + 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67, + 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA, + 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02, + 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5, + 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E, + 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1, + 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59, + 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98, + 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4, + 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0, + 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C, + 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30 +}; /* - * Get the platform attestation token through the PSA delegated attestation - * layer. - * - * FVP cannot support RSS hardware at the moment, but it can still mock the - * RSS implementation of the PSA interface (see PLAT_RSS_NOT_SUPPORTED). + * Get the hardcoded platform attestation token as FVP does not support + * RSS. */ int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len, uintptr_t hash, size_t hash_size) { - psa_status_t ret; + (void)hash; + (void)hash_size; - ret = rss_delegated_attest_get_token((const uint8_t *)hash, hash_size, - (uint8_t *)buf, *len, len); + if (*len < sizeof(sample_platform_token)) { + return -EINVAL; + } - return ret; + (void)memcpy((void *)buf, (const void *)sample_platform_token, + sizeof(sample_platform_token)); + *len = sizeof(sample_platform_token); + + return 0; }
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index a3289b6..51dda9e 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c
@@ -65,25 +65,6 @@ /* Disable coherency if this cluster is to be turned off */ fvp_interconnect_disable(); -#if HW_ASSISTED_COHERENCY - uint32_t reg; - - /* - * If we have determined this core to be the last man standing and we - * intend to power down the cluster proactively, we provide a hint to - * the power controller that cluster power is not required when all - * cores are powered down. - * Note that this is only an advisory to power controller and is supported - * by SoCs with DynamIQ Shared Units only. - */ - reg = read_clusterpwrdn(); - - /* Clear and set bit 0 : Cluster power not required */ - reg &= ~DSU_CLUSTER_PWR_MASK; - reg |= DSU_CLUSTER_PWR_OFF; - write_clusterpwrdn(reg); -#endif - /* Program the power controller to turn the cluster off */ fvp_pwrc_write_pcoffr(mpidr); } @@ -228,11 +209,7 @@ * FVP handler called when a power domain is about to be suspended. The * target_state encodes the power state that each level should transition to. ******************************************************************************/ -#if PSCI_OS_INIT_MODE -static int fvp_pwr_domain_suspend(const psci_power_state_t *target_state) -#else static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) -#endif { unsigned long mpidr; @@ -242,11 +219,7 @@ */ if (target_state->pwr_domain_state[ARM_PWR_LVL0] == ARM_LOCAL_STATE_RET) -#if PSCI_OS_INIT_MODE - return PSCI_E_SUCCESS; -#else return; -#endif assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == ARM_LOCAL_STATE_OFF); @@ -279,11 +252,7 @@ /* Program the power controller to power off this cpu. */ fvp_pwrc_write_ppoffr(read_mpidr_el1()); -#if PSCI_OS_INIT_MODE - return PSCI_E_SUCCESS; -#else return; -#endif } /******************************************************************************* @@ -405,6 +374,10 @@ for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; + +#if PSCI_OS_INIT_MODE + req_state->last_at_pwrlvl = PLAT_MAX_PWR_LVL; +#endif } #endif
diff --git a/plat/arm/board/fvp/fvp_realm_attest_key.c b/plat/arm/board/fvp/fvp_realm_attest_key.c index 26354f4..fe0cde7 100644 --- a/plat/arm/board/fvp/fvp_realm_attest_key.c +++ b/plat/arm/board/fvp/fvp_realm_attest_key.c
@@ -4,27 +4,33 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#include <assert.h> -#include <delegated_attestation.h> -#include <psa/error.h> -#include <services/rmmd_svc.h> +#include <errno.h> +#include <string.h> + +#include <plat/common/platform.h> + +static const uint8_t sample_delegated_key[] = { + 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E, + 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6, + 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E, + 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7, + 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68 +}; /* - * Get the delegated realm attestation key through the PSA delegated - * attestation layer. - * - * FVP cannot support RSS hardware at the moment, but it can still mock - * the RSS implementation of the PSA interface (see PLAT_RSS_NOT_SUPPORTED). + * Get the hardcoded delegated realm attestation key as FVP + * does not support RSS. */ int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len, unsigned int type) { - psa_status_t ret; + if (*len < sizeof(sample_delegated_key)) { + return -EINVAL; + } - assert(type == ATTEST_KEY_CURVE_ECC_SECP384R1); + (void)memcpy((void *)buf, (const void *)sample_delegated_key, + sizeof(sample_delegated_key)); + *len = sizeof(sample_delegated_key); - ret = rss_delegated_attest_get_delegated_key(0U, 0U, (uint8_t *)buf, - *len, len, 0U); - - return ret; + return 0; }
diff --git a/plat/arm/board/fvp/fvp_spmd_logical_sp.c b/plat/arm/board/fvp/fvp_spmd_logical_sp.c new file mode 100644 index 0000000..8841fc1 --- /dev/null +++ b/plat/arm/board/fvp/fvp_spmd_logical_sp.c
@@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <common/debug.h> +#include <services/el3_spmd_logical_sp.h> +#include <services/ffa_svc.h> +#include <smccc_helpers.h> + +#define SPMD_LP_PARTITION_ID SPMD_LP_ID_START +#define SPMD_LP_UUID {0xe98e43ad, 0xb7db524f, 0x47a3bf57, 0x1588f4e3} + +/* SPMD Logical SP currently only supports sending direct message. */ +#define SPMD_PARTITION_PROPERTIES FFA_PARTITION_DIRECT_REQ_SEND + +#define SPMD_LP_MAX_SUPPORTED_SP 10 +static void fvp_get_partition_info(void) +{ + struct ffa_value ret = { 0 }; + uint32_t target_uuid[4] = { 0 }; + static struct ffa_partition_info_v1_1 + part_info[SPMD_LP_MAX_SUPPORTED_SP] = { 0 }; + + uint16_t num_partitions = 0; + + if (!spmd_el3_invoke_partition_info_get(target_uuid, 0, 0, &ret)) { + panic(); + } + + if (is_ffa_error(&ret)) { + panic(); + } + + num_partitions = ffa_partition_info_regs_get_last_idx(&ret) + 1; + if (num_partitions > SPMD_LP_MAX_SUPPORTED_SP) { + panic(); + } + + INFO("Number of secure partitions = %d\n", num_partitions); + + for (uint16_t i = 0; i < num_partitions; i++) { + INFO("***Start Partition***\n"); + if (!ffa_partition_info_regs_get_part_info(&ret, i, &part_info[i])) + panic(); + INFO("\tPartition ID: 0x%x\n", part_info[i].ep_id); + INFO("\tvCPU count:0x%x\n", part_info[i].execution_ctx_count); + INFO("\tProperties: 0x%x\n", part_info[i].properties); + INFO("\tUUID: 0x%x 0x%x 0x%x 0x%x\n", part_info[i].uuid[0], + part_info[i].uuid[1], part_info[i].uuid[2], + part_info[i].uuid[3]); + INFO("***End Partition***\n"); + } + +} + +static int32_t fvp_spmd_logical_partition_init(void) +{ + INFO("FVP SPMD LSP: Init function called.\n"); + + fvp_get_partition_info(); + return 0; +} + +/* + * Platform specific SMC handler used to translate SIP SMCs or other platform + * specific SMCs into FF-A direct messages. + */ +uintptr_t plat_spmd_logical_sp_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + struct ffa_value retval = { 0 }; + uint64_t send_recv_id = SPMD_LP_PARTITION_ID << 16 | 0x8001; + + /* + * Forward the SMC as direct request. + */ + if (!spmd_el3_ffa_msg_direct_req(send_recv_id, x2, x3, x4, handle, &retval)) { + panic(); + } + + SMC_RET8(handle, retval.func, retval.arg1, retval.arg2, retval.arg3, + retval.arg4, retval.arg5, retval.arg6, retval.arg7); +} + +/* Register SPMD logical partition */ +DECLARE_SPMD_LOGICAL_PARTITION( + fvp_spmd_logical_partition, + fvp_spmd_logical_partition_init,/* Init Function */ + SPMD_LP_PARTITION_ID, /* FF-A Partition ID */ + SPMD_LP_UUID, /* UUID */ + SPMD_PARTITION_PROPERTIES /* Partition Properties. */ +);
diff --git a/plat/arm/board/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_trusted_boot.c index 1ea37f7..4c3201e 100644 --- a/plat/arm/board/fvp/fvp_trusted_boot.c +++ b/plat/arm/board/fvp/fvp_trusted_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ #include <plat/arm/common/fconf_nv_cntr_getter.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <tools_share/tbbr_oid.h> +#include <tools_share/cca_oid.h> /* * Return the ROTPK hash in the following ASN.1 structure in DER format: @@ -36,6 +36,33 @@ } /* + * Return the non-volatile counter address stored in the platform. The cookie + * will contain the OID of the counter in the certificate. + * + * Return: 0 = success, Otherwise = error + */ +static int plat_get_nv_ctr_addr(void *cookie, uintptr_t *nv_ctr_addr) +{ + const char *oid = (const char *)cookie; + + if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { + *nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, + TRUSTED_NV_CTR_ID); + } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { + *nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, + NON_TRUSTED_NV_CTR_ID); + } else if (strcmp(oid, CCA_FW_NVCOUNTER_OID) == 0) { + /* FVP does not support the CCA NV Counter so use the Trusted NV */ + *nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, + TRUSTED_NV_CTR_ID); + } else { + return 1; + } + + return 0; +} + +/* * Store a new non-volatile counter value. * * On some FVP versions, the non-volatile counters are read-only so this @@ -45,20 +72,14 @@ */ int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) { - const char *oid; uintptr_t nv_ctr_addr; + int rc; assert(cookie != NULL); - oid = (const char *)cookie; - if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, - TRUSTED_NV_CTR_ID); - } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = FCONF_GET_PROPERTY(cot, nv_cntr_addr, - NON_TRUSTED_NV_CTR_ID); - } else { - return 1; + rc = plat_get_nv_ctr_addr(cookie, &nv_ctr_addr); + if (rc != 0) { + return rc; } mmio_write_32(nv_ctr_addr, nv_ctr); @@ -69,3 +90,27 @@ */ return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1; } + +/* + * Return the non-volatile counter value stored in the platform. The cookie + * will contain the OID of the counter in the certificate. + * + * Return: 0 = success, Otherwise = error + */ +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + uintptr_t nv_ctr_addr; + int rc; + + assert(cookie != NULL); + assert(nv_ctr != NULL); + + rc = plat_get_nv_ctr_addr(cookie, &nv_ctr_addr); + if (rc != 0) { + return rc; + } + + *nv_ctr = *((unsigned int *)nv_ctr_addr); + + return 0; +}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 9e72ba0..aad0417 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h
@@ -43,7 +43,7 @@ */ #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) -#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ +#define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ @@ -128,6 +128,11 @@ */ #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) +#if TRANSFER_LIST +#define FW_HANDOFF_SIZE 0x4000 +#define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - FW_HANDOFF_SIZE) +#endif + /* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. @@ -168,8 +173,13 @@ # define MAX_XLAT_TABLES 6 # endif #elif !USE_ROMLIB -# define PLAT_ARM_MMAP_ENTRIES 11 -# define MAX_XLAT_TABLES 5 +# if ENABLE_RME && defined(IMAGE_BL2) +# define PLAT_ARM_MMAP_ENTRIES 12 +# define MAX_XLAT_TABLES 6 +# else +# define PLAT_ARM_MMAP_ENTRIES 11 +# define MAX_XLAT_TABLES 5 +# endif /* (IMAGE_BL2 && ENABLE_RME) */ #else # define PLAT_ARM_MMAP_ENTRIES 12 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ @@ -183,8 +193,10 @@ /* * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. + * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW + * area. */ -#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA +#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) #else #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) @@ -205,14 +217,18 @@ #endif /* - * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a - * little space for growth. + * Set the maximum size of BL2 to be close to half of the Trusted SRAM. + * Maximum size of BL2 increases as Trusted SRAM size increases. */ #if CRYPTO_SUPPORT #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB -# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) +# define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ + (2 * PAGE_SIZE) - \ + FVP_BL2_ROMLIB_OPTIMIZATION) #else -# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) +# define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ + (3 * PAGE_SIZE) - \ + FVP_BL2_ROMLIB_OPTIMIZATION) #endif #elif ARM_BL31_IN_DRAM /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ @@ -230,9 +246,12 @@ /* * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is * calculated using the current BL31 PROGBITS debug size plus the sizes of - * BL2 and BL1-RW + * BL2 and BL1-RW. + * Size of the BL31 PROGBITS increases as the SRAM size increases. */ -#define PLAT_ARM_MAX_BL31_SIZE (UL(0x3D000) - ARM_L0_GPT_SIZE) +#define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE - \ + ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) #endif /* RESET_TO_BL31 */ #ifndef __aarch64__ @@ -430,7 +449,12 @@ /* * Maximum size of Event Log buffer used in Measured Boot Event Log driver */ +#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) +/* Account for additional measurements of secure partitions and SPM. */ +#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) +#else #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) +#endif /* * Maximum size of Event Log buffer used for DRTM
diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i index 927ffef..dc8032f 100644 --- a/plat/arm/board/fvp/jmptbl.i +++ b/plat/arm/board/fvp/jmptbl.i
@@ -43,6 +43,7 @@ mbedtls mbedtls_asn1_get_bitstring_null mbedtls mbedtls_asn1_get_bool mbedtls mbedtls_asn1_get_int +mbedtls mbedtls_asn1_get_len mbedtls mbedtls_asn1_get_tag mbedtls mbedtls_free mbedtls mbedtls_md
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 0433b61..2fdff34 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk
@@ -24,6 +24,13 @@ FVP_DT_PREFIX := fvp-base-gicv3-psci +# Size (in kilobytes) of the Trusted SRAM region to utilize when building for +# the FVP platform. This option defaults to 256. +FVP_TRUSTED_SRAM_SIZE := 256 + +# Macro to enable helpers for running SPM tests. Disabled by default. +PLAT_TEST_SPM := 0 + # This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's # progbits limit. We need a way to build all useful configurations while waiting # on the fvp to increase its SRAM size. The problem is twofild: @@ -46,15 +53,12 @@ ENABLE_FEAT_AMU := 2 ENABLE_FEAT_AMUv1p1 := 2 ENABLE_FEAT_HCX := 2 - ENABLE_MPAM_FOR_LOWER_ELS := 2 ENABLE_FEAT_RNG := 2 ENABLE_FEAT_TWED := 2 ENABLE_FEAT_GCS := 2 - ENABLE_FEAT_RAS := 2 ifeq (${ARCH}, aarch64) ifneq (${SPD}, spmd) ifeq (${SPM_MM}, 0) -ifeq (${ENABLE_RME}, 0) ifeq (${CTX_INCLUDE_FPREGS}, 0) ENABLE_SME_FOR_NS := 2 ENABLE_SME2_FOR_NS := 2 @@ -63,19 +67,17 @@ endif endif endif -endif # enable unconditionally for all builds ifeq (${ARCH}, aarch64) -ifeq (${ENABLE_RME},0) - ENABLE_BRBE_FOR_NS := 2 + ENABLE_BRBE_FOR_NS := 2 + ENABLE_TRBE_FOR_NS := 2 endif -endif -ENABLE_TRBE_FOR_NS := 2 ENABLE_SYS_REG_TRACE_FOR_NS := 2 ENABLE_FEAT_CSV2_2 := 2 ENABLE_FEAT_DIT := 2 ENABLE_FEAT_PAN := 2 +ENABLE_FEAT_MTE_PERM := 2 ENABLE_FEAT_VHE := 2 CTX_INCLUDE_NEVE_REGS := 2 ENABLE_FEAT_SEL2 := 2 @@ -104,6 +106,9 @@ # Pass FVP_GICR_REGION_PROTECTION to the build system. $(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) +# Pass FVP_TRUSTED_SRAM_SIZE to the build system. +$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) + # Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, # choose the CCI driver , else the CCN driver ifeq ($(FVP_CLUSTER_COUNT), 0) @@ -197,6 +202,7 @@ lib/cpus/aarch64/cortex_a76ae.S \ lib/cpus/aarch64/cortex_a77.S \ lib/cpus/aarch64/cortex_a78.S \ + lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_a78c.S \ lib/cpus/aarch64/cortex_a710.S \ lib/cpus/aarch64/neoverse_n_common.S \ @@ -204,7 +210,10 @@ lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_v1.S \ lib/cpus/aarch64/neoverse_e1.S \ - lib/cpus/aarch64/cortex_x2.S + lib/cpus/aarch64/cortex_x2.S \ + lib/cpus/aarch64/cortex_gelas.S \ + lib/cpus/aarch64/nevis.S \ + lib/cpus/aarch64/travis.S endif # AArch64/AArch32 cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ @@ -213,7 +222,8 @@ else FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ - lib/cpus/aarch32/cortex_a57.S + lib/cpus/aarch32/cortex_a57.S \ + lib/cpus/aarch32/cortex_a53.S endif BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ @@ -257,11 +267,6 @@ BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ plat/arm/board/fvp/fvp_realm_attest_key.c - -# FVP platform does not support RSS, but it can leverage RSS APIs to -# provide hardcoded token/key on request. -BL31_SOURCES += lib/psa/delegated_attestation.c - endif ifeq (${ENABLE_FEAT_RNG_TRAP},1) @@ -346,6 +351,10 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) endif +ifeq (${TRANSFER_LIST}, 1) +include lib/transfer_list/transfer_list.mk +endif + ifeq (${SPD},spmd) ifeq ($(ARM_SPMC_MANIFEST_DTS),) @@ -388,18 +397,18 @@ endif endif -ifeq (${RAS_FFH_SUPPORT},1) +ifeq (${HANDLE_EA_EL3_FIRST_NS},1) +ifeq (${ENABLE_FEAT_RAS},1) BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c +else +BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c +endif endif ifneq (${ENABLE_STACK_PROTECTOR},0) PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c endif -ifeq (${ARCH},aarch32) - NEED_BL32 := yes -endif - # Enable the dynamic translation tables library. ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) ifeq (${ARCH},aarch32) @@ -513,19 +522,25 @@ # Test specific macros, keep them at bottom of this file $(eval $(call add_define,PLATFORM_TEST_EA_FFH)) ifeq (${PLATFORM_TEST_EA_FFH}, 1) - ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) - $(error "PLATFORM_TEST_EA_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") + ifeq (${FFH_SUPPORT}, 0) + $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") endif -BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c + endif $(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) ifeq (${PLATFORM_TEST_RAS_FFH}, 1) - ifeq (${RAS_EXTENSION}, 0) - $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1") + ifeq (${ENABLE_FEAT_RAS}, 0) + $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") + endif + ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) + $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") endif endif ifeq (${ERRATA_ABI_SUPPORT}, 1) include plat/arm/board/fvp/fvp_cpu_errata.mk endif + +# Build macro necessary for running SPM tests on FVP platform +$(eval $(call add_define,PLAT_TEST_SPM))
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c index ae6af6c..820470bc 100644 --- a/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c +++ b/plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c
@@ -17,19 +17,3 @@ { /* v8-R64 does not include SCRs. */ } - -/******************************************************************************* - * Set the Secure EL1 required architectural state - ******************************************************************************/ -void bl1_arch_next_el_setup(void) -{ - u_register_t next_sctlr; - - /* Use the same endianness than the current BL */ - next_sctlr = (read_sctlr_el2() & SCTLR_EE_BIT); - - /* Set SCTLR Secure EL1 */ - next_sctlr |= SCTLR_EL1_RES1; - - write_sctlr_el1(next_sctlr); -}
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_main.c b/plat/arm/board/fvp_r/fvp_r_bl1_main.c index 841a176..252fc31 100644 --- a/plat/arm/board/fvp_r/fvp_r_bl1_main.c +++ b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
@@ -15,7 +15,7 @@ #include <common/debug.h> #include <drivers/auth/auth_mod.h> #include <drivers/console.h> -#include <lib/cpus/errata_report.h> +#include <lib/cpus/errata.h> #include <lib/utils.h> #include <smccc_helpers.h> #include <tools_share/uuid.h>
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c index a642929..6a7c0c8 100644 --- a/plat/arm/board/fvp_r/fvp_r_bl1_setup.c +++ b/plat/arm/board/fvp_r/fvp_r_bl1_setup.c
@@ -105,9 +105,6 @@ ARM_MAP_ROMLIB_CODE, ARM_MAP_ROMLIB_DATA, #endif -#if ARM_CRYPTOCELL_INTEG - ARM_MAP_BL_COHERENT_RAM, -#endif /* DRAM1_region: */ MAP_REGION_FLAT( PLAT_ARM_DRAM1_BASE,
diff --git a/plat/arm/board/fvp_r/platform.mk b/plat/arm/board/fvp_r/platform.mk index 5dd28b9..f14ea54 100644 --- a/plat/arm/board/fvp_r/platform.mk +++ b/plat/arm/board/fvp_r/platform.mk
@@ -83,6 +83,7 @@ drivers/io/io_storage.c \ drivers/io/io_semihosting.c \ lib/cpus/aarch64/cpu_helpers.S \ + lib/cpus/errata_report.c \ lib/fconf/fconf_dyn_cfg_getter.c \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \
diff --git a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c index 4ccae27..cc29f36 100644 --- a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c +++ b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
@@ -39,3 +39,8 @@ generic_delay_timer_init(); #endif /* USE_SP804_TIMER */ } + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return arm_bl2_plat_handle_post_image_load(image_id); +}
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk index f7eace8..79cf356 100644 --- a/plat/arm/board/fvp_ve/platform.mk +++ b/plat/arm/board/fvp_ve/platform.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2021, Arm Limited. All rights reserved. +# Copyright (c) 2019-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -96,6 +96,10 @@ NEED_BL32 := yes +ifeq (${AARCH32_SP},none) + $(error Variable AARCH32_SP has to be set for AArch32) +endif + # Modification of arm_common.mk # Process ARM_DISABLE_TRUSTED_WDOG flag
diff --git a/plat/arm/board/juno/cert_create_tbbr.mk b/plat/arm/board/juno/cert_create_tbbr.mk index c092fe0..4d133b2 100644 --- a/plat/arm/board/juno/cert_create_tbbr.mk +++ b/plat/arm/board/juno/cert_create_tbbr.mk
@@ -7,7 +7,7 @@ PLAT_DEF_OID := 1 ifeq (${PLAT_DEF_OID},1) - ifeq (${ARM_ETHOSN_NPU_DRIVER},1) + ifeq (${ETHOSN_NPU_DRIVER},1) $(eval $(call add_define, PLAT_DEF_OID)) $(eval $(call add_define, PDEF_CERTS)) $(eval $(call add_define, PDEF_EXTS))
diff --git a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts index 986299e..ec72160 100644 --- a/plat/arm/board/juno/fdts/juno_tb_fw_config.dts +++ b/plat/arm/board/juno/fdts/juno_tb_fw_config.dts
@@ -51,10 +51,10 @@ tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d"; nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7"; plat_sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f"; -#if ARM_ETHOSN_NPU_TZMP1 - arm_ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1"; - arm_ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2"; - arm_ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed"; +#if ETHOSN_NPU_TZMP1 + ethosn_npu_fw_uuid = "cfd499b5-a3bc-4a7e-98cb-48a41cb8dae1"; + ethosn_npu_fw_key_cert_uuid = "5666d004-ab98-40aa-8988-b72a03a256e2"; + ethosn_npu_fw_content_cert_uuid = "a5c418da-430f-48b1-88cd-93f67889d9ed"; #endif }; };
diff --git a/plat/arm/board/juno/fip/plat_def_fip_uuid.h b/plat/arm/board/juno/fip/plat_def_fip_uuid.h index 0f0d11d..46adf24 100644 --- a/plat/arm/board/juno/fip/plat_def_fip_uuid.h +++ b/plat/arm/board/juno/fip/plat_def_fip_uuid.h
@@ -7,8 +7,8 @@ #ifndef PLAT_DEF_FIP_UUID_H #define PLAT_DEF_FIP_UUID_H -#ifdef ARM_ETHOSN_NPU_TZMP1 +#ifdef ETHOSN_NPU_TZMP1 #include <drivers/arm/ethosn_fip.h> -#endif +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* PLAT_DEF_FIP_UUID_H */
diff --git a/plat/arm/board/juno/fip/plat_def_uuid_config.c b/plat/arm/board/juno/fip/plat_def_uuid_config.c index 8133927..705a8ca 100644 --- a/plat/arm/board/juno/fip/plat_def_uuid_config.c +++ b/plat/arm/board/juno/fip/plat_def_uuid_config.c
@@ -12,11 +12,11 @@ #include "plat_def_fip_uuid.h" toc_entry_t plat_def_toc_entries[] = { -#ifdef ARM_ETHOSN_NPU_TZMP1 +#ifdef ETHOSN_NPU_TZMP1 ETHOSN_FW_KEY_CERTIFICATE_DEF, ETHOSN_FW_CONTENT_CERTIFICATE_DEF, ETHOSN_FW_DEF, -#endif +#endif /* ETHOSN_NPU_TZMP1 */ { .name = NULL, .uuid = { { 0 } },
diff --git a/plat/arm/board/juno/include/plat_tbbr_img_def.h b/plat/arm/board/juno/include/plat_tbbr_img_def.h index 3e17ed3..5fbeb4e 100644 --- a/plat/arm/board/juno/include/plat_tbbr_img_def.h +++ b/plat/arm/board/juno/include/plat_tbbr_img_def.h
@@ -7,12 +7,12 @@ #ifndef JUNO_IMG_DEF_H #define JUNO_IMG_DEF_H -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 /* Arm(R) Ethos(TM)-N NPU images */ -#define ARM_ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1) -#define ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2) -#define ARM_ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3) +#define ETHOSN_NPU_FW_KEY_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 1) +#define ETHOSN_NPU_FW_CONTENT_CERT_ID U(MAX_IMG_IDS_WITH_SPMDS + 2) +#define ETHOSN_NPU_FW_IMAGE_ID U(MAX_IMG_IDS_WITH_SPMDS + 3) #define MAX_NUMBER_IDS U(MAX_IMG_IDS_WITH_SPMDS + 4) -#endif +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* JUNO_IMG_DEF_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 47258cb..5c9a7a3 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h
@@ -32,9 +32,6 @@ #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ JUNO_CLUSTER1_CORE_COUNT) -/* Cryptocell HW Base address */ -#define PLAT_CRYPTOCELL_BASE UL(0x60050000) - /* * Other platform porting definitions are provided by included headers */ @@ -327,15 +324,15 @@ /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */ #ifdef JUNO_ETHOSN_TZMP1 -#define ARM_ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT -#define ARM_ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT -#define ARM_ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT +#define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT +#define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT +#define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT -#define ARM_ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS -#define ARM_ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS +#define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS +#define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS -#define ARM_ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE -#define ARM_ETHOSN_NPU_FW_IMAGE_LIMIT \ +#define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE +#define ETHOSN_NPU_FW_IMAGE_LIMIT \ (JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE) #endif
diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i index 8932aa0..327a345 100644 --- a/plat/arm/board/juno/jmptbl.i +++ b/plat/arm/board/juno/jmptbl.i
@@ -41,6 +41,7 @@ mbedtls mbedtls_asn1_get_bitstring_null mbedtls mbedtls_asn1_get_bool mbedtls mbedtls_asn1_get_int +mbedtls mbedtls_asn1_get_len mbedtls mbedtls_asn1_get_tag mbedtls mbedtls_free mbedtls mbedtls_md
diff --git a/plat/arm/board/juno/juno_tbbr_cot_bl2.c b/plat/arm/board/juno/juno_tbbr_cot_bl2.c index d48d2e6..8930dbb 100644 --- a/plat/arm/board/juno/juno_tbbr_cot_bl2.c +++ b/plat/arm/board/juno/juno_tbbr_cot_bl2.c
@@ -32,9 +32,9 @@ #if defined(SPD_spmd) static unsigned char sp_pkg_hash_buf[MAX_SP_IDS][HASH_DER_LEN]; #endif /* SPD_spmd */ -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 static unsigned char npu_fw_image_hash_buf[HASH_DER_LEN]; -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#endif /* ETHOSN_NPU_TZMP1 */ static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( @@ -87,12 +87,12 @@ static auth_param_type_desc_t sp_pkg8_hash = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_HASH, SP_PKG8_HASH_OID); #endif /* SPD_spmd */ -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 static auth_param_type_desc_t npu_fw_cert_pk = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_PUB_KEY, ETHOSN_NPU_FW_CONTENT_CERT_PK_OID); static auth_param_type_desc_t npu_fw_image_hash = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_HASH, ETHOSN_NPU_FW_BINARY_OID); -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#endif /* ETHOSN_NPU_TZMP1 */ /* * Trusted key certificate @@ -662,9 +662,9 @@ DEFINE_SIP_SP_PKG(8); #endif /* SPD_spmd */ -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 static const auth_img_desc_t npu_fw_key_cert = { - .img_id = ARM_ETHOSN_NPU_FW_KEY_CERT_ID, + .img_id = ETHOSN_NPU_FW_KEY_CERT_ID, .img_type = IMG_CERT, .parent = &trusted_key_cert, .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { @@ -697,7 +697,7 @@ }; static const auth_img_desc_t npu_fw_content_cert = { - .img_id = ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, + .img_id = ETHOSN_NPU_FW_CONTENT_CERT_ID, .img_type = IMG_CERT, .parent = &npu_fw_key_cert, .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { @@ -730,7 +730,7 @@ }; static const auth_img_desc_t npu_fw_image = { - .img_id = ARM_ETHOSN_NPU_FW_IMAGE_ID, + .img_id = ETHOSN_NPU_FW_IMAGE_ID, .img_type = IMG_RAW, .parent = &npu_fw_content_cert, .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) { @@ -743,7 +743,7 @@ } } }; -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#endif /* ETHOSN_NPU_TZMP1 */ static const auth_img_desc_t * const cot_desc[] = { @@ -778,11 +778,11 @@ [SP_PKG7_ID] = &sp_pkg7, [SP_PKG8_ID] = &sp_pkg8, #endif -#if ARM_ETHOSN_NPU_TZMP1 - [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert, - [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert, - [ARM_ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_KEY_CERT_ID] = &npu_fw_key_cert, + [ETHOSN_NPU_FW_CONTENT_CERT_ID] = &npu_fw_content_cert, + [ETHOSN_NPU_FW_IMAGE_ID] = &npu_fw_image, +#endif /* ETHOSN_NPU_TZMP1 */ }; /* Register the CoT in the authentication module */
diff --git a/plat/arm/board/juno/juno_trusted_boot.c b/plat/arm/board/juno/juno_trusted_boot.c index 25a7470..c730406 100644 --- a/plat/arm/board/juno/juno_trusted_boot.c +++ b/plat/arm/board/juno/juno_trusted_boot.c
@@ -8,7 +8,6 @@ #include <stdint.h> #include <string.h> -#include <drivers/arm/cryptocell/cc_rotpk.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/common_def.h> #include <plat/common/platform.h> @@ -109,10 +108,6 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, unsigned int *flags) { -#if ARM_CRYPTOCELL_INTEG - return arm_get_rotpk_info_cc(key_ptr, key_len, flags); -#else - #if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) return arm_get_rotpk_info_dev(key_ptr, key_len, flags); @@ -121,6 +116,4 @@ #else return 1; #endif - -#endif /* ARM_CRYPTOCELL_INTEG */ }
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk index a4e6407..a00bf26 100644 --- a/plat/arm/board/juno/platform.mk +++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2023, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -43,8 +43,8 @@ JUNO_TZMP1 := 0 $(eval $(call assert_boolean,JUNO_TZMP1)) ifeq (${JUNO_TZMP1}, 1) - ifeq (${ARM_ETHOSN_NPU_TZMP1},1) - $(error JUNO_TZMP1 cannot be used together with ARM_ETHOSN_NPU_TZMP1) + ifeq (${ETHOSN_NPU_TZMP1},1) + $(error JUNO_TZMP1 cannot be used together with ETHOSN_NPU_TZMP1) else $(eval $(call add_define,JUNO_TZMP1)) endif @@ -63,6 +63,10 @@ ifneq (${ARCH}, aarch32) override BL32_SOURCES = endif +else + ifeq (${ARCH}, aarch32) + $(error JUNO_AARCH32_EL3_RUNTIME has to be enabled to build BL32 for AArch32) + endif endif ifeq (${ARCH},aarch64) @@ -207,6 +211,7 @@ # Add the HW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) +include drivers/arm/ethosn/ethosn_npu.mk include plat/arm/board/common/board_common.mk include plat/arm/common/arm_common.mk include plat/arm/soc/common/soc_css.mk
diff --git a/plat/arm/board/morello/fdts/morello_nt_fw_config.dts b/plat/arm/board/morello/fdts/morello_nt_fw_config.dts index e730d34..6ec282d 100644 --- a/plat/arm/board/morello/fdts/morello_nt_fw_config.dts +++ b/plat/arm/board/morello/fdts/morello_nt_fw_config.dts
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, Arm Limited. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,4 +23,19 @@ scc-config = <0x0>; #endif }; + + /* + * Placeholder for firmware-version node with default values. + * The value will be set to the correct values during + * the BL2 stage of boot. + */ + firmware-version { +#ifdef TARGET_PLATFORM_SOC + mcc-fw-version = <0x0>; + pcc-fw-version = <0x0>; +#endif + scp-fw-version = <0x0>; + scp-fw-commit = <0x0>; + tfa-fw-version = "unknown-dirty_00000000"; + }; };
diff --git a/plat/arm/board/morello/include/platform_def.h b/plat/arm/board/morello/include/platform_def.h index 76e63aa..993aa46 100644 --- a/plat/arm/board/morello/include/platform_def.h +++ b/plat/arm/board/morello/include/platform_def.h
@@ -163,7 +163,59 @@ #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE #define PLAT_MAX_PWR_LVL U(2) -#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) +/* Interrupt handling constants */ +#define MORELLO_IRQ_SEC_UART U(87) +#define MORELLO_IRQ_DISPLAY_TCU_EVENT_Q U(107) +#define MORELLO_IRQ_DISPLAY_TCU_CMD_SYNC U(111) +#define MORELLO_IRQ_DISPLAY_TCU_GLOBAL U(113) +#define MORELLO_IRQ_MMU_TCU1_EVENT_Q U(257) +#define MORELLO_IRQ_MMU_TCU1_CMD_SYNC U(258) +#define MORELLO_IRQ_MMU_TCU1_GLOBAL U(259) +#define MORELLO_IRQ_MMU_TCU2_EVENT_Q U(264) +#define MORELLO_IRQ_MMU_TCU2_CMD_SYNC U(265) +#define MORELLO_IRQ_MMU_TCU2_GLOBAL U(266) +#define MORELLO_IRQ_CLUSTER0_MHU U(349) +#define MORELLO_IRQ_CLUSTER1_MHU U(351) +#define MORELLO_IRQ_P0_REFCLK U(412) +#define MORELLO_IRQ_P1_REFCLK U(413) + +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(CSS_IRQ_MHU, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_SEC_UART, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_EVENT_Q, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_CMD_SYNC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_GLOBAL, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_EVENT_Q, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_CMD_SYNC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_GLOBAL, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_EVENT_Q, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_CMD_SYNC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_GLOBAL, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_CLUSTER0_MHU, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_CLUSTER1_MHU, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_P0_REFCLK, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MORELLO_IRQ_P1_REFCLK, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL) + #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) #define MORELLO_DEVICE_BASE ULL(0x08000000)
diff --git a/plat/arm/board/morello/morello_def.h b/plat/arm/board/morello/morello_def.h index e42a03c..25122e6 100644 --- a/plat/arm/board/morello/morello_def.h +++ b/plat/arm/board/morello/morello_def.h
@@ -15,6 +15,15 @@ MORELLO_NS_SRAM_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE) +/* SDS Firmware version defines */ +#define MORELLO_SDS_FIRMWARE_VERSION_STRUCT_ID U(2) +#define MORELLO_SDS_FIRMWARE_VERSION_OFFSET U(0) +#ifdef TARGET_PLATFORM_FVP +# define MORELLO_SDS_FIRMWARE_VERSION_SIZE U(8) +#else +# define MORELLO_SDS_FIRMWARE_VERSION_SIZE U(16) +#endif + /* SDS Platform information defines */ #define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8) #define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0) @@ -122,8 +131,40 @@ } __packed; #endif -/* Compile time assertion to ensure the size of structure is of the required bytes */ +/* SDS Firmware revision struct definition */ +#ifdef TARGET_PLATFORM_FVP +/* + * Firmware revision structure stored in SDS. + * This structure holds information about firmware versions. + * - SCP firmware version + * - SCP firmware commit + */ +struct morello_firmware_version { + uint32_t scp_fw_ver; + uint32_t scp_fw_commit; +} __packed; +#else +/* + * Firmware revision structure stored in SDS. + * This structure holds information about firmware versions. + * - SCP firmware version + * - SCP firmware commit + * - MCC firmware version + * - PCC firmware version + */ +struct morello_firmware_version { + uint32_t scp_fw_ver; + uint32_t scp_fw_commit; + uint32_t mcc_fw_ver; + uint32_t pcc_fw_ver; +} __packed; +#endif + +/* Compile time assertions to ensure the size of structures are of the required bytes */ CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, assert_invalid_plat_info_size); +CASSERT(sizeof(struct morello_firmware_version) == MORELLO_SDS_FIRMWARE_VERSION_SIZE, + assert_invalid_firmware_version_size); + #endif /* MORELLO_DEF_H */
diff --git a/plat/arm/board/morello/morello_image_load.c b/plat/arm/board/morello/morello_image_load.c index b5d9bd5..4ea2bb3 100644 --- a/plat/arm/board/morello/morello_image_load.c +++ b/plat/arm/board/morello/morello_image_load.c
@@ -23,7 +23,8 @@ } /******************************************************************************* - * This function inserts Platform information via device tree nodes as, + * This function inserts Platform information and firmware versions + * via device tree nodes as, * platform-info { * local-ddr-size = <0x0 0x0>; *#ifdef TARGET_PLATFORM_SOC @@ -33,12 +34,22 @@ * scc-config = <0x0>; *#endif * }; + * firmware-version { + *#ifdef TARGET_PLATFORM_SOC + * mcc-fw-version = <0x0>; + * pcc-fw-version = <0x0>; + *#endif + * scp-fw-version = <0x0>; + * scp-fw-commit = <0x0>; + * tfa-fw-version = "unknown-dirty_00000000"; + * }; ******************************************************************************/ -static int plat_morello_append_config_node(struct morello_plat_info *plat_info) +static int plat_morello_append_config_node(struct morello_plat_info *plat_info, + struct morello_firmware_version *fw_version) { bl_mem_params_node_t *mem_params; void *fdt; - int nodeoffset, err; + int nodeoffset_plat, nodeoffset_fw, err; uint64_t usable_mem_size; usable_mem_size = plat_info->local_ddr_size; @@ -57,35 +68,41 @@ return -1; } - nodeoffset = fdt_subnode_offset(fdt, 0, "platform-info"); - if (nodeoffset < 0) { + nodeoffset_plat = fdt_subnode_offset(fdt, 0, "platform-info"); + if (nodeoffset_plat < 0) { ERROR("NT_FW_CONFIG: Failed to get platform-info node offset\n"); return -1; } + nodeoffset_fw = fdt_subnode_offset(fdt, 0, "firmware-version"); + if (nodeoffset_fw < 0) { + ERROR("NT_FW_CONFIG: Failed to get firmware-version node offset\n"); + return -1; + } + #ifdef TARGET_PLATFORM_SOC - err = fdt_setprop_u64(fdt, nodeoffset, "remote-ddr-size", + err = fdt_setprop_u64(fdt, nodeoffset_plat, "remote-ddr-size", plat_info->remote_ddr_size); if (err < 0) { ERROR("NT_FW_CONFIG: Failed to set remote-ddr-size\n"); return -1; } - err = fdt_setprop_u32(fdt, nodeoffset, "remote-chip-count", + err = fdt_setprop_u32(fdt, nodeoffset_plat, "remote-chip-count", plat_info->remote_chip_count); if (err < 0) { ERROR("NT_FW_CONFIG: Failed to set remote-chip-count\n"); return -1; } - err = fdt_setprop_u32(fdt, nodeoffset, "multichip-mode", + err = fdt_setprop_u32(fdt, nodeoffset_plat, "multichip-mode", plat_info->multichip_mode); if (err < 0) { ERROR("NT_FW_CONFIG: Failed to set multichip-mode\n"); return -1; } - err = fdt_setprop_u32(fdt, nodeoffset, "scc-config", + err = fdt_setprop_u32(fdt, nodeoffset_plat, "scc-config", plat_info->scc_config); if (err < 0) { ERROR("NT_FW_CONFIG: Failed to set scc-config\n"); @@ -95,8 +112,41 @@ if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) { usable_mem_size = get_mem_client_mode(plat_info->local_ddr_size); } + + err = fdt_setprop_u32(fdt, nodeoffset_fw, "mcc-fw-version", + fw_version->mcc_fw_ver); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set mcc-fw-version\n"); + return -1; + } + + err = fdt_setprop_u32(fdt, nodeoffset_fw, "pcc-fw-version", + fw_version->pcc_fw_ver); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set pcc-fw-version\n"); + return -1; + } #endif - err = fdt_setprop_u64(fdt, nodeoffset, "local-ddr-size", + err = fdt_setprop_u32(fdt, nodeoffset_fw, "scp-fw-version", + fw_version->scp_fw_ver); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set scp-fw-version\n"); + return -1; + } + + err = fdt_setprop_u32(fdt, nodeoffset_fw, "scp-fw-commit", + fw_version->scp_fw_commit); + if (err < 0) { + ERROR("NT_FW_CONFIG: Failed to set scp-fw-commit\n"); + return -1; + } + + err = fdt_setprop_string(fdt, nodeoffset_fw, "tfa-fw-version", version_string); + if (err < 0) { + WARN("NT_FW_CONFIG: Unable to set tfa-fw-version\n"); + } + + err = fdt_setprop_u64(fdt, nodeoffset_plat, "local-ddr-size", usable_mem_size); if (err < 0) { ERROR("NT_FW_CONFIG: Failed to set local-ddr-size\n"); @@ -115,6 +165,7 @@ { int ret; struct morello_plat_info plat_info; + struct morello_firmware_version fw_version; ret = sds_init(); if (ret != SDS_OK) { @@ -132,6 +183,16 @@ panic(); } + ret = sds_struct_read(MORELLO_SDS_FIRMWARE_VERSION_STRUCT_ID, + MORELLO_SDS_FIRMWARE_VERSION_OFFSET, + &fw_version, + MORELLO_SDS_FIRMWARE_VERSION_SIZE, + SDS_ACCESS_MODE_NON_CACHED); + if (ret != SDS_OK) { + ERROR("Error getting firmware version from SDS. ret:%d\n", ret); + panic(); + } + /* Validate plat_info SDS */ #ifdef TARGET_PLATFORM_FVP if (plat_info.local_ddr_size == 0U) { @@ -146,7 +207,7 @@ panic(); } - ret = plat_morello_append_config_node(&plat_info); + ret = plat_morello_append_config_node(&plat_info, &fw_version); if (ret != 0) { panic(); }
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk index 0ae7693..12ffb5a 100644 --- a/plat/arm/board/morello/platform.mk +++ b/plat/arm/board/morello/platform.mk
@@ -89,6 +89,9 @@ override ARM_BL31_IN_DRAM := 1 +override PSCI_EXTENDED_STATE_ID := 1 +override ARM_RECOM_STATE_ID_ENC := 1 + # Errata workarounds: ERRATA_N1_1868343 := 1
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index b3799a7..74d0c91 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, Arm Limited. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -190,11 +190,47 @@ #define PLAT_CSS_MHU_BASE 0x45000000 #define PLAT_MAX_PWR_LVL 2 -#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ - CSS_IRQ_MHU -#define PLAT_ARM_G0_IRQS ARM_G0_IRQS +/* Interrupt handling constants */ +#define N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC U(257) +#define N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC U(258) +#define N1SDP_IRQ_MMU_TCU1_GLOBAL U(259) +#define N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC U(264) +#define N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC U(265) +#define N1SDP_IRQ_MMU_TCU2_GLOBAL U(266) +#define N1SDP_IRQ_CLUSTER0_MHU U(349) +#define N1SDP_IRQ_CLUSTER1_MHU U(351) +#define N1SDP_IRQ_P0_REFCLK U(412) +#define N1SDP_IRQ_P1_REFCLK U(413) -#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) +#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ + ARM_G1S_IRQ_PROPS(grp), \ + INTR_PROP_DESC(CSS_IRQ_MHU, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_EVENT_Q_SEC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_CMD_SYNC_SEC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU1_GLOBAL, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_EVENT_Q_SEC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_CMD_SYNC_SEC, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_MMU_TCU2_GLOBAL, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_CLUSTER0_MHU, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_CLUSTER1_MHU, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_P0_REFCLK, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(N1SDP_IRQ_P1_REFCLK, \ + GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL) + #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index 2b9ed25..430aab6 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c
@@ -52,8 +52,8 @@ PLAT_ARM_GICD_BASE >> 16 }, .spi_ids = { - {PLAT_ARM_GICD_BASE, 32, 479}, - {PLAT_ARM_GICD_BASE, 512, 959} + {PLAT_ARM_GICD_BASE, 32, 511}, + {PLAT_ARM_GICD_BASE, 512, 991} } };
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk index bd62614..f937ee7 100644 --- a/plat/arm/board/n1sdp/platform.mk +++ b/plat/arm/board/n1sdp/platform.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2022, Arm Limited. All rights reserved. +# Copyright (c) 2018-2023, Arm Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -14,6 +14,10 @@ N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S +# Neoverse N1 cores support Armv8.2 extensions +ARM_ARCH_MAJOR := 8 +ARM_ARCH_MINOR := 2 + # GIC-600 configuration GICV3_SUPPORT_GIC600 := 1 GICV3_IMPL_GIC600_MULTICHIP := 1
diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h index 8e63de5..2391b72 100644 --- a/plat/arm/board/rdn2/include/platform_def.h +++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -8,7 +8,7 @@ #define PLATFORM_DEF_H #include <lib/utils_def.h> - +#include <sgi_sdei.h> #include <sgi_soc_platform_def_v2.h> #if (CSS_SGI_PLATFORM_VARIANT == 1) @@ -102,4 +102,25 @@ #define PLAT_REBOOT_PRI GIC_HIGHEST_SEC_PRIORITY #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_REBOOT_PRI) +/* + * Number of Secure Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * secure partitions. + */ +#define SECURE_PARTITION_COUNT 1 + +/* + * Number of NWd Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * nwld partitions. + */ +#define NS_PARTITION_COUNT 1 + +/* + * Number of Logical Partitions supported. + * SPMC at EL3, uses this count to configure the maximum number of supported + * logical partitions. + */ +#define MAX_EL3_LP_DESCS_COUNT 1 + #endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn2/include/rdn2_ras.h b/plat/arm/board/rdn2/include/rdn2_ras.h new file mode 100644 index 0000000..1d9af60 --- /dev/null +++ b/plat/arm/board/rdn2/include/rdn2_ras.h
@@ -0,0 +1,14 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RDN2_RAS_H +#define RDN2_RAS_H + +#include <sgi_ras.h> + +extern struct plat_sgi_ras_config ras_config; + +#endif /* RDN2_RAS_H */
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk index ca55036..ef8f3d4 100644 --- a/plat/arm/board/rdn2/platform.mk +++ b/plat/arm/board/rdn2/platform.mk
@@ -69,6 +69,13 @@ BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC endif +ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1) +BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \ + ${CSS_ENT_BASE}/ras/sgi_ras_common.c \ + ${CSS_ENT_BASE}/ras/sgi_ras_sram.c \ + ${CSS_ENT_BASE}/ras/sgi_ras_cpu.c +endif + # Add the FDT_SOURCES and options for Dynamic Config FDT_SOURCES += ${RDN2_BASE}/fdts/${PLAT}_fw_config.dts \ ${RDN2_BASE}/fdts/${PLAT}_tb_fw_config.dts
diff --git a/plat/arm/board/rdn2/rdn2_plat.c b/plat/arm/board/rdn2/rdn2_plat.c index a5564ce..2a6c658 100644 --- a/plat/arm/board/rdn2/rdn2_plat.c +++ b/plat/arm/board/rdn2/rdn2_plat.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,8 @@ #include <drivers/arm/gic600_multichip.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> +#include <services/el3_spmc_ffa_memory.h> +#include <rdn2_ras.h> #include <sgi_soc_platform_def_v2.h> #include <sgi_plat.h> @@ -134,5 +136,47 @@ #endif sgi_bl31_common_platform_setup(); + +#if ENABLE_FEAT_RAS && FFH_SUPPORT + sgi_ras_platform_setup(&ras_config); +#endif } #endif /* IMAGE_BL31 */ + +#if SPMC_AT_EL3 + +#define DATASTORE_SIZE 1024 + +__section("arm_el3_tzc_dram") uint8_t plat_spmc_shmem_datastore[DATASTORE_SIZE]; + +int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) +{ + *datastore = plat_spmc_shmem_datastore; + *size = DATASTORE_SIZE; + return 0; +} + +/* + * Add dummy implementations of memory management related platform hooks. + * Memory share/lend operation are not required on RdN2 platform. + */ +int plat_spmc_shmem_begin(struct ffa_mtd *desc) +{ + return 0; +} + +int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) +{ + return 0; +} + +int plat_spmd_handle_group0_interrupt(uint32_t intid) +{ + /* + * As of now, there are no sources of Group0 secure interrupt enabled + * for RDN2. + */ + (void)intid; + return -1; +} +#endif
diff --git a/plat/arm/board/rdn2/rdn2_ras.c b/plat/arm/board/rdn2/rdn2_ras.c new file mode 100644 index 0000000..3aed58e --- /dev/null +++ b/plat/arm/board/rdn2/rdn2_ras.c
@@ -0,0 +1,53 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> +#include <sgi_ras.h> +#include <sgi_sdei.h> + +struct sgi_ras_ev_map plat_ras_map[] = { + /* Non Secure base RAM ECC CE interrupt */ + {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI}, + + /* Non Secure base RAM ECC UE interrupt */ + {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI}, + + /* CPU 1-bit ECC CE error interrupt */ + {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI} +}; + +/* RAS error record list definition, used by the common RAS framework. */ +struct err_record_info plat_err_records[] = { + /* Base element RAM Non-secure error record. */ + ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL, + &sgi_ras_sram_intr_handler, 0), + ERR_RECORD_SYSREG_V1(0, 1, NULL, &sgi_ras_cpu_intr_handler, 0), +}; + +/* RAS error interrupt list definition, used by the common RAS framework. */ +struct ras_interrupt plat_ras_interrupts[] = { + { + .intr_number = PLAT_CORE_FAULT_IRQ, + .err_record = &plat_err_records[1], + }, { + .intr_number = NS_RAM_ECC_CE_INT, + .err_record = &plat_err_records[0], + }, { + .intr_number = NS_RAM_ECC_UE_INT, + .err_record = &plat_err_records[0], + }, +}; + +/* Registers the RAS error record list with common RAS framework. */ +REGISTER_ERR_RECORD_INFO(plat_err_records); +/* Registers the RAS error interrupt info list with common RAS framework. */ +REGISTER_RAS_INTERRUPTS(plat_ras_interrupts); + +/* Platform RAS handling config data definition */ +struct plat_sgi_ras_config ras_config = { + plat_ras_map, + ARRAY_SIZE(plat_ras_map) +};
diff --git a/plat/arm/board/rdn2/rdn2_security.c b/plat/arm/board/rdn2/rdn2_security.c index dff6a19..7cd4a1c 100644 --- a/plat/arm/board/rdn2/rdn2_security.c +++ b/plat/arm/board/rdn2/rdn2_security.c
@@ -8,8 +8,16 @@ #include <plat/arm/common/plat_arm.h> #include <platform_def.h> +#define RDN2_TZC_CPER_REGION \ + {CSS_SGI_SP_CPER_BUF_BASE, (CSS_SGI_SP_CPER_BUF_BASE + \ + CSS_SGI_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} + static const arm_tzc_regions_info_t tzc_regions[] = { ARM_TZC_REGIONS_DEF, +#if ENABLE_FEAT_RAS && FFH_SUPPORT + RDN2_TZC_CPER_REGION, +#endif {} };
diff --git a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts index 92e2ddd..382f0e1 100644 --- a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts +++ b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021, Arm Limited. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,7 +8,7 @@ / { compatible = "arm,ffa-core-manifest-1.0"; #address-cells = <2>; - #size-cells = <1>; + #size-cells = <2>; attribute { spmc_id = <0x8000>; @@ -116,9 +116,14 @@ }; }; - /* 32MB of TC_TZC_DRAM1_BASE */ - memory@fd000000 { + memory@0 { device_type = "memory"; - reg = <0x0 0xfd000000 0x2000000>; + reg = <0x0 0xfd000000 0x0 0x2000000>; + }; + + memory@1 { + device_type = "ns-memory"; + reg = <0x0 0x80000000 0x0 0x79000000>, + <0x80 0x80000000 0x1 0x80000000>; }; };
diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h index 117fbb4..a6b2b0d 100644 --- a/plat/arm/board/tc/include/tc_plat.h +++ b/plat/arm/board/tc/include/tc_plat.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,10 @@ #ifndef TC_PLAT_H #define TC_PLAT_H +#ifdef PLATFORM_TEST_ROTPK +#include <rss_crypto_defs.h> +#endif + void tc_bl31_common_platform_setup(void); #ifdef PLATFORM_TEST_TFM_TESTSUITE @@ -17,4 +21,13 @@ int nv_counter_test(void); #endif +#ifdef PLATFORM_TEST_ROTPK +struct key_id_info { + enum rss_key_id_builtin_t key_id; + const char *key_id_name; +}; + +int rotpk_test(void); +#endif + #endif /* TC_PLAT_H */
diff --git a/plat/arm/board/tc/nv_counter_test.c b/plat/arm/board/tc/nv_counter_test.c index f9e001e..179ec4b 100644 --- a/plat/arm/board/tc/nv_counter_test.c +++ b/plat/arm/board/tc/nv_counter_test.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2023, ARM Limited. All rights reserved. + * Copyright (c) 2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,29 +22,29 @@ status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE); if (status != PSA_SUCCESS) { - printf("Failed to initialize RSS communication channel\n"); + printf("Failed to initialize RSS communication channel - psa_status = %d\n", status); return -1; } for (id = 0; id < 3; id++) { status = rss_platform_nv_counter_read(id, sizeof(old_val), (uint8_t *)&old_val); if (status != PSA_SUCCESS) { - printf("Failed during first id=(%d) rss_platform_nv_counter_read\n", - id); + printf("Failed during first id=(%d) rss_platform_nv_counter_read - psa_status = %d\n", + id, status); return -1; } status = rss_platform_nv_counter_increment(id); if (status != PSA_SUCCESS) { - printf("Failed during id=(%d) rss_platform_nv_counter_increment\n", - id); + printf("Failed during id=(%d) rss_platform_nv_counter_increment - psa_status = %d\n", + id, status); return -1; } status = rss_platform_nv_counter_read(id, sizeof(new_val), (uint8_t *)&new_val); if (status != PSA_SUCCESS) { - printf("Failed during second id=(%d) rss_platform_nv_counter_read\n", - id); + printf("Failed during second id=(%d) rss_platform_nv_counter_read - psa_status = %d\n", + id, status); return -1; }
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk index c29537c..6874cfa 100644 --- a/plat/arm/board/tc/platform.mk +++ b/plat/arm/board/tc/platform.mk
@@ -6,8 +6,12 @@ include common/fdt_wrappers.mk ifeq ($(TARGET_PLATFORM), 0) -$(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \ -Some of the features might not work as expected) + $(error Platform ${PLAT}$(TARGET_PLATFORM) is deprecated.) +endif + +ifeq ($(TARGET_PLATFORM), 1) + $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \ + Some of the features might not work as expected) endif ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0) @@ -22,8 +26,6 @@ ENABLE_FEAT_RAS := 1 -RAS_FFH_SUPPORT := 0 - SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 @@ -70,13 +72,6 @@ PLAT_INCLUDES += -I${TC_BASE}/include/ -# CPU libraries for TARGET_PLATFORM=0 -ifeq (${TARGET_PLATFORM}, 0) -TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ - lib/cpus/aarch64/cortex_a710.S \ - lib/cpus/aarch64/cortex_x2.S -endif - # CPU libraries for TARGET_PLATFORM=1 ifeq (${TARGET_PLATFORM}, 1) TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \ @@ -86,9 +81,9 @@ # CPU libraries for TARGET_PLATFORM=2 ifeq (${TARGET_PLATFORM}, 2) -TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \ - lib/cpus/aarch64/cortex_hunter.S \ - lib/cpus/aarch64/cortex_hunter_elp_arm.S +TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a520.S \ + lib/cpus/aarch64/cortex_a720.S \ + lib/cpus/aarch64/cortex_x4.S endif INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c @@ -197,31 +192,11 @@ endif ifneq (${PLATFORM_TEST},) - $(eval $(call add_define,PLATFORM_TESTS)) - - ifeq (${PLATFORM_TEST},rss-nv-counters) - include drivers/arm/rss/rss_comms.mk - - # Test code. - BL31_SOURCES += plat/arm/board/tc/nv_counter_test.c - - # Code under testing. - BL31_SOURCES += lib/psa/rss_platform.c \ - drivers/arm/rss/rss_comms.c \ - ${RSS_COMMS_SOURCES} - - PLAT_INCLUDES += -Iinclude/lib/psa - - $(eval $(call add_define,PLATFORM_TEST_NV_COUNTERS)) - else ifeq (${PLATFORM_TEST},tfm-testsuite) - # Add this include as first, before arm_common.mk. This is necessary - # because arm_common.mk builds Mbed TLS, and platform_test.mk can - # change the list of Mbed TLS files that are to be compiled - # (LIBMBEDTLS_SRCS). - include plat/arm/board/tc/platform_test.mk - else - $(error "Unsupported PLATFORM_TEST value") - endif + # Add this include as first, before arm_common.mk. This is necessary + # because arm_common.mk builds Mbed TLS, and platform_test.mk can + # change the list of Mbed TLS files that are to be compiled + # (LIBMBEDTLS_SRCS). + include plat/arm/board/tc/platform_test.mk endif
diff --git a/plat/arm/board/tc/platform_test.mk b/plat/arm/board/tc/platform_test.mk index e974855..2fd5ea0 100644 --- a/plat/arm/board/tc/platform_test.mk +++ b/plat/arm/board/tc/platform_test.mk
@@ -3,7 +3,37 @@ # SPDX-License-Identifier: BSD-3-Clause # -ifeq (${PLATFORM_TEST},tfm-testsuite) +$(eval $(call add_define,PLATFORM_TESTS)) + +ifeq (${PLATFORM_TEST},rss-nv-counters) + include drivers/arm/rss/rss_comms.mk + + # Test code. + BL31_SOURCES += plat/arm/board/tc/nv_counter_test.c + + # Code under testing. + BL31_SOURCES += lib/psa/rss_platform.c \ + drivers/arm/rss/rss_comms.c \ + ${RSS_COMMS_SOURCES} + + PLAT_INCLUDES += -Iinclude/lib/psa + + $(eval $(call add_define,PLATFORM_TEST_NV_COUNTERS)) +else ifeq (${PLATFORM_TEST},rss-rotpk) + include drivers/arm/rss/rss_comms.mk + + # Test code. + BL31_SOURCES += plat/arm/board/tc/rotpk_test.c + + # Code under testing. + BL31_SOURCES += lib/psa/rss_platform.c \ + drivers/arm/rss/rss_comms.c \ + ${RSS_COMMS_SOURCES} + + PLAT_INCLUDES += -Iinclude/lib/psa + + $(eval $(call add_define,PLATFORM_TEST_ROTPK)) +else ifeq (${PLATFORM_TEST},tfm-testsuite) # The variables need to be set to compile the platform test: ifeq (${TF_M_TESTS_PATH},) @@ -77,4 +107,6 @@ $(eval $(call add_define,DELEG_ATTEST_DUMP_TOKEN_AND_KEY)) $(eval $(call add_define,PLATFORM_TEST_TFM_TESTSUITE)) +else + $(error "Unsupported PLATFORM_TEST value") endif
diff --git a/plat/arm/board/tc/region_defs.h b/plat/arm/board/tc/region_defs.h index d3dfd13..50ec2f1 100644 --- a/plat/arm/board/tc/region_defs.h +++ b/plat/arm/board/tc/region_defs.h
@@ -7,6 +7,6 @@ #ifndef REGION_DEFS_H #define REGION_DEFS_H -#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x800 +#define PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE 0x800 #endif /* REGION_DEFS_H */
diff --git a/plat/arm/board/tc/rotpk_test.c b/plat/arm/board/tc/rotpk_test.c new file mode 100644 index 0000000..ed56c31 --- /dev/null +++ b/plat/arm/board/tc/rotpk_test.c
@@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> +#include <stdio.h> + +#include <drivers/arm/rss_comms.h> +#include <plat/common/platform.h> +#include <rss_platform_api.h> +#include <tc_plat.h> + +static void print_hex(const char *key_id_name, size_t key_size, const uint8_t *key_buf) +{ + printf("%s = ", key_id_name); + for (int i = 0; i < key_size; i++) { + printf("%02x", key_buf[i]); + } + printf("\n\n"); +} + +int rotpk_test(void) +{ + psa_status_t status; + uint8_t key_buf[128]; + size_t key_size; + + struct key_id_info key_ids[3] = { + {.key_id = RSS_BUILTIN_KEY_ID_HOST_S_ROTPK, .key_id_name = "Secure-ROTPK"}, + {.key_id = RSS_BUILTIN_KEY_ID_HOST_NS_ROTPK, .key_id_name = "NS-ROTPK"}, + {.key_id = RSS_BUILTIN_KEY_ID_HOST_CCA_ROTPK, .key_id_name = "CCA-ROTPK"} + }; + + status = rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE); + if (status != PSA_SUCCESS) { + printf("Failed to initialize RSS communication channel - psa_status = %d\n", status); + return -1; + } + + for (int i = 0; i < ARRAY_SIZE(key_ids); i++) { + status = rss_platform_key_read(key_ids[i].key_id, key_buf, + sizeof(key_buf), &key_size); + if (status != PSA_SUCCESS) { + printf("Failed to retrieve %s - psa_status = %d\n", key_ids[i].key_id_name, status); + return -1; + } + print_hex(key_ids[i].key_id_name, key_size, key_buf); + } + + printf("Passed rotpk_test\n"); + + return 0; +}
diff --git a/plat/arm/board/tc/rss_ap_tests.c b/plat/arm/board/tc/rss_ap_tests.c index 8c40271..ea90ac3 100644 --- a/plat/arm/board/tc/rss_ap_tests.c +++ b/plat/arm/board/tc/rss_ap_tests.c
@@ -56,7 +56,7 @@ return 0; } -void run_platform_tests(void) +int run_platform_tests(void) { size_t i; int ret;
diff --git a/plat/arm/board/tc/tc_bl1_measured_boot.c b/plat/arm/board/tc/tc_bl1_measured_boot.c index 0d29c51..6821a6a 100644 --- a/plat/arm/board/tc/tc_bl1_measured_boot.c +++ b/plat/arm/board/tc/tc_bl1_measured_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <drivers/arm/rss_comms.h> #include <drivers/measured_boot/rss/rss_measured_boot.h> #include <lib/psa/measured_boot.h> +#include <tools_share/zero_oid.h> #include <plat/arm/common/plat_arm.h> #include <platform_def.h> @@ -22,18 +23,21 @@ .slot = U(6), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_FW_CONFIG_STRING, + .pk_oid = ZERO_OID, .lock_measurement = true }, { .id = TB_FW_CONFIG_ID, .slot = U(7), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_TB_FW_CONFIG_STRING, + .pk_oid = ZERO_OID, .lock_measurement = true }, { .id = BL2_IMAGE_ID, .slot = U(8), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_BL2_STRING, + .pk_oid = ZERO_OID, .lock_measurement = true }, { @@ -46,7 +50,7 @@ (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE); - rss_measured_boot_init(); + rss_measured_boot_init(tc_rss_mboot_metadata); } void bl1_plat_mboot_finish(void)
diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c index 7ea2c2e..4b79170 100644 --- a/plat/arm/board/tc/tc_bl2_measured_boot.c +++ b/plat/arm/board/tc/tc_bl2_measured_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include <drivers/arm/rss_comms.h> #include <drivers/measured_boot/rss/rss_measured_boot.h> #include <lib/psa/measured_boot.h> +#include <tools_share/tbbr_oid.h> #include <plat/common/common_def.h> #include <platform_def.h> @@ -22,18 +23,21 @@ .slot = U(9), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_BL31_STRING, + .pk_oid = BL31_IMAGE_KEY_OID, .lock_measurement = true }, { .id = HW_CONFIG_ID, .slot = U(10), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_HW_CONFIG_STRING, + .pk_oid = HW_CONFIG_KEY_OID, .lock_measurement = true }, { .id = SOC_FW_CONFIG_ID, .slot = U(11), .signer_id_size = SIGNER_ID_MIN_SIZE, .sw_type = RSS_MBOOT_SOC_FW_CONFIG_STRING, + .pk_oid = SOC_FW_CONFIG_KEY_OID, .lock_measurement = true }, { .id = RSS_MBOOT_INVALID_ID } @@ -45,7 +49,7 @@ (void)rss_comms_init(PLAT_RSS_AP_SND_MHU_BASE, PLAT_RSS_AP_RCV_MHU_BASE); - rss_measured_boot_init(); + rss_measured_boot_init(tc_rss_mboot_metadata); } void bl2_plat_mboot_finish(void)
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c index ca3a032..ff7809d 100644 --- a/plat/arm/board/tc/tc_bl31_setup.c +++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -59,6 +59,8 @@ #ifdef PLATFORM_TEST_NV_COUNTERS tests_failed = nv_counter_test(); +#elif PLATFORM_TEST_ROTPK + tests_failed = rotpk_test(); #elif PLATFORM_TEST_TFM_TESTSUITE tests_failed = run_platform_tests(); #endif @@ -120,12 +122,9 @@ { /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ if (intid == SBSA_SECURE_WDOG_INTID) { - INFO("Watchdog restarted\n"); /* Refresh the timer. */ plat_arm_secure_wdt_refresh(); - /* Deactivate the corresponding interrupt. */ - plat_ic_end_of_interrupt(intid); return 0; }
diff --git a/plat/arm/board/tc/tc_common_measured_boot.c b/plat/arm/board/tc/tc_common_measured_boot.c index fe71899..925a411 100644 --- a/plat/arm/board/tc/tc_common_measured_boot.c +++ b/plat/arm/board/tc/tc_common_measured_boot.c
@@ -1,6 +1,5 @@ - /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,17 +12,13 @@ extern struct rss_mboot_metadata tc_rss_mboot_metadata[]; -struct rss_mboot_metadata *plat_rss_mboot_get_metadata(void) -{ - return tc_rss_mboot_metadata; -} - int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data) { int err; /* Calculate image hash and record data in RSS */ - err = rss_mboot_measure_and_record(image_data->image_base, + err = rss_mboot_measure_and_record(tc_rss_mboot_metadata, + image_data->image_base, image_data->image_size, image_id); if (err != 0) { @@ -33,3 +28,9 @@ return err; } + +int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len) +{ + return rss_mboot_set_signer_id(tc_rss_mboot_metadata, pk_oid, pk_ptr, + pk_len); +}
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c index e512192..9a65e7c 100644 --- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -223,17 +223,17 @@ }, #endif /* EL3_PAYLOAD_BASE */ -# if ARM_ETHOSN_NPU_TZMP1 +# if ETHOSN_NPU_TZMP1 { - .image_id = ARM_ETHOSN_NPU_FW_IMAGE_ID, + .image_id = ETHOSN_NPU_FW_IMAGE_ID, SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, VERSION_2, image_info_t, 0), - .image_info.image_base = ARM_ETHOSN_NPU_FW_IMAGE_BASE, - .image_info.image_max_size = ARM_ETHOSN_NPU_FW_IMAGE_LIMIT - - ARM_ETHOSN_NPU_FW_IMAGE_BASE, + .image_info.image_base = ETHOSN_NPU_FW_IMAGE_BASE, + .image_info.image_max_size = ETHOSN_NPU_FW_IMAGE_LIMIT - + ETHOSN_NPU_FW_IMAGE_BASE, .next_handoff_image_id = INVALID_IMAGE_ID, }, -# endif +#endif /* ETHOSN_NPU_TZMP1 */ }; REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S index ed85ea1..3e56691 100644 --- a/plat/arm/common/aarch64/arm_helpers.S +++ b/plat/arm/common/aarch64/arm_helpers.S
@@ -86,51 +86,3 @@ func platform_mem_init ret endfunc platform_mem_init - -/* - * Need to use coherent stack when ARM Cryptocell is used to autheticate images - * since Cryptocell uses DMA to transfer data and it is not coherent with the - * AP CPU. - */ -#if ARM_CRYPTOCELL_INTEG -#if defined(IMAGE_BL1) || defined(IMAGE_BL2) - .globl plat_get_my_stack - .globl plat_set_my_stack - .local platform_coherent_stacks - - /* ------------------------------------------------------- - * uintptr_t plat_get_my_stack () - * - * For cold-boot BL images, only the primary CPU needs a - * stack. This function returns the stack pointer for a - * stack allocated in coherent memory. - * ------------------------------------------------------- - */ -func plat_get_my_stack - get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE - ret -endfunc plat_get_my_stack - - /* ------------------------------------------------------- - * void plat_set_my_stack () - * - * For cold-boot BL images, only the primary CPU needs a - * stack. This function sets the stack pointer to a stack - * allocated in coherent memory. - * ------------------------------------------------------- - */ -func plat_set_my_stack - get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE - mov sp, x0 - ret -endfunc plat_set_my_stack - - /* ---------------------------------------------------- - * Single cpu stack in coherent memory. - * ---------------------------------------------------- - */ -declare_stack platform_coherent_stacks, .tzfw_coherent_mem, \ - PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE - -#endif /* defined(IMAGE_BL1) || defined(IMAGE_BL2) */ -#endif /* ARM_CRYPTOCELL_INTEG */
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 7000236..feff691 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c
@@ -108,11 +108,8 @@ *****************************************************************************/ void arm_bl1_plat_arch_setup(void) { -#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG - /* - * Ensure ARM platforms don't use coherent memory in BL1 unless - * cryptocell integration is enabled. - */ +#if USE_COHERENT_MEM + /* Ensure ARM platforms don't use coherent memory in BL1. */ assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif @@ -123,9 +120,6 @@ ARM_MAP_ROMLIB_CODE, ARM_MAP_ROMLIB_DATA, #endif -#if ARM_CRYPTOCELL_INTEG - ARM_MAP_BL_COHERENT_RAM, -#endif {0} };
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c index b598c59..01e0db0 100644 --- a/plat/arm/common/arm_bl2_el3_setup.c +++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -7,6 +7,7 @@ #include <assert.h> #include <drivers/generic_delay_timer.h> +#include <drivers/partition/partition.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> #include <platform_def.h> @@ -94,7 +95,15 @@ void bl2_el3_plat_arch_setup(void) { + int __maybe_unused ret; arm_bl2_el3_plat_arch_setup(); +#if ARM_GPT_SUPPORT + ret = gpt_partition_init(); + if (ret != 0) { + ERROR("GPT partition initialisation failed!\n"); + panic(); + } +#endif /* ARM_GPT_SUPPORT */ } void bl2_el3_plat_prepare_exit(void)
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index b142b62..3e8109e 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c
@@ -69,6 +69,8 @@ void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout) { + int __maybe_unused ret; + /* Initialize the console to provide early debug support */ arm_console_boot_init(); @@ -82,9 +84,13 @@ /* Load partition table */ #if ARM_GPT_SUPPORT - partition_init(GPT_IMAGE_ID); -#endif /* ARM_GPT_SUPPORT */ + ret = gpt_partition_init(); + if (ret != 0) { + ERROR("GPT partition initialisation failed!\n"); + panic(); + } +#endif /* ARM_GPT_SUPPORT */ } void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) @@ -178,11 +184,8 @@ ******************************************************************************/ void arm_bl2_plat_arch_setup(void) { -#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG - /* - * Ensure ARM platforms don't use coherent memory in BL2 unless - * cryptocell integration is enabled. - */ +#if USE_COHERENT_MEM + /* Ensure ARM platforms don't use coherent memory in BL2. */ assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif @@ -193,9 +196,6 @@ ARM_MAP_ROMLIB_CODE, ARM_MAP_ROMLIB_DATA, #endif -#if ARM_CRYPTOCELL_INTEG - ARM_MAP_BL_COHERENT_RAM, -#endif ARM_MAP_BL_CONFIG_REGION, #if ENABLE_RME ARM_MAP_L0_GPT_REGION, @@ -312,8 +312,3 @@ #endif return arm_bl2_handle_post_image_load(image_id); } - -int bl2_plat_handle_post_image_load(unsigned int image_id) -{ - return arm_bl2_plat_handle_post_image_load(image_id); -}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index cfd1aac..8e90615 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c
@@ -198,6 +198,24 @@ while (bl_params != NULL) { if (bl_params->image_id == BL32_IMAGE_ID) { bl32_image_ep_info = *bl_params->ep_info; +#if SPMC_AT_EL3 + /* + * Populate the BL32 image base, size and max limit in + * the entry point information, since there is no + * platform function to retrieve them in generic + * code. We choose arg2, arg3 and arg4 since the generic + * code uses arg1 for stashing the SP manifest size. The + * SPMC setup uses these arguments to update SP manifest + * with actual SP's base address and it size. + */ + bl32_image_ep_info.args.arg2 = + bl_params->image_info->image_base; + bl32_image_ep_info.args.arg3 = + bl_params->image_info->image_size; + bl32_image_ep_info.args.arg4 = + bl_params->image_info->image_base + + bl_params->image_info->image_max_size; +#endif } #if ENABLE_RME else if (bl_params->image_id == RMM_IMAGE_ID) { @@ -295,7 +313,7 @@ /* Initialize power controller before setting up topology */ plat_arm_pwrc_setup(); -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS && FFH_SUPPORT ras_init(); #endif
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 647a9d9..ae0d85d 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk
@@ -6,6 +6,12 @@ include common/fdt_wrappers.mk +ifeq (${ARCH},aarch32) + ifeq (${AARCH32_SP},none) + $(error Variable AARCH32_SP has to be set for AArch32) + endif +endif + ifeq (${ARCH}, aarch64) # On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted # DRAM (if available) or the TZC secured area of DRAM. @@ -114,48 +120,6 @@ endif endif -# Arm(R) Ethos(TM)-N NPU SiP service -ARM_ETHOSN_NPU_DRIVER := 0 -$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER)) -$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER)) - -# Arm(R) Ethos(TM)-N NPU TZMP1 -ARM_ETHOSN_NPU_TZMP1 := 0 -$(eval $(call assert_boolean,ARM_ETHOSN_NPU_TZMP1)) -$(eval $(call add_define,ARM_ETHOSN_NPU_TZMP1)) -ifeq (${ARM_ETHOSN_NPU_TZMP1},1) - ifeq (${ARM_ETHOSN_NPU_DRIVER},0) - $(error ARM_ETHOSN_NPU_TZMP1 is only available if ARM_ETHOSN_NPU_DRIVER=1) - endif - ifeq (${PLAT},juno) - $(eval $(call add_define,JUNO_ETHOSN_TZMP1)) - else - $(error ARM_ETHOSN_NPU_TZMP1 only supported on Juno platform, not ${PLAT}) - endif - - ifeq (${TRUSTED_BOARD_BOOT},0) - # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being - # tampered with, which is required to protect the confidentiality of protected - # inference data. - $(error ARM_ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled) - endif - - # We need the FW certificate and key certificate - $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert)) - $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert)) - # Needed for our OIDs to be available in tbbr_cot_bl2.c - $(eval $(call add_define, PLAT_DEF_OID)) - PLAT_INCLUDES += -I${PLAT_DIR}certificate/include - PLAT_INCLUDES += -Iinclude/drivers/arm/ - - # We need the firmware to be built into the FIP - $(eval $(call TOOL_ADD_IMG,ARM_ETHOSN_NPU_FW,--npu-fw)) - - # Needed so that UUIDs from the FIP are available in BL2 - $(eval $(call add_define,PLAT_DEF_FIP_UUID)) - PLAT_INCLUDES += -I${PLAT_DIR}fip -endif # ARM_ETHOSN_NPU_TZMP1 - # Use an implementation of SHA-256 with a smaller memory footprint but reduced # speed. $(eval $(call add_define,MBEDTLS_SHA256_SMALLER)) @@ -200,24 +164,11 @@ endif endif -# Disable ARM Cryptocell by default -ARM_CRYPTOCELL_INTEG := 0 -$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG)) -$(eval $(call add_define,ARM_CRYPTOCELL_INTEG)) - # Enable PIE support for RESET_TO_BL31/RESET_TO_SP_MIN case ifneq ($(filter 1,${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) ENABLE_PIE := 1 endif -# CryptoCell integration relies on coherent buffers for passing data from -# the AP CPU to the CryptoCell -ifeq (${ARM_CRYPTOCELL_INTEG},1) - ifeq (${USE_COHERENT_MEM},0) - $(error "ARM_CRYPTOCELL_INTEG needs USE_COHERENT_MEM to be set.") - endif -endif - # Disable GPT parser support, use FIP image by default ARM_GPT_SUPPORT := 0 $(eval $(call assert_boolean,ARM_GPT_SUPPORT)) @@ -348,18 +299,18 @@ plat/arm/common/arm_topology.c \ plat/common/plat_psci_common.c -ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),) +ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),) ARM_SVC_HANDLER_SRCS := ifeq (${ENABLE_PMF},1) ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c endif -ifeq (${ARM_ETHOSN_NPU_DRIVER},1) +ifeq (${ETHOSN_NPU_DRIVER},1) ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \ drivers/delay_timer/delay_timer.c \ drivers/arm/ethosn/ethosn_smc.c -ifeq (${ARM_ETHOSN_NPU_TZMP1},1) +ifeq (${ETHOSN_NPU_TZMP1},1) ARM_SVC_HANDLER_SRCS += drivers/arm/ethosn/ethosn_big_fw.c endif endif @@ -367,9 +318,11 @@ ifeq (${ARCH}, aarch64) BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\ plat/arm/common/arm_sip_svc.c \ + plat/arm/common/plat_arm_sip_svc.c \ ${ARM_SVC_HANDLER_SRCS} else BL32_SOURCES += plat/arm/common/arm_sip_svc.c \ + plat/arm/common/plat_arm_sip_svc.c \ ${ARM_SVC_HANDLER_SRCS} endif endif @@ -386,7 +339,7 @@ endif # RAS sources -ifeq (${RAS_FFH_SUPPORT},1) +ifeq (${ENABLE_FEAT_RAS}-${HANDLE_EA_EL3_FIRST_NS},1-1) BL31_SOURCES += lib/extensions/ras/std_err_record.c \ lib/extensions/ras/ras_common.c endif @@ -481,11 +434,7 @@ BL31_SOURCES += drivers/auth/crypto_mod.c # We expect to locate the *.mk files under the directories specified below - ifeq (${ARM_CRYPTOCELL_INTEG},0) - CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk - else - CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk - endif + CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk $(info Including ${CRYPTO_LIB_MK}) include ${CRYPTO_LIB_MK}
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 1c95afb..5becbcd 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c
@@ -40,7 +40,11 @@ static const interrupt_prop_t arm_interrupt_props[] = { PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), - PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) + PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0), +#if ENABLE_FEAT_RAS && FFH_SUPPORT + INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0, + GIC_INTR_CFG_LEVEL) +#endif }; /*
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c index af8a02f..09226f4 100644 --- a/plat/arm/common/arm_sip_svc.c +++ b/plat/arm/common/arm_sip_svc.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,13 +34,13 @@ #endif /* USE_DEBUGFS */ -#if ARM_ETHOSN_NPU_DRIVER +#if ETHOSN_NPU_DRIVER if (ethosn_smc_setup() != 0) { return 1; } -#endif /* ARM_ETHOSN_NPU_DRIVER */ +#endif /* ETHOSN_NPU_DRIVER */ return 0; } @@ -81,14 +81,14 @@ #endif /* USE_DEBUGFS */ -#if ARM_ETHOSN_NPU_DRIVER +#if ETHOSN_NPU_DRIVER if (is_ethosn_fid(smc_fid)) { return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); } -#endif /* ARM_ETHOSN_NPU_DRIVER */ +#endif /* ETHOSN_NPU_DRIVER */ switch (smc_fid) { case ARM_SIP_SVC_EXE_STATE_SWITCH: { @@ -114,10 +114,10 @@ /* PMF calls */ call_count += PMF_NUM_SMC_CALLS; -#if ARM_ETHOSN_NPU_DRIVER +#if ETHOSN_NPU_DRIVER /* ETHOSN calls */ call_count += ETHOSN_NUM_SMC_CALLS; -#endif /* ARM_ETHOSN_NPU_DRIVER */ +#endif /* ETHOSN_NPU_DRIVER */ /* State switch call */ call_count += 1; @@ -133,10 +133,16 @@ SMC_RET2(handle, ARM_SIP_SVC_VERSION_MAJOR, ARM_SIP_SVC_VERSION_MINOR); default: - WARN("Unimplemented ARM SiP Service Call: 0x%x \n", smc_fid); - SMC_RET1(handle, SMC_UNK); + break; } + /* + * Fall back to allow Arm platform specific handler. + * TODO: Refactor needed to move out generic handlers from this file and + * only keep Arm Platform specific handlers here. + */ + return plat_arm_sip_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); }
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c index 743cc90..07f6a82 100644 --- a/plat/arm/common/fconf/arm_fconf_io.c +++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -45,10 +45,21 @@ * each sector has 4 partition entries, and there are * 2 reserved sectors i.e. protective MBR and primary * GPT header hence length gets calculated as, - * length = 512 * (128/4 + 2) + * length = PLAT_PARTITION_BLOCK_SIZE * (128/4 + 2) */ - .length = PLAT_PARTITION_BLOCK_SIZE * - (PLAT_PARTITION_MAX_ENTRIES / 4 + 2), + .length = LBA(PLAT_PARTITION_MAX_ENTRIES / 4 + 2), +}; + +/* + * length will be assigned at runtime based on MBR header data. + * Backup GPT Header is present in Last LBA-1 and its entries + * are last 32 blocks starts at LBA-33, On runtime update these + * before device usage. Update offset to beginning LBA-33 and + * length to LBA-33. + */ +static io_block_spec_t bkup_gpt_spec = { + .offset = PLAT_ARM_FLASH_IMAGE_BASE, + .length = 0, }; #endif /* ARM_GPT_SUPPORT */ @@ -68,9 +79,9 @@ [TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG}, [NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG}, [RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE}, -#if ARM_ETHOSN_NPU_TZMP1 - [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW}, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW}, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT}, @@ -91,10 +102,10 @@ [SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT}, [PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT}, #endif -#if ARM_ETHOSN_NPU_TZMP1 - [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE}, - [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE}, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE}, + [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE}, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #endif /* TRUSTED_BOARD_BOOT */ }; @@ -107,6 +118,11 @@ (uintptr_t)&gpt_spec, open_memmap }, + [BKUP_GPT_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&bkup_gpt_spec, + open_memmap + }, #endif /* ARM_GPT_SUPPORT */ #if PSA_FWU_SUPPORT [FWU_METADATA_IMAGE_ID] = { @@ -198,13 +214,13 @@ (uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID], open_fip }, -#if ARM_ETHOSN_NPU_TZMP1 - [ARM_ETHOSN_NPU_FW_IMAGE_ID] = { +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_IMAGE_ID] = { &fip_dev_handle, - (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_IMAGE_ID], + (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID], open_fip }, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = { @@ -285,18 +301,18 @@ open_fip }, #endif -#if ARM_ETHOSN_NPU_TZMP1 - [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = { +#if ETHOSN_NPU_TZMP1 + [ETHOSN_NPU_FW_KEY_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_KEY_CERT_ID], + (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID], open_fip }, - [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = { + [ETHOSN_NPU_FW_CONTENT_CERT_ID] = { &fip_dev_handle, - (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID], + (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID], open_fip }, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* ARM_IO_IN_DTB */ #endif /* TRUSTED_BOARD_BOOT */ }; @@ -305,11 +321,11 @@ #define FCONF_ARM_IO_UUID_NUM_BASE U(10) -#if ARM_ETHOSN_NPU_TZMP1 +#if ETHOSN_NPU_TZMP1 #define FCONF_ARM_IO_UUID_NUM_NPU U(1) #else #define FCONF_ARM_IO_UUID_NUM_NPU U(0) -#endif +#endif /* ETHOSN_NPU_TZMP1 */ #if TRUSTED_BOARD_BOOT #define FCONF_ARM_IO_UUID_NUM_TBB U(12) @@ -323,11 +339,11 @@ #define FCONF_ARM_IO_UUID_NUM_SPD U(0) #endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */ -#if TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 +#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 #define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2) #else #define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0) -#endif /* TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 */ +#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */ #define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \ FCONF_ARM_IO_UUID_NUM_NPU + \ @@ -355,9 +371,9 @@ {SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"}, {TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"}, {NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"}, -#if ARM_ETHOSN_NPU_TZMP1 - {ARM_ETHOSN_NPU_FW_IMAGE_ID, "arm_ethosn_npu_fw_uuid"}, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#if ETHOSN_NPU_TZMP1 + {ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"}, +#endif /* ETHOSN_NPU_TZMP1 */ #if TRUSTED_BOARD_BOOT {CCA_CONTENT_CERT_ID, "cca_cert_uuid"}, {CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"}, @@ -375,10 +391,10 @@ {SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"}, {PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"}, #endif -#if ARM_ETHOSN_NPU_TZMP1 - {ARM_ETHOSN_NPU_FW_KEY_CERT_ID, "arm_ethosn_npu_fw_key_cert_uuid"}, - {ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, "arm_ethosn_npu_fw_content_cert_uuid"}, -#endif /* ARM_ETHOSN_NPU_TZMP1 */ +#if ETHOSN_NPU_TZMP1 + {ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"}, + {ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"}, +#endif /* ETHOSN_NPU_TZMP1 */ #endif /* TRUSTED_BOARD_BOOT */ };
diff --git a/plat/arm/common/plat_arm_sip_svc.c b/plat/arm/common/plat_arm_sip_svc.c new file mode 100644 index 0000000..b1dab16 --- /dev/null +++ b/plat/arm/common/plat_arm_sip_svc.c
@@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdint.h> + +#include <common/debug.h> +#include <common/runtime_svc.h> + +#include <plat/arm/common/arm_sip_svc.h> +#include <plat/common/platform.h> + +#if ENABLE_SPMD_LP +#include <services/el3_spmd_logical_sp.h> +#endif + +uintptr_t plat_arm_sip_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ +#if PLAT_TEST_SPM + bool secure_origin; + + /* Determine which security state this SMC originated from */ + secure_origin = is_caller_secure(flags); + + switch (smc_fid) { + case ARM_SIP_SET_INTERRUPT_PENDING: + if (!secure_origin) { + SMC_RET1(handle, SMC_UNK); + } + + VERBOSE("SiP Call- Set interrupt pending %d\n", (uint32_t)x1); + plat_ic_set_interrupt_pending(x1); + + SMC_RET1(handle, SMC_OK); + break; /* Not reached */ + default: + break; + } +#endif + +#if ENABLE_SPMD_LP + return plat_spmd_logical_sp_smc_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); +#else + WARN("Unimplemented ARM SiP Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); +#endif +}
diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c index 002c6eb..1e055c5 100644 --- a/plat/arm/css/common/css_bl2_setup.c +++ b/plat/arm/css/common/css_bl2_setup.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -84,3 +84,8 @@ # endif /* EL3_PAYLOAD_BASE */ #endif /* CSS_USE_SCMI_SDS_DRIVER */ + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return arm_bl2_plat_handle_post_image_load(image_id); +}
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c index 3222226..bb64e73 100644 --- a/plat/arm/css/common/css_pm.c +++ b/plat/arm/css/common/css_pm.c
@@ -131,28 +131,8 @@ plat_arm_gic_cpuif_disable(); /* Cluster is to be turned off, so disable coherency */ - if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { + if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) plat_arm_interconnect_exit_coherency(); - -#if HW_ASSISTED_COHERENCY - uint32_t reg; - - /* - * If we have determined this core to be the last man standing and we - * intend to power down the cluster proactively, we provide a hint to - * the power controller that cluster power is not required when all - * cores are powered down. - * Note that this is only an advisory to power controller and is supported - * by SoCs with DynamIQ Shared Units only. - */ - reg = read_clusterpwrdn(); - - /* Clear and set bit 0 : Cluster power not required */ - reg &= ~DSU_CLUSTER_PWR_MASK; - reg |= DSU_CLUSTER_PWR_OFF; - write_clusterpwrdn(reg); -#endif - } } /*******************************************************************************
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h index c6cf0e6..610f1fc 100644 --- a/plat/arm/css/sgi/include/sgi_base_platform_def.h +++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -33,11 +33,11 @@ * chips are accessed - secure ram, css device and soc device regions. */ #if defined(IMAGE_BL31) -# if SPM_MM -# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) -# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) -# define PLAT_SP_IMAGE_MMAP_REGIONS 10 -# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 +# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) +# define PLAT_ARM_MMAP_ENTRIES (10 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# define MAX_XLAT_TABLES (8 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) +# define PLAT_SP_IMAGE_MMAP_REGIONS 12 +# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 14 # else # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) @@ -204,9 +204,13 @@ SOC_CSS_DEVICE_SIZE, \ MT_DEVICE | MT_RW | MT_SECURE | MT_USER) +#if ENABLE_FEAT_RAS && FFH_SUPPORT #define PLAT_SP_PRI PLAT_RAS_PRI +#else +#define PLAT_SP_PRI 0x10 +#endif -#if SPM_MM && RAS_FFH_SUPPORT +#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) && ENABLE_FEAT_RAS && FFH_SUPPORT /* * CPER buffer memory of 128KB is reserved and it is placed adjacent to the * memory shared between EL3 and S-EL0. @@ -228,14 +232,14 @@ #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE + \ CSS_SGI_SP_CPER_BUF_SIZE) -#elif SPM_MM +#elif (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)) /* * Secure partition stack follows right after the memory region that is shared * between EL3 and S-EL0. */ #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ PLAT_SP_IMAGE_NS_BUF_SIZE) -#endif /* SPM_MM && RAS_FFH_SUPPORT */ +#endif /* SPM_MM && ENABLE_FEAT_RAS && FFH_SUPPORT */ /* Platform ID address */ #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
diff --git a/plat/arm/css/sgi/include/sgi_ras.h b/plat/arm/css/sgi/include/sgi_ras.h index e69a684..d311807 100644 --- a/plat/arm/css/sgi/include/sgi_ras.h +++ b/plat/arm/css/sgi/include/sgi_ras.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,15 +7,62 @@ #ifndef SGI_RAS_H #define SGI_RAS_H +#include <lib/extensions/ras.h> +#include <plat/common/platform.h> + /* - * Mapping the RAS interrupt with SDEI event number and the event - * id used with Standalone MM code + * Interrupt type supported. + * - SGI_RAS_INTR_TYPE_SPI: Denotes a SPI interrupt + * - SGI_RAS_INTR_TYPE_PPI: Denotes a PPI interrupt */ +#define SGI_RAS_INTR_TYPE_SPI 0 +#define SGI_RAS_INTR_TYPE_PPI 1 + +/* + * MM Communicate information structure. Required to generate MM Communicate + * payload to be shared with Standalone MM. + */ +typedef struct mm_communicate_header { + struct efi_guid header_guid; + size_t message_len; + uint8_t data[1]; +} mm_communicate_header_t; + +/* RAS error info data structure. */ struct sgi_ras_ev_map { int sdei_ev_num; /* SDEI Event number */ int intr; /* Physical intr number */ + int intr_type; /* Interrupt Type (SPI or PPI)*/ }; -int sgi_ras_intr_handler_setup(void); +/* RAS config data structure. Must be defined by each platform. */ +struct plat_sgi_ras_config { + struct sgi_ras_ev_map *ev_map; + int ev_map_size; +}; + +/* + * Find event map for a given interrupt number. On success, returns pointer + * to the event map. On error, returns NULL. + */ +struct sgi_ras_ev_map *sgi_find_ras_event_map_by_intr(uint32_t intr_num); + +/* + * Initialization function for the framework. + * + * Registers RAS config provided by the platform and then configures and + * enables interrupt for each registered error. On success, return 0. + */ +int sgi_ras_platform_setup(struct plat_sgi_ras_config *config); + +/* Base element RAM RAS interrupt handler function. */ +int sgi_ras_sram_intr_handler(const struct err_record_info *err_rec, + int probe_data, + const struct err_handler_data *const data); + +/* CPU RAS interrupt handler */ +int sgi_ras_cpu_intr_handler(const struct err_record_info *err_rec, + int probe_data, + const struct err_handler_data *const data); #endif /* SGI_RAS_H */
diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h index acf31eb..d659ae5 100644 --- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h +++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
@@ -58,6 +58,11 @@ #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) #define END_KEY_SIZE U(32) +/* Base Element RAM error definitions */ +#define SOC_NS_RAM_ERR_REC_BASE UL(0x2A4C0000) +#define NS_RAM_ECC_CE_INT U(87) +#define NS_RAM_ECC_UE_INT U(88) + #define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ SOC_PLATFORM_PERIPH_BASE, \ SOC_PLATFORM_PERIPH_SIZE, \
diff --git a/plat/arm/css/sgi/ras/sgi_ras_common.c b/plat/arm/css/sgi/ras/sgi_ras_common.c new file mode 100644 index 0000000..9789670 --- /dev/null +++ b/plat/arm/css/sgi/ras/sgi_ras_common.c
@@ -0,0 +1,99 @@ +/* + * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <string.h> + +#include <bl31/interrupt_mgmt.h> +#include <plat/common/platform.h> +#include <platform_def.h> + +#include <sgi_ras.h> + +static struct plat_sgi_ras_config *sgi_ras_config; + +/* + * Find event map for a given interrupt number. On success, returns pointer to + * the event map. On error, returns NULL. + */ +struct sgi_ras_ev_map *sgi_find_ras_event_map_by_intr(uint32_t intr_num) +{ + struct sgi_ras_ev_map *map; + int size; + int i; + + if (sgi_ras_config == NULL) { + ERROR("RAS config is NULL\n"); + return NULL; + } + + map = sgi_ras_config->ev_map; + size = sgi_ras_config->ev_map_size; + + for (i = 0; i < size; i++) { + if (map->intr == intr_num) + return map; + + map++; + } + + return NULL; +} + +/* + * Programs GIC registers and configures interrupt ID's as Group0 EL3 + * interrupts. Current support is to register PPI and SPI interrupts. + */ +static void sgi_ras_intr_configure(int intr, int intr_type) +{ + plat_ic_set_interrupt_type(intr, INTR_TYPE_EL3); + plat_ic_set_interrupt_priority(intr, PLAT_RAS_PRI); + plat_ic_clear_interrupt_pending(intr); + + /* Routing mode option available only for SPI interrupts */ + if (intr_type == SGI_RAS_INTR_TYPE_SPI) { + plat_ic_set_spi_routing(intr, INTR_ROUTING_MODE_ANY, + (u_register_t)read_mpidr_el1()); + } + plat_ic_enable_interrupt(intr); +} + +/* + * Initialization function for the framework. + * + * Registers RAS config provided by the platform and then configures and + * enables interrupt for each registered error. On success, return 0. + */ +int sgi_ras_platform_setup(struct plat_sgi_ras_config *config) +{ + struct sgi_ras_ev_map *map; + int size; + int i; + + /* Check if parameter is valid. */ + if (config == NULL) { + ERROR("SGI: Failed to register RAS config\n"); + return -1; + } + + /* + * Maintain a reference to the platform RAS config data for later + * use. + */ + sgi_ras_config = config; + + map = sgi_ras_config->ev_map; + size = sgi_ras_config->ev_map_size; + + for (i = 0; i < size; i++) { + sgi_ras_intr_configure(map->intr, map->intr_type); + map++; + } + + INFO("SGI: Platform RAS setup successful\n"); + + return 0; +}
diff --git a/plat/arm/css/sgi/ras/sgi_ras_cpu.c b/plat/arm/css/sgi/ras/sgi_ras_cpu.c new file mode 100644 index 0000000..5e77dbb --- /dev/null +++ b/plat/arm/css/sgi/ras/sgi_ras_cpu.c
@@ -0,0 +1,211 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <string.h> + +#include <bl31/interrupt_mgmt.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/extensions/ras.h> +#include <plat/common/platform.h> +#include <services/sdei.h> +#include <services/spm_mm_svc.h> + +#include <sgi_ras.h> + +#define CPU_CONTEXT_REG_GPR_ARR_SIZE 32 +#define CPU_CONTEXT_REG_EL1_ARR_SIZE 17 +#define CPU_CONTEXT_REG_EL2_ARR_SIZE 16 +#define CPU_CONTEXT_REG_EL3_ARR_SIZE 10 + +/* + * MM Communicate message header GUID to indicate the payload is intended for + * CPU MM driver. + */ +struct efi_guid cpu_ecc_event_guid = { + 0x2c1b3bfc, 0x42cd, 0x4a66, + {0xac, 0xd1, 0xa4, 0xd1, 0x63, 0xe9, 0x90, 0xf6} + }; + +/* + * CPU error information data structure communicated as part of MM + * Communication data payload. + */ +typedef struct { + uint64_t ErrStatus; + uint64_t ErrMisc0; + uint64_t ErrAddr; + uint64_t SecurityState; + uint64_t ErrCtxGpr[CPU_CONTEXT_REG_GPR_ARR_SIZE]; + uint64_t ErrCtxEl1Reg[CPU_CONTEXT_REG_EL1_ARR_SIZE]; + uint64_t ErrCtxEl2Reg[CPU_CONTEXT_REG_EL2_ARR_SIZE]; + uint64_t ErrCtxEl3Reg[CPU_CONTEXT_REG_EL3_ARR_SIZE]; +} cpu_err_info; + +/* + * Reads the CPU context and error information from the relevant registers and + * populates the CPU error information data structure. + */ +static void populate_cpu_err_data(cpu_err_info *cpu_info, + uint64_t security_state) +{ + void *ctx; + + ctx = cm_get_context(security_state); + + cpu_info->ErrStatus = read_erxstatus_el1(); + cpu_info->ErrMisc0 = read_erxmisc0_el1(); + cpu_info->ErrAddr = read_erxaddr_el1(); + cpu_info->SecurityState = security_state; + + /* populate CPU EL1 context information. */ + cpu_info->ErrCtxEl1Reg[0] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_ELR_EL1); + cpu_info->ErrCtxEl1Reg[1] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_ESR_EL1); + cpu_info->ErrCtxEl1Reg[2] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_FAR_EL1); + cpu_info->ErrCtxEl1Reg[3] = read_isr_el1(); + cpu_info->ErrCtxEl1Reg[4] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_MAIR_EL1); + cpu_info->ErrCtxEl1Reg[5] = read_midr_el1(); + cpu_info->ErrCtxEl1Reg[6] = read_mpidr_el1(); + cpu_info->ErrCtxEl1Reg[7] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_SCTLR_EL1); + cpu_info->ErrCtxEl1Reg[8] = read_ctx_reg(get_gpregs_ctx(ctx), + CTX_GPREG_SP_EL0); + cpu_info->ErrCtxEl1Reg[9] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_SP_EL1); + cpu_info->ErrCtxEl1Reg[10] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_SPSR_EL1); + cpu_info->ErrCtxEl1Reg[11] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_TCR_EL1); + cpu_info->ErrCtxEl1Reg[12] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_TPIDR_EL0); + cpu_info->ErrCtxEl1Reg[13] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_TPIDR_EL1); + cpu_info->ErrCtxEl1Reg[14] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_TPIDRRO_EL0); + cpu_info->ErrCtxEl1Reg[15] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_TTBR0_EL1); + cpu_info->ErrCtxEl1Reg[16] = read_ctx_reg(get_el1_sysregs_ctx(ctx), + CTX_TTBR1_EL1); + +#if CTX_INCLUDE_EL2_REGS + cpu_info->ErrCtxEl2Reg[0] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_ELR_EL2); + cpu_info->ErrCtxEl2Reg[1] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_ESR_EL2); + cpu_info->ErrCtxEl2Reg[2] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_FAR_EL2); + cpu_info->ErrCtxEl2Reg[3] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_HACR_EL2); + cpu_info->ErrCtxEl2Reg[4] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_HCR_EL2); + cpu_info->ErrCtxEl2Reg[5] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_HPFAR_EL2); + cpu_info->ErrCtxEl2Reg[6] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_MAIR_EL2); + cpu_info->ErrCtxEl2Reg[7] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_SCTLR_EL2); + cpu_info->ErrCtxEl2Reg[8] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_SP_EL2); + cpu_info->ErrCtxEl2Reg[9] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_SPSR_EL2); + cpu_info->ErrCtxEl2Reg[10] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_TCR_EL2); + cpu_info->ErrCtxEl2Reg[11] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_TPIDR_EL2); + cpu_info->ErrCtxEl2Reg[12] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_TTBR0_EL2); + cpu_info->ErrCtxEl2Reg[13] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_VTCR_EL2); + cpu_info->ErrCtxEl2Reg[14] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_VTTBR_EL2); + cpu_info->ErrCtxEl2Reg[15] = read_ctx_reg(get_el2_sysregs_ctx(ctx), + CTX_ESR_EL2); +#endif + + cpu_info->ErrCtxEl3Reg[0] = read_ctx_reg(get_el3state_ctx(ctx), + CTX_ELR_EL3); + cpu_info->ErrCtxEl3Reg[1] = read_ctx_reg(get_el3state_ctx(ctx), + CTX_ESR_EL3); + cpu_info->ErrCtxEl3Reg[2] = read_far_el3(); + cpu_info->ErrCtxEl3Reg[4] = read_mair_el3(); + cpu_info->ErrCtxEl3Reg[5] = read_sctlr_el3(); + cpu_info->ErrCtxEl3Reg[6] = 0; /* sp_el3 */ + cpu_info->ErrCtxEl3Reg[7] = read_tcr_el3(); + cpu_info->ErrCtxEl3Reg[8] = read_tpidr_el3(); + cpu_info->ErrCtxEl3Reg[9] = read_ttbr0_el3(); +} + +/* CPU RAS interrupt handler */ +int sgi_ras_cpu_intr_handler(const struct err_record_info *err_rec, + int probe_data, + const struct err_handler_data *const data) +{ + struct sgi_ras_ev_map *ras_map; + mm_communicate_header_t *header; + cpu_err_info cpu_info = {0}; + uint64_t clear_status; + uint32_t intr; + int ret; + + cm_el1_sysregs_context_save(NON_SECURE); + intr = data->interrupt; + + INFO("[CPU RAS] CPU intr received = %d on cpu_id = %d\n", + intr, plat_my_core_pos()); + + INFO("[CPU RAS] ERXMISC0_EL1 = 0x%lx\n", read_erxmisc0_el1()); + INFO("[CPU RAS] ERXSTATUS_EL1 = 0x%lx\n", read_erxstatus_el1()); + INFO("[CPU RAS] ERXADDR_EL1 = 0x%lx\n", read_erxaddr_el1()); + + /* Populate CPU Error Source Information. */ + populate_cpu_err_data(&cpu_info, get_interrupt_src_ss(data->flags)); + + /* Clear the interrupt. */ + clear_status = read_erxstatus_el1(); + write_erxstatus_el1(clear_status); + plat_ic_end_of_interrupt(intr); + + header = (void *) PLAT_SPM_BUF_BASE; + memset(header, 0, sizeof(*header)); + memcpy(&header->data, &cpu_info, sizeof(cpu_info)); + header->message_len = sizeof(cpu_info); + memcpy(&header->header_guid, (void *) &cpu_ecc_event_guid, + sizeof(struct efi_guid)); + + spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0, + plat_my_core_pos()); + + /* + * Find if this is a RAS interrupt. There must be an event against + * this interrupt + */ + ras_map = sgi_find_ras_event_map_by_intr(intr); + if (ras_map == NULL) { + ERROR("SGI: RAS error info for interrupt id: %d not found\n", + intr); + return -1; + } + + /* Dispatch the event to the SDEI client */ + ret = sdei_dispatch_event(ras_map->sdei_ev_num); + if (ret != 0) { + /* + * sdei_dispatch_event() may return failing result in some + * cases, for example kernel may not have registered a handler + * or RAS event may happen early during boot. We restore the NS + * context when sdei_dispatch_event() returns failing result. + */ + ERROR("SDEI dispatch failed: %d", ret); + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + } + + return ret; +}
diff --git a/plat/arm/css/sgi/ras/sgi_ras_sram.c b/plat/arm/css/sgi/ras/sgi_ras_sram.c new file mode 100644 index 0000000..b100700 --- /dev/null +++ b/plat/arm/css/sgi/ras/sgi_ras_sram.c
@@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <bl31/interrupt_mgmt.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <plat/common/platform.h> +#include <services/sdei.h> +#include <services/spm_mm_svc.h> + +#include <platform_def.h> +#include <sgi_ras.h> + +/* Base Element RAM Error Record offsets. */ +#define ERRSTATUS U(0) +#define ERRCODE U(8) +#define ERRADDR U(12) + +/* + * Base Element RAM error information data structure communicated as part of MM + * Communication data payload. + */ +typedef struct sgi_sram_err_info { + uint32_t err_status; + uint32_t err_code; + uint32_t err_addr; +} sgi_sram_err_info_t; + +/* + * MM Communicate message header GUID to indicate the payload is intended for + * base element RAM MM driver. + */ +struct efi_guid sram_ecc_event_guid = { + 0x7312db4f, 0xd0c4, 0x4fb5, + { 0x81, 0x2c, 0xb7, 0x4b, 0xc6, 0xc4, 0xa9, 0x38 } +}; + +/* Base element RAM RAS error interrupt handler */ +int sgi_ras_sram_intr_handler(const struct err_record_info *err_rec, + int probe_data, + const struct err_handler_data *const data) +{ + struct sgi_ras_ev_map *ras_map; + mm_communicate_header_t *header; + sgi_sram_err_info_t sram_info; + uintptr_t base_addr; + uint32_t clear_status, intr; + int ret; + + cm_el1_sysregs_context_save(NON_SECURE); + intr = data->interrupt; + + INFO("SGI: Base element RAM interrupt [%d] handler\n", intr); + + /* Determine error record base address to read. */ + base_addr = 0; + if (intr == NS_RAM_ECC_CE_INT || intr == NS_RAM_ECC_UE_INT) { + base_addr = SOC_NS_RAM_ERR_REC_BASE; + } + sram_info.err_status = mmio_read_32(base_addr + ERRSTATUS); + sram_info.err_code = mmio_read_32(base_addr + ERRCODE); + sram_info.err_addr = mmio_read_32(base_addr + ERRADDR); + + /* Clear the interrupt. */ + clear_status = mmio_read_32(base_addr + ERRSTATUS); + mmio_write_32((base_addr + ERRSTATUS), clear_status); + + /* + * Prepare the MM Communication buffer to pass the base element RAM + * error information to Secure Partition. + */ + header = (void *)PLAT_SPM_BUF_BASE; + memset(header, 0, sizeof(*header)); + memcpy(&header->data, &sram_info, sizeof(sram_info)); + header->message_len = sizeof(sram_info); + memcpy(&header->header_guid, (void *)&sram_ecc_event_guid, + sizeof(struct efi_guid)); + + spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0, + plat_my_core_pos()); + + plat_ic_end_of_interrupt(intr); + + /* + * Find if this is a RAS interrupt. There must be an event against + * this interrupt + */ + ras_map = sgi_find_ras_event_map_by_intr(intr); + if (ras_map == NULL) { + ERROR("SGI: RAS error info for interrupt id: %d not found\n", + intr); + return -1; + } + + /* Dispatch the event to the SDEI client */ + ret = sdei_dispatch_event(ras_map->sdei_ev_num); + if (ret != 0) { + /* + * sdei_dispatch_event() may return failing result in some + * cases, for example kernel may not have registered a handler + * or RAS event may happen early during boot. We restore the NS + * context when sdei_dispatch_event() returns failing result. + */ + ERROR("SDEI dispatch failed: %d", ret); + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + } + + return ret; +}
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk index 6d17bc2..2cd7034 100644 --- a/plat/arm/css/sgi/sgi-common.mk +++ b/plat/arm/css/sgi/sgi-common.mk
@@ -10,8 +10,6 @@ ENABLE_FEAT_RAS := 1 -RAS_FFH_SUPPORT := 0 - SDEI_SUPPORT := 0 EL3_EXCEPTION_HANDLING := 0 @@ -54,10 +52,6 @@ ${CSS_ENT_BASE}/sgi_bl31_setup.c \ ${CSS_ENT_BASE}/sgi_topology.c -ifeq (${RAS_FFH_SUPPORT},1) -BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c -endif - ifneq (${RESET_TO_BL31},0) $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ Please set RESET_TO_BL31 to 0.")
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c index 9c8d163..7aa7b34 100644 --- a/plat/arm/css/sgi/sgi_bl31_setup.c +++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -106,10 +106,6 @@ { arm_bl31_platform_setup(); -#if RAS_FFH_SUPPORT - sgi_ras_intr_handler_setup(); -#endif - /* Configure the warm reboot SGI for primary core */ css_setup_cpu_pwr_down_intr();
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c index 7f79d54..01b426e 100644 --- a/plat/arm/css/sgi/sgi_plat.c +++ b/plat/arm/css/sgi/sgi_plat.c
@@ -93,7 +93,7 @@ PLAT_ARM_SECURE_MAP_DEVICE, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS && FFH_SUPPORT CSS_SGI_SP_CPER_BUF_MMAP, #endif ARM_SP_IMAGE_RW_MMAP,
diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c index 8d38108..624fed3 100644 --- a/plat/arm/css/sgi/sgi_plat_v2.c +++ b/plat/arm/css/sgi/sgi_plat_v2.c
@@ -54,7 +54,7 @@ #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) ARM_SP_IMAGE_MMAP, #endif #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2 @@ -73,7 +73,7 @@ CSS_SGI_MAP_DEVICE, SOC_PLATFORM_PERIPH_MAP_DEVICE, SOC_SYSTEM_PERIPH_MAP_DEVICE, -#if SPM_MM +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) ARM_SPM_BUF_EL3_MMAP, #endif {0} @@ -87,6 +87,9 @@ SOC_PLATFORM_PERIPH_MAP_DEVICE_USER, ARM_SP_IMAGE_MMAP, ARM_SP_IMAGE_NS_BUF_MMAP, +#if ENABLE_FEAT_RAS && FFH_SUPPORT + CSS_SGI_SP_CPER_BUF_MMAP, +#endif ARM_SP_IMAGE_RW_MMAP, ARM_SPM_BUF_EL0_MMAP, {0}
diff --git a/plat/arm/css/sgi/sgi_ras.c b/plat/arm/css/sgi/sgi_ras.c deleted file mode 100644 index 4f03ac4..0000000 --- a/plat/arm/css/sgi/sgi_ras.c +++ /dev/null
@@ -1,194 +0,0 @@ -/* - * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <assert.h> -#include <string.h> - -#include <bl31/interrupt_mgmt.h> -#include <lib/el3_runtime/context_mgmt.h> -#include <lib/extensions/ras.h> -#include <plat/arm/common/arm_spm_def.h> -#include <plat/common/platform.h> -#include <services/sdei.h> -#include <services/spm_mm_svc.h> - -#include <sgi_ras.h> - -static int sgi_ras_intr_handler(const struct err_record_info *err_rec, - int probe_data, - const struct err_handler_data *const data); -typedef struct mm_communicate_header { - struct efi_guid header_guid; - size_t message_len; - uint8_t data[8]; -} mm_communicate_header_t; - -/* - * GUID to indicate that the MM communication message is intended for DMC-620 - * MM driver. - */ -const struct efi_guid dmc620_ecc_event_guid = { - 0x5ef0afd5, 0xe01a, 0x4c30, - {0x86, 0x19, 0x45, 0x46, 0x26, 0x91, 0x80, 0x98} -}; - -struct sgi_ras_ev_map sgi575_ras_map[] = { - - /* DMC 0 error ECC error interrupt*/ - {SGI_SDEI_DS_EVENT_0, 35}, - - /* DMC 1 error ECC error interrupt*/ - {SGI_SDEI_DS_EVENT_1, 39}, -}; - -#define SGI575_RAS_MAP_SIZE ARRAY_SIZE(sgi575_ras_map) - -struct err_record_info sgi_err_records[] = { - { - /* DMC 0 error record info */ - .handler = &sgi_ras_intr_handler, - .aux_data = (void *)0, - }, { - /* DMC 1 error record info */ - .handler = &sgi_ras_intr_handler, - .aux_data = (void *)1, - }, -}; - -struct ras_interrupt sgi_ras_interrupts[] = { - { - .intr_number = 35, - .err_record = &sgi_err_records[0], - }, { - .intr_number = 39, - .err_record = &sgi_err_records[1], - } -}; - -REGISTER_ERR_RECORD_INFO(sgi_err_records); -REGISTER_RAS_INTERRUPTS(sgi_ras_interrupts); - -static struct sgi_ras_ev_map *plat_sgi_get_ras_ev_map(void) -{ - return sgi575_ras_map; -} - -static int plat_sgi_get_ras_ev_map_size(void) -{ - return SGI575_RAS_MAP_SIZE; -} - -/* - * Find event mapping for a given interrupt number: On success, returns pointer - * to the event mapping. On error, returns NULL. - */ -static struct sgi_ras_ev_map *find_ras_event_map_by_intr(uint32_t intr_num) -{ - struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map(); - int i; - int size = plat_sgi_get_ras_ev_map_size(); - - for (i = 0; i < size; i++) { - if (map->intr == intr_num) - return map; - - map++; - } - - return NULL; -} - -static void sgi_ras_intr_configure(int intr) -{ - plat_ic_set_interrupt_type(intr, INTR_TYPE_EL3); - plat_ic_set_interrupt_priority(intr, PLAT_RAS_PRI); - plat_ic_clear_interrupt_pending(intr); - plat_ic_set_spi_routing(intr, INTR_ROUTING_MODE_ANY, - (u_register_t)read_mpidr_el1()); - plat_ic_enable_interrupt(intr); -} - -static int sgi_ras_intr_handler(const struct err_record_info *err_rec, - int probe_data, - const struct err_handler_data *const data) -{ - struct sgi_ras_ev_map *ras_map; - mm_communicate_header_t *header; - uint32_t intr; - int ret; - - cm_el1_sysregs_context_save(NON_SECURE); - intr = data->interrupt; - - /* - * Find if this is a RAS interrupt. There must be an event against - * this interrupt - */ - ras_map = find_ras_event_map_by_intr(intr); - assert(ras_map != NULL); - - /* - * Populate the MM_COMMUNICATE payload to share the - * event info with StandaloneMM code. This allows us to use - * MM_COMMUNICATE as a common entry mechanism into S-EL0. The - * header data will be parsed in StandaloneMM to process the - * corresponding event. - * - * TBD - Currently, the buffer allocated by SPM for communication - * between EL3 and S-EL0 is being used(PLAT_SPM_BUF_BASE). But this - * should happen via a dynamic mem allocation, which should be - * managed by SPM -- the individual platforms then call the mem - * alloc api to get memory for the payload. - */ - header = (void *) PLAT_SPM_BUF_BASE; - memset(header, 0, sizeof(*header)); - memcpy(&header->data, &err_rec->aux_data, sizeof(err_rec->aux_data)); - header->message_len = sizeof(err_rec->aux_data); - memcpy(&header->header_guid, (void *) &dmc620_ecc_event_guid, - sizeof(const struct efi_guid)); - - spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0, - plat_my_core_pos()); - - /* - * Do an EOI of the RAS interrupt. This allows the - * sdei event to be dispatched at the SDEI event's - * priority. - */ - plat_ic_end_of_interrupt(intr); - - /* Dispatch the event to the SDEI client */ - ret = sdei_dispatch_event(ras_map->sdei_ev_num); - if (ret != 0) { - /* - * sdei_dispatch_event() may return failing result in some cases, - * for example kernel may not have registered a handler or RAS event - * may happen early during boot. We restore the NS context when - * sdei_dispatch_event() returns failing result. - */ - ERROR("SDEI dispatch failed: %d", ret); - cm_el1_sysregs_context_restore(NON_SECURE); - cm_set_next_eret_context(NON_SECURE); - } - - return ret; -} - -int sgi_ras_intr_handler_setup(void) -{ - int i; - struct sgi_ras_ev_map *map = plat_sgi_get_ras_ev_map(); - int size = plat_sgi_get_ras_ev_map_size(); - - for (i = 0; i < size; i++) { - sgi_ras_intr_configure(map->intr); - map++; - } - - INFO("SGI: RAS Interrupt Handler successfully registered\n"); - - return 0; -}
diff --git a/plat/aspeed/ast2700/include/plat_macros.S b/plat/aspeed/ast2700/include/plat_macros.S new file mode 100644 index 0000000..a58fd74 --- /dev/null +++ b/plat/aspeed/ast2700/include/plat_macros.S
@@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_MACROS_S +#define PLAT_MACROS_S + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + .endm + +#endif /* PLAT_MACROS_S */
diff --git a/plat/aspeed/ast2700/include/platform_def.h b/plat/aspeed/ast2700/include/platform_def.h new file mode 100644 index 0000000..8be26c3 --- /dev/null +++ b/plat/aspeed/ast2700/include/platform_def.h
@@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <arch.h> +#include <plat/common/common_def.h> +#include <platform_reg.h> + +#define PLATFORM_STACK_SIZE UL(0x1000) + +/* cpu topology */ +#define PLATFORM_SYSTEM_COUNT U(1) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CORE_PRIMARY U(0) +#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_CORE_COUNT_PER_CLUSTER) + +/* arch timer */ +#define PLAT_SYSCNT_CLKIN_HZ U(1600000000) + +/* power domain */ +#define PLAT_MAX_PWR_LVL U(1) +#define PLAT_NUM_PWR_DOMAINS U(5) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(2) + +/* cache line size */ +#define CACHE_WRITEBACK_SHIFT U(6) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) + +/* translation tables */ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) +#define MAX_XLAT_TABLES U(8) +#define MAX_MMAP_REGIONS U(32) + +/* BL31 region */ +#define BL31_BASE ULL(0x430000000) +#define BL31_SIZE SZ_512K +#define BL31_LIMIT (BL31_BASE + BL31_SIZE) + +/* BL32 region */ +#define BL32_BASE BL31_LIMIT +#define BL32_SIZE SZ_16M +#define BL32_LIMIT (BL32_BASE + BL32_SIZE) + +/* console */ +#define CONSOLE_UART_BASE UART12_BASE +#define CONSOLE_UART_CLKIN_HZ U(1846153) +#define CONSOLE_UART_BAUDRATE U(115200) + +#endif /* PLATFORM_DEF_H */
diff --git a/plat/aspeed/ast2700/include/platform_reg.h b/plat/aspeed/ast2700/include/platform_reg.h new file mode 100644 index 0000000..7f26865 --- /dev/null +++ b/plat/aspeed/ast2700/include/platform_reg.h
@@ -0,0 +1,27 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLATFORM_REG_H +#define PLATFORM_REG_H + +/* GIC */ +#define GICD_BASE U(0x12200000) +#define GICD_SIZE U(0x10000) +#define GICR_BASE U(0x12280000) +#define GICR_SIZE U(0x100000) + +/* UART */ +#define UART_BASE U(0x14c33000) +#define UART12_BASE (UART_BASE + 0xb00) + +/* CPU-die SCU */ +#define SCU_CPU_BASE U(0x12c02000) +#define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780) +#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) +#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) +#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) + +#endif /* PLATFORM_REG_H */
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c new file mode 100644 index 0000000..92a48ff --- /dev/null +++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -0,0 +1,114 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <common/debug.h> +#include <common/desc_image_load.h> +#include <drivers/arm/gicv3.h> +#include <drivers/console.h> +#include <drivers/ti/uart/uart_16550.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> +#include <platform_def.h> + +static console_t console; + +static entry_point_info_t bl32_ep_info; +static entry_point_info_t bl33_ep_info; + +static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr) +{ + /* to workaround the return type mismatch */ + return plat_core_pos_by_mpidr(mpidr); +} + +static const gicv3_driver_data_t plat_gic_data = { + .gicd_base = GICD_BASE, + .gicr_base = GICR_BASE, + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = plat_mpidr_to_core_pos, +}; + +static const mmap_region_t plat_mmap[] = { + MAP_REGION_FLAT(GICD_BASE, GICD_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(GICR_BASE, GICR_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART_BASE, PAGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(SCU_CPU_BASE, PAGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + console_16550_register(CONSOLE_UART_BASE, CONSOLE_UART_CLKIN_HZ, + CONSOLE_UART_BAUDRATE, &console); + + console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); + + SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_2, 0); + bl32_ep_info.pc = BL32_BASE; + SET_SECURITY_STATE(bl32_ep_info.h.attr, SECURE); + + SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_2, 0); + bl33_ep_info.pc = mmio_read_64(SCU_CPU_SMP_EP0); + bl33_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE); +} + +void bl31_plat_arch_setup(void) +{ + mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, + BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE); + + mmap_add_region(BL_CODE_END, BL_CODE_END, + BL_END - BL_CODE_END, + MT_RW_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, + MT_MEMORY | MT_RW); + + mmap_add(plat_mmap); + + init_xlat_tables(); + + enable_mmu_el3(0); +} + +void bl31_platform_setup(void) +{ + gicv3_driver_init(&plat_gic_data); + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *ep_info; + + ep_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; + + if (!ep_info->pc) { + return NULL; + } + + return ep_info; +}
diff --git a/plat/aspeed/ast2700/plat_helpers.S b/plat/aspeed/ast2700/plat_helpers.S new file mode 100644 index 0000000..c6d987e --- /dev/null +++ b/plat/aspeed/ast2700/plat_helpers.S
@@ -0,0 +1,86 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <arch.h> +#include <cortex_a35.h> +#include <platform_def.h> + + .globl platform_mem_init + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_secondary_cold_boot_setup + .globl plat_get_syscnt_freq2 + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_crash_console_flush + +/* void platform_mem_init(void); */ +func platform_mem_init + /* DRAM init. is done by preceding MCU */ + ret +endfunc platform_mem_init + +/* unsigned int plat_is_my_cpu_primary(void); */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #PLATFORM_CORE_PRIMARY + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + +/* unsigned int plat_my_core_pos(void); */ +func plat_my_core_pos + mrs x0, mpidr_el1 + mov x2, #PLATFORM_CORE_COUNT_PER_CLUSTER + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + madd x0, x0, x2, x1 + ret +endfunc plat_my_core_pos + +/* void plat_secondary_cold_boot_setup (void); */ +func plat_secondary_cold_boot_setup + mov x0, xzr + bl plat_my_core_pos + mov_imm x1, SCU_CPU_SMP_EP0 + add x1, x1, x0, lsl #3 + +poll_smp_mbox_go: + wfe + ldr x0, [x1] + cmp x0, xzr + beq poll_smp_mbox_go + br x0 +endfunc plat_secondary_cold_boot_setup + +/* unsigned int plat_get_syscnt_freq2(void); */ +func plat_get_syscnt_freq2 + mov_imm w0, PLAT_SYSCNT_CLKIN_HZ + ret +endfunc plat_get_syscnt_freq2 + +/* int plat_crash_console_init(void); */ +func plat_crash_console_init + mov_imm x0, CONSOLE_UART_BASE + mov_imm x1, CONSOLE_UART_CLKIN_HZ + mov_imm x2, CONSOLE_UART_BAUDRATE + b console_16550_core_init +endfunc plat_crash_console_init + +/* int plat_crash_console_putc(int); */ +func plat_crash_console_putc + mov_imm x1, CONSOLE_UART_BASE + b console_16550_core_putc +endfunc plat_crash_console_putc + +/* void plat_crash_console_flush(void); */ +func plat_crash_console_flush + mov_imm x0, CONSOLE_UART_BASE + b console_16550_core_flush +endfunc plat_crash_console_flush
diff --git a/plat/aspeed/ast2700/plat_pm.c b/plat/aspeed/ast2700/plat_pm.c new file mode 100644 index 0000000..8e69243 --- /dev/null +++ b/plat/aspeed/ast2700/plat_pm.c
@@ -0,0 +1,63 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <common/debug.h> +#include <drivers/arm/gicv3.h> +#include <drivers/console.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> +#include <plat/common/platform.h> + +static uintptr_t sec_ep; + +static int plat_pwr_domain_on(u_register_t mpidr) +{ + unsigned int cpu = plat_core_pos_by_mpidr(mpidr); + uintptr_t ep_reg; + + switch (cpu) { + case 1U: + ep_reg = SCU_CPU_SMP_EP1; + break; + case 2U: + ep_reg = SCU_CPU_SMP_EP2; + break; + case 3U: + ep_reg = SCU_CPU_SMP_EP3; + break; + default: + return PSCI_E_INVALID_PARAMS; + } + + mmio_write_64(ep_reg, sec_ep); + + dsbsy(); + + sev(); + + return PSCI_E_SUCCESS; +} + +static void plat_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +static const plat_psci_ops_t plat_psci_ops = { + .pwr_domain_on = plat_pwr_domain_on, + .pwr_domain_on_finish = plat_pwr_domain_on_finish, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + sec_ep = sec_entrypoint; + *psci_ops = &plat_psci_ops; + + return 0; +}
diff --git a/plat/aspeed/ast2700/plat_topology.c b/plat/aspeed/ast2700/plat_topology.c new file mode 100644 index 0000000..1476fba --- /dev/null +++ b/plat/aspeed/ast2700/plat_topology.c
@@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023, Aspeed Technology Inc. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <lib/psci/psci.h> +#include <platform_def.h> + +static const unsigned char ast2700_power_domain_tree_desc[] = { + PLATFORM_SYSTEM_COUNT, + PLATFORM_CORE_COUNT_PER_CLUSTER, +}; + +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return ast2700_power_domain_tree_desc; +} + +unsigned int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -1; + } + + if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { + return -1; + } + + return (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER) + cpu_id; +}
diff --git a/plat/aspeed/ast2700/platform.mk b/plat/aspeed/ast2700/platform.mk new file mode 100644 index 0000000..873c60e --- /dev/null +++ b/plat/aspeed/ast2700/platform.mk
@@ -0,0 +1,34 @@ +# +# Copyright (c) 2023, Aspeed Technology Inc. +# +# SPDX-License-Identifier: BSD-3-Clause +# + +include drivers/arm/gic/v3/gicv3.mk +include lib/xlat_tables_v2/xlat_tables.mk + +PLAT_AST2700 := plat/aspeed/ast2700 + +PLAT_INCLUDES := \ + -I${PLAT_AST2700}/include + +BL31_SOURCES += \ + common/desc_image_load.c \ + lib/cpus/aarch64/cortex_a35.S \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + drivers/ti/uart/aarch64/16550_console.S \ + ${PLAT_AST2700}/plat_helpers.S \ + ${PLAT_AST2700}/plat_topology.c \ + ${PLAT_AST2700}/plat_bl31_setup.c \ + ${PLAT_AST2700}/plat_pm.c \ + ${GICV3_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +RESET_TO_BL31 := 1 + +PROGRAMMABLE_RESET_ADDRESS := 1 + +COLD_BOOT_SINGLE_CPU := 0 + +ENABLE_SVE_FOR_NS := 0
diff --git a/plat/brcm/board/stingray/include/scp_cmd.h b/plat/brcm/board/stingray/include/scp_cmd.h index 806ef56..a7ab0e5 100644 --- a/plat/brcm/board/stingray/include/scp_cmd.h +++ b/plat/brcm/board/stingray/include/scp_cmd.h
@@ -5,7 +5,7 @@ */ #ifndef SCP_CMD_H -#define SCP_SMD_H +#define SCP_CMD_H #include <stdint.h>
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk index aa2fe86..67413c6 100644 --- a/plat/brcm/board/stingray/platform.mk +++ b/plat/brcm/board/stingray/platform.mk
@@ -210,7 +210,8 @@ BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \ plat/${SOC_DIR}/src/bl2_setup.c \ - plat/${SOC_DIR}/driver/swreg.c + plat/${SOC_DIR}/driver/swreg.c \ + lib/cpus/aarch64/cpu_helpers.S ifeq (${USE_DDR},yes) PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index eca81b1..ab99b15 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c
@@ -11,7 +11,7 @@ #include <arch_helpers.h> #include <common/debug.h> #include <drivers/console.h> -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS #include <lib/extensions/ras.h> #endif #include <lib/xlat_tables/xlat_mmu_helpers.h> @@ -29,7 +29,9 @@ #pragma weak plat_sdei_validate_entry_point #endif +#if FFH_SUPPORT #pragma weak plat_ea_handler = plat_default_ea_handler +#endif void bl31_plat_runtime_setup(void) { @@ -77,11 +79,12 @@ return "EL1"; } +#if FFH_SUPPORT /* Handler for External Aborts from lower EL including RAS errors */ void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, void *handle, uint64_t flags) { -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS /* Call RAS EA handler */ int handled = ras_ea_handler(ea_reason, syndrome, cookie, handle, flags); if (handled != 0) @@ -99,3 +102,4 @@ */ lower_el_panic(); } +#endif
diff --git a/plat/common/aarch64/plat_ehf.c b/plat/common/aarch64/plat_ehf.c index 4ec69b1..6100a20 100644 --- a/plat/common/aarch64/plat_ehf.c +++ b/plat/common/aarch64/plat_ehf.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, Broadcom * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,7 +12,7 @@ * Enumeration of priority levels on ARM platforms. */ ehf_pri_desc_t plat_exceptions[] = { -#if RAS_FFH_SUPPORT +#if ENABLE_FEAT_RAS && FFH_SUPPORT /* RAS Priority */ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_RAS_PRI), #endif @@ -24,9 +24,17 @@ /* Normal priority SDEI */ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI), #endif -#if SPM_MM + +#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) +#if ENABLE_FEAT_RAS && FFH_SUPPORT +#if (PLAT_SP_PRI != PLAT_RAS_PRI) EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), #endif +#else + EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SP_PRI), +#endif +#endif + /* Platform specific exceptions description */ #ifdef PLAT_EHF_DESC PLAT_EHF_DESC,
diff --git a/plat/common/plat_gicv2.c b/plat/common/plat_gicv2.c index 0f988dc..f78d2df 100644 --- a/plat/common/plat_gicv2.c +++ b/plat/common/plat_gicv2.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -193,9 +193,9 @@ gicv2_set_interrupt_priority(id, priority); } -int plat_ic_has_interrupt_type(unsigned int type) +bool plat_ic_has_interrupt_type(unsigned int type) { - int has_interrupt_type = 0; + bool has_interrupt_type = false; switch (type) { #if GICV2_G0_FOR_EL3 @@ -204,7 +204,7 @@ case INTR_TYPE_S_EL1: #endif case INTR_TYPE_NS: - has_interrupt_type = 1; + has_interrupt_type = true; break; default: /* Do nothing in default case */ @@ -216,7 +216,7 @@ void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) { - unsigned int gicv2_type = 0U; + unsigned int gicv2_group = 0U; /* Map canonical interrupt type to GICv2 type */ switch (type) { @@ -225,17 +225,17 @@ #else case INTR_TYPE_S_EL1: #endif - gicv2_type = GICV2_INTR_GROUP0; + gicv2_group = GICV2_INTR_GROUP0; break; case INTR_TYPE_NS: - gicv2_type = GICV2_INTR_GROUP1; + gicv2_group = GICV2_INTR_GROUP1; break; default: - assert(0); /* Unreachable */ + assert(false); /* Unreachable */ break; } - gicv2_set_interrupt_type(id, gicv2_type); + gicv2_set_interrupt_group(id, gicv2_group); } void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c index e1420bb..baa70e0 100644 --- a/plat/common/plat_gicv3.c +++ b/plat/common/plat_gicv3.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -47,10 +47,6 @@ #pragma weak plat_ic_set_interrupt_pending #pragma weak plat_ic_clear_interrupt_pending -CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && - (INTR_TYPE_NS == INTR_GROUP1NS) && - (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); - /* * This function returns the highest priority pending interrupt at * the Interrupt controller @@ -116,12 +112,26 @@ /* * This function returns the type of the interrupt `id`, depending on how - * the interrupt has been configured in the interrupt controller + * the interrupt has been configured in the interrupt controller. */ uint32_t plat_ic_get_interrupt_type(uint32_t id) { + unsigned int group; + assert(IS_IN_EL3()); - return gicv3_get_interrupt_type(id, plat_my_core_pos()); + group = gicv3_get_interrupt_group(id, plat_my_core_pos()); + + switch (group) { + case INTR_GROUP0: + return INTR_TYPE_EL3; + case INTR_GROUP1S: + return INTR_TYPE_S_EL1; + case INTR_GROUP1NS: + return INTR_TYPE_NS; + default: + assert(false); /* Unreachable */ + return INTR_TYPE_EL3; + } } /* @@ -225,16 +235,37 @@ gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); } -int plat_ic_has_interrupt_type(unsigned int type) +bool plat_ic_has_interrupt_type(unsigned int type) { - assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || - (type == INTR_TYPE_NS)); - return 1; + if ((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || + (type == INTR_TYPE_NS)) { + return true; + } + + return false; } void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) { - gicv3_set_interrupt_type(id, plat_my_core_pos(), type); + unsigned int group; + + switch (type) { + case INTR_TYPE_EL3: + group = INTR_GROUP0; + break; + case INTR_TYPE_S_EL1: + group = INTR_GROUP1S; + break; + case INTR_TYPE_NS: + group = INTR_GROUP1NS; + break; + default: + assert(false); /* Unreachable */ + group = INTR_GROUP0; + break; + } + + gicv3_set_interrupt_group(id, plat_my_core_pos(), group); } void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target)
diff --git a/plat/imx/common/aarch32/imx_uart_console.S b/plat/imx/common/aarch32/imx_uart_console.S index 1a1229a..2a35b5e 100644 --- a/plat/imx/common/aarch32/imx_uart_console.S +++ b/plat/imx/common/aarch32/imx_uart_console.S
@@ -28,7 +28,7 @@ mov r0, r4 pop {r4, lr} - finish_console_register imx_uart putc=1, getc=1, flush=1 + finish_console_register imx_uart putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: pop {r4, pc}
diff --git a/plat/imx/common/imx_uart_console.S b/plat/imx/common/imx_uart_console.S index 4d17288..560db15 100644 --- a/plat/imx/common/imx_uart_console.S +++ b/plat/imx/common/imx_uart_console.S
@@ -33,7 +33,7 @@ mov x0, x6 mov x30, x7 - finish_console_register imx_uart putc=1, getc=1, flush=1 + finish_console_register imx_uart putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/plat/imx/common/lpuart_console.S b/plat/imx/common/lpuart_console.S index ff01e35..7acf773 100644 --- a/plat/imx/common/lpuart_console.S +++ b/plat/imx/common/lpuart_console.S
@@ -27,7 +27,7 @@ mov x0, x6 mov x30, x7 - finish_console_register lpuart putc=1, getc=1, flush=1 + finish_console_register lpuart putc=1, getc=ENABLE_CONSOLE_GETC, flush=1 register_fail: ret x7
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk index f4f5bfc..156c55d 100644 --- a/plat/imx/imx7/common/imx7.mk +++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -110,3 +110,7 @@ ifeq (${ARCH},aarch64) $(error Error: AArch64 not supported on i.mx7) endif + +ifeq (${AARCH32_SP}, none) + $(error Variable AARCH32_SP has to be set for AArch32) +endif
diff --git a/plat/imx/imx7/picopi/platform.mk b/plat/imx/imx7/picopi/platform.mk index 0267a8b..c599675 100644 --- a/plat/imx/imx7/picopi/platform.mk +++ b/plat/imx/imx7/picopi/platform.mk
@@ -34,7 +34,6 @@ USE_COHERENT_MEM := 1 # Use multi console API -MULTI_CONSOLE_API := 1 PLAT_PICOPI_UART :=5 $(eval $(call add_define,PLAT_PICOPI_UART))
diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c index 8b132d2..31f2f56 100644 --- a/plat/imx/imx8m/ddr/clock.c +++ b/plat/imx/imx8m/ddr/clock.c
@@ -91,6 +91,10 @@ case 4000: mmio_write_32(DRAM_PLL_CTRL + 0x4, (250 << 12) | (3 << 4) | 1); break; + case 3733: + case 3732: + mmio_write_32(DRAM_PLL_CTRL + 0x4, (311 << 12) | (4 << 4) | 1); + break; case 3200: mmio_write_32(DRAM_PLL_CTRL + 0x4, (200 << 12) | (3 << 4) | 1); break;
diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c index 983f6e2..d98a37e 100644 --- a/plat/imx/imx8m/ddr/dram_retention.c +++ b/plat/imx/imx8m/ddr/dram_retention.c
@@ -8,14 +8,12 @@ #include <lib/mmio.h> #include <dram.h> +#include <gpc_reg.h> #include <platform_def.h> #define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000) #define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004) -#define PU_PGC_UP_TRG 0xf8 -#define PU_PGC_DN_TRG 0x104 -#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC) #define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800) #define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000) #define CCM_TARGET_ROOT_OFFSET (IMX_CCM_BASE + 0x8000) @@ -102,21 +100,12 @@ } dwc_ddrphy_apb_wr(0xd0000, 0x1); -#if defined(PLAT_imx8mq) /* pwrdnreqn_async adbm/adbs of ddr */ - mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1)); - while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) { + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); + while (mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & DDRMIX_ADB400_ACK) ; - } - mmio_setbits_32(GPC_PU_PWRHSK, BIT(1)); -#else - /* pwrdnreqn_async adbm/adbs of ddr */ - mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2)); - while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) { - ; - } - mmio_setbits_32(GPC_PU_PWRHSK, BIT(2)); -#endif + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); + /* remove PowerOk */ mmio_write_32(SRC_DDR1_RCR, 0x8F000008); @@ -124,8 +113,8 @@ mmio_write_32(CCM_SRC_CTRL(15), 2); /* enable the phy iso */ - mmio_setbits_32(IMX_GPC_BASE + 0xd40, 1); - mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5)); + mmio_setbits_32(IMX_GPC_BASE + DDRMIX_PGC, 1); + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, DDRMIX_PWR_REQ); VERBOSE("dram enter retention\n"); } @@ -150,7 +139,7 @@ mmio_write_32(CCM_TARGET_ROOT(65) + 0x4, (0x4 << 24) | (0x3 << 16)); /* disable iso */ - mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5)); + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, DDRMIX_PWR_REQ); mmio_write_32(SRC_DDR1_RCR, 0x8F000006); /* wait dram pll locked */
diff --git a/plat/imx/imx8m/imx8m_ccm.c b/plat/imx/imx8m/imx8m_ccm.c new file mode 100644 index 0000000..10a00c9 --- /dev/null +++ b/plat/imx/imx8m/imx8m_ccm.c
@@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023, Pengutronix. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> +#include <platform_def.h> + +#define UCR1 0x80 +#define UCR1_UARTEN BIT(0) +#define DOMAIN0_RUNNING(d) (((d) & 0x3) != 0) + +static struct imx_uart { + unsigned int ccm_reg; + unsigned int uart_base; +} imx8m_uart_info[] = { + { /* UART 1 */ + .ccm_reg = 0x4490, + .uart_base = 0x30860000, + }, { /* UART 2 */ + .ccm_reg = 0x44a0, + .uart_base = 0x30890000, + }, { /* UART 3 */ + .ccm_reg = 0x44b0, + .uart_base = 0x30880000, + }, { /* UART 4 */ + .ccm_reg = 0x44c0, + .uart_base = 0x30a60000, + } +}; + +unsigned int imx8m_uart_get_base(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(imx8m_uart_info); i++) { + uint32_t val; + + /* + * At least check that the clock-gate is ungated before we + * access the UART register. + */ + val = mmio_read_32(IMX_CCM_BASE + imx8m_uart_info[i].ccm_reg); + if (DOMAIN0_RUNNING(val)) { + val = mmio_read_32(imx8m_uart_info[i].uart_base + UCR1); + if (val & UCR1_UARTEN) { + return imx8m_uart_info[i].uart_base; + } + } + } + + /* + * We should return an error and inform the user but we can't do it + * this early. + */ + return 0; +}
diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c index e9ea2d8..bfcd6ce 100644 --- a/plat/imx/imx8m/imx8m_measured_boot.c +++ b/plat/imx/imx8m/imx8m_measured_boot.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022-2023, Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro. * * SPDX-License-Identifier: BSD-3-Clause @@ -79,3 +79,9 @@ dump_event_log((uint8_t *)event_log, event_log_cur_size); } + +int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, + size_t pk_len) +{ + return 0; +}
diff --git a/plat/imx/imx8m/imx8m_snvs.c b/plat/imx/imx8m/imx8m_snvs.c new file mode 100644 index 0000000..7874a68 --- /dev/null +++ b/plat/imx/imx8m/imx8m_snvs.c
@@ -0,0 +1,19 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> +#include <platform_def.h> + +#define SNVS_HPCOMR U(0x04) +#define SNVS_NPSWA_EN BIT(31) + +void enable_snvs_privileged_access(void) +{ + unsigned int val; + + val = mmio_read_32(IMX_SNVS_BASE + SNVS_HPCOMR); + mmio_write_32(IMX_SNVS_BASE + SNVS_HPCOMR, val | SNVS_NPSWA_EN); +}
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index e0e38a9..f173a16 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c
@@ -19,46 +19,7 @@ #include <gpc.h> #include <imx_sip_svc.h> -#define MIPI_PWR_REQ BIT(0) -#define PCIE_PWR_REQ BIT(1) -#define OTG1_PWR_REQ BIT(2) -#define OTG2_PWR_REQ BIT(3) -#define HSIOMIX_PWR_REQ BIT(4) -#define GPU2D_PWR_REQ BIT(6) -#define GPUMIX_PWR_REQ BIT(7) -#define VPUMIX_PWR_REQ BIT(8) -#define GPU3D_PWR_REQ BIT(9) -#define DISPMIX_PWR_REQ BIT(10) -#define VPU_G1_PWR_REQ BIT(11) -#define VPU_G2_PWR_REQ BIT(12) -#define VPU_H1_PWR_REQ BIT(13) - -#define HSIOMIX_ADB400_SYNC (0x3 << 5) -#define DISPMIX_ADB400_SYNC BIT(7) -#define VPUMIX_ADB400_SYNC BIT(8) -#define GPU3D_ADB400_SYNC BIT(9) -#define GPU2D_ADB400_SYNC BIT(10) -#define GPUMIX_ADB400_SYNC BIT(11) -#define HSIOMIX_ADB400_ACK (0x3 << 23) -#define DISPMIX_ADB400_ACK BIT(25) -#define VPUMIX_ADB400_ACK BIT(26) -#define GPU3D_ADB400_ACK BIT(27) -#define GPU2D_ADB400_ACK BIT(28) -#define GPUMIX_ADB400_ACK BIT(29) - -#define MIPI_PGC 0xc00 -#define PCIE_PGC 0xc40 -#define OTG1_PGC 0xc80 -#define OTG2_PGC 0xcc0 -#define HSIOMIX_PGC 0xd00 -#define GPU2D_PGC 0xd80 -#define GPUMIX_PGC 0xdc0 -#define VPUMIX_PGC 0xe00 -#define GPU3D_PGC 0xe40 -#define DISPMIX_PGC 0xe80 -#define VPU_G1_PGC 0xec0 -#define VPU_G2_PGC 0xf00 -#define VPU_H1_PGC 0xf40 +#define CCGR(x) (0x4000 + (x) * 16) enum pu_domain_id { HSIOMIX,
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index 67bfd36..dc9dd59 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -27,7 +27,9 @@ #include <imx_uart.h> #include <imx_rdc.h> #include <imx8m_caam.h> +#include <imx8m_ccm.h> #include <imx8m_csu.h> +#include <imx8m_snvs.h> #include <plat_imx8.h> #define TRUSTY_PARAMS_LEN_BYTES (4096*2) @@ -130,6 +132,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + unsigned int console_base = IMX_BOOT_UART_BASE; static console_t console; int i; @@ -144,7 +147,11 @@ imx_csu_init(csu_cfg); - console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + if (console_base == 0U) { + console_base = imx8m_uart_get_base(); + } + + console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); @@ -181,6 +188,10 @@ #endif #endif +#if !defined(SPD_opteed) && !defined(SPD_trusty) + enable_snvs_privileged_access(); +#endif + bl31_tzc380_setup(); } @@ -202,8 +213,10 @@ #if USE_COHERENT_MEM MAP_COHERENT_MEM, #endif +#if defined(SPD_opteed) || defined(SPD_trusty) /* Map TEE memory */ MAP_BL32_TOTAL, +#endif {0} };
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk index 24582f8..97f4f24 100644 --- a/plat/imx/imx8m/imx8mm/platform.mk +++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -37,7 +37,9 @@ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_csu.c \ plat/imx/imx8m/imx8m_caam.c \ + plat/imx/imx8m/imx8m_ccm.c \ plat/imx/imx8m/imx8m_psci_common.c \ + plat/imx/imx8m/imx8m_snvs.c \ plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c \ plat/imx/imx8m/imx8mm/imx8mm_psci.c \ plat/imx/imx8m/imx8mm/gpc.c \ @@ -158,6 +160,9 @@ $(eval $(call add_define,BL32_SIZE)) IMX_BOOT_UART_BASE ?= 0x30890000 +ifeq (${IMX_BOOT_UART_BASE},auto) + override IMX_BOOT_UART_BASE := 0 +endif $(eval $(call add_define,IMX_BOOT_UART_BASE)) EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c index eff198d..f9e430b 100644 --- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c +++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -25,7 +25,9 @@ #include <imx_uart.h> #include <imx_rdc.h> #include <imx8m_caam.h> +#include <imx8m_ccm.h> #include <imx8m_csu.h> +#include <imx8m_snvs.h> #include <platform_def.h> #include <plat_imx8.h> @@ -121,6 +123,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + unsigned int console_base = IMX_BOOT_UART_BASE; static console_t console; unsigned int val; int i; @@ -136,12 +139,23 @@ imx_csu_init(csu_cfg); + /* + * Configure the force_incr programmable bit in GPV_5 of PL301_display, which fixes + * partial write issue. The AXI2AHB bridge is used for masters that access the TCM + * through system bus. Please refer to errata ERR050362 for more information. + */ + mmio_setbits_32((GPV5_BASE_ADDR + FORCE_INCR_OFFSET), FORCE_INCR_BIT_MASK); + /* config the ocram memory range for secure access */ mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, 0x4c1); val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); - console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + if (console_base == 0U) { + console_base = imx8m_uart_get_base(); + } + + console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); @@ -178,6 +192,10 @@ #endif #endif +#if !defined(SPD_opteed) && !defined(SPD_trusty) + enable_snvs_privileged_access(); +#endif + bl31_tzc380_setup(); } @@ -199,8 +217,10 @@ #if USE_COHERENT_MEM MAP_COHERENT_MEM, #endif +#if defined(SPD_opteed) || defined(SPD_trusty) /* Map TEE memory */ MAP_BL32_TOTAL, +#endif {0} };
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h index c75e250..d5176dd 100644 --- a/plat/imx/imx8m/imx8mn/include/platform_def.h +++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -141,6 +141,10 @@ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ +#define GPV5_BASE_ADDR U(0x32500000) +#define FORCE_INCR_OFFSET U(0x4044) +#define FORCE_INCR_BIT_MASK U(0x2) + #define IMX_WDOG_B_RESET #define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW)
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk index 1c0ad4f..e0826e2 100644 --- a/plat/imx/imx8m/imx8mn/platform.mk +++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -31,8 +31,10 @@ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_caam.c \ + plat/imx/imx8m/imx8m_ccm.c \ plat/imx/imx8m/imx8m_csu.c \ plat/imx/imx8m/imx8m_psci_common.c \ + plat/imx/imx8m/imx8m_snvs.c \ plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c \ plat/imx/imx8m/imx8mn/imx8mn_psci.c \ plat/imx/imx8m/imx8mn/gpc.c \ @@ -64,6 +66,9 @@ $(eval $(call add_define,BL32_SIZE)) IMX_BOOT_UART_BASE ?= 0x30890000 +ifeq (${IMX_BOOT_UART_BASE},auto) + override IMX_BOOT_UART_BASE := 0 +endif $(eval $(call add_define,IMX_BOOT_UART_BASE)) EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c index 4c31fa2..43fa064 100644 --- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c +++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -25,7 +25,9 @@ #include <imx_uart.h> #include <imx_rdc.h> #include <imx8m_caam.h> +#include <imx8m_ccm.h> #include <imx8m_csu.h> +#include <imx8m_snvs.h> #include <platform_def.h> #include <plat_imx8.h> @@ -117,6 +119,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + unsigned int console_base = IMX_BOOT_UART_BASE; static console_t console; unsigned int val; unsigned int i; @@ -137,7 +140,11 @@ val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c); mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); - console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + if (console_base == 0U) { + console_base = imx8m_uart_get_base(); + } + + console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE, &console); /* This console is only used for boot stage */ console_set_scope(&console, CONSOLE_FLAG_BOOT); @@ -174,6 +181,10 @@ #endif #endif +#if !defined(SPD_opteed) && !defined(SPD_trusty) + enable_snvs_privileged_access(); +#endif + bl31_tzc380_setup(); } @@ -195,8 +206,10 @@ #if USE_COHERENT_MEM MAP_COHERENT_MEM, #endif +#if defined(SPD_opteed) || defined(SPD_trusty) /* Map TEE memory */ MAP_BL32_TOTAL, +#endif {0} };
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk index 1102316..ce69071 100644 --- a/plat/imx/imx8m/imx8mp/platform.mk +++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -32,8 +32,10 @@ plat/imx/imx8m/imx_aipstz.c \ plat/imx/imx8m/imx_rdc.c \ plat/imx/imx8m/imx8m_caam.c \ + plat/imx/imx8m/imx8m_ccm.c \ plat/imx/imx8m/imx8m_csu.c \ plat/imx/imx8m/imx8m_psci_common.c \ + plat/imx/imx8m/imx8m_snvs.c \ plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c \ plat/imx/imx8m/imx8mp/imx8mp_psci.c \ plat/imx/imx8m/imx8mp/gpc.c \ @@ -155,6 +157,9 @@ $(eval $(call add_define,BL32_SIZE)) IMX_BOOT_UART_BASE ?= 0x30890000 +ifeq (${IMX_BOOT_UART_BASE},auto) + override IMX_BOOT_UART_BASE := 0 +endif $(eval $(call add_define,IMX_BOOT_UART_BASE)) EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/include/imx8m_ccm.h b/plat/imx/imx8m/include/imx8m_ccm.h new file mode 100644 index 0000000..acbd135 --- /dev/null +++ b/plat/imx/imx8m/include/imx8m_ccm.h
@@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023, Pengutronix. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX8M_CCM_H +#define IMX8M_CCM_H + +unsigned int imx8m_uart_get_base(void); + +#endif /* IMX8M_CCM_H */
diff --git a/plat/imx/imx8m/include/imx8m_snvs.h b/plat/imx/imx8m/include/imx8m_snvs.h new file mode 100644 index 0000000..799e1d5 --- /dev/null +++ b/plat/imx/imx8m/include/imx8m_snvs.h
@@ -0,0 +1,12 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef IMX8M_SNVS_H +#define IMX8M_SNVS_H + +void enable_snvs_privileged_access(void); + +#endif
diff --git a/plat/imx/imx93/aarch64/plat_helpers.S b/plat/imx/imx93/aarch64/plat_helpers.S new file mode 100644 index 0000000..9987a53 --- /dev/null +++ b/plat/imx/imx93/aarch64/plat_helpers.S
@@ -0,0 +1,74 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <cortex_a55.h> + +#include <platform_def.h> + + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_calc_core_pos + .globl platform_mem_init + + /* ------------------------------------------------------ + * Helper macro that reads the part number of the current + * CPU and jumps to the given label if it matches the CPU + * MIDR provided. + * + * Clobbers x0. + * ------------------------------------------------------ + */ + .macro jump_if_cpu_midr _cpu_midr, _label + + mrs x0, midr_el1 + ubfx x0, x0, MIDR_PN_SHIFT, #12 + cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq \_label + + .endm + + /* ---------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * This function checks if this is the primary CPU + * ---------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + mov_imm x1, MPIDR_AFFINITY_MASK + and x0, x0, x1 + cmp x0, #PLAT_PRIMARY_CPU + cset x0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ---------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_calc_core_pos() + * to get the index of the calling CPU. + * ---------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + mov x1, #MPIDR_AFFLVL_MASK + and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT + ret +endfunc plat_my_core_pos + + /* + * unsigned int plat_calc_core_pos(uint64_t mpidr) + * helper function to calculate the core position. + * With this function. + */ +func plat_calc_core_pos + mov x1, #MPIDR_AFFLVL_MASK + and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT + ret +endfunc plat_calc_core_pos + +func platform_mem_init + ret +endfunc platform_mem_init
diff --git a/plat/imx/imx93/imx93_bl31_setup.c b/plat/imx/imx93/imx93_bl31_setup.c new file mode 100644 index 0000000..8458f6c --- /dev/null +++ b/plat/imx/imx93/imx93_bl31_setup.c
@@ -0,0 +1,160 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdbool.h> + +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <context.h> +#include <drivers/console.h> +#include <drivers/generic_delay_timer.h> +#include <drivers/nxp/trdc/imx_trdc.h> +#include <lib/el3_runtime/context_mgmt.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> + +#include <imx8_lpuart.h> +#include <plat_imx8.h> +#include <platform_def.h> + +#define MAP_BL31_TOTAL \ + MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL31_RO \ + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) + +static const mmap_region_t imx_mmap[] = { + AIPS1_MAP, AIPS2_MAP, AIPS4_MAP, GIC_MAP, + TRDC_A_MAP, TRDC_W_MAP, TRDC_M_MAP, + TRDC_N_MAP, + {0}, +}; + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/* get SPSR for BL33 entry */ +static uint32_t get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned long mode; + uint32_t spsr; + + /* figure out what mode we enter the non-secure world */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + static console_t console; + + console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); + + /* This console is only used for boot stage */ + console_set_scope(&console, CONSOLE_FLAG_BOOT); + + /* + * tell BL3-1 where the non-secure software image is located + * and the entry state information. + */ + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; + bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#if defined(SPD_opteed) + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + + /* Pass TEE base and size to bl33 */ + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; + + /* Make sure memory is clean */ + mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); + bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; + bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; +#endif +} + +void bl31_plat_arch_setup(void) +{ + /* no coherence memory support on i.MX9 */ + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + MAP_BL31_RO, + }; + + /* Assign all the GPIO pins to non-secure world by default */ + mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff); + mmio_write_32(GPIO2_BASE + 0x14, 0x3); + mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff); + mmio_write_32(GPIO2_BASE + 0x1c, 0x3); + + mmio_write_32(GPIO3_BASE + 0x10, 0xffffffff); + mmio_write_32(GPIO3_BASE + 0x14, 0x3); + mmio_write_32(GPIO3_BASE + 0x18, 0xffffffff); + mmio_write_32(GPIO3_BASE + 0x1c, 0x3); + + mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff); + mmio_write_32(GPIO4_BASE + 0x14, 0x3); + mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff); + mmio_write_32(GPIO4_BASE + 0x1c, 0x3); + + mmio_write_32(GPIO1_BASE + 0x10, 0xffffffff); + mmio_write_32(GPIO1_BASE + 0x14, 0x3); + mmio_write_32(GPIO1_BASE + 0x18, 0xffffffff); + mmio_write_32(GPIO1_BASE + 0x1c, 0x3); + + setup_page_tables(bl_regions, imx_mmap); + enable_mmu_el3(0); + + /* trdc must be initialized */ + trdc_config(); +} + +void bl31_platform_setup(void) +{ + generic_delay_timer_init(); + + plat_gic_driver_init(); + plat_gic_init(); +} + +void bl31_plat_runtime_setup(void) +{ + console_switch_state(CONSOLE_FLAG_RUNTIME); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) +{ + if (type == NON_SECURE) { + return &bl33_image_ep_info; + } + + if (type == SECURE) { + return &bl32_image_ep_info; + } + + return NULL; +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return COUNTER_FREQUENCY; +}
diff --git a/plat/imx/imx93/imx93_psci.c b/plat/imx/imx93/imx93_psci.c new file mode 100644 index 0000000..5e1fa95 --- /dev/null +++ b/plat/imx/imx93/imx93_psci.c
@@ -0,0 +1,253 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <stdbool.h> + +#include <arch.h> +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/psci/psci.h> + +#include <plat_imx8.h> +#include <pwr_ctrl.h> + +#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + +/* platform secure warm boot entry */ +static uintptr_t secure_entrypoint; + +static bool boot_stage = true; + +int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) +{ + /* The non-secure entrypoint should be in RAM space */ + if (ns_entrypoint < PLAT_NS_IMAGE_OFFSET) { + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; +} + +int imx_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int pwr_type = psci_get_pstate_type(power_state); + int state_id = psci_get_pstate_id(power_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) { + return PSCI_E_INVALID_PARAMS; + } + + if (pwr_type == PSTATE_TYPE_STANDBY) { + CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + } + + if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { + CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + } + + return PSCI_E_SUCCESS; +} + +void imx_set_cpu_boot_entry(unsigned int core_id, uint64_t boot_entry) +{ + /* set the cpu core reset entry: BLK_CTRL_S */ + mmio_write_32(BLK_CTRL_S_BASE + CA55_RVBADDR0_L + core_id * 8, boot_entry >> 2); +} + +int imx_pwr_domain_on(u_register_t mpidr) +{ + unsigned int core_id; + + core_id = MPIDR_AFFLVL1_VAL(mpidr); + + imx_set_cpu_boot_entry(core_id, secure_entrypoint); + + /* + * When the core is first time boot up, the core is already ON after SoC POR, + * So 'SW_WAKEUP' can not work, so need to toggle core's reset then release + * the core from cpu_wait. + */ + if (boot_stage) { + /* assert CPU core SW reset */ + mmio_clrbits_32(SRC_SLICE(SRC_A55C0 + core_id) + 0x24, BIT(2) | BIT(0)); + /* deassert CPU core SW reset */ + mmio_setbits_32(SRC_SLICE(SRC_A55C0 + core_id) + 0x24, BIT(2) | BIT(0)); + /* release the cpuwait to kick the cpu */ + mmio_clrbits_32(BLK_CTRL_S_BASE + CA55_CPUWAIT, BIT(core_id)); + } else { + /* assert the CMC MISC SW WAKEUP BIT to kick the offline core */ + gpc_assert_sw_wakeup(CPU_A55C0 + core_id); + } + + return PSCI_E_SUCCESS; +} + +void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr); + + plat_gic_pcpu_init(); + plat_gic_cpuif_enable(); + + /* below config is ok both for boot & hotplug */ + /* clear the CPU power mode */ + gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_RUN); + /* clear the SW wakeup */ + gpc_deassert_sw_wakeup(CPU_A55C0 + core_id); + /* switch to GIC wakeup source */ + gpc_select_wakeup_gic(CPU_A55C0 + core_id); + + if (boot_stage) { + /* SRC config */ + /* config the MEM LPM */ + src_mem_lpm_en(SRC_A55P0_MEM + core_id, MEM_OFF); + /* LPM config to only ON in run mode to its domain */ + src_mix_set_lpm(SRC_A55C0 + core_id, core_id, CM_MODE_WAIT); + /* white list config, only enable its own domain */ + src_authen_config(SRC_A55C0 + core_id, 1 << core_id, 0x1); + + boot_stage = false; + } +} + +void imx_pwr_domain_off(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int i; + + plat_gic_cpuif_disable(); + write_clusterpwrdn(DSU_CLUSTER_PWR_OFF); + + /* + * mask all the GPC IRQ wakeup to make sure no IRQ can wakeup this core + * as we need to use SW_WAKEUP for hotplug purpose + */ + for (i = 0U; i < IMR_NUM; i++) { + gpc_set_irq_mask(CPU_A55C0 + core_id, i, 0xffffffff); + } + /* switch to GPC wakeup source */ + gpc_select_wakeup_raw_irq(CPU_A55C0 + core_id); + /* config the target mode to suspend */ + gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_SUSPEND); +} + +void imx_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr); + + /* do cpu level config */ + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + plat_gic_cpuif_disable(); + imx_set_cpu_boot_entry(core_id, secure_entrypoint); + /* config the target mode to WAIT */ + gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_WAIT); + } + + /* do cluster level config */ + if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { + /* config the A55 cluster target mode to WAIT */ + gpc_set_cpu_mode(CPU_A55_PLAT, CM_MODE_WAIT); + + /* config DSU for cluster power down with L3 MEM RET */ + if (is_local_state_retn(CLUSTER_PWR_STATE(target_state))) { + write_clusterpwrdn(DSU_CLUSTER_PWR_OFF | BIT(1)); + } + } +} + +void imx_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL1_VAL(mpidr); + + /* cluster level */ + if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { + /* set the cluster's target mode to RUN */ + gpc_set_cpu_mode(CPU_A55_PLAT, CM_MODE_RUN); + } + + /* do core level */ + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + /* set A55 CORE's power mode to RUN */ + gpc_set_cpu_mode(CPU_A55C0 + core_id, CM_MODE_RUN); + plat_gic_cpuif_enable(); + } +} + +void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + unsigned int i; + + for (i = IMX_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + } + + SYSTEM_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; +} + +void __dead2 imx_system_reset(void) +{ + mmio_write_32(WDOG3_BASE + WDOG_CNT, 0xd928c520); + while ((mmio_read_32(WDOG3_BASE + WDOG_CS) & WDOG_CS_ULK) == 0U) { + ; + } + + mmio_write_32(WDOG3_BASE + WDOG_TOVAL, 0x10); + mmio_write_32(WDOG3_BASE + WDOG_CS, 0x21e3); + + while (1) { + wfi(); + } +} + +void __dead2 imx_system_off(void) +{ + mmio_setbits_32(BBNSM_BASE + BBNSM_CTRL, BBNSM_DP_EN | BBNSM_TOSP); + + while (1) { + wfi(); + } +} + +static const plat_psci_ops_t imx_plat_psci_ops = { + .validate_ns_entrypoint = imx_validate_ns_entrypoint, + .validate_power_state = imx_validate_power_state, + .pwr_domain_on = imx_pwr_domain_on, + .pwr_domain_off = imx_pwr_domain_off, + .pwr_domain_on_finish = imx_pwr_domain_on_finish, + .pwr_domain_suspend = imx_pwr_domain_suspend, + .pwr_domain_suspend_finish = imx_pwr_domain_suspend_finish, + .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, + .system_reset = imx_system_reset, + .system_off = imx_system_off, +}; + +/* export the platform specific psci ops */ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + /* sec_entrypoint is used for warm reset */ + secure_entrypoint = sec_entrypoint; + imx_set_cpu_boot_entry(0, sec_entrypoint); + + pwr_sys_init(); + + *psci_ops = &imx_plat_psci_ops; + + return 0; +}
diff --git a/plat/imx/imx93/include/platform_def.h b/plat/imx/imx93/include/platform_def.h new file mode 100644 index 0000000..7efbf1c --- /dev/null +++ b/plat/imx/imx93/include/platform_def.h
@@ -0,0 +1,97 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef PLATFORM_DEF_H +#define PLATFORM_DEF_H + +#include <lib/utils_def.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +#define PLATFORM_STACK_SIZE 0xB00 +#define CACHE_WRITEBACK_GRANULE 64 + +#define PLAT_PRIMARY_CPU U(0x0) +#define PLATFORM_MAX_CPU_PER_CLUSTER U(2) +#define PLATFORM_CLUSTER_COUNT U(1) +#define PLATFORM_CLUSTER0_CORE_COUNT U(2) +#define PLATFORM_CORE_COUNT U(2) + +#define IMX_PWR_LVL0 MPIDR_AFFLVL0 + +#define PWR_DOMAIN_AT_MAX_LVL U(1) +#define PLAT_MAX_PWR_LVL U(2) +#define PLAT_MAX_OFF_STATE U(4) +#define PLAT_MAX_RET_STATE U(2) + +#define BL31_BASE U(0x204E0000) +#define BL31_LIMIT U(0x20520000) + +/* non-secure uboot base */ +/* TODO */ +#define PLAT_NS_IMAGE_OFFSET U(0x80200000) +#define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) + +/* GICv4 base address */ +#define PLAT_GICD_BASE U(0x48000000) +#define PLAT_GICR_BASE U(0x48040000) + +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) + +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 + +#define IMX_LPUART_BASE U(0x44380000) +#define IMX_BOOT_UART_CLK_IN_HZ U(24000000) /* Select 24MHz oscillator */ +#define IMX_CONSOLE_BAUDRATE 115200 + +#define AIPSx_SIZE U(0x800000) +#define AIPS1_BASE U(0x44000000) +#define AIPS2_BASE U(0x42000000) +#define AIPS3_BASE U(0x42800000) +#define AIPS4_BASE U(0x49000000) +#define GPIO1_BASE U(0x47400000) +#define GPIO2_BASE U(0x43810000) +#define GPIO3_BASE U(0x43820000) +#define GPIO4_BASE U(0x43830000) + +#define TRDC_A_BASE U(0x44270000) +#define TRDC_W_BASE U(0x42460000) +#define TRDC_M_BASE U(0x42810000) +#define TRDC_N_BASE U(0x49010000) +#define TRDC_x_SISE U(0x20000) + +#define WDOG3_BASE U(0x42490000) +#define WDOG_CS U(0x0) +#define WDOG_CS_ULK BIT(11) +#define WDOG_CNT U(0x4) +#define WDOG_TOVAL U(0x8) + +#define BBNSM_BASE U(0x44440000) +#define BBNSM_CTRL U(0x8) +#define BBNSM_DP_EN BIT(24) +#define BBNSM_TOSP BIT(25) + +#define SRC_BASE U(0x44460000) +#define GPC_BASE U(0x44470000) +#define BLK_CTRL_S_BASE U(0x444F0000) +#define S400_MU_BASE U(0x47520000) + +/* system memory map define */ +#define AIPS2_MAP MAP_REGION_FLAT(AIPS2_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW | MT_NS) +#define AIPS1_MAP MAP_REGION_FLAT(AIPS1_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW) +#define AIPS4_MAP MAP_REGION_FLAT(AIPS4_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW | MT_NS) +#define GIC_MAP MAP_REGION_FLAT(PLAT_GICD_BASE, 0x200000, MT_DEVICE | MT_RW) +#define TRDC_A_MAP MAP_REGION_FLAT(TRDC_A_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) +#define TRDC_W_MAP MAP_REGION_FLAT(TRDC_W_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) +#define TRDC_M_MAP MAP_REGION_FLAT(TRDC_M_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) +#define TRDC_N_MAP MAP_REGION_FLAT(TRDC_N_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) + +#define COUNTER_FREQUENCY 24000000 + +#endif /* platform_def.h */
diff --git a/plat/imx/imx93/include/pwr_ctrl.h b/plat/imx/imx93/include/pwr_ctrl.h new file mode 100644 index 0000000..9bcf486 --- /dev/null +++ b/plat/imx/imx93/include/pwr_ctrl.h
@@ -0,0 +1,216 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PWR_CTRL_H +#define PWR_CTRL_H + +#include <stdbool.h> + +#include <lib/mmio.h> + +#include <platform_def.h> + +/******************************************************************************* + * GPC definitions & declarations + ******************************************************************************/ +/* GPC GLOBAL */ +#define GPC_GLOBAL_BASE U(GPC_BASE + 0x4000) +#define GPC_AUTHEN_CTRL U(0x4) +#define GPC_DOMAIN U(0x10) +#define GPC_MASTER U(0x1c) +#define GPC_SYS_SLEEP U(0x40) +#define PMIC_CTRL U(0x100) +#define PMIC_PRE_DLY_CTRL U(0x104) +#define PMIC_STBY_ACK_CTRL U(0x108) +#define GPC_ROSC_CTRL U(0x200) +#define GPC_AON_MEM_CTRL U(0x204) +#define GPC_EFUSE_CTRL U(0x208) + +#define FORCE_CPUx_DISABLE(x) (1 << (16 + (x))) +#define PMIC_STBY_EN BIT(0) +#define ROSC_OFF_EN BIT(0) + +/* GPC CPU_CTRL */ +#define CM_SLICE(x) (GPC_BASE + 0x800 * (x)) +#define CM_AUTHEN_CTRL U(0x4) +#define CM_MISC U(0xc) +#define CM_MODE_CTRL U(0x10) +#define CM_IRQ_WAKEUP_MASK0 U(0x100) +#define CM_SYS_SLEEP_CTRL U(0x380) +#define IMR_NUM U(8) + +/* CM_MISC */ +#define SLEEP_HOLD_EN BIT(1) +#define IRQ_MUX BIT(5) +#define SW_WAKEUP BIT(6) + +/* CM_SYS_SLEEP_CTRL */ +#define SS_WAIT BIT(0) +#define SS_STOP BIT(1) +#define SS_SUSPEND BIT(2) + +#define CM_MODE_RUN U(0x0) +#define CM_MODE_WAIT U(0x1) +#define CM_MODE_STOP U(0x2) +#define CM_MODE_SUSPEND U(0x3) + +#define LPM_SETTING(d, m) ((m) << (((d) % 8) * 4)) + +enum gpc_cmc_slice { + CPU_M33, + CPU_A55C0, + CPU_A55C1, + CPU_A55_PLAT, +}; + +/* set gpc domain assignment */ +static inline void gpc_assign_domains(unsigned int domains) +{ + mmio_write_32(GPC_GLOBAL_BASE + GPC_DOMAIN, domains); +} + +/* force a cpu into sleep status */ +static inline void gpc_force_cpu_suspend(unsigned int cpu) +{ + mmio_setbits_32(GPC_GLOBAL_BASE + GPC_SYS_SLEEP, FORCE_CPUx_DISABLE(cpu)); +} + +static inline void gpc_pmic_stby_en(bool en) +{ + mmio_write_32(GPC_GLOBAL_BASE + PMIC_CTRL, en ? 1 : 0); +} + +static inline void gpc_rosc_off(bool off) +{ + mmio_write_32(GPC_GLOBAL_BASE + GPC_ROSC_CTRL, off ? 1 : 0); +} + +static inline void gpc_set_cpu_mode(unsigned int cpu, unsigned int mode) +{ + mmio_write_32(CM_SLICE(cpu) + CM_MODE_CTRL, mode); +} + +static inline void gpc_select_wakeup_gic(unsigned int cpu) +{ + mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX); +} + +static inline void gpc_select_wakeup_raw_irq(unsigned int cpu) +{ + mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX); +} + +static inline void gpc_assert_sw_wakeup(unsigned int cpu) +{ + mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP); +} + +static inline void gpc_deassert_sw_wakeup(unsigned int cpu) +{ + mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP); +} + +static inline void gpc_clear_cpu_sleep_hold(unsigned int cpu) +{ + mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SLEEP_HOLD_EN); +} + +static inline void gpc_set_irq_mask(unsigned int cpu, unsigned int idx, uint32_t mask) +{ + mmio_write_32(CM_SLICE(cpu) + idx * 0x4 + CM_IRQ_WAKEUP_MASK0, mask); +} + +/******************************************************************************* + * SRC definitions & declarations + ******************************************************************************/ +#define SRC_SLICE(x) (SRC_BASE + 0x400 * (x)) +#define SRC_AUTHEN_CTRL U(0x4) +#define SRC_LPM_SETTING0 U(0x10) +#define SRC_LPM_SETTING1 U(0x14) +#define SRC_LPM_SETTING2 U(0x18) +#define SRC_SLICE_SW_CTRL U(0x20) + +#define SRC_MEM_CTRL U(0x4) +#define MEM_LP_EN BIT(2) +#define MEM_LP_RETN BIT(1) + +enum mix_mem_mode { + MEM_OFF, + MEM_RETN, +}; + +enum src_mix_mem_slice { + SRC_GLOBAL, + + /* MIX slice */ + SRC_SENTINEL, + SRC_AON, + SRC_WKUP, + SRC_DDR, + SRC_DPHY, + SRC_ML, + SRC_NIC, + SRC_HSIO, + SRC_MEDIA, + SRC_M33P, + SRC_A55C0, + SRC_A55C1, + SRC_A55P, + + /* MEM slice */ + SRC_AON_MEM, + SRC_WKUP_MEM, + SRC_DDR_MEM, + SRC_DPHY_MEM, + SRC_ML_MEM, + SRC_NIC_MEM, + SRC_NIC_OCRAM, + SRC_HSIO_MEM, + SRC_MEDIA_MEM, + SRC_A55P0_MEM, + SRC_A55P1_MEM, + SRC_A55_SCU_MEM, + SRC_A55_L3_MEM, +}; + +static inline void src_authen_config(unsigned int mix, unsigned int wlist, + unsigned int lpm_en) +{ + mmio_write_32(SRC_SLICE(mix) + SRC_AUTHEN_CTRL, (wlist << 16) | (lpm_en << 2)); +} + +static inline void src_mix_set_lpm(unsigned int mix, unsigned int did, unsigned int lpm_mode) +{ + mmio_clrsetbits_32(SRC_SLICE(mix) + SRC_LPM_SETTING1 + (did / 8) * 0x4, + LPM_SETTING(did, 0x7), LPM_SETTING(did, lpm_mode)); +} + +static inline void src_mem_lpm_en(unsigned int mix, bool retn) +{ + mmio_setbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | (retn ? MEM_LP_RETN : 0)); +} + +static inline void src_mem_lpm_dis(unsigned int mix) +{ + mmio_clrbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | MEM_LP_RETN); +} + +/******************************************************************************* + * BLK_CTRL_S definitions & declarations + ******************************************************************************/ +#define HW_LP_HANDHSK U(0x110) +#define HW_LP_HANDHSK2 U(0x114) +#define CA55_CPUWAIT U(0x118) +#define CA55_RVBADDR0_L U(0x11c) +#define CA55_RVBADDR0_H U(0x120) + +/******************************************************************************* + * Other definitions & declarations + ******************************************************************************/ +void pwr_sys_init(void); + +#endif /* PWR_CTRL_H */ +
diff --git a/plat/imx/imx93/plat_topology.c b/plat/imx/imx93/plat_topology.c new file mode 100644 index 0000000..739e2b9 --- /dev/null +++ b/plat/imx/imx93/plat_topology.c
@@ -0,0 +1,39 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <plat/common/platform.h> + +const unsigned char imx_power_domain_tree_desc[] = { + PWR_DOMAIN_AT_MAX_LVL, + PLATFORM_CLUSTER_COUNT, + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return imx_power_domain_tree_desc; +} + +/* + * Only one cluster is planned for i.MX9 family, no need + * to consider the cluster id + */ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + cpu_id = MPIDR_AFFLVL1_VAL(mpidr); + + return cpu_id; +}
diff --git a/plat/imx/imx93/platform.mk b/plat/imx/imx93/platform.mk new file mode 100644 index 0000000..ed7e81f --- /dev/null +++ b/plat/imx/imx93/platform.mk
@@ -0,0 +1,46 @@ +# +# Copyright 2022-2023 NXP +# +# SPDX-License-Identifier: BSD-3-Clause +# + +PLAT_INCLUDES := -Iplat/imx/common/include \ + -Iplat/imx/imx93/include \ +# Translation tables library +include lib/xlat_tables_v2/xlat_tables.mk + +GICV3_SUPPORT_GIC600 := 1 + +# Include GICv3 driver files +include drivers/arm/gic/v3/gicv3.mk + +IMX_GIC_SOURCES := ${GICV3_SOURCES} \ + plat/common/plat_gicv3.c \ + plat/common/plat_psci_common.c \ + plat/imx/common/plat_imx8_gic.c + +BL31_SOURCES += plat/common/aarch64/crash_console_helpers.S \ + plat/imx/imx93/aarch64/plat_helpers.S \ + plat/imx/imx93/plat_topology.c \ + plat/imx/common/lpuart_console.S \ + plat/imx/imx93/trdc.c \ + plat/imx/imx93/pwr_ctrl.c \ + plat/imx/imx93/imx93_bl31_setup.c \ + plat/imx/imx93/imx93_psci.c \ + lib/cpus/aarch64/cortex_a55.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/nxp/trdc/imx_trdc.c \ + ${IMX_GIC_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +RESET_TO_BL31 := 1 +HW_ASSISTED_COHERENCY := 1 +USE_COHERENT_MEM := 0 +PROGRAMMABLE_RESET_ADDRESS := 1 +COLD_BOOT_SINGLE_CPU := 1 + +BL32_BASE ?= 0x96000000 +BL32_SIZE ?= 0x02000000 +$(eval $(call add_define,BL32_BASE)) +$(eval $(call add_define,BL32_SIZE))
diff --git a/plat/imx/imx93/pwr_ctrl.c b/plat/imx/imx93/pwr_ctrl.c new file mode 100644 index 0000000..624c605 --- /dev/null +++ b/plat/imx/imx93/pwr_ctrl.c
@@ -0,0 +1,63 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <stdbool.h> + +#include <platform_def.h> +#include <pwr_ctrl.h> + +/*Do the necessary GPC, SRC, BLK_CTRL_S init */ +void pwr_sys_init(void) +{ + unsigned int cpu; + + /* + * Assigned A55 cluster to 3, m33 to 2, A55 CORE0 & CORE1 to 0/1. + * domain0/1 only used for trigger LPM of themselves. A55 cluster & M33's + * domain assignment should be align with the TRDC DID. + */ + gpc_assign_domains(0x3102); + + /* CA55 core0/1 config */ + for (cpu = CPU_A55C0; cpu <= CPU_A55_PLAT; cpu++) { + /* clear the cpu sleep hold */ + gpc_clear_cpu_sleep_hold(cpu); + /* use gic wakeup source by default */ + gpc_select_wakeup_gic(cpu); + /* + * Ignore A55 core0/1's LPM trigger for system sleep. + * normally, for A55 side, only the A55 cluster(plat) + * domain will be used to trigger the system wide low + * power mode transition. + */ + if (cpu != CPU_A55_PLAT) { + gpc_force_cpu_suspend(cpu); + } + } + + /* boot core(A55C0) */ + src_mem_lpm_en(SRC_A55P0_MEM, MEM_OFF); + /* For A55 core, only need to be on in RUN mode */ + src_mix_set_lpm(SRC_A55C0, 0x0, CM_MODE_WAIT); + /* whitelist: 0x1 for domain 0 only */ + src_authen_config(SRC_A55C0, 0x1, 0x1); + + /* A55 cluster */ + gpc_select_wakeup_gic(CPU_A55_PLAT); + gpc_clear_cpu_sleep_hold(CPU_A55_PLAT); + + /* SCU MEM must be OFF when A55 PLAT OFF */ + src_mem_lpm_en(SRC_A55_SCU_MEM, MEM_OFF); + /* L3 memory in retention by default */ + src_mem_lpm_en(SRC_A55_L3_MEM, MEM_RETN); + + src_mix_set_lpm(SRC_A55P, 0x3, 0x1); + /* whitelist: 0x8 for domain 3 only */ + src_authen_config(SRC_A55P, 0x8, 0x1); + + /* enable the HW LP handshake between S401 & A55 cluster */ + mmio_setbits_32(BLK_CTRL_S_BASE + HW_LP_HANDHSK, BIT(5)); +} +
diff --git a/plat/imx/imx93/trdc.c b/plat/imx/imx93/trdc.c new file mode 100644 index 0000000..0d09aa6 --- /dev/null +++ b/plat/imx/imx93/trdc.c
@@ -0,0 +1,68 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> + +#include <common/bl_common.h> +#include <common/debug.h> +#include <lib/mmio.h> + +#include "trdc_config.h" + +struct trdc_mgr_info trdc_mgr_blks[] = { + { TRDC_A_BASE, 0, 0, 39, 40 }, + { TRDC_W_BASE, 0, 0, 70, 71 }, + { TRDC_M_BASE, 1, 0, 1, 2 }, + { TRDC_N_BASE, 0, 1, 1, 2 }, +}; + +unsigned int trdc_mgr_num = ARRAY_SIZE(trdc_mgr_blks); + +struct trdc_config_info trdc_cfg_info[] = { + { TRDC_A_BASE, + trdc_a_mbc_glbac, ARRAY_SIZE(trdc_a_mbc_glbac), + trdc_a_mbc, ARRAY_SIZE(trdc_a_mbc), + trdc_a_mrc_glbac, ARRAY_SIZE(trdc_a_mrc_glbac), + trdc_a_mrc, ARRAY_SIZE(trdc_a_mrc) + }, /* TRDC_A */ + { TRDC_W_BASE, + trdc_w_mbc_glbac, ARRAY_SIZE(trdc_w_mbc_glbac), + trdc_w_mbc, ARRAY_SIZE(trdc_w_mbc), + trdc_w_mrc_glbac, ARRAY_SIZE(trdc_w_mrc_glbac), + trdc_w_mrc, ARRAY_SIZE(trdc_w_mrc) + }, /* TRDC_W */ + { TRDC_N_BASE, + trdc_n_mbc_glbac, ARRAY_SIZE(trdc_n_mbc_glbac), + trdc_n_mbc, ARRAY_SIZE(trdc_n_mbc), + trdc_n_mrc_glbac, ARRAY_SIZE(trdc_n_mrc_glbac), + trdc_n_mrc, ARRAY_SIZE(trdc_n_mrc) + }, /* TRDC_N */ +}; + +void trdc_config(void) +{ + unsigned int i; + + /* Set MTR to DID1 */ + trdc_mda_set_noncpu(TRDC_A_BASE, 4, false, 0x2, 0x2, 0x1); + + /* Set M33 to DID2*/ + trdc_mda_set_cpu(TRDC_A_BASE, 1, 0, 0x2, 0x0, 0x2, 0x0, 0x0, 0x0); + + /* Configure the access permission for TRDC MGR and MC slots */ + for (i = 0U; i < ARRAY_SIZE(trdc_mgr_blks); i++) { + trdc_mgr_mbc_setup(&trdc_mgr_blks[i]); + } + + /* Configure TRDC user settings from config table */ + for (i = 0U; i < ARRAY_SIZE(trdc_cfg_info); i++) { + trdc_setup(&trdc_cfg_info[i]); + } + + NOTICE("TRDC init done\n"); +}
diff --git a/plat/imx/imx93/trdc_config.h b/plat/imx/imx93/trdc_config.h new file mode 100644 index 0000000..c623a19 --- /dev/null +++ b/plat/imx/imx93/trdc_config.h
@@ -0,0 +1,254 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <drivers/nxp/trdc/imx_trdc.h> + +#define TRDC_A_BASE U(0x44270000) +#define TRDC_W_BASE U(0x42460000) +#define TRDC_M_BASE U(0x42460000) +#define TRDC_N_BASE U(0x49010000) + +/* GLBAC7 is used for TRDC only, any setting to GLBAC7 will be ignored */ + +/* aonmix */ +struct trdc_glbac_config trdc_a_mbc_glbac[] = { + /* MBC0 */ + { 0, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + /* MBC1 */ + { 1, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + { 1, 1, SP(RW) | SU(R) | NP(RW) | NU(R) }, + { 1, 2, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) }, +}; + +struct trdc_mbc_config trdc_a_mbc[] = { + { 0, 0, 0, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS1 for S401 DID0 */ + { 0, 0, 1, MBC_BLK_ALL, 0, true }, /* MBC0 Sentinel_SOC_In for S401 DID0 */ + { 0, 0, 2, MBC_BLK_ALL, 0, true }, /* MBC0 GPIO1 for S401 DID0 */ + { 1, 0, 0, MBC_BLK_ALL, 0, true }, /* MBC1 CM33 code TCM for S401 DID0 */ + { 1, 0, 1, MBC_BLK_ALL, 0, true }, /* MBC1 CM33 system TCM for S401 DID0 */ + + { 0, 1, 0, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS1 for MTR DID1 */ + { 0, 1, 1, MBC_BLK_ALL, 0, true }, /* MBC0 Sentinel_SOC_In for MTR DID1 */ + + { 0, 2, 0, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS1 for M33 DID2 */ + { 0, 2, 1, MBC_BLK_ALL, 0, true }, /* MBC0 Sentinel_SOC_In for M33 DID2 */ + { 0, 2, 2, MBC_BLK_ALL, 0, true }, /* MBC0 GPIO1 for M33 DID2 */ + { 1, 2, 0, MBC_BLK_ALL, 2, true }, /* MBC1 CM33 code TCM for M33 DID2 */ + { 1, 2, 1, MBC_BLK_ALL, 2, true }, /* MBC1 CM33 system TCM for M33 DID2 */ + + { 0, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS1 for A55 DID3 */ + { 0, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC0 Sentinel_SOC_In for A55 DID3 */ + { 0, 3, 2, MBC_BLK_ALL, 0, false }, /* MBC0 GPIO1 for A55 DID3 */ + { 1, 3, 0, MBC_BLK_ALL, 1, false }, /* MBC1 CM33 code TCM for A55 DID3 */ + { 1, 3, 1, MBC_BLK_ALL, 1, false }, /* MBC1 CM33 system TCM for A55 DID3 */ + { 1, 10, 1, MBC_BLK_ALL, 2, false }, /* MBC1 CM33 system TCM for SoC masters DID10 */ + + { 0, 7, 0, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS1 for eDMA DID7 */ +}; + +struct trdc_glbac_config trdc_a_mrc_glbac[] = { + { 0, 0, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) }, + { 0, 1, SP(R) | SU(0) | NP(R) | NU(0) }, +}; + +struct trdc_mrc_config trdc_a_mrc[] = { + { 0, 2, 0, 0x00000000, 0x00040000, 0, true }, /* MRC0 M33 ROM for M33 DID2 */ + { 0, 3, 0, 0x00100000, 0x00040000, 1, true }, /* MRC0 M33 ROM for A55 DID3 */ +}; + +/* wakeupmix */ +struct trdc_glbac_config trdc_w_mbc_glbac[] = { + /* MBC0 */ + { 0, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + /* MBC1 */ + { 1, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, +}; + +struct trdc_mbc_config trdc_w_mbc[] = { + { 0, 1, 0, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS2 for MTR DID1 */ + { 1, 1, 0, MBC_BLK_ALL, 0, true }, /* MBC1 AIPS3 for MTR DID1 */ + + { 0, 2, 0, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS2 for M33 DID2 */ + { 0, 2, 1, MBC_BLK_ALL, 0, true }, /* MBC0 GPIO2_In for M33 DID2 */ + { 0, 2, 2, MBC_BLK_ALL, 0, true }, /* MBC0 GPIO3 for M33 DID2 */ + { 0, 2, 3, MBC_BLK_ALL, 0, true }, /* MBC0 DAP for M33 DID2 */ + { 1, 2, 0, MBC_BLK_ALL, 0, true }, /* MBC1 AIPS3 for M33 DID2 */ + { 1, 2, 1, MBC_BLK_ALL, 0, true }, /* MBC1 AHB_ISPAP for M33 DID2 */ + { 1, 2, 2, MBC_BLK_ALL, 0, true }, /* MBC1 NIC_MAIN_GPV for M33 DID2 */ + { 1, 2, 3, MBC_BLK_ALL, 0, true }, /* MBC1 GPIO4 for M33 DID2 */ + + { 0, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS2 for A55 DID3 */ + { 0, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC0 GPIO2_In for A55 DID3 */ + { 0, 3, 2, MBC_BLK_ALL, 0, false }, /* MBC0 GPIO3 for A55 DID3 */ + { 0, 3, 3, MBC_BLK_ALL, 0, false }, /* MBC0 DAP for A55 DID3 */ + { 1, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC1 AIPS3 for A55 DID3 */ + { 1, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC1 AHB_ISPAP for A55 DID3 */ + { 1, 3, 2, MBC_BLK_ALL, 0, true }, /* MBC1 NIC_MAIN_GPV for A55 DID3 */ + { 1, 3, 3, MBC_BLK_ALL, 0, false }, /* MBC1 GPIO4 for A55 DID3 */ + + { 0, 7, 0, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS2 for eDMA DID7 */ + { 1, 7, 0, MBC_BLK_ALL, 0, false }, /* MBC1 AIPS3 for eDMA DID7 */ +}; + +struct trdc_glbac_config trdc_w_mrc_glbac[] = { + /* MRC0 */ + { 0, 0, SP(RX) | SU(RX) | NP(RX) | NU(RX) }, + /* MRC1 */ + { 1, 0, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) }, +}; + +struct trdc_mrc_config trdc_w_mrc[] = { + { 0, 3, 0, 0x00000000, 0x00040000, 0, false }, /* MRC0 A55 ROM for A55 DID3 */ + { 1, 2, 0, 0x28000000, 0x08000000, 0, true }, /* MRC1 FLEXSPI1 for M33 DID2 */ + { 1, 3, 0, 0x28000000, 0x08000000, 0, false }, /* MRC1 FLEXSPI1 for A55 DID3 */ +}; + +/* nicmix */ +struct trdc_glbac_config trdc_n_mbc_glbac[] = { + /* MBC0 */ + { 0, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + /* MBC1 */ + { 1, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + /* MBC2 */ + { 2, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + { 2, 1, SP(R) | SU(R) | NP(R) | NU(R) }, + /* MBC3 */ + { 3, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + { 3, 1, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) }, +}; + +struct trdc_mbc_config trdc_n_mbc[] = { + { 0, 0, 0, MBC_BLK_ALL, 0, true }, /* MBC0 DDRCFG for S401 DID0 */ + { 0, 0, 1, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS4 for S401 DID0 */ + { 0, 0, 2, MBC_BLK_ALL, 0, true }, /* MBC0 MEDIAMIX for S401 DID0 */ + { 0, 0, 3, MBC_BLK_ALL, 0, true }, /* MBC0 HSIOMIX for S401 DID0 */ + { 1, 0, 0, MBC_BLK_ALL, 0, true }, /* MBC1 MTR_DCA, TCU, TROUT for S401 DID0 */ + { 1, 0, 1, MBC_BLK_ALL, 0, true }, /* MBC1 MTR_DCA, TCU, TROUT for S401 DID0 */ + { 1, 0, 2, MBC_BLK_ALL, 0, true }, /* MBC1 MLMIX for S401 DID0 */ + { 1, 0, 3, MBC_BLK_ALL, 0, true }, /* MBC1 MLMIX for S401 DID0 */ + { 2, 0, 0, MBC_BLK_ALL, 0, true }, /* MBC2 GIC for S401 DID0 */ + { 2, 0, 1, MBC_BLK_ALL, 0, true }, /* MBC2 GIC for S401 DID0 */ + { 3, 0, 0, MBC_BLK_ALL, 0, true }, /* MBC3 OCRAM for S401 DID0 */ + { 3, 0, 1, MBC_BLK_ALL, 0, true }, /* MBC3 OCRAM for S401 DID0 */ + + { 0, 1, 0, MBC_BLK_ALL, 0, true }, /* MBC0 DDRCFG for MTR DID1 */ + { 0, 1, 1, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS4 for MTR DID1 */ + { 0, 1, 2, MBC_BLK_ALL, 0, true }, /* MBC0 MEDIAMIX for MTR DID1 */ + { 0, 1, 3, MBC_BLK_ALL, 0, true }, /* MBC0 HSIOMIX for MTR DID1 */ + { 1, 1, 0, MBC_BLK_ALL, 0, true }, /* MBC1 MTR_DCA, TCU, TROUT for MTR DID1 */ + { 1, 1, 1, MBC_BLK_ALL, 0, true }, /* MBC1 MTR_DCA, TCU, TROUT for MTR DID1 */ + { 1, 1, 2, MBC_BLK_ALL, 0, true }, /* MBC1 MLMIX for MTR DID1 */ + { 1, 1, 3, MBC_BLK_ALL, 0, true }, /* MBC1 MLMIX for MTR DID1 */ + + { 0, 2, 0, MBC_BLK_ALL, 0, true }, /* MBC0 DDRCFG for M33 DID2 */ + { 0, 2, 1, MBC_BLK_ALL, 0, true }, /* MBC0 AIPS4 for M33 DID2 */ + { 0, 2, 2, MBC_BLK_ALL, 0, true }, /* MBC0 MEDIAMIX for M33 DID2 */ + { 0, 2, 3, MBC_BLK_ALL, 0, true }, /* MBC0 HSIOMIX for M33 DID2 */ + { 1, 2, 0, MBC_BLK_ALL, 0, true }, /* MBC1 MTR_DCA, TCU, TROUT for M33 DID2 */ + { 1, 2, 1, MBC_BLK_ALL, 0, true }, /* MBC1 MTR_DCA, TCU, TROUT for M33 DID2 */ + { 1, 2, 2, MBC_BLK_ALL, 0, true }, /* MBC1 MLMIX for M33 DID2 */ + { 1, 2, 3, MBC_BLK_ALL, 0, true }, /* MBC1 MLMIX for M33 DID2 */ + { 2, 2, 0, MBC_BLK_ALL, 1, true }, /* MBC2 GIC for M33 DID2 */ + { 2, 2, 1, MBC_BLK_ALL, 1, true }, /* MBC2 GIC for M33 DID2 */ + { 3, 2, 0, MBC_BLK_ALL, 0, true }, /* MBC3 OCRAM for M33 DID2 */ + { 3, 2, 1, MBC_BLK_ALL, 0, true }, /* MBC3 OCRAM for M33 DID2 */ + + { 0, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC0 DDRCFG for A55 DID3 */ + { 0, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS4 for A55 DID3 */ + { 0, 3, 2, MBC_BLK_ALL, 0, false }, /* MBC0 MEDIAMIX for A55 DID3 */ + { 0, 3, 3, MBC_BLK_ALL, 0, false }, /* MBC0 HSIOMIX for A55 DID3 */ + { 1, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC1 MTR_DCA, TCU, TROUT for A55 DID3 */ + { 1, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC1 MTR_DCA, TCU, TROUT for A55 DID3 */ + { 1, 3, 2, MBC_BLK_ALL, 0, false }, /* MBC1 MLMIX for A55 DID3 */ + { 1, 3, 3, MBC_BLK_ALL, 0, false }, /* MBC1 MLMIX for A55 DID3 */ + { 2, 3, 0, MBC_BLK_ALL, 0, false }, /* MBC2 GIC for A55 DID3 */ + { 2, 3, 1, MBC_BLK_ALL, 0, false }, /* MBC2 GIC for A55 DID3 */ + { 3, 3, 0, MBC_BLK_ALL, 1, true }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, MBC_BLK_ALL, 1, true }, /* MBC3 OCRAM for A55 DID3 */ + + { 3, 3, 0, 0, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 0, 1, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 0, 2, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 0, 3, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 0, 4, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 0, 5, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, 0, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, 1, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, 2, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, 3, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, 4, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + { 3, 3, 1, 5, 0, false }, /* MBC3 OCRAM for A55 DID3 */ + + { 0, 7, 1, MBC_BLK_ALL, 0, false }, /* MBC0 AIPS4 for eDMA DID7 */ + { 0, 7, 2, MBC_BLK_ALL, 0, false }, /* MBC0 MEDIAMIX for eDMA DID7 */ + { 0, 7, 3, MBC_BLK_ALL, 0, false }, /* MBC0 HSIOMIX for eDMA DID7 */ + + { 3, 10, 0, MBC_BLK_ALL, 0, false }, /* MBC3 OCRAM for DID10 */ + { 3, 10, 1, MBC_BLK_ALL, 0, false }, /* MBC3 OCRAM for DID10 */ +}; + +struct trdc_glbac_config trdc_n_mrc_glbac[] = { + { 0, 0, SP(RW) | SU(RW) | NP(RW) | NU(RW) }, + { 0, 1, SP(RWX) | SU(RWX) | NP(RWX) | NU(RWX) }, +}; + +#if defined(SPD_opteed) +#define TEE_SHM_SIZE 0x200000 + +#define DRAM_MEM_0_START (0x80000000) +#define DRAM_MEM_0_SIZE (BL32_BASE - 0x80000000) + +#define DRAM_MEM_1_START (BL32_BASE) +#define DRAM_MEM_1_SIZE (BL32_SIZE - TEE_SHM_SIZE) + +#define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE) +#define DRAM_MEM_2_SIZE (0x80000000 - DRAM_MEM_1_SIZE - DRAM_MEM_0_SIZE) + +struct trdc_mrc_config trdc_n_mrc[] = { + { 0, 0, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for S400 DID0 */ + { 0, 1, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for MTR DID1 */ + { 0, 2, 0, 0x80000000, 0x80000000, 0, true }, /* MRC0 DRAM for M33 DID2 */ + { 0, 8, 0, 0x80000000, 0x80000000, 1, false }, /* MRC0 DRAM for Coresight, Testport DID8 */ + { 0, 9, 0, 0x80000000, 0x80000000, 1, false }, /* MRC0 DRAM for DAP DID9 */ + + { 0, 3, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, 1, false }, /* MRC0 DRAM for A55 DID3 */ + { 0, 5, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, 0, false }, /* MRC0 DRAM for USDHC1 DID5 */ + { 0, 6, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, 0, false }, /* MRC0 DRAM for USDHC2 DID6 */ + { 0, 7, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, 0, false }, /* MRC0 DRAM for eDMA DID7 */ + { 0, 10, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, 0, false }, /* MRC0 DRAM for SoC masters DID10 */ + { 0, 11, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, 0, false }, /* MRC0 DRAM for USB DID11 */ + + /* OPTEE memory for secure access only. */ + { 0, 3, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 1, true }, /* MRC0 DRAM for A55 DID3 */ + { 0, 5, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for USDHC1 DID5 */ + { 0, 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for USDHC2 DID6 */ + { 0, 7, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for eDMA DID7 */ + { 0, 10, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for SoC masters DID10 */ + { 0, 11, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, 0, true }, /* MRC0 DRAM for USB DID11 */ + + { 0, 3, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, 1, false }, /* MRC0 DRAM for A55 DID3 */ + { 0, 5, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, 0, false }, /* MRC0 DRAM for USDHC1 DID5 */ + { 0, 6, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, 0, false }, /* MRC0 DRAM for USDHC2 DID6 */ + { 0, 7, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, 0, false }, /* MRC0 DRAM for eDMA DID7 */ + { 0, 10, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, 0, false }, /* MRC0 DRAM for SoC masters DID10 */ + { 0, 11, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, 0, false }, /* MRC0 DRAM for USB DID11 */ + +}; +#else +struct trdc_mrc_config trdc_n_mrc[] = { + { 0, 0, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for S400 DID0 */ + { 0, 1, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for MTR DID1 */ + { 0, 2, 0, 0x80000000, 0x80000000, 0, true }, /* MRC0 DRAM for M33 DID2 */ + { 0, 3, 0, 0x80000000, 0x80000000, 1, false }, /* MRC0 DRAM for A55 DID3 */ + { 0, 5, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for USDHC1 DID5 */ + { 0, 6, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for USDHC2 DID6 */ + { 0, 7, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for eDMA DID7 */ + { 0, 8, 0, 0x80000000, 0x80000000, 1, false }, /* MRC0 DRAM for Coresight, Testport DID8 */ + { 0, 9, 0, 0x80000000, 0x80000000, 1, false }, /* MRC0 DRAM for DAP DID9 */ + { 0, 10, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for SoC masters DID10 */ + { 0, 11, 0, 0x80000000, 0x80000000, 0, false }, /* MRC0 DRAM for USB DID11 */ +}; +#endif
diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h index 3746d92..9db4292 100644 --- a/plat/intel/soc/agilex/include/agilex_memory_controller.h +++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h
@@ -158,6 +158,19 @@ #define AGX_SDRAM_0_LB_ADDR 0x0 #define AGX_DDR_SIZE 0x40000000 +/* Macros */ +#define SOCFPGA_MEMCTRL_ECCCTRL1 0x008 +#define SOCFPGA_MEMCTRL_ERRINTEN 0x010 +#define SOCFPGA_MEMCTRL_ERRINTENS 0x014 +#define SOCFPGA_MEMCTRL_ERRINTENR 0x018 +#define SOCFPGA_MEMCTRL_INTMODE 0x01C +#define SOCFPGA_MEMCTRL_INTSTAT 0x020 +#define SOCFPGA_MEMCTRL_DIAGINTTEST 0x024 +#define SOCFPGA_MEMCTRL_DERRADDRA 0x02C + +#define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ + + (SOCFPGA_MEMCTRL_##_reg)) + int init_hard_memory_controller(void); #endif
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h new file mode 100644 index 0000000..cb9222d --- /dev/null +++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -0,0 +1,195 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef AGX_SOCFPGA_SYSTEMMANAGER_H +#define AGX_SOCFPGA_SYSTEMMANAGER_H + +#include "socfpga_plat_def.h" + +/* System Manager Register Map */ +#define SOCFPGA_SYSMGR_SILICONID_1 0x00 +#define SOCFPGA_SYSMGR_SILICONID_2 0x04 +#define SOCFPGA_SYSMGR_WDDBG 0x08 +#define SOCFPGA_SYSMGR_MPU_STATUS 0x10 +#define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C +#define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34 +#define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38 +#define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C +#define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40 +#define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */ +#define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */ +#define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */ +#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 +#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 +#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C +#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 +#define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74 +#define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78 +#define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C +#define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80 +#define SOCFPGA_SYSMGR_OSC_TRIM 0x84 +#define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88 +#define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C +#define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94 +#define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C +#define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0 +/* NOC configuration value for Agilex5 */ +#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC +#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0 +#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4 +#define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8 +#define SOCFPGA_SYSMGR_FPGA_CFG 0xDC +#define SOCFPGA_SYSMGR_GPO 0xE4 +#define SOCFPGA_SYSMGR_GPI 0xE8 +#define SOCFPGA_SYSMGR_MPU 0xF0 +#define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4 +#define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8 +#define SOCFPGA_SYSMGR_DFI_INTF 0xFC +#define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100 +#define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104 +#define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108 +#define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C +#define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 +#define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120 +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124 +#define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128 +#define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C +#define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130 +#define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134 +#define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138 +#define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C +#define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148 +#define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150 +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154 +#define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180 +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4 + +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 +#define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228 +#define SOCFPGA_SYSMGR_MPFE_status 0x22C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C + +#define DMA0_STREAM_CTRL_REG 0x10D1217C +#define DMA1_STREAM_CTRL_REG 0x10D12180 +#define SDM_STREAM_CTRL_REG 0x10D12184 +#define USB2_STREAM_CTRL_REG 0x10D12188 +#define USB3_STREAM_CTRL_REG 0x10D1218C +#define SDMMC_STREAM_CTRL_REG 0x10D12190 +#define NAND_STREAM_CTRL_REG 0x10D12194 +#define ETR_STREAM_CTRL_REG 0x10D12198 +#define TSN0_STREAM_CTRL_REG 0x10D1219C +#define TSN1_STREAM_CTRL_REG 0x10D121A0 +#define TSN2_STREAM_CTRL_REG 0x10D121A4 + +/* Stream ID configuration value for Agilex5 */ +#define TSN0 0x00010001 +#define TSN1 0x00020002 +#define TSN2 0x00030003 +#define NAND 0x00040004 +#define SDMMC 0x00050005 +#define USB0 0x00060006 +#define USB1 0x00070007 +#define DMA0 0x00080008 +#define DMA1 0x00090009 +#define SDM 0x000A000A +#define CORE_SIGHT_DEBUG 0x000B000B + +/* Field Masking */ +#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) +#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) +#define IDLE_DATA_LWSOC2FPGA BIT(4) +#define IDLE_DATA_SOC2FPGA BIT(0) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) +#define SYSMGR_ECC_OCRAM_MASK BIT(1) +#define SYSMGR_ECC_DDR0_MASK BIT(16) +#define SYSMGR_ECC_DDR1_MASK BIT(17) +#define WSTREAMIDEN_REG_CTRL BIT(0) +#define RSTREAMIDEN_REG_CTRL BIT(1) +#define WMMUSECSID_REG_VAL BIT(4) +#define RMMUSECSID_REG_VAL BIT(5) + +/* Macros */ +#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + + (SOCFPGA_SYSMGR_##_reg)) + +#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL | \ + RSTREAMIDEN_REG_CTRL +#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL | \ + RSTREAMIDEN_REG_CTRL | \ + WMMUSECSID_REG_VAL | RMMUSECSID_REG_VAL + +#endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h index 4d7198c..a744d09 100644 --- a/plat/intel/soc/agilex/include/socfpga_plat_def.h +++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,22 +8,30 @@ #ifndef PLAT_SOCFPGA_DEF_H #define PLAT_SOCFPGA_DEF_H +#include "agilex_system_manager.h" #include <platform_def.h> /* Platform Setting */ -#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX -#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX +#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#define PLAT_PRIMARY_CPU 0 +#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT +#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT /* FPGA config helpers */ #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 +/* QSPI Setting */ +#define CAD_QSPIDATA_OFST 0xff900000 +#define CAD_QSPI_OFFSET 0xff8d2000 + /* Register Mapping */ #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) #define SOCFPGA_MMC_REG_BASE 0xff808000 - +#define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100 #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 @@ -32,6 +40,65 @@ #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define DRAM_BASE (0x0) +#define DRAM_SIZE (0x80000000) + +#define OCRAM_BASE (0xFFE00000) +#define OCRAM_SIZE (0x00040000) + +#define MEM64_BASE (0x0100000000) +#define MEM64_SIZE (0x1F00000000) + +#define DEVICE1_BASE (0x80000000) +#define DEVICE1_SIZE (0x60000000) + +#define DEVICE2_BASE (0xF7000000) +#define DEVICE2_SIZE (0x08E00000) + +#define DEVICE3_BASE (0xFFFC0000) +#define DEVICE3_SIZE (0x00008000) + +#define DEVICE4_BASE (0x2000000000) +#define DEVICE4_SIZE (0x0100000000) + +#define BL2_BASE (0xffe00000) +#define BL2_LIMIT (0xffe1b000) + +#define BL31_BASE (0x1000) +#define BL31_LIMIT (0x81000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define PLAT_UART0_BASE (0xFFC02000) +#define PLAT_UART1_BASE (0xFFC02100) + +/******************************************************************************* + * GIC related constants + ******************************************************************************/ +#define PLAT_GIC_BASE (0xFFFC0000) +#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) +#define PLAT_GICR_BASE 0 + +#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) +#define PLAT_HZ_CONVERT_TO_MHZ (1000000) + +/******************************************************************************* + * SDMMC related pointer function + ******************************************************************************/ +#define SDMMC_READ_BLOCKS mmc_read_blocks +#define SDMMC_WRITE_BLOCKS mmc_write_blocks + +/******************************************************************************* + * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset + * is done and HPS should trigger warm reset via RMR_EL3. + ******************************************************************************/ +#define L2_RESET_DONE_REG 0xFFD12218 + /* Platform specific system counter */ #define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index e9fa666..5c92f72 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk
@@ -79,5 +79,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0 RESET_TO_BL2 := 1 BL2_INV_DCACHE := 0 -MULTI_CONSOLE_API := 1 USE_COHERENT_MEM := 1
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c index 10ef11b..d32c3f1 100644 --- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c +++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +11,8 @@ #include <lib/mmio.h> #include "agilex_clock_manager.h" +#include "agilex_system_manager.h" #include "socfpga_handoff.h" -#include "socfpga_system_manager.h" uint32_t wait_pll_lock(void)
diff --git a/plat/intel/soc/agilex/soc/agilex_pinmux.c b/plat/intel/soc/agilex/soc/agilex_pinmux.c index 96e1ade..d2a06fb 100644 --- a/plat/intel/soc/agilex/soc/agilex_pinmux.c +++ b/plat/intel/soc/agilex/soc/agilex_pinmux.c
@@ -7,7 +7,7 @@ #include <lib/mmio.h> #include "agilex_pinmux.h" -#include "socfpga_system_manager.h" +#include "agilex_system_manager.h" const uint32_t sysmgr_pinmux_array_sel[] = { 0x00000000, 0x00000001, /* usb */
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c new file mode 100644 index 0000000..a2fafd2 --- /dev/null +++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -0,0 +1,174 @@ +/* + * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <arch.h> +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <common/debug.h> +#include <common/desc_image_load.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/generic_delay_timer.h> +#include <drivers/synopsys/dw_mmc.h> +#include <drivers/ti/uart/uart_16550.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_tables_v2.h> + +#include "agilex5_clock_manager.h" +#include "agilex5_memory_controller.h" +#include "agilex5_mmc.h" +#include "agilex5_pinmux.h" +#include "agilex5_system_manager.h" +#include "ccu/ncore_ccu.h" +#include "combophy/combophy.h" +#include "nand/nand.h" +#include "qspi/cadence_qspi.h" +#include "sdmmc/sdmmc.h" +#include "socfpga_emac.h" +#include "socfpga_f2sdram_manager.h" +#include "socfpga_handoff.h" +#include "socfpga_mailbox.h" +#include "socfpga_private.h" +#include "socfpga_reset_manager.h" +#include "wdt/watchdog.h" + + +/* Declare mmc_info */ +static struct mmc_device_info mmc_info; + +/* Declare cadence idmac descriptor */ +extern struct cdns_idmac_desc cdns_desc[8] __aligned(32); + +const mmap_region_t agilex_plat_mmap[] = { + MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, + MT_MEMORY | MT_RW | MT_NS), + MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, + MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, + MT_NON_CACHEABLE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, + MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + {0}, +}; + +boot_source_type boot_source = BOOT_SOURCE; + +void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, + u_register_t x2, u_register_t x4) +{ + static console_t console; + + handoff reverse_handoff_ptr = { 0 }; + + generic_delay_timer_init(); + config_clkmgr_handoff(&reverse_handoff_ptr); + mailbox_init(); + enable_nonsecure_access(); + + deassert_peripheral_reset(); + if (combo_phy_init(&reverse_handoff_ptr) != 0) { + ERROR("Combo Phy initialization failed\n"); + } + + console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, + PLAT_BAUDRATE, &console); + + /* Store magic number */ + mmio_write_32(L2_RESET_DONE_REG, PLAT_L2_RESET_REQ); +} + +void bl2_el3_plat_arch_setup(void) +{ + handoff reverse_handoff_ptr; + + struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk()); + + mmc_info.mmc_dev_type = MMC_DEVICE_TYPE; + mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; + + /* Request ownership and direct access to QSPI */ + mailbox_hps_qspi_enable(); + + switch (boot_source) { + case BOOT_SOURCE_SDMMC: + NOTICE("SDMMC boot\n"); + sdmmc_init(&reverse_handoff_ptr, ¶ms, &mmc_info); + socfpga_io_setup(boot_source); + break; + + case BOOT_SOURCE_QSPI: + NOTICE("QSPI boot\n"); + cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, + QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, + QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); + socfpga_io_setup(boot_source); + break; + + case BOOT_SOURCE_NAND: + NOTICE("NAND boot\n"); + nand_init(&reverse_handoff_ptr); + socfpga_io_setup(boot_source); + break; + + default: + ERROR("Unsupported boot source\n"); + panic(); + break; + } +} + +uint32_t get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); + + assert(bl_mem_params); + + switch (image_id) { + case BL33_IMAGE_ID: + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); + break; + default: + break; + } + + return 0; +} + +/******************************************************************************* + * Perform any BL3-1 platform setup code + ******************************************************************************/ +void bl2_platform_setup(void) +{ +}
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c new file mode 100644 index 0000000..5ae4bf7 --- /dev/null +++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -0,0 +1,284 @@ +/* + * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <arch.h> +#include <arch_helpers.h> +#include <common/bl_common.h> +#include <drivers/arm/gic_common.h> +#include <drivers/arm/gicv3.h> +#include <drivers/ti/uart/uart_16550.h> +#include <lib/mmio.h> +#include <lib/xlat_tables/xlat_mmu_helpers.h> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <plat/common/platform.h> + +#include "agilex5_power_manager.h" +#include "ccu/ncore_ccu.h" +#include "socfpga_mailbox.h" +#include "socfpga_private.h" +#include "socfpga_reset_manager.h" + +/* Get non-secure SPSR for BL33. Zephyr and Linux */ +uint32_t arm_get_spsr_for_bl33_entry(void); + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/* The GICv3 driver only needs to be initialized in EL3 */ +static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +#define SMMU_SDMMC + +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? + &bl33_image_ep_info : &bl32_image_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + static console_t console; + + mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); + + console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, + PLAT_BAUDRATE, &console); + + init_ncore_ccu(); + setup_smmu_stream_id(); + + /* + * Check params passed from BL31 should not be NULL, + */ + void *from_bl2 = (void *) arg0; + +#if RESET_TO_BL31 + /* There are no parameters from BL2 if BL31 is a reset vector */ + assert(from_bl2 == NULL); + void *plat_params_from_bl2 = (void *) arg3; + + assert(plat_params_from_bl2 == NULL); + + /* Populate entry point information for BL33 */ + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + +# if ARM_LINUX_KERNEL_AS_BL33 + /* + * According to the file ``Documentation/arm64/booting.txt`` of the + * Linux kernel tree, Linux expects the physical address of the device + * tree blob (DTB) in x0, while x1-x3 are reserved for future use and + * must be 0. + */ + bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg1 = 0U; + bl33_image_ep_info.args.arg2 = 0U; + bl33_image_ep_info.args.arg3 = 0U; +# endif + +#else /* RESET_TO_BL31 */ + bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; + + assert(params_from_bl2 != NULL); + + /* + * Copy BL32 (if populated by BL31) and BL33 entry point information. + * They are stored in Secure RAM, in BL31's address space. + */ + + if (params_from_bl2->h.type == PARAM_BL_PARAMS && + params_from_bl2->h.version >= VERSION_2) { + + bl_params_node_t *bl_params = params_from_bl2->head; + + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) { + bl33_image_ep_info = *bl_params->ep_info; + } + bl_params = bl_params->next_params_info; + } + } else { + struct socfpga_bl31_params *arg_from_bl2 = + (struct socfpga_bl31_params *) from_bl2; + + assert(arg_from_bl2->h.type == PARAM_BL31); + assert(arg_from_bl2->h.version >= VERSION_1); + + bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; + bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; + } + + bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; + bl33_image_ep_info.args.arg1 = 0U; + bl33_image_ep_info.args.arg2 = 0U; + bl33_image_ep_info.args.arg3 = 0U; +#endif + + /* + * Tell BL31 where the non-trusted software image + * is located and the entry state information + */ + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); + + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +} + +static const interrupt_prop_t agx5_interrupt_props[] = { + PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(INTR_GROUP1S), + PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(INTR_GROUP0) +}; + +static const gicv3_driver_data_t plat_gicv3_gic_data = { + .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, + .gicr_base = PLAT_INTEL_SOCFPGA_GICR_BASE, + .interrupt_props = agx5_interrupt_props, + .interrupt_props_num = ARRAY_SIZE(agx5_interrupt_props), + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, +}; + +/******************************************************************************* + * Perform any BL3-1 platform setup code + ******************************************************************************/ +void bl31_platform_setup(void) +{ + socfpga_delay_timer_init(); + + /* Initialize the gic cpu and distributor interfaces */ + gicv3_driver_init(&plat_gicv3_gic_data); + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); + mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); +#if !defined(SIMICS_RUN) + ncore_enable_ocram_firewall(); +#endif + +} + +const mmap_region_t plat_agilex_mmap[] = { + MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), + MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), + MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + uint32_t boot_core = 0x00; + uint32_t cpuid = 0x00; + + cpuid = read_mpidr(); + boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); + NOTICE("BL31: Boot Core = %x\n", boot_core); + NOTICE("BL31: CPU ID = %x\n", cpuid); + +} + +/* Get non-secure image entrypoint for BL33. Zephyr and Linux */ +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_NS_IMAGE_OFFSET; +#endif +} + +/* Get non-secure SPSR for BL33. Zephyr and Linux */ +uint32_t arm_get_spsr_for_bl33_entry(void) +{ + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +/* SMP: Secondary cores BL31 setup reset vector */ +void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id) +{ + unsigned int pch_cpu = 0x00; + unsigned int pchctlr_old = 0x00; + unsigned int pchctlr_new = 0x00; + uint32_t boot_core = 0x00; + + boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); + /* Update the p-channel based on cpu id */ + pch_cpu = 1 << cpu_id; + + if (boot_core == 0x00) { + /* Update reset vector to 0x00 */ + mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2, +(uint64_t) plat_secondary_cpus_bl31_entry >> 2); + } else { + /* Update reset vector to 0x00 */ + mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0, +(uint64_t) plat_secondary_cpus_bl31_entry >> 2); + } + + /* Update reset vector to 0x00 */ + mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); + mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2); + + /* On all cores - temporary */ + pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); + pchctlr_new = pchctlr_old | (pch_cpu<<1); + mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new); + + /* We will only release the target secondary CPUs */ + /* Bit mask for each CPU BIT0-3 */ + mmio_write_32(RSTMGR_CPUSTRELEASE_CPUx, pch_cpu); +} + +void bl31_plat_set_secondary_cpu_off(void) +{ + unsigned int pch_cpu = 0x00; + unsigned int pch_cpu_off = 0x00; + unsigned int cpu_id = plat_my_core_pos(); + + pch_cpu_off = 1 << cpu_id; + + pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); + pch_cpu = pch_cpu & ~(pch_cpu_off << 1); + + mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu); +} + +void bl31_plat_enable_mmu(uint32_t flags) +{ + /* TODO: Enable mmu when needed */ +}
diff --git a/plat/intel/soc/agilex5/include/agilex5_clock_manager.h b/plat/intel/soc/agilex5/include/agilex5_clock_manager.h new file mode 100644 index 0000000..566a80d --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_clock_manager.h
@@ -0,0 +1,150 @@ +/* + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CLOCKMANAGER_H +#define CLOCKMANAGER_H + +#include "socfpga_handoff.h" + +/* Clock Manager Registers */ +#define CLKMGR_OFFSET 0x10d10000 + +#define CLKMGR_CTRL 0x0 +#define CLKMGR_STAT 0x4 +#define CLKMGR_TESTIOCTROL 0x8 +#define CLKMGR_INTRGEN 0xc +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20 + +/* Main PLL Group */ +#define CLKMGR_MAINPLL 0x10d10024 +#define CLKMGR_MAINPLL_EN 0x0 +#define CLKMGR_MAINPLL_ENS 0x4 +#define CLKMGR_MAINPLL_BYPASS 0xc +#define CLKMGR_MAINPLL_BYPASSS 0x10 +#define CLKMGR_MAINPLL_BYPASSR 0x14 +#define CLKMGR_MAINPLL_NOCCLK 0x1c +#define CLKMGR_MAINPLL_NOCDIV 0x20 +#define CLKMGR_MAINPLL_PLLGLOB 0x24 +#define CLKMGR_MAINPLL_FDBCK 0x28 +#define CLKMGR_MAINPLL_MEM 0x2c +#define CLKMGR_MAINPLL_MEMSTAT 0x30 +#define CLKMGR_MAINPLL_VCOCALIB 0x34 +#define CLKMGR_MAINPLL_PLLC0 0x38 +#define CLKMGR_MAINPLL_PLLC1 0x3c +#define CLKMGR_MAINPLL_PLLC2 0x40 +#define CLKMGR_MAINPLL_PLLC3 0x44 +#define CLKMGR_MAINPLL_PLLM 0x48 +#define CLKMGR_MAINPLL_FHOP 0x4c +#define CLKMGR_MAINPLL_SSC 0x50 +#define CLKMGR_MAINPLL_LOSTLOCK 0x54 + +/* Peripheral PLL Group */ +#define CLKMGR_PERPLL 0x10d1007c +#define CLKMGR_PERPLL_EN 0x0 +#define CLKMGR_PERPLL_ENS 0x4 +#define CLKMGR_PERPLL_BYPASS 0xc +#define CLKMGR_PERPLL_EMACCTL 0x18 +#define CLKMGR_PERPLL_GPIODIV 0x1c +#define CLKMGR_PERPLL_PLLGLOB 0x20 +#define CLKMGR_PERPLL_FDBCK 0x24 +#define CLKMGR_PERPLL_MEM 0x28 +#define CLKMGR_PERPLL_MEMSTAT 0x2c +#define CLKMGR_PERPLL_PLLC0 0x30 +#define CLKMGR_PERPLL_PLLC1 0x34 +#define CLKMGR_PERPLL_VCOCALIB 0x38 +#define CLKMGR_PERPLL_PLLC2 0x3c +#define CLKMGR_PERPLL_PLLC3 0x40 +#define CLKMGR_PERPLL_PLLM 0x44 +#define CLKMGR_PERPLL_LOSTLOCK 0x50 + +/* Altera Group */ +#define CLKMGR_ALTERA 0x10d100d0 +#define CLKMGR_ALTERA_JTAG 0x0 +#define CLKMGR_ALTERA_EMACACTR 0x4 +#define CLKMGR_ALTERA_EMACBCTR 0x8 +#define CLKMGR_ALTERA_EMACPTPCTR 0xc +#define CLKMGR_ALTERA_GPIODBCTR 0x10 +#define CLKMGR_ALTERA_S2FUSER0CTR 0x18 +#define CLKMGR_ALTERA_S2FUSER1CTR 0x1c +#define CLKMGR_ALTERA_PSIREFCTR 0x20 +#define CLKMGR_ALTERA_EXTCNTRST 0x24 +#define CLKMGR_ALTERA_USB31CTR 0x28 +#define CLKMGR_ALTERA_DSUCTR 0x2c +#define CLKMGR_ALTERA_CORE01CTR 0x30 +#define CLKMGR_ALTERA_CORE23CTR 0x34 +#define CLKMGR_ALTERA_CORE2CTR 0x38 +#define CLKMGR_ALTERA_CORE3CTR 0x3c + +/* Membus */ +#define CLKMGR_MEM_REQ BIT(24) +#define CLKMGR_MEM_WR BIT(25) +#define CLKMGR_MEM_ERR BIT(26) +#define CLKMGR_MEM_WDAT_OFFSET 16 +#define CLKMGR_MEM_ADDR 0x4027 +#define CLKMGR_MEM_WDAT 0x80 + +/* Clock Manager Macros */ +#define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 +#define CLKMGR_STAT_BUSY_E_BUSY 0x1 +#define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) +#define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) +#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) +#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 +#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 +#define CLKMGR_INTOSC_HZ 460000000 + +/* Main PLL Macros */ +#define CLKMGR_MAINPLL_EN_RESET 0x0000005e +#define CLKMGR_MAINPLL_ENS_RESET 0x0000005e + +/* Peripheral PLL Macros */ +#define CLKMGR_PERPLL_EN_RESET 0x040007FF +#define CLKMGR_PERPLL_ENS_RESET 0x040007FF + +#define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5) +#define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) + +/* Altera Macros */ +#define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff + +/* Shared Macros */ +#define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) +#define CLKMGR_PSRC_MAIN 0 +#define CLKMGR_PSRC_PER 1 + +#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 +#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 +#define CLKMGR_PLLGLOB_PSRC_F2S 0x2 + +#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) +#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001 +#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 + +#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) +#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) + +#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) +#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) + +#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 + +typedef struct { + uint32_t clk_freq_of_eosc1; + uint32_t clk_freq_of_f2h_free; + uint32_t clk_freq_of_cb_intosc_ls; +} CLOCK_SOURCE_CONFIG; + +void config_clkmgr_handoff(handoff *hoff_ptr); +uint32_t get_wdt_clk(void); +uint32_t get_uart_clk(void); +uint32_t get_mmc_clk(void); + +#endif
diff --git a/plat/intel/soc/agilex5/include/agilex5_memory_controller.h b/plat/intel/soc/agilex5/include/agilex5_memory_controller.h new file mode 100644 index 0000000..1708488 --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_memory_controller.h
@@ -0,0 +1,175 @@ +/* + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AGX_MEMORYCONTROLLER_H +#define AGX_MEMORYCONTROLLER_H + +#include "socfpga_plat_def.h" + +#define AGX_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8 +#define AGX_MPFE_IOHMC_CTRLCFG0 0xf8010028 +#define AGX_MPFE_IOHMC_CTRLCFG1 0xf801002c +#define AGX_MPFE_IOHMC_CTRLCFG2 0xf8010030 +#define AGX_MPFE_IOHMC_CTRLCFG3 0xf8010034 +#define AGX_MPFE_IOHMC_DRAMADDRW 0xf80100a8 +#define AGX_MPFE_IOHMC_DRAMTIMING0 0xf8010050 +#define AGX_MPFE_IOHMC_CALTIMING0 0xf801007c +#define AGX_MPFE_IOHMC_CALTIMING1 0xf8010080 +#define AGX_MPFE_IOHMC_CALTIMING2 0xf8010084 +#define AGX_MPFE_IOHMC_CALTIMING3 0xf8010088 +#define AGX_MPFE_IOHMC_CALTIMING4 0xf801008c +#define AGX_MPFE_IOHMC_CALTIMING9 0xf80100a0 +#define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) +#define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) (((value) & 0x00000060) >> 5) + +#define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100 +#define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104 +#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218 +#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x000000ff +#define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214 + + +#define AGX_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c + +#define AGX_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110 + +#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) +#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) +#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) +#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) +#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) + +#define AGX_MPFE_DDR(x) (0xf8000000 + x) +#define AGX_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c +#define AGX_MPFE_DDR_MAIN_SCHED 0xf8000400 +#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408 +#define AGX_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c +#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f +#define AGX_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c +#define AGX_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4 +#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0 +#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK (BIT(0) | BIT(1)) +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK (BIT(2) | BIT(3)) +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4 +#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK (BIT(4) | BIT(5)) + +#define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x)) +#define AGX_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210 +#define AGX_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008 +#define HMC_ADP_DDRIOCTRL 0x8 +#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) +#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9) +#define ADP_DRAMADDRWIDTH 0xe0 + +#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18) +#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) +#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0) +#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12) + +/* timing 2 */ +#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6) +#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24) +#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) +#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6) + +/* timing 3 */ +#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12) +#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) + +/* timing 4 */ +#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6) + +#define DDRTIMING_BWRATIO_OFST 31 +#define DDRTIMING_WRTORD_OFST 26 +#define DDRTIMING_RDTOWR_OFST 21 +#define DDRTIMING_BURSTLEN_OFST 18 +#define DDRTIMING_WRTOMISS_OFST 12 +#define DDRTIMING_RDTOMISS_OFST 6 +#define DDRTIMING_ACTTOACT_OFST 0 + +#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x3) >> 0) + +#define DDRMODE_AUTOPRECHARGE_OFST 1 +#define DDRMODE_BWRATIOEXTENDED_OFST 0 + + +#define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x7f) >> 0) +#define AGX_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0f) >> 0) + +#define AGX_CCU_CPU0_MPRT_DDR 0xf7004400 +#define AGX_CCU_CPU0_MPRT_MEM0 0xf70045c0 +#define AGX_CCU_CPU0_MPRT_MEM1A 0xf70045e0 +#define AGX_CCU_CPU0_MPRT_MEM1B 0xf7004600 +#define AGX_CCU_CPU0_MPRT_MEM1C 0xf7004620 +#define AGX_CCU_CPU0_MPRT_MEM1D 0xf7004640 +#define AGX_CCU_CPU0_MPRT_MEM1E 0xf7004660 +#define AGX_CCU_IOM_MPRT_MEM0 0xf7018560 +#define AGX_CCU_IOM_MPRT_MEM1A 0xf7018580 +#define AGX_CCU_IOM_MPRT_MEM1B 0xf70185a0 +#define AGX_CCU_IOM_MPRT_MEM1C 0xf70185c0 +#define AGX_CCU_IOM_MPRT_MEM1D 0xf70185e0 +#define AGX_CCU_IOM_MPRT_MEM1E 0xf7018600 + +#define AGX_NOC_FW_DDR_SCR 0xf8020200 +#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802021c +#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020218 +#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802029c +#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020298 + +#define AGX_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020200 +#define AGX_SOC_NOC_FW_DDR_SCR_ENABLESET 0xf8020204 +#define AGX_CCU_NOC_DI_SET_MSK 0x10 + +#define AGX_SYSMGR_CORE_HMC_CLK 0xffd120b4 +#define AGX_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001 + +#define AGX_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0xffff) >> 0) +#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003 +#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0 +#define AGX_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f +#define AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7 + +#define AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000 +#define AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100 +#define AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001 + +#define AGX_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001 +#define AGX_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000 +#define AGX_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100 +#define AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x1) >> 0) + + +#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00003) >> 0) +#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x03c00) >> 10) +#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0c000) >> 14) +#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0001f) >> 0) +#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x70000) >> 16) +#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x003e0) >> 5) + +#define AGX_SDRAM_0_LB_ADDR 0x0 +#define AGX_DDR_SIZE 0x40000000 + +/* Macros */ +#define SOCFPGA_MEMCTRL_ECCCTRL1 0x008 +#define SOCFPGA_MEMCTRL_ERRINTEN 0x010 +#define SOCFPGA_MEMCTRL_ERRINTENS 0x014 +#define SOCFPGA_MEMCTRL_ERRINTENR 0x018 +#define SOCFPGA_MEMCTRL_INTMODE 0x01C +#define SOCFPGA_MEMCTRL_INTSTAT 0x020 +#define SOCFPGA_MEMCTRL_DIAGINTTEST 0x024 +#define SOCFPGA_MEMCTRL_DERRADDRA 0x02C + +#define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \ + + (SOCFPGA_MEMCTRL_##_reg)) + +#endif
diff --git a/plat/intel/soc/agilex5/include/agilex5_mmc.h b/plat/intel/soc/agilex5/include/agilex5_mmc.h new file mode 100644 index 0000000..c8a5fba --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_mmc.h
@@ -0,0 +1,7 @@ +/* + * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +void agx5_mmc_init(void);
diff --git a/plat/intel/soc/agilex5/include/agilex5_pinmux.h b/plat/intel/soc/agilex5/include/agilex5_pinmux.h new file mode 100644 index 0000000..8a8e8c7 --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_pinmux.h
@@ -0,0 +1,202 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef AGX5_PINMUX_H +#define AGX5_PINMUX_H + +/* PINMUX REGISTER ADDRESS */ +#define AGX5_PINMUX_PIN0SEL 0x10d13000 +#define AGX5_PINMUX_IO0CTRL 0x10d13130 +#define AGX5_PINMUX_EMAC0_USEFPGA 0x10d13300 +#define AGX5_PINMUX_IO0_DELAY 0x10d13400 +#define AGX5_PERIPHERAL 0x10d14044 + +#include "socfpga_handoff.h" + +/* PINMUX DEFINE */ +#define PINMUX_HANDOFF_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define PINMUX_HANDOFF_CONFIG_ADDR 0xbeec +#define PINMUX_HANDOFF_CONFIG_VAL 0x7e000 + +/* Macros */ +#define SOCFPGA_PINMUX_SEL_NAND (0x03) +#define SOCFPGA_PINMUX_PIN0SEL (0x00) +#define SOCFPGA_PINMUX_PIN1SEL (0x04) +#define SOCFPGA_PINMUX_PIN2SEL (0x08) +#define SOCFPGA_PINMUX_PIN3SEL (0x0C) +#define SOCFPGA_PINMUX_PIN4SEL (0x10) +#define SOCFPGA_PINMUX_PIN5SEL (0x14) +#define SOCFPGA_PINMUX_PIN6SEL (0x18) +#define SOCFPGA_PINMUX_PIN7SEL (0x1C) +#define SOCFPGA_PINMUX_PIN8SEL (0x20) +#define SOCFPGA_PINMUX_PIN9SEL (0x24) +#define SOCFPGA_PINMUX_PIN10SEL (0x28) +#define SOCFPGA_PINMUX_PIN11SEL (0x2C) +#define SOCFPGA_PINMUX_PIN12SEL (0x30) +#define SOCFPGA_PINMUX_PIN13SEL (0x34) +#define SOCFPGA_PINMUX_PIN14SEL (0x38) +#define SOCFPGA_PINMUX_PIN15SEL (0x3C) +#define SOCFPGA_PINMUX_PIN16SEL (0x40) +#define SOCFPGA_PINMUX_PIN17SEL (0x44) +#define SOCFPGA_PINMUX_PIN18SEL (0x48) +#define SOCFPGA_PINMUX_PIN19SEL (0x4C) +#define SOCFPGA_PINMUX_PIN20SEL (0x50) +#define SOCFPGA_PINMUX_PIN21SEL (0x54) +#define SOCFPGA_PINMUX_PIN22SEL (0x58) +#define SOCFPGA_PINMUX_PIN23SEL (0x5C) +#define SOCFPGA_PINMUX_PIN24SEL (0x60) +#define SOCFPGA_PINMUX_PIN25SEL (0x64) +#define SOCFPGA_PINMUX_PIN26SEL (0x68) +#define SOCFPGA_PINMUX_PIN27SEL (0x6C) +#define SOCFPGA_PINMUX_PIN28SEL (0x70) +#define SOCFPGA_PINMUX_PIN29SEL (0x74) +#define SOCFPGA_PINMUX_PIN30SEL (0x78) +#define SOCFPGA_PINMUX_PIN31SEL (0x7C) +#define SOCFPGA_PINMUX_PIN32SEL (0x80) +#define SOCFPGA_PINMUX_PIN33SEL (0x84) +#define SOCFPGA_PINMUX_PIN34SEL (0x88) +#define SOCFPGA_PINMUX_PIN35SEL (0x8C) +#define SOCFPGA_PINMUX_PIN36SEL (0x90) +#define SOCFPGA_PINMUX_PIN37SEL (0x94) +#define SOCFPGA_PINMUX_PIN38SEL (0x98) +#define SOCFPGA_PINMUX_PIN39SEL (0x9C) +#define SOCFPGA_PINMUX_PIN40SEL (0x100) +#define SOCFPGA_PINMUX_PIN41SEL (0x104) +#define SOCFPGA_PINMUX_PIN42SEL (0x108) +#define SOCFPGA_PINMUX_PIN43SEL (0x10C) +#define SOCFPGA_PINMUX_PIN44SEL (0x110) +#define SOCFPGA_PINMUX_PIN45SEL (0x114) +#define SOCFPGA_PINMUX_PIN46SEL (0x118) +#define SOCFPGA_PINMUX_PIN47SEL (0x11C) + +#define SOCFPGA_PINMUX_IO0CTRL (0x00) +#define SOCFPGA_PINMUX_IO1CTRL (0x04) +#define SOCFPGA_PINMUX_IO2CTRL (0x08) +#define SOCFPGA_PINMUX_IO3CTRL (0x0C) +#define SOCFPGA_PINMUX_IO4CTRL (0x10) +#define SOCFPGA_PINMUX_IO5CTRL (0x14) +#define SOCFPGA_PINMUX_IO6CTRL (0x18) +#define SOCFPGA_PINMUX_IO7CTRL (0x1C) +#define SOCFPGA_PINMUX_IO8CTRL (0x20) +#define SOCFPGA_PINMUX_IO9CTRL (0x24) +#define SOCFPGA_PINMUX_IO10CTRL (0x28) +#define SOCFPGA_PINMUX_IO11CTRL (0x2C) +#define SOCFPGA_PINMUX_IO12CTRL (0x30) +#define SOCFPGA_PINMUX_IO13CTRL (0x34) +#define SOCFPGA_PINMUX_IO14CTRL (0x38) +#define SOCFPGA_PINMUX_IO15CTRL (0x3C) +#define SOCFPGA_PINMUX_IO16CTRL (0x40) +#define SOCFPGA_PINMUX_IO17CTRL (0x44) +#define SOCFPGA_PINMUX_IO18CTRL (0x48) +#define SOCFPGA_PINMUX_IO19CTRL (0x4C) +#define SOCFPGA_PINMUX_IO20CTRL (0x50) +#define SOCFPGA_PINMUX_IO21CTRL (0x54) +#define SOCFPGA_PINMUX_IO22CTRL (0x58) +#define SOCFPGA_PINMUX_IO23CTRL (0x5C) +#define SOCFPGA_PINMUX_IO24CTRL (0x60) +#define SOCFPGA_PINMUX_IO25CTRL (0x64) +#define SOCFPGA_PINMUX_IO26CTRL (0x68) +#define SOCFPGA_PINMUX_IO27CTRL (0x6C) +#define SOCFPGA_PINMUX_IO28CTRL (0xD0) +#define SOCFPGA_PINMUX_IO29CTRL (0xD4) +#define SOCFPGA_PINMUX_IO30CTRL (0xD8) +#define SOCFPGA_PINMUX_IO31CTRL (0xDC) +#define SOCFPGA_PINMUX_IO32CTRL (0xE0) +#define SOCFPGA_PINMUX_IO33CTRL (0xE4) +#define SOCFPGA_PINMUX_IO34CTRL (0xE8) +#define SOCFPGA_PINMUX_IO35CTRL (0xEC) +#define SOCFPGA_PINMUX_IO36CTRL (0xF0) +#define SOCFPGA_PINMUX_IO37CTRL (0xF4) +#define SOCFPGA_PINMUX_IO38CTRL (0xF8) +#define SOCFPGA_PINMUX_IO39CTRL (0xFC) +#define SOCFPGA_PINMUX_IO40CTRL (0x100) +#define SOCFPGA_PINMUX_IO41CTRL (0x104) +#define SOCFPGA_PINMUX_IO42CTRL (0x108) +#define SOCFPGA_PINMUX_IO43CTRL (0x10C) +#define SOCFPGA_PINMUX_IO44CTRL (0x110) +#define SOCFPGA_PINMUX_IO45CTRL (0x114) +#define SOCFPGA_PINMUX_IO46CTRL (0x118) +#define SOCFPGA_PINMUX_IO47CTRL (0x11C) + +#define SOCFPGA_PINMUX_EMAC0_USEFPGA (0x00) +#define SOCFPGA_PINMUX_EMAC1_USEFPGA (0x04) +#define SOCFPGA_PINMUX_EMAC2_USEFPGA (0x08) +#define SOCFPGA_PINMUX_I2C0_USEFPGA (0x0C) +#define SOCFPGA_PINMUX_I2C1_USEFPGA (0x10) +#define SOCFPGA_PINMUX_I2C_EMAC0_USEFPGA (0x14) +#define SOCFPGA_PINMUX_I2C_EMAC1_USEFPGA (0x18) +#define SOCFPGA_PINMUX_I2C_EMAC2_USEFPGA (0x1C) +#define SOCFPGA_PINMUX_NAND_USEFPGA (0x20) +#define SOCFPGA_PINMUX_SPIM0_USEFPGA (0x28) +#define SOCFPGA_PINMUX_SPIM1_USEFPGA (0x2C) +#define SOCFPGA_PINMUX_SPIS0_USEFPGA (0x30) +#define SOCFPGA_PINMUX_SPIS1_USEFPGA (0x34) +#define SOCFPGA_PINMUX_UART0_USEFPGA (0x38) +#define SOCFPGA_PINMUX_UART1_USEFPGA (0x3C) +#define SOCFPGA_PINMUX_MDIO0_USEFPGA (0x40) +#define SOCFPGA_PINMUX_MDIO1_USEFPGA (0x44) +#define SOCFPGA_PINMUX_MDIO2_USEFPGA (0x48) +#define SOCFPGA_PINMUX_JTAG_USEFPGA (0x50) +#define SOCFPGA_PINMUX_SDMMC_USEFPGA (0x54) + +#define SOCFPGA_PINMUX_IO0DELAY (0x00) +#define SOCFPGA_PINMUX_IO1DELAY (0x04) +#define SOCFPGA_PINMUX_IO2DELAY (0x08) +#define SOCFPGA_PINMUX_IO3DELAY (0x0C) +#define SOCFPGA_PINMUX_IO4DELAY (0x10) +#define SOCFPGA_PINMUX_IO5DELAY (0x14) +#define SOCFPGA_PINMUX_IO6DELAY (0x18) +#define SOCFPGA_PINMUX_IO7DELAY (0x1C) +#define SOCFPGA_PINMUX_IO8DELAY (0x20) +#define SOCFPGA_PINMUX_IO9DELAY (0x24) +#define SOCFPGA_PINMUX_IO10DELAY (0x28) +#define SOCFPGA_PINMUX_IO11DELAY (0x2C) +#define SOCFPGA_PINMUX_IO12DELAY (0x30) +#define SOCFPGA_PINMUX_IO13DELAY (0x34) +#define SOCFPGA_PINMUX_IO14DELAY (0x38) +#define SOCFPGA_PINMUX_IO15DELAY (0x3C) +#define SOCFPGA_PINMUX_IO16DELAY (0x40) +#define SOCFPGA_PINMUX_IO17DELAY (0x44) +#define SOCFPGA_PINMUX_IO18DELAY (0x48) +#define SOCFPGA_PINMUX_IO19DELAY (0x4C) +#define SOCFPGA_PINMUX_IO20DELAY (0x50) +#define SOCFPGA_PINMUX_IO21DELAY (0x54) +#define SOCFPGA_PINMUX_IO22DELAY (0x58) +#define SOCFPGA_PINMUX_IO23DELAY (0x5C) +#define SOCFPGA_PINMUX_IO24DELAY (0x60) +#define SOCFPGA_PINMUX_IO25DELAY (0x64) +#define SOCFPGA_PINMUX_IO26DELAY (0x68) +#define SOCFPGA_PINMUX_IO27DELAY (0x6C) +#define SOCFPGA_PINMUX_IO28DELAY (0x70) +#define SOCFPGA_PINMUX_IO29DELAY (0x74) +#define SOCFPGA_PINMUX_IO30DELAY (0x78) +#define SOCFPGA_PINMUX_IO31DELAY (0x7C) +#define SOCFPGA_PINMUX_IO32DELAY (0x80) +#define SOCFPGA_PINMUX_IO33DELAY (0x84) +#define SOCFPGA_PINMUX_IO34DELAY (0x88) +#define SOCFPGA_PINMUX_IO35DELAY (0x8C) +#define SOCFPGA_PINMUX_IO36DELAY (0x90) +#define SOCFPGA_PINMUX_IO37DELAY (0x94) +#define SOCFPGA_PINMUX_IO38DELAY (0x98) +#define SOCFPGA_PINMUX_IO39DELAY (0x9C) +#define SOCFPGA_PINMUX_IO40DELAY (0xA0) +#define SOCFPGA_PINMUX_IO41DELAY (0xA4) +#define SOCFPGA_PINMUX_IO42DELAY (0xA8) +#define SOCFPGA_PINMUX_IO43DELAY (0xAC) +#define SOCFPGA_PINMUX_IO44DELAY (0xB0) +#define SOCFPGA_PINMUX_IO45DELAY (0xB4) +#define SOCFPGA_PINMUX_IO46DELAY (0xB8) +#define SOCFPGA_PINMUX_IO47DELAY (0xBC) + +#define SOCFPGA_PINMUX_I3C0_USEFPGA (0xC0) +#define SOCFPGA_PINMUX_I3C1_USEFPGA (0xC4) + +#define SOCFPGA_PINMUX(_reg) (SOCFPGA_PINMUX_REG_BASE \ + + (SOCFPGA_PINMUX_##_reg)) + +void config_pinmux(handoff *handoff); +void config_peripheral(handoff *handoff); +#endif
diff --git a/plat/intel/soc/agilex5/include/agilex5_power_manager.h b/plat/intel/soc/agilex5/include/agilex5_power_manager.h new file mode 100644 index 0000000..1bba74b --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_power_manager.h
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef POWERMANAGER_H +#define POWERMANAGER_H + +#include "socfpga_handoff.h" + +#define AGX5_PWRMGR_BASE 0x10d14000 + +/* DSU */ +#define AGX5_PWRMGR_DSU_FWENCTL 0x0 +#define AGX5_PWRMGR_DSU_PGENCTL 0x4 +#define AGX5_PWRMGR_DSU_PGSTAT 0x8 +#define AGX5_PWRMGR_DSU_PWRCTLR 0xc +#define AGX5_PWRMGR_DSU_PWRSTAT0 0x10 +#define AGX5_PWRMGR_DSU_PWRSTAT1 0x14 + +/* DSU Macros*/ +#define AGX5_PWRMGR_DSU_FWEN(x) ((x) & 0xf) +#define AGX5_PWRMGR_DSU_PGEN(x) ((x) & 0xf) +#define AGX5_PWRMGR_DSU_PGEN_OUT(x) ((x) & 0xf) +#define AGX5_PWRMGR_DSU_SINGLE_PACCEPT(x) ((x) & 0x1) +#define AGX5_PWRMGR_DSU_SINGLE_PDENY(x) (((x) & 0x1) << 1) +#define AGX5_PWRMGR_DSU_SINGLE_FSM_STATE(x) (((x) & 0xff) << 8) +#define AGX5_PWRMGR_DSU_SINGLE_PCH_DONE(x) (((x) & 0x1) << 31) +#define AGX5_PWRMGR_DSU_MULTI_PACTIVE_IN(x) ((x) & 0xff) +#define AGX5_PWRMGR_DSU_MULTI_PACCEPT(x) (((x) & 0xff) << 8) +#define AGX5_PWRMGR_DSU_MULTI_PDENY(x) (((x) & 0xff) << 16) +#define AGX5_PWRMGR_DSU_MULTI_PCH_DONE(x) (((x) & 0x1) << 31) + +/* CPU */ +#define AGX5_PWRMGR_CPU_PWRCTLR0 0x18 +#define AGX5_PWRMGR_CPU_PWRCTLR1 0x20 +#define AGX5_PWRMGR_CPU_PWRCTLR2 0x28 +#define AGX5_PWRMGR_CPU_PWRCTLR3 0x30 +#define AGX5_PWRMGR_CPU_PWRSTAT0 0x1c +#define AGX5_PWRMGR_CPU_PWRSTAT1 0x24 +#define AGX5_PWRMGR_CPU_PWRSTAT2 0x2c +#define AGX5_PWRMGR_CPU_PWRSTAT3 0x34 + +/* APS */ +#define AGX5_PWRMGR_APS_FWENCTL 0x38 +#define AGX5_PWRMGR_APS_PGENCTL 0x3C +#define AGX5_PWRMGR_APS_PGSTAT 0x40 + +/* PSS */ +#define AGX5_PWRMGR_PSS_FWENCTL 0x44 +#define AGX5_PWRMGR_PSS_PGENCTL 0x48 +#define AGX5_PWRMGR_PSS_PGSTAT 0x4c + +/* PSS Macros*/ +#define AGX5_PWRMGR_PSS_FWEN(x) ((x) & 0xff) +#define AGX5_PWRMGR_PSS_PGEN(x) ((x) & 0xff) +#define AGX5_PWRMGR_PSS_PGEN_OUT(x) ((x) & 0xff) + +/* MPU */ +#define AGX5_PWRMGR_MPU_PCHCTLR 0x50 +#define AGX5_PWRMGR_MPU_PCHSTAT 0x54 +#define AGX5_PWRMGR_MPU_BOOTCONFIG 0x58 +#define AGX5_PWRMGR_CPU_POWER_STATE_MASK 0x1E + +/* MPU Macros*/ +#define AGX5_PWRMGR_MPU_TRIGGER_PCH_DSU(x) ((x) & 0x1) +#define AGX5_PWRMGR_MPU_TRIGGER_PCH_CPU(x) (((x) & 0xf) << 1) +#define AGX5_PWRMGR_MPU_STATUS_PCH_CPU(x) (((x) & 0xf) << 1) + +/* Shared Macros */ +#define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ + (AGX5_PWRMGR_##_reg)) + +/* POWER MANAGER ERROR CODE */ +#define AGX5_PWRMGR_HANDOFF_PERIPHERAL -1 +#define AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY 0x0 +#define AGX5_PWRMGR_PSS_STAT_BUSY(x) (((x) & 0x000000FF) >> 0) + +int pss_sram_power_off(handoff *hoff_ptr); +int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff); + +#endif
diff --git a/plat/intel/soc/agilex5/include/agilex5_system_manager.h b/plat/intel/soc/agilex5/include/agilex5_system_manager.h new file mode 100644 index 0000000..9a58cdb --- /dev/null +++ b/plat/intel/soc/agilex5/include/agilex5_system_manager.h
@@ -0,0 +1,200 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef AGX5_SOCFPGA_SYSTEMMANAGER_H +#define AGX5_SOCFPGA_SYSTEMMANAGER_H + +#include "socfpga_plat_def.h" + +/* System Manager Register Map */ +#define SOCFPGA_SYSMGR_SILICONID_1 0x00 +#define SOCFPGA_SYSMGR_SILICONID_2 0x04 +#define SOCFPGA_SYSMGR_WDDBG 0x08 +#define SOCFPGA_SYSMGR_MPU_STATUS 0x10 +#define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C +#define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34 +#define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38 +#define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C +#define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40 +#define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */ +#define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */ +#define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */ +#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50 +#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54 +#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68 +#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C +#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 +#define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74 +#define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78 +#define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C +#define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80 +#define SOCFPGA_SYSMGR_OSC_TRIM 0x84 +#define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88 +#define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C +#define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94 +#define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98 +#define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C +#define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0 +/* NOC configuration value */ +#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8 +#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC +#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0 +#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4 +#define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8 +#define SOCFPGA_SYSMGR_FPGA_CFG 0xDC +#define SOCFPGA_SYSMGR_GPO 0xE4 +#define SOCFPGA_SYSMGR_GPI 0xE8 +#define SOCFPGA_SYSMGR_MPU 0xF0 +#define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4 +#define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8 +#define SOCFPGA_SYSMGR_DFI_INTF 0xFC +#define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100 +#define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104 +#define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108 +#define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C +#define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110 +#define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118 +#define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120 +#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124 +#define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128 +#define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C +#define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130 +#define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134 +#define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138 +#define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C +#define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144 +#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148 +#define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150 +#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154 +#define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168 +#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174 +#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180 +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0 +#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8 +#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC +#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8 +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC +#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0 +#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4 + +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 +#define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228 +#define SOCFPGA_SYSMGR_MPFE_status 0x22C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278 +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C + +#define DMA0_STREAM_CTRL_REG 0x10D1217C +#define DMA1_STREAM_CTRL_REG 0x10D12180 +#define SDM_STREAM_CTRL_REG 0x10D12184 +#define USB2_STREAM_CTRL_REG 0x10D12188 +#define USB3_STREAM_CTRL_REG 0x10D1218C +#define SDMMC_STREAM_CTRL_REG 0x10D12190 +#define NAND_STREAM_CTRL_REG 0x10D12194 +#define ETR_STREAM_CTRL_REG 0x10D12198 +#define TSN0_STREAM_CTRL_REG 0x10D1219C +#define TSN1_STREAM_CTRL_REG 0x10D121A0 +#define TSN2_STREAM_CTRL_REG 0x10D121A4 + +/* Stream ID configuration value for Agilex5 */ +#define TSN0 0x00010001 +#define TSN1 0x00020002 +#define TSN2 0x00030003 +#define NAND 0x00040004 +#define SDMMC 0x00050005 +#define USB0 0x00060006 +#define USB1 0x00070007 +#define DMA0 0x00080008 +#define DMA1 0x00090009 +#define SDM 0x000A000A +#define CORE_SIGHT_DEBUG 0x000B000B + +/* Field Masking */ +#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) +#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) + +#define SYSMGR_F2S_BRIDGE_CTRL_EN BIT(0) +#define IDLE_DATA_LWSOC2FPGA BIT(4) +#define IDLE_DATA_SOC2FPGA BIT(0) +#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA \ + | IDLE_DATA_SOC2FPGA) +#define SYSMGR_ECC_OCRAM_MASK BIT(1) +#define SYSMGR_ECC_DDR0_MASK BIT(16) +#define SYSMGR_ECC_DDR1_MASK BIT(17) + +#define WSTREAMIDEN_REG_CTRL BIT(0) +#define RSTREAMIDEN_REG_CTRL BIT(1) +#define WMMUSECSID_REG_VAL BIT(4) +#define RMMUSECSID_REG_VAL BIT(5) + +/* Macros */ +#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ + + (SOCFPGA_SYSMGR_##_reg)) + +#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL \ + | RSTREAMIDEN_REG_CTRL +#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL \ + | RSTREAMIDEN_REG_CTRL \ + | WMMUSECSID_REG_VAL \ + | RMMUSECSID_REG_VAL + +#endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h new file mode 100644 index 0000000..8a49d61 --- /dev/null +++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -0,0 +1,119 @@ +/* + * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef PLAT_SOCFPGA_DEF_H +#define PLAT_SOCFPGA_DEF_H + +#include "agilex5_memory_controller.h" +#include "agilex5_system_manager.h" +#include <platform_def.h> + +/* Platform Setting */ +#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 +#define BOOT_SOURCE BOOT_SOURCE_SDMMC +#define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ +#define XLAT_TABLES_V2 U(1) +#define PLAT_PRIMARY_CPU_A55 0x000 +#define PLAT_PRIMARY_CPU_A76 0x200 +#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT +#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT +#define PLAT_L2_RESET_REQ 0xB007C0DE + +/* System Counter */ /* TODO: Update back to 400MHz */ +#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (80000000) +#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (80) + +/* FPGA config helpers */ +#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 +#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000 + +/* QSPI Setting */ +#define CAD_QSPIDATA_OFST 0x10900000 +#define CAD_QSPI_OFFSET 0x108d2000 + +/* Register Mapping */ +#define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 +#define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 + +#define SOCFPGA_MMC_REG_BASE 0x10808000 +#define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 +#define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 +#define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 +#define SOCFPGA_PINMUX_REG_BASE 0x10d13000 +#define SOCFPGA_NAND_REG_BASE 0x10B80000 + +#define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 +#define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 +#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 +#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 + +/* Define maximum page size for NAND flash devices */ +#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +#define DRAM_BASE (0x80000000) +#define DRAM_SIZE (0x80000000) + +#define OCRAM_BASE (0x00000000) +#define OCRAM_SIZE (0x00080000) + +#define MEM64_BASE (0x0080000000) +#define MEM64_SIZE (0x0080000000) + +//128MB PSS +#define PSS_BASE (0x10000000) +#define PSS_SIZE (0x08000000) + +//64MB MPFE +#define MPFE_BASE (0x18000000) +#define MPFE_SIZE (0x04000000) + +//16MB CCU +#define CCU_BASE (0x1C000000) +#define CCU_SIZE (0x01000000) + +//1MB GIC +#define GIC_BASE (0x1D000000) +#define GIC_SIZE (0x00100000) + +#define BL2_BASE (0x00000000) +#define BL2_LIMIT (0x0001b000) + +#define BL31_BASE (0x80000000) +#define BL31_LIMIT (0x82000000) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define PLAT_UART0_BASE (0x10C02000) +#define PLAT_UART1_BASE (0x10C02100) + +/******************************************************************************* + * GIC related constants + ******************************************************************************/ +#define PLAT_GIC_BASE (0x1D000000) +#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) +#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) +#define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) + +#define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE + +/******************************************************************************* + * SDMMC related pointer function + ******************************************************************************/ +#define SDMMC_READ_BLOCKS sdmmc_read_blocks +#define SDMMC_WRITE_BLOCKS sdmmc_write_blocks + +/******************************************************************************* + * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset + * is done and HPS should trigger warm reset via RMR_EL3. + ******************************************************************************/ +#define L2_RESET_DONE_REG 0x10D12218 + +#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk new file mode 100644 index 0000000..546bc2e --- /dev/null +++ b/plat/intel/soc/agilex5/platform.mk
@@ -0,0 +1,106 @@ +# +# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2019-2023, Intel Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause +# +include lib/xlat_tables_v2/xlat_tables.mk +PLAT_INCLUDES := \ + -Iplat/intel/soc/agilex5/include/ \ + -Iplat/intel/soc/common/drivers/ \ + -Iplat/intel/soc/common/include/ + +# GIC-600 configuration +GICV3_SUPPORT_GIC600 := 1 +# Include GICv3 driver files +include drivers/arm/gic/v3/gicv3.mk +AGX5_GICv3_SOURCES := \ + ${GICV3_SOURCES} \ + plat/common/plat_gicv3.c + +PLAT_BL_COMMON_SOURCES := \ + ${AGX5_GICv3_SOURCES} \ + drivers/cadence/combo_phy/cdns_combo_phy.c \ + drivers/cadence/emmc/cdns_sdmmc.c \ + drivers/cadence/nand/cdns_nand.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/ti/uart/aarch64/16550_console.S \ + plat/intel/soc/common/aarch64/platform_common.c \ + plat/intel/soc/common/aarch64/plat_helpers.S \ + plat/intel/soc/common/drivers/ccu/ncore_ccu.c \ + plat/intel/soc/common/drivers/combophy/combophy.c \ + plat/intel/soc/common/drivers/sdmmc/sdmmc.c \ + plat/intel/soc/common/drivers/ddr/ddr.c \ + plat/intel/soc/common/drivers/nand/nand.c \ + plat/intel/soc/common/socfpga_delay_timer.c + +BL2_SOURCES += \ + common/desc_image_load.c \ + lib/xlat_tables_v2/aarch64/enable_mmu.S \ + lib/xlat_tables_v2/xlat_tables_context.c \ + lib/xlat_tables_v2/xlat_tables_core.c \ + lib/xlat_tables_v2/aarch64/xlat_tables_arch.c \ + lib/xlat_tables_v2/xlat_tables_utils.c \ + drivers/mmc/mmc.c \ + drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \ + drivers/io/io_storage.c \ + drivers/io/io_block.c \ + drivers/io/io_fip.c \ + drivers/io/io_mtd.c \ + drivers/partition/partition.c \ + drivers/partition/gpt.c \ + drivers/synopsys/emmc/dw_mmc.c \ + lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a76.S \ + plat/intel/soc/agilex5/soc/agilex5_clock_manager.c \ + plat/intel/soc/agilex5/soc/agilex5_memory_controller.c \ + plat/intel/soc/agilex5/soc/agilex5_mmc.c \ + plat/intel/soc/agilex5/soc/agilex5_pinmux.c \ + plat/intel/soc/agilex5/soc/agilex5_power_manager.c \ + plat/intel/soc/common/bl2_plat_mem_params_desc.c \ + plat/intel/soc/common/socfpga_image_load.c \ + plat/intel/soc/common/socfpga_storage.c \ + plat/intel/soc/common/socfpga_vab.c \ + plat/intel/soc/common/soc/socfpga_emac.c \ + plat/intel/soc/common/soc/socfpga_firewall.c \ + plat/intel/soc/common/soc/socfpga_handoff.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c \ + plat/intel/soc/common/drivers/qspi/cadence_qspi.c \ + plat/intel/soc/agilex5/bl2_plat_setup.c \ + plat/intel/soc/common/drivers/wdt/watchdog.c + +include lib/zlib/zlib.mk +PLAT_INCLUDES += -Ilib/zlib +BL2_SOURCES += $(ZLIB_SOURCES) + +BL31_SOURCES += \ + drivers/arm/cci/cci.c \ + ${XLAT_TABLES_LIB_SRCS} \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a76.S \ + plat/common/plat_psci_common.c \ + plat/intel/soc/agilex5/bl31_plat_setup.c \ + plat/intel/soc/agilex5/soc/agilex5_power_manager.c \ + plat/intel/soc/common/socfpga_psci.c \ + plat/intel/soc/common/socfpga_sip_svc.c \ + plat/intel/soc/common/socfpga_sip_svc_v2.c \ + plat/intel/soc/common/socfpga_topology.c \ + plat/intel/soc/common/sip/socfpga_sip_ecc.c \ + plat/intel/soc/common/sip/socfpga_sip_fcs.c \ + plat/intel/soc/common/soc/socfpga_mailbox.c \ + plat/intel/soc/common/soc/socfpga_reset_manager.c + +# Configs for A76 and A55 +HW_ASSISTED_COHERENCY := 1 +USE_COHERENT_MEM := 0 +CTX_INCLUDE_AARCH32_REGS := 0 +ERRATA_A55_1530923 := 1 + +$(eval $(call add_define,ARM_PRELOADED_DTB_BASE)) + +PROGRAMMABLE_RESET_ADDRESS := 0 +RESET_TO_BL2 := 1 +BL2_INV_DCACHE := 0
diff --git a/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c new file mode 100644 index 0000000..cc68153 --- /dev/null +++ b/plat/intel/soc/agilex5/soc/agilex5_clock_manager.c
@@ -0,0 +1,253 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> + +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> + +#include "agilex5_clock_manager.h" +#include "agilex5_system_manager.h" +#include "socfpga_handoff.h" + +uint32_t wait_pll_lock(void) +{ + uint32_t data; + uint32_t count = 0; + + do { + data = mmio_read_32(CLKMGR_OFFSET + CLKMGR_STAT); + count++; + if (count >= 1000) + return -ETIMEDOUT; + + } while ((CLKMGR_STAT_MAINPLLLOCKED(data) == 0) || + (CLKMGR_STAT_PERPLLLOCKED(data) == 0)); + return 0; +} + +uint32_t wait_fsm(void) +{ + uint32_t data; + uint32_t count = 0; + + do { + data = mmio_read_32(CLKMGR_OFFSET + CLKMGR_STAT); + count++; + if (count >= 1000) + return -ETIMEDOUT; + + } while (CLKMGR_STAT_BUSY(data) == CLKMGR_STAT_BUSY_E_BUSY); + + return 0; +} + +uint32_t pll_source_sync_config(uint32_t pll_mem_offset, uint32_t data) +{ + uint32_t val = 0; + uint32_t count = 0; + uint32_t req_status = 0; + + val = (CLKMGR_MEM_WR | CLKMGR_MEM_REQ | + (data << CLKMGR_MEM_WDAT_OFFSET) | CLKMGR_MEM_ADDR); + mmio_write_32(pll_mem_offset, val); + + do { + req_status = mmio_read_32(pll_mem_offset); + count++; + } while ((req_status & CLKMGR_MEM_REQ) && (count < 10)); + + if (count >= 10) + return -ETIMEDOUT; + + return 0; +} + +uint32_t pll_source_sync_read(uint32_t pll_mem_offset) +{ + uint32_t val = 0; + uint32_t rdata = 0; + uint32_t count = 0; + uint32_t req_status = 0; + + val = (CLKMGR_MEM_REQ | CLKMGR_MEM_ADDR); + mmio_write_32(pll_mem_offset, val); + + do { + req_status = mmio_read_32(pll_mem_offset); + count++; + } while ((req_status & CLKMGR_MEM_REQ) && (count < 10)); + + if (count >= 10) + return -ETIMEDOUT; + + rdata = mmio_read_32(pll_mem_offset + 0x4); + INFO("rdata (%x) = %x\n", pll_mem_offset + 0x4, rdata); + + return rdata; +} + +void config_clkmgr_handoff(handoff *hoff_ptr) +{ + /* Take both PLL out of reset and power up */ + + mmio_setbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_SET_MSK | + CLKMGR_PLLGLOB_RST_SET_MSK); + mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_SET_MSK | + CLKMGR_PLLGLOB_RST_SET_MSK); + + /* PLL lock */ + wait_pll_lock(); + + /* Bypass all mainpllgrp's clocks to input clock ref */ + mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASSS, 0xff); + /* Bypass all perpllgrp's clocks to input clock ref */ + mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_BYPASS, 0xff); + + /* Pass clock source frequency into scratch register */ + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1), + hoff_ptr->hps_osc_clk_hz); + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2), + hoff_ptr->fpga_clk_hz); + + /* Take all PLLs out of bypass */ + mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0); + wait_fsm(); + mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_BYPASS, 0); + wait_fsm(); + + /* Enable mainpllgrp's software-managed clock */ + mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_EN, + CLKMGR_MAINPLL_EN_RESET); + mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, + CLKMGR_PERPLL_EN_RESET); +} + +/* Extract reference clock from platform clock source */ +uint32_t get_ref_clk(uint32_t pllglob) +{ + uint32_t arefclkdiv, ref_clk; + uint32_t scr_reg; + + switch (CLKMGR_PSRC(pllglob)) { + case CLKMGR_PLLGLOB_PSRC_EOSC1: + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1); + ref_clk = mmio_read_32(scr_reg); + break; + case CLKMGR_PLLGLOB_PSRC_INTOSC: + ref_clk = CLKMGR_INTOSC_HZ; + break; + case CLKMGR_PLLGLOB_PSRC_F2S: + scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2); + ref_clk = mmio_read_32(scr_reg); + break; + default: + ref_clk = 0; + assert(0); + break; + } + + arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob); + ref_clk /= arefclkdiv; + + return ref_clk; +} + +/* Calculate clock frequency based on parameter */ +uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc) +{ + uint32_t ref_clk = 0; + + uint32_t clk_psrc, mdiv; + uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; + + + clk_psrc = mmio_read_32(CLKMGR_MAINPLL + psrc_reg); + clk_psrc = 0; + + switch (clk_psrc) { + case 0: + pllm_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM; + pllc_reg = CLKMGR_MAINPLL + main_pllc; + pllglob_reg = CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB; + break; + } + + ref_clk = get_ref_clk(mmio_read_32(pllglob_reg)); + mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg)); + ref_clk *= mdiv; + + pllc_div = mmio_read_32(pllc_reg) & 0x7ff; + NOTICE("return = %d Hz\n", (ref_clk / pllc_div)); + + ref_clk = 200000000; + return (uint32_t) ref_clk; + +} + +/* Return L3 interconnect clock */ +uint32_t get_l3_clk(void) +{ + uint32_t l3_clk; + + l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1, + CLKMGR_PERPLL_PLLC1); + return l3_clk; +} + +/* Calculate clock frequency to be used for watchdog timer */ +uint32_t get_wdt_clk(void) +{ + uint32_t l3_clk, l4_sys_clk; + + l3_clk = get_l3_clk(); + l4_sys_clk = l3_clk / 4; + + return l4_sys_clk; +} + +/* Calculate clock frequency to be used for UART driver */ +uint32_t get_uart_clk(void) +{ + uint32_t data32, l3_clk, l4_sp_clk; + + l3_clk = get_l3_clk(); + + data32 = mmio_read_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_NOCDIV); + data32 = (data32 >> 16) & 0x3; + + l4_sp_clk = l3_clk >> data32; + + return l4_sp_clk; +} + +/* Calculate clock frequency to be used for SDMMC driver */ +uint32_t get_mmc_clk(void) +{ + uint32_t mmc_clk; + + //TODO: To update when handoff data is ready + //uint32_t data32; + + //mmc_clk = get_clk_freq(CLKMGR_ALTERA_SDMMCCTR, CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3); + + //data32 = mmio_read_32(CLKMGR_ALTERA + CLKMGR_ALTERA_SDMMCCTR); + //data32 = (data32 & 0x7ff) + 1; + //mmc_clk = (mmc_clk / data32) / 4; + + + mmc_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC3, + CLKMGR_PERPLL_PLLC3); + + // TODO: To update when handoff data is ready + NOTICE("mmc_clk = %d Hz\n", mmc_clk); + + return mmc_clk; +}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_memory_controller.c b/plat/intel/soc/agilex5/soc/agilex5_memory_controller.c new file mode 100644 index 0000000..0ddff4a --- /dev/null +++ b/plat/intel/soc/agilex5/soc/agilex5_memory_controller.c
@@ -0,0 +1,400 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <errno.h> + +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +#include "agilex5_memory_controller.h" +#include <platform_def.h> + +#define ALT_CCU_NOC_DI_SET_MSK 0x10 + +#define DDR_READ_LATENCY_DELAY 40 +#define MAX_MEM_CAL_RETRY 3 +#define PRE_CALIBRATION_DELAY 1 +#define POST_CALIBRATION_DELAY 1 +#define TIMEOUT_EMIF_CALIBRATION 1000 +#define CLEAR_EMIF_DELAY 1000 +#define CLEAR_EMIF_TIMEOUT 1000 + +#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) +#define DDR_CONFIG_ELEMENTS (ARRAY_SIZE(ddr_config)) + +/* tWR = Min. 15ns constant, see JEDEC standard eg. DDR4 is JESD79-4.pdf */ +#define tWR_IN_NS 15 + +void configure_hmc_adaptor_regs(void); +void configure_ddr_sched_ctrl_regs(void); + +/* The followring are the supported configurations */ +uint32_t ddr_config[] = { + /* DDR_CONFIG(Address order,Bank,Column,Row) */ + /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */ + DDR_CONFIG(0, 3, 10, 12), + DDR_CONFIG(0, 3, 9, 13), + DDR_CONFIG(0, 3, 10, 13), + DDR_CONFIG(0, 3, 9, 14), + DDR_CONFIG(0, 3, 10, 14), + DDR_CONFIG(0, 3, 10, 15), + DDR_CONFIG(0, 3, 11, 14), + DDR_CONFIG(0, 3, 11, 15), + DDR_CONFIG(0, 3, 10, 16), + DDR_CONFIG(0, 3, 11, 16), + DDR_CONFIG(0, 3, 12, 15), /* 0xa */ + /* List for DDR4 only (pinout order > chip, bank, row, column) */ + DDR_CONFIG(1, 3, 10, 14), + DDR_CONFIG(1, 4, 10, 14), + DDR_CONFIG(1, 3, 10, 15), + DDR_CONFIG(1, 4, 10, 15), + DDR_CONFIG(1, 3, 10, 16), + DDR_CONFIG(1, 4, 10, 16), + DDR_CONFIG(1, 3, 10, 17), + DDR_CONFIG(1, 4, 10, 17), +}; + +static int match_ddr_conf(uint32_t ddr_conf) +{ + int i; + + for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) { + if (ddr_conf == ddr_config[i]) + return i; + } + return 0; +} + +static int check_hmc_clk(void) +{ + unsigned long timeout = 0; + uint32_t hmc_clk; + + do { + hmc_clk = mmio_read_32(AGX_SYSMGR_CORE_HMC_CLK); + if (hmc_clk & AGX_SYSMGR_CORE_HMC_CLK_STATUS) + break; + udelay(1); + } while (++timeout < 1000); + if (timeout >= 1000) + return -ETIMEDOUT; + + return 0; +} + +static int clear_emif(void) +{ + uint32_t data; + unsigned long timeout; + + mmio_write_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL, 0); + + timeout = 0; + do { + data = mmio_read_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT); + if ((data & AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0) + break; + udelay(CLEAR_EMIF_DELAY); + } while (++timeout < CLEAR_EMIF_TIMEOUT); + if (timeout >= CLEAR_EMIF_TIMEOUT) + return -ETIMEDOUT; + + return 0; +} + +static int mem_calibration(void) +{ + int status; + uint32_t data; + unsigned long timeout; + unsigned long retry = 0; + + udelay(PRE_CALIBRATION_DELAY); + + do { + if (retry != 0) + INFO("DDR: Retrying DRAM calibration\n"); + + timeout = 0; + do { + data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); + if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) + break; + udelay(500); + } while (++timeout < TIMEOUT_EMIF_CALIBRATION); + + if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { + status = clear_emif(); + if (status) + ERROR("Failed to clear Emif\n"); + } else { + break; + } + } while (++retry < MAX_MEM_CAL_RETRY); + + if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { + ERROR("DDR: DRAM calibration failed.\n"); + status = -EIO; + } else { + INFO("DDR: DRAM calibration success.\n"); + status = 0; + } + + udelay(POST_CALIBRATION_DELAY); + + return status; +} + +int init_hard_memory_controller(void) +{ + int status; + + status = check_hmc_clk(); + if (status) { + ERROR("DDR: Error, HMC clock not running\n"); + return status; + } + + status = mem_calibration(); + if (status) { + ERROR("DDR: Memory Calibration Failed\n"); + return status; + } + + configure_hmc_adaptor_regs(); + + return 0; +} + +void configure_ddr_sched_ctrl_regs(void) +{ + uint32_t data, dram_addr_order, ddr_conf, bank, row, col, + rd_to_miss, wr_to_miss, burst_len, burst_len_ddr_clk, + burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, + t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles, + bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw, + faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd; + + INFO("Init HPS NOC's DDR Scheduler.\n"); + + data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); + dram_addr_order = AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(data); + + data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW); + + col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); + row = IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(data); + bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + + IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(data); + + ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); + + if (ddr_conf) { + mmio_clrsetbits_32( + AGX_MPFE_DDR_MAIN_SCHED_DDRCONF, + AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK, + AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(ddr_conf)); + } else { + ERROR("DDR: Cannot find predefined ddrConf configuration.\n"); + } + + mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data); + + data = mmio_read_32(AGX_MPFE_IOHMC_DRAMTIMING0); + rd_latency = AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(data); + + data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING0); + act_to_act = ACT_TO_ACT(data); + t_rcd = ACT_TO_RDWR(data); + act_to_act_bank = ACT_TO_ACT_DIFF_BANK(data); + + data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING1); + rd_to_wr = RD_TO_WR(data); + bus_rd_to_rd = RD_TO_RD_DIFF_CHIP(data); + bus_rd_to_wr = RD_TO_WR_DIFF_CHIP(data); + + data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING2); + t_rtp = RD_TO_PCH(data); + + data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING3); + wr_to_rd = CALTIMING3_WR_TO_RD(data); + bus_wr_to_rd = CALTIMING3_WR_TO_RD_DIFF_CHIP(data); + + data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING4); + t_rp = PCH_TO_VALID(data); + + data = mmio_read_32(AGX_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL)); + bw_ratio = ((HMC_ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 0 : 1); + + data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG0); + burst_len = HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(data); + burst_len_ddr_clk = burst_len / 2; + burst_len_sched_clk = ((burst_len/2) / 2); + + data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG0); + switch (AGX_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(data)) { + case 1: + /* DDR4 - 1333MHz */ + /* 20 (19.995) clock cycles = 15ns */ + /* Calculate with rounding */ + tw_rin_clk_cycles = (((tWR_IN_NS * 1333) % 1000) >= 500) ? + ((tWR_IN_NS * 1333) / 1000) + 1 : + ((tWR_IN_NS * 1333) / 1000); + break; + default: + /* Others - 1066MHz or slower */ + /* 16 (15.990) clock cycles = 15ns */ + /* Calculate with rounding */ + tw_rin_clk_cycles = (((tWR_IN_NS * 1066) % 1000) >= 500) ? + ((tWR_IN_NS * 1066) / 1000) + 1 : + ((tWR_IN_NS * 1066) / 1000); + break; + } + + rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk; + wr_to_miss = ((rd_latency + burst_len_ddr_clk + 2 + tw_rin_clk_cycles) + / 2) - rd_to_wr + t_rp + t_rcd; + + mmio_write_32(AGX_MPFE_DDR_MAIN_SCHED_DDRTIMING, + bw_ratio << DDRTIMING_BWRATIO_OFST | + wr_to_rd << DDRTIMING_WRTORD_OFST| + rd_to_wr << DDRTIMING_RDTOWR_OFST | + burst_len_sched_clk << DDRTIMING_BURSTLEN_OFST | + wr_to_miss << DDRTIMING_WRTOMISS_OFST | + rd_to_miss << DDRTIMING_RDTOMISS_OFST | + act_to_act << DDRTIMING_ACTTOACT_OFST); + + data = mmio_read_32(AGX_MPFE_HMC_ADP(HMC_ADP_DDRIOCTRL)); + bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0); + + mmio_write_32(AGX_MPFE_DDR_MAIN_SCHED_DDRMODE, + bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST | + auto_precharge << DDRMODE_AUTOPRECHARGE_OFST); + + mmio_write_32(AGX_MPFE_DDR_MAIN_SCHED_READLATENCY, + (rd_latency / 2) + DDR_READ_LATENCY_DELAY); + + data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING9); + faw = AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(data); + + faw_bank = 1; // always 1 because we always have 4 bank DDR. + + mmio_write_32(AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE, + faw_bank << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST | + faw << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST | + act_to_act_bank << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST); + + mmio_write_32(AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV, + ((bus_rd_to_rd + << AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST) + & AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK) | + ((bus_rd_to_wr + << AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST) + & AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK) | + ((bus_wr_to_rd + << AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST) + & AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK)); + +} + +unsigned long get_physical_dram_size(void) +{ + uint32_t data; + unsigned long ram_addr_width, ram_ext_if_io_width; + + data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRIOCTRL); + switch (AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(data)) { + case 0: + ram_ext_if_io_width = 16; + break; + case 1: + ram_ext_if_io_width = 32; + break; + case 2: + ram_ext_if_io_width = 64; + break; + default: + ram_ext_if_io_width = 0; + break; + } + + data = mmio_read_32(AGX_MPFE_IOHMC_REG_DRAMADDRW); + ram_addr_width = IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(data) + + IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(data) + + IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(data) + + IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(data) + + IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(data); + + return (1 << ram_addr_width) * (ram_ext_if_io_width / 8); +} + + + +void configure_hmc_adaptor_regs(void) +{ + uint32_t data; + uint32_t dram_io_width; + + /* Configure DDR data rate */ + dram_io_width = AGX_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0( + mmio_read_32(AGX_MPFE_IOHMC_REG_NIOSRESERVE0_OFST)); + dram_io_width = (dram_io_width & 0xFF) >> 5; + + data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG3); + + dram_io_width |= (data & 0x4); + + mmio_write_32(AGX_MPFE_HMC_ADP_DDRIOCTRL, dram_io_width); + + /* Copy dram addr width from IOHMC to HMC ADP */ + data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW); + mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data); + + /* Enable nonsecure access to DDR */ + data = get_physical_dram_size(); + + if (data < AGX_DDR_SIZE) + data = AGX_DDR_SIZE; + + mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1); + mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f); + + mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1); + + mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8)); + + /* ECC enablement */ + data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1); + if (data & (1 << AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST)) { + mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, + AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK, + AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK); + + mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL2, + AGX_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK, + AGX_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK); + + mmio_clrsetbits_32(AGX_MPFE_HMC_ADP_ECCCTRL1, + AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK | + AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK, + AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK); + INFO("Scrubbing ECC\n"); + + /* ECC Scrubbing */ + zeromem((void *)DRAM_BASE, DRAM_SIZE); + } else { + INFO("ECC is disabled.\n"); + } +}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_mmc.c b/plat/intel/soc/agilex5/soc/agilex5_mmc.c new file mode 100644 index 0000000..48f7341 --- /dev/null +++ b/plat/intel/soc/agilex5/soc/agilex5_mmc.c
@@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include <lib/mmio.h> + +#include "agilex5_clock_manager.h" +#include "agilex5_system_manager.h" + +void agx5_mmc_init(void) +{ +// TODO: To update when handoff data is ready + + //mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, + // CLKMGR_PERPLL_EN_SDMMCCLK); + //mmio_write_32(SOCFPGA_SYSMGR(SDMMC), + // SYSMGR_SDMMC_SMPLSEL(0) | SYSMGR_SDMMC_DRVSEL(3)); + //mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, + // CLKMGR_PERPLL_EN_SDMMCCLK); + +}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_pinmux.c b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c new file mode 100644 index 0000000..50d9e36 --- /dev/null +++ b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
@@ -0,0 +1,225 @@ +/* + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <lib/mmio.h> + +#include "agilex5_pinmux.h" +#include "agilex5_system_manager.h" + +const uint32_t sysmgr_pinmux_array_sel[] = { + 0x00000000, 0x00000001, /* usb */ + 0x00000004, 0x00000001, + 0x00000008, 0x00000001, + 0x0000000c, 0x00000001, + 0x00000010, 0x00000001, + 0x00000014, 0x00000001, + 0x00000018, 0x00000001, + 0x0000001c, 0x00000001, + 0x00000020, 0x00000001, + 0x00000024, 0x00000001, + 0x00000028, 0x00000001, + 0x0000002c, 0x00000001, + 0x00000030, 0x00000000, /* emac0 */ + 0x00000034, 0x00000000, + 0x00000038, 0x00000000, + 0x0000003c, 0x00000000, + 0x00000040, 0x00000000, + 0x00000044, 0x00000000, + 0x00000048, 0x00000000, + 0x0000004c, 0x00000000, + 0x00000050, 0x00000000, + 0x00000054, 0x00000000, + 0x00000058, 0x00000000, + 0x0000005c, 0x00000000, + 0x00000060, 0x00000008, /* gpio1 */ + 0x00000064, 0x00000008, + 0x00000068, 0x00000005, /* uart0 tx */ + 0x0000006c, 0x00000005, /* uart 0 rx */ + 0x00000070, 0x00000008, /* gpio */ + 0x00000074, 0x00000008, + 0x00000078, 0x00000004, /* i2c1 */ + 0x0000007c, 0x00000004, + 0x00000080, 0x00000007, /* jtag */ + 0x00000084, 0x00000007, + 0x00000088, 0x00000007, + 0x0000008c, 0x00000007, + 0x00000090, 0x00000001, /* sdmmc data0 */ + 0x00000094, 0x00000001, + 0x00000098, 0x00000001, + 0x0000009c, 0x00000001, + 0x00000100, 0x00000001, + 0x00000104, 0x00000001, /* sdmmc.data3 */ + 0x00000108, 0x00000008, /* loan */ + 0x0000010c, 0x00000008, /* gpio */ + 0x00000110, 0x00000008, + 0x00000114, 0x00000008, /* gpio1.io21 */ + 0x00000118, 0x00000005, /* mdio0.mdio */ + 0x0000011c, 0x00000005 /* mdio0.mdc */ +}; + +const uint32_t sysmgr_pinmux_array_ctrl[] = { + 0x00000000, 0x00502c38, /* Q1_1 */ + 0x00000004, 0x00102c38, + 0x00000008, 0x00502c38, + 0x0000000c, 0x00502c38, + 0x00000010, 0x00502c38, + 0x00000014, 0x00502c38, + 0x00000018, 0x00502c38, + 0x0000001c, 0x00502c38, + 0x00000020, 0x00502c38, + 0x00000024, 0x00502c38, + 0x00000028, 0x00502c38, + 0x0000002c, 0x00502c38, + 0x00000030, 0x00102c38, /* Q2_1 */ + 0x00000034, 0x00102c38, + 0x00000038, 0x00502c38, + 0x0000003c, 0x00502c38, + 0x00000040, 0x00102c38, + 0x00000044, 0x00102c38, + 0x00000048, 0x00502c38, + 0x0000004c, 0x00502c38, + 0x00000050, 0x00102c38, + 0x00000054, 0x00102c38, + 0x00000058, 0x00502c38, + 0x0000005c, 0x00502c38, + 0x00000060, 0x00502c38, /* Q3_1 */ + 0x00000064, 0x00502c38, + 0x00000068, 0x00102c38, + 0x0000006c, 0x00502c38, + 0x000000d0, 0x00502c38, + 0x000000d4, 0x00502c38, + 0x000000d8, 0x00542c38, + 0x000000dc, 0x00542c38, + 0x000000e0, 0x00502c38, + 0x000000e4, 0x00502c38, + 0x000000e8, 0x00102c38, + 0x000000ec, 0x00502c38, + 0x000000f0, 0x00502c38, /* Q4_1 */ + 0x000000f4, 0x00502c38, + 0x000000f8, 0x00102c38, + 0x000000fc, 0x00502c38, + 0x00000100, 0x00502c38, + 0x00000104, 0x00502c38, + 0x00000108, 0x00102c38, + 0x0000010c, 0x00502c38, + 0x00000110, 0x00502c38, + 0x00000114, 0x00502c38, + 0x00000118, 0x00542c38, + 0x0000011c, 0x00102c38 +}; + +const uint32_t sysmgr_pinmux_array_fpga[] = { + 0x00000000, 0x00000000, + 0x00000004, 0x00000000, + 0x00000008, 0x00000000, + 0x0000000c, 0x00000000, + 0x00000010, 0x00000000, + 0x00000014, 0x00000000, + 0x00000018, 0x00000000, + 0x0000001c, 0x00000000, + 0x00000020, 0x00000000, + 0x00000028, 0x00000000, + 0x0000002c, 0x00000000, + 0x00000030, 0x00000000, + 0x00000034, 0x00000000, + 0x00000038, 0x00000000, + 0x0000003c, 0x00000000, + 0x00000040, 0x00000000, + 0x00000044, 0x00000000, + 0x00000048, 0x00000000, + 0x00000050, 0x00000000, + 0x00000054, 0x00000000, + 0x00000058, 0x0000002a +}; + +const uint32_t sysmgr_pinmux_array_iodelay[] = { + 0x00000000, 0x00000000, + 0x00000004, 0x00000000, + 0x00000008, 0x00000000, + 0x0000000c, 0x00000000, + 0x00000010, 0x00000000, + 0x00000014, 0x00000000, + 0x00000018, 0x00000000, + 0x0000001c, 0x00000000, + 0x00000020, 0x00000000, + 0x00000024, 0x00000000, + 0x00000028, 0x00000000, + 0x0000002c, 0x00000000, + 0x00000030, 0x00000000, + 0x00000034, 0x00000000, + 0x00000038, 0x00000000, + 0x0000003c, 0x00000000, + 0x00000040, 0x00000000, + 0x00000044, 0x00000000, + 0x00000048, 0x00000000, + 0x0000004c, 0x00000000, + 0x00000050, 0x00000000, + 0x00000054, 0x00000000, + 0x00000058, 0x00000000, + 0x0000005c, 0x00000000, + 0x00000060, 0x00000000, + 0x00000064, 0x00000000, + 0x00000068, 0x00000000, + 0x0000006c, 0x00000000, + 0x00000070, 0x00000000, + 0x00000074, 0x00000000, + 0x00000078, 0x00000000, + 0x0000007c, 0x00000000, + 0x00000080, 0x00000000, + 0x00000084, 0x00000000, + 0x00000088, 0x00000000, + 0x0000008c, 0x00000000, + 0x00000090, 0x00000000, + 0x00000094, 0x00000000, + 0x00000098, 0x00000000, + 0x0000009c, 0x00000000, + 0x00000100, 0x00000000, + 0x00000104, 0x00000000, + 0x00000108, 0x00000000, + 0x0000010c, 0x00000000, + 0x00000110, 0x00000000, + 0x00000114, 0x00000000, + 0x00000118, 0x00000000, + 0x0000011c, 0x00000000 +}; + +void config_fpgaintf_mod(void) +{ + mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8); +} + +void config_pinmux(handoff *hoff_ptr) +{ + unsigned int i; + + mmio_write_32(PINMUX_HANDOFF_CONFIG_ADDR, PINMUX_HANDOFF_CONFIG_VAL); + for (i = 0; i < PINMUX_HANDOFF_ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) { + mmio_write_32(AGX5_PINMUX_PIN0SEL + + hoff_ptr->pinmux_sel_array[i], + hoff_ptr->pinmux_sel_array[i + 1]); + } + + config_fpgaintf_mod(); +} + +void config_peripheral(handoff *hoff_ptr) +{ + + // TODO: This need to be update due to peripheral_pwr_gate_array handoff change + // Pending SDM to pass over handoff data + // unsigned int i; + + // for (i = 0; i < 4; i += 2) { + // mmio_write_32(AGX_EDGE_PERIPHERAL + + // hoff_ptr->peripheral_pwr_gate_array[i], + // hoff_ptr->peripheral_pwr_gate_array[i+1]); + // } + + + // TODO: This need to be update due to peripheral_pwr_gate_array handoff change + mmio_write_32(AGX5_PERIPHERAL, + hoff_ptr->peripheral_pwr_gate_array); +}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_power_manager.c b/plat/intel/soc/agilex5/soc/agilex5_power_manager.c new file mode 100644 index 0000000..0d81970 --- /dev/null +++ b/plat/intel/soc/agilex5/soc/agilex5_power_manager.c
@@ -0,0 +1,81 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <common/debug.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> + +#include "agilex5_power_manager.h" +#include "socfpga_reset_manager.h" + +int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff) +{ + uint32_t data = 0; + uint32_t count = 0; + uint32_t pgstat = 0; + + /* Wait FSM ready */ + do { + data = mmio_read_32(AGX5_PWRMGR(PSS_PGSTAT)); + count++; + if (count >= 1000) { + return -ETIMEDOUT; + } + + } while (AGX5_PWRMGR_PSS_STAT_BUSY(data) == AGX5_PWRMGR_PSS_STAT_BUSY_E_BUSY); + + /* Verify PSS SRAM power gated */ + pgstat = mmio_read_32(AGX5_PWRMGR(PSS_PGSTAT)); + if (pgstat != (AGX5_PWRMGR_PSS_PGEN_OUT(peripheral_handoff))) { + return AGX5_PWRMGR_HANDOFF_PERIPHERAL; + } + + return 0; +} + +int pss_sram_power_off(handoff *hoff_ptr) +{ + int ret = 0; + uint32_t peripheral_handoff = 0; + + /* Get PSS SRAM handoff data */ + peripheral_handoff = hoff_ptr->peripheral_pwr_gate_array; + + /* Enable firewall for PSS SRAM */ + mmio_write_32(AGX5_PWRMGR(PSS_FWENCTL), + AGX5_PWRMGR_PSS_FWEN(peripheral_handoff)); + + /* Wait */ + udelay(1); + + /* Power gating PSS SRAM */ + mmio_write_32(AGX5_PWRMGR(PSS_PGENCTL), + AGX5_PWRMGR_PSS_PGEN(peripheral_handoff)); + + ret = wait_verify_fsm(1000, peripheral_handoff); + + return ret; +} + +void config_pwrmgr_handoff(handoff *hoff_ptr) +{ + int ret = 0; + + switch (hoff_ptr->header_magic) { + case HANDOFF_MAGIC_PERIPHERAL: + ret = pss_sram_power_off(hoff_ptr); + break; + default: + break; + } + + if (ret != 0) { + ERROR("Config PwrMgr handoff failed. error %d\n", ret); + assert(false); + } +}
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index 213fd3c..cbd0121 100644 --- a/plat/intel/soc/common/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,6 +34,11 @@ func plat_secondary_cold_boot_setup /* Wait until the it gets reset signal from rstmgr gets populated */ poll_mailbox: +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + mov_imm x0, PLAT_SEC_ENTRY + cbz x0, poll_mailbox + br x0 +#else wfi mov_imm x0, PLAT_SEC_ENTRY ldr x1, [x0] @@ -44,8 +49,13 @@ cmp x3, x4 b.ne poll_mailbox br x1 +#endif endfunc plat_secondary_cold_boot_setup +#if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \ + (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \ + (PLATFORM_MODEL == PLAT_SOCFPGA_N5X)) + func platform_is_primary_cpu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) cmp x0, #PLAT_PRIMARY_CPU @@ -53,6 +63,21 @@ ret endfunc platform_is_primary_cpu +#else + +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #(PLAT_PRIMARY_CPU_A76) + b.eq primary_cpu + cmp x0, #(PLAT_PRIMARY_CPU_A55) + b.eq primary_cpu +primary_cpu: + cset x0, eq + ret +endfunc platform_is_primary_cpu + +#endif + func plat_is_my_cpu_primary mrs x0, mpidr_el1 b platform_is_primary_cpu @@ -62,11 +87,27 @@ mrs x0, mpidr_el1 and x1, x0, #MPIDR_CPU_MASK and x0, x0, #MPIDR_CLUSTER_MASK +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + add x0, x1, x0, LSR #8 +#else add x0, x1, x0, LSR #6 +#endif ret endfunc plat_my_core_pos func warm_reset_req +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + bl plat_is_my_cpu_primary + cbnz x0, warm_reset +warm_reset: + mov_imm x1, PLAT_SEC_ENTRY + str xzr, [x1] + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +#else str xzr, [x4] bl plat_is_my_cpu_primary cbz x0, cpu_in_wfi @@ -80,8 +121,25 @@ cpu_in_wfi: wfi b cpu_in_wfi +#endif endfunc warm_reset_req +/* TODO: Zephyr warm reset test */ +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +func plat_get_my_entrypoint + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =PLAT_L2_RESET_REQ + cmp x1, x5 + b.eq zephyr_reset_req + mov_imm x1, PLAT_SEC_ENTRY + ldr x0, [x1] + ret +zephyr_reset_req: + ldr x0, =0x00 + ret +endfunc plat_get_my_entrypoint +#else func plat_get_my_entrypoint ldr x4, =L2_RESET_DONE_REG ldr x5, [x4] @@ -92,7 +150,7 @@ ldr x0, [x1] ret endfunc plat_get_my_entrypoint - +#endif /* --------------------------------------------- * int plat_crash_console_init(void) @@ -138,6 +196,13 @@ ret endfunc platform_mem_init + /* -------------------------------------------------------- + * macro plat_secondary_cpus_bl31_entry; + * + * el3_entrypoint_common init param configuration. + * Called very early in the secondary cores boot process. + * -------------------------------------------------------- + */ func plat_secondary_cpus_bl31_entry el3_entrypoint_common \ _init_sctlr=0 \
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c index 99d48d2..684a625 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -1,101 +1,86 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ - #include <assert.h> #include <common/debug.h> #include <errno.h> #include <lib/mmio.h> +#include <platform_def.h> #include "ncore_ccu.h" +#include "socfpga_plat_def.h" +#include "socfpga_system_manager.h" uint32_t poll_active_bit(uint32_t dir); +#define SMMU_DMI 1 + + static coh_ss_id_t subsystem_id; - - void get_subsystem_id(void) { uint32_t snoop_filter, directory, coh_agent; - snoop_filter = CSIDR_NUM_SF(mmio_read_32(NCORE_CCU_CSR(NCORE_CSIDR))); directory = CSUIDR_NUM_DIR(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR))); coh_agent = CSUIDR_NUM_CAI(mmio_read_32(NCORE_CCU_CSR(NCORE_CSUIDR))); - subsystem_id.num_snoop_filter = snoop_filter + 1; subsystem_id.num_directory = directory; subsystem_id.num_coh_agent = coh_agent; } - uint32_t directory_init(void) { uint32_t dir_sf_mtn, dir_sf_en; uint32_t dir, sf, ret; - for (dir = 0; dir < subsystem_id.num_directory; dir++) { for (sf = 0; sf < subsystem_id.num_snoop_filter; sf++) { dir_sf_mtn = DIRECTORY_UNIT(dir, NCORE_DIRUSFMCR); dir_sf_en = DIRECTORY_UNIT(dir, NCORE_DIRUSFER); - /* Initialize All Entries */ mmio_write_32(dir_sf_mtn, SNOOP_FILTER_ID(sf)); - /* Poll Active Bit */ ret = poll_active_bit(dir); if (ret != 0) { ERROR("Timeout during active bit polling"); return -ETIMEDOUT; } - /* Disable snoop filter, a bit per snoop filter */ mmio_clrbits_32(dir_sf_en, BIT(sf)); - } } - return 0; } - uint32_t coherent_agent_intfc_init(void) { uint32_t dir, ca, ca_id, ca_type, ca_snoop_en; - for (dir = 0; dir < subsystem_id.num_directory; dir++) { for (ca = 0; ca < subsystem_id.num_coh_agent; ca++) { ca_snoop_en = DIRECTORY_UNIT(ca, NCORE_DIRUCASER0); ca_id = mmio_read_32(COH_AGENT_UNIT(ca, NCORE_CAIUIDR)); - /* Coh Agent Snoop Enable */ if (CACHING_AGENT_BIT(ca_id)) - mmio_write_32(ca_snoop_en, BIT(ca)); - + mmio_setbits_32(ca_snoop_en, BIT(ca)); /* Coh Agent Snoop DVM Enable */ ca_type = CACHING_AGENT_TYPE(ca_id); if (ca_type == ACE_W_DVM || ca_type == ACE_L_W_DVM) - mmio_write_32(NCORE_CCU_CSR(NCORE_CSADSER0), + mmio_setbits_32(NCORE_CCU_CSR(NCORE_CSADSER0), BIT(ca)); } } - return 0; } - uint32_t poll_active_bit(uint32_t dir) { uint32_t timeout = 80000; uint32_t poll_dir = DIRECTORY_UNIT(dir, NCORE_DIRUSFMAR); - while (timeout > 0) { if (mmio_read_32(poll_dir) == 0) return 0; timeout--; } - return -1; } - void bypass_ocram_firewall(void) { mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1), @@ -107,7 +92,6 @@ mmio_clrbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); } - void ncore_enable_ocram_firewall(void) { mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF1), @@ -119,15 +103,44 @@ mmio_setbits_32(COH_CPU0_BYPASS_REG(NCORE_FW_OCRAM_BLK_CGF4), OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); } - uint32_t init_ncore_ccu(void) { uint32_t status; - get_subsystem_id(); status = directory_init(); status = coherent_agent_intfc_init(); bypass_ocram_firewall(); - return status; } + +void setup_smmu_stream_id(void) +{ + /* Configure Stream ID for Agilex5 */ + mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_ID_AX_REG_0_DMA0), DMA0); + mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_ID_AX_REG_0_DMA1), DMA1); + mmio_write_32(SOCFPGA_SYSMGR(SDM_TBU_STREAM_ID_AX_REG_1_SDM), SDM); + /* Reg map showing USB2 but Linux USB0? */ + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_USB2), USB0); + /* Reg map showing USB3 but Linux USB1? */ + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_USB3), USB1); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_SDMMC), SDMMC); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_NAND), NAND); + /* To confirm ETR - core sight debug*/ + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_ETR), CORE_SIGHT_DEBUG); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN0), TSN0); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN1), TSN1); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_ID_AX_REG_2_TSN2), TSN2); + + /* Enabled Stream ctrl register for Agilex5 */ + mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA0), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(DMA_TBU_STREAM_CTRL_REG_0_DMA1), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(SDM_TBU_STREAM_CTRL_REG_1_SDM), ENABLE_STREAMID_SECURE_TX); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_USB2), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_USB3), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_SDMMC), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_NAND), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(IO_TBU_STREAM_CTRL_REG_2_ETR), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN0), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN1), ENABLE_STREAMID); + mmio_write_32(SOCFPGA_SYSMGR(TSN_TBU_STREAM_CTRL_REG_3_TSN2), ENABLE_STREAMID); +}
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h index 3f662ff..6cdbeb8 100644 --- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.h +++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.h
@@ -1,99 +1,420 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ - #ifndef NCORE_CCU_H #define NCORE_CCU_H +#include <stdbool.h> +#include <stdint.h> -#define NCORE_CCU_OFFSET 0xf7000000 +#ifndef CCU_ACTIVATE_COH_FPGA +#define CCU_ACTIVATE_COH_FPGA 0 +#endif +// Address map for ccu init +#define addr_CAIUIDR1 (0x1C000000) +#define addr_GRBUNRRUCR (0x1c0ffff8) +#define base_addr_NRS_CAIU0 (0x1c000000) +#define base_addr_NRS_NCAIU0 (0x1c001000) +#define base_addr_NRS_NCAIU1 (0x1c002000) +#define base_addr_NRS_NCAIU2 (0x1c003000) +#define base_addr_NRS_NCAIU3 (0x1c004000) +#define base_addr_NRS_DCE0 (0x1c005000) +#define base_addr_NRS_DCE1 (0x1c006000) +//#define base_addr_NRS_DMI0 (0x1c007000) +//#define base_addr_NRS_DMI1 (0x1c008000) +//DMI +#define ALT_CCU_CCU_DMI0_DMIUSMCTCR_ADDR 0x1C007300 +#define ALT_CCU_CCU_DMI1_DMIUSMCTCR_ADDR 0x1C008300 +//DSU +#define ALT_CCU_DSU_CAIUAMIGR_ADDR 0x1C0003C0 +#define ALT_CCU_DSU_CAIUMIFSR_ADDR 0x1C0003C4 +#define ALT_CCU_DSU_CAIUGPRBLR1_ADDR 0x1C000414 +#define ALT_CCU_DSU_CAIUGPRBHR1_ADDR 0x1C000418 +#define ALT_CCU_DSU_CAIUGPRAR1_ADDR 0x1C000410 +#define ALT_CCU_DSU_CAIUGPRBLR2_ADDR 0x1C000424 +#define ALT_CCU_DSU_CAIUGPRBHR2_ADDR 0x1C000428 +#define ALT_CCU_DSU_CAIUGPRAR2_ADDR 0x1C000420 +#define ALT_CCU_DSU_CAIUGPRBLR4_ADDR 0x1C000444 +#define ALT_CCU_DSU_CAIUGPRBHR4_ADDR 0x1C000448 +#define ALT_CCU_DSU_CAIUGPRAR4_ADDR 0x1C000440 +#define ALT_CCU_DSU_CAIUGPRBLR5_ADDR 0x1C000454 +#define ALT_CCU_DSU_CAIUGPRBHR5_ADDR 0x1C000458 +#define ALT_CCU_DSU_CAIUGPRAR5_ADDR 0x1C000450 +#define ALT_CCU_DSU_CAIUGPRBLR6_ADDR 0x1C000464 +#define ALT_CCU_DSU_CAIUGPRBHR6_ADDR 0x1C000468 +#define ALT_CCU_DSU_CAIUGPRAR6_ADDR 0x1C000460 +#define ALT_CCU_DSU_CAIUGPRBLR7_ADDR 0x1C000474 +#define ALT_CCU_DSU_CAIUGPRBHR7_ADDR 0x1C000478 +#define ALT_CCU_DSU_CAIUGPRAR7_ADDR 0x1C000470 +#define ALT_CCU_DSU_CAIUGPRBLR8_ADDR 0x1C000484 +#define ALT_CCU_DSU_CAIUGPRBHR8_ADDR 0x1C000488 +#define ALT_CCU_DSU_CAIUGPRAR8_ADDR 0x1C000480 +#define ALT_CCU_DSU_CAIUGPRBLR9_ADDR 0x1C000494 +#define ALT_CCU_DSU_CAIUGPRBHR9_ADDR 0x1C000498 +#define ALT_CCU_DSU_CAIUGPRAR9_ADDR 0x1C000490 +#define ALT_CCU_DSU_CAIUGPRBLR10_ADDR 0x1C0004A4 +#define ALT_CCU_DSU_CAIUGPRBHR10_ADDR 0x1C0004A8 +#define ALT_CCU_DSU_CAIUGPRAR10_ADDR 0x1C0004A0 +//GIC +#define ALT_CCU_GIC_M_XAIUAMIGR_ADDR 0x1C0023C0 +#define ALT_CCU_GIC_M_XAIUMIFSR_ADDR 0x1C0023C4 +#define ALT_CCU_GIC_M_XAIUGPRBLR1_ADDR 0x1C002414 +#define ALT_CCU_GIC_M_XAIUGPRBHR1_ADDR 0x1C002418 +#define ALT_CCU_GIC_M_XAIUGPRAR1_ADDR 0x1C002410 +#define ALT_CCU_GIC_M_XAIUGPRBLR6_ADDR 0x1C002464 +#define ALT_CCU_GIC_M_XAIUGPRBHR6_ADDR 0x1C002468 +#define ALT_CCU_GIC_M_XAIUGPRAR6_ADDR 0x1C002460 +#define ALT_CCU_GIC_M_XAIUGPRBLR8_ADDR 0x1C002484 +#define ALT_CCU_GIC_M_XAIUGPRBHR8_ADDR 0x1C002488 +#define ALT_CCU_GIC_M_XAIUGPRAR8_ADDR 0x1C002480 +#define ALT_CCU_GIC_M_XAIUGPRBLR10_ADDR 0x1C0024A4 +#define ALT_CCU_GIC_M_XAIUGPRBHR10_ADDR 0x1C0024A8 +#define ALT_CCU_GIC_M_XAIUGPRAR10_ADDR 0x1C0024A0 +//FPGA2SOC +#define ALT_CCU_FPGA2SOC_XAIUAMIGR_ADDR 0x1C0013C0 +#define ALT_CCU_FPGA2SOC_XAIUMIFSR_ADDR 0x1C0013C4 +#define ALT_CCU_FPGA2SOC_XAIUGPRBLR1_ADDR 0x1C001414 +#define ALT_CCU_FPGA2SOC_XAIUGPRBHR1_ADDR 0x1C001418 +#define ALT_CCU_FPGA2SOC_XAIUGPRAR1_ADDR 0x1C001410 +#define ALT_CCU_FPGA2SOC_XAIUGPRBLR6_ADDR 0x1C001464 +#define ALT_CCU_FPGA2SOC_XAIUGPRBHR6_ADDR 0x1C001468 +#define ALT_CCU_FPGA2SOC_XAIUGPRAR6_ADDR 0x1C001460 +#define ALT_CCU_FPGA2SOC_XAIUGPRBLR8_ADDR 0x1C001484 +#define ALT_CCU_FPGA2SOC_XAIUGPRBHR8_ADDR 0x1C001488 +#define ALT_CCU_FPGA2SOC_XAIUGPRAR8_ADDR 0x1C001480 +#define ALT_CCU_FPGA2SOC_XAIUGPRBLR10_ADDR 0x1C0014A4 +#define ALT_CCU_FPGA2SOC_XAIUGPRBHR10_ADDR 0x1C0014A8 +#define ALT_CCU_FPGA2SOC_XAIUGPRAR10_ADDR 0x1C0014A0 +//TCU +#define ALT_CCU_TCU_BASE 0x1C003000 +#define ALT_CCU_TCU_XAIUAMIGR_ADDR ALT_CCU_TCU_BASE + 0x03C0 +#define ALT_CCU_TCU_XAIUMIFSR_ADDR ALT_CCU_TCU_BASE + 0x03C4 +#define ALT_CCU_TCU_XAIUGPRBLR0_ADDR ALT_CCU_TCU_BASE + 0x0404 +#define ALT_CCU_TCU_XAIUGPRBHR0_ADDR ALT_CCU_TCU_BASE + 0x0408 +#define ALT_CCU_TCU_XAIUGPRAR0_ADDR ALT_CCU_TCU_BASE + 0x0400 +#define ALT_CCU_TCU_XAIUGPRBLR1_ADDR ALT_CCU_TCU_BASE + 0x0414 +#define ALT_CCU_TCU_XAIUGPRBHR1_ADDR ALT_CCU_TCU_BASE + 0x0418 +#define ALT_CCU_TCU_XAIUGPRAR1_ADDR ALT_CCU_TCU_BASE + 0x0410 +#define ALT_CCU_TCU_XAIUGPRBLR2_ADDR ALT_CCU_TCU_BASE + 0x0424 +#define ALT_CCU_TCU_XAIUGPRBHR2_ADDR ALT_CCU_TCU_BASE + 0x0428 +#define ALT_CCU_TCU_XAIUGPRAR2_ADDR ALT_CCU_TCU_BASE + 0x0420 +#define ALT_CCU_TCU_XAIUGPRBLR6_ADDR 0x1C003464 +#define ALT_CCU_TCU_XAIUGPRBHR6_ADDR 0x1C003468 +#define ALT_CCU_TCU_XAIUGPRAR6_ADDR 0x1C003460 +#define ALT_CCU_TCU_XAIUGPRBLR8_ADDR 0x1C003484 +#define ALT_CCU_TCU_XAIUGPRBHR8_ADDR 0x1C003488 +#define ALT_CCU_TCU_XAIUGPRAR8_ADDR 0x1C003480 +#define ALT_CCU_TCU_XAIUGPRBLR10_ADDR 0x1C0034A4 +#define ALT_CCU_TCU_XAIUGPRBHR10_ADDR 0x1C0034A8 +#define ALT_CCU_TCU_XAIUGPRAR10_ADDR 0x1C0034A0 +//IOM +#define ALT_CCU_CCU_IOM_XAIUAMIGR_ADDR 0x1C0043C0 +#define ALT_CCU_CCU_IOM_XAIUMIFSR_ADDR 0x1C0013C4 +#define ALT_CCU_IOM_XAIUGPRBLR1_ADDR 0x1C001414 +#define ALT_CCU_IOM_XAIUGPRBHR1_ADDR 0x1C001418 +#define ALT_CCU_IOM_XAIUGPRAR1_ADDR 0x1C001410 +#define ALT_CCU_CCU_IOM_XAIUGPRBLR6_ADDR 0x1C001464 +#define ALT_CCU_CCU_IOM_XAIUGPRBHR6_ADDR 0x1C001468 +#define ALT_CCU_CCU_IOM_XAIUGPRAR6_ADDR 0x1C001460 +#define ALT_CCU_CCU_IOM_XAIUGPRBLR8_ADDR 0x1C001484 +#define ALT_CCU_CCU_IOM_XAIUGPRBHR8_ADDR 0x1C001488 +#define ALT_CCU_CCU_IOM_XAIUGPRAR8_ADDR 0x1C001480 +#define ALT_CCU_CCU_IOM_XAIUGPRBLR10_ADDR 0x1C0014A4 +#define ALT_CCU_CCU_IOM_XAIUGPRBHR10_ADDR 0x1C0014A8 +#define ALT_CCU_CCU_IOM_XAIUGPRAR10_ADDR 0x1C0014A0 +//DCE +#define ALT_CCU_DCE0_DCEUAMIGR_ADDR 0x1C0053C0 +#define ALT_CCU_DCE0_DCEUMIFSR_ADDR 0x1C0053C4 +#define ALT_CCU_DCE0_DCEUGPRBLR6_ADDR 0x1C005464 +#define ALT_CCU_DCE0_DCEUGPRBHR6_ADDR 0x1C005468 +#define ALT_CCU_DCE0_DCEUGPRAR6_ADDR 0x1C005460 +#define ALT_CCU_DCE0_DCEUGPRBLR8_ADDR 0x1C005484 +#define ALT_CCU_DCE0_DCEUGPRBHR8_ADDR 0x1C005488 +#define ALT_CCU_DCE0_DCEUGPRAR8_ADDR 0x1C005480 +#define ALT_CCU_DCE0_DCEUGPRBLR10_ADDR 0x1C0054A4 +#define ALT_CCU_DCE0_DCEUGPRBHR10_ADDR 0x1C0054A8 +#define ALT_CCU_DCE0_DCEUGPRAR10_ADDR 0x1C0054A0 +#define ALT_CCU_DCE1_DCEUAMIGR_ADDR 0x1C0063C0 +#define ALT_CCU_DCE1_DCEUMIFSR_ADDR 0x1C0063C4 +#define ALT_CCU_DCE1_DCEUGPRBLR6_ADDR 0x1C006464 +#define ALT_CCU_DCE1_DCEUGPRBHR6_ADDR 0x1C006468 +#define ALT_CCU_DCE1_DCEUGPRAR6_ADDR 0x1C006460 +#define ALT_CCU_DCE1_DCEUGPRBLR8_ADDR 0x1C006484 +#define ALT_CCU_DCE1_DCEUGPRBHR8_ADDR 0x1C006488 +#define ALT_CCU_DCE1_DCEUGPRAR8_ADDR 0x1C006480 +#define ALT_CCU_DCE1_DCEUGPRBLR10_ADDR 0x1C0064A4 +#define ALT_CCU_DCE1_DCEUGPRBHR10_ADDR 0x1C0064A8 +#define ALT_CCU_DCE1_DCEUGPRAR10_ADDR 0x1C0064A0 +#define offset_NRS_GPRAR0 (0x400) +#define offset_NRS_GPRBLR0 (0x404) +#define offset_NRS_GPRBHR0 (0x408) +#define offset_NRS_GPRAR1 (0x410) +#define offset_NRS_GPRBLR1 (0x414) +#define offset_NRS_GPRBHR1 (0x418) +#define offset_NRS_GPRAR2 (0x420) +#define offset_NRS_GPRBLR2 (0x424) +#define offset_NRS_GPRBHR2 (0x428) +#define offset_NRS_GPRAR3 (0x430) +#define offset_NRS_GPRBLR3 (0x434) +#define offset_NRS_GPRBHR3 (0x438) +#define offset_NRS_GPRAR4 (0x440) +#define offset_NRS_GPRBLR4 (0x444) +#define offset_NRS_GPRBHR4 (0x448) +#define offset_NRS_GPRAR5 (0x450) +#define offset_NRS_GPRBLR5 (0x454) +#define offset_NRS_GPRBHR5 (0x458) +#define offset_NRS_GPRAR6 (0x460) +#define offset_NRS_GPRBLR6 (0x464) +#define offset_NRS_GPRBHR6 (0x468) +#define offset_NRS_GPRAR7 (0x470) +#define offset_NRS_GPRBLR7 (0x474) +#define offset_NRS_GPRBHR7 (0x478) +#define offset_NRS_GPRAR8 (0x480) +#define offset_NRS_GPRBLR8 (0x484) +#define offset_NRS_GPRBHR8 (0x488) +#define offset_NRS_GPRAR9 (0x490) +#define offset_NRS_GPRBLR9 (0x494) +#define offset_NRS_GPRBHR9 (0x498) +#define offset_NRS_GPRAR10 (0x4a0) +#define offset_NRS_GPRBLR10 (0x4a4) +#define offset_NRS_GPRBHR10 (0x4a8) +#define offset_NRS_AMIGR (0x3c0) +#define offset_NRS_MIFSR (0x3c4) +#define offset_NRS_DMIUSMCTCR (0x300) +#define base_addr_DII0_PSSPERIPHS (0x10000) +#define base_addr_DII0_LWHPS2FPGA (0x20000) +#define base_addr_DII0_HPS2FPGA_1G (0x40000) +#define base_addr_DII0_HPS2FPGA_15G (0x400000) +#define base_addr_DII0_HPS2FPGA_240G (0x4000000) +#define base_addr_DII1_MPFEREGS (0x18000) +#define base_addr_DII2_GICREGS (0x1D000) +#define base_addr_DII3_OCRAM (0x0) +#define base_addr_BHR (0x0) +#define base_addr_DMI_SDRAM_2G (0x80000) +#define base_addr_DMI_SDRAM_30G (0x800000) +#define base_addr_DMI_SDRAM_480G (0x8000000) +// ((0x0<<9) | (0xf<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII0_PSSPERIPHS 0xC0F00000 +// ((0x0<<9) | (0x11<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII0_LWHPS2FPGA 0xC1100000 +// ((0x0<<9) | (0x12<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII0_HPS2FPGA_1G 0xC1200000 +// ((0x0<<9) | (0x16<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII0_HPS2FPGA_15G 0xC1600000 +// ((0x0<<9) | (0x1a<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII0_HPS2FPGA_240G 0xC1A00000 +// ((0x1<<9) | (0xe<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII1_MPFEREGS 0xC0E00200 +// ((0x2<<9) | (0x8<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII2_GICREGS 0xC0800400 +// ((0x3<<9) | (0x9<<20) | (0x1<<30) | (0x1<<31)) +#define wr_DII3_OCRAM 0xC0900600 +// ((0x0<<9) | (0x12<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_1G_ORDERED 0x81200000 +// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x12<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_1G 0x81200006 +// ((0x0<<9) | (0x13<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_2G_ORDERED 0x81300000 +// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x13<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_2G 0x81300006 +// ((0x0<<9) | (0x16<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_15G_ORDERED 0x81600000 +// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x16<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_15G 0x81600006 +// ((0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_30G_ORDERED 0x81700000 +// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x17<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_30G 0x81700006 +// ((0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_240G_ORDERED 0x81a00000 +// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1a<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_240G 0x81a00006 +// ((0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_480G_ORDERED 0x81b00000 +// ((0x1<<1) | (0x1<<2) | (0x0<<9) | (0x1b<<20) | (0x0<<30) | (0x1<<31)) +#define wr_DMI_SDRAM_480G 0x81b00006 +typedef enum CCU_REGION_SECURITY_e { + // + // Allow secure accesses only. + // + CCU_REGION_SECURITY_SECURE_ONLY, + // + // Allow non-secure accesses only. + // + CCU_REGION_SECURITY_NON_SECURE_ONLY, + // + // Allow accesses of any security state. + // + CCU_REGION_SECURITY_DONT_CARE +} CCU_REGION_SECURITY_t; +typedef enum CCU_REGION_PRIVILEGE_e { + // + // Allow privileged accesses only. + // + CCU_REGION_PRIVILEGE_PRIVILEGED_ONLY, + // + // Allow unprivileged accesses only. + // + CCU_REGION_PRIVILEGE_NON_PRIVILEGED_ONLY, + // + // Allow accesses of any privilege. + // + CCU_REGION_PRIVILEGE_DONT_CARE +} CCU_REGION_PRIVILEGE_t; +// +// Initializes the CCU by enabling all regions except RAM 1 - 5. +// This is needed because of an RTL change around 2016.02.24. +// +// Runtime measurement: +// - arm : 14,830,000 ps (2016.05.31; sanity/printf_aarch32) +// - aarch64 : 14,837,500 ps (2016.05.31; sanity/printf) +// +// Runtime history: +// - arm : 20,916,668 ps (2016.05.30; sanity/printf_aarch32) +// - aarch64 : 20,924,168 ps (2016.05.30; sanity/printf) +// +int ccu_hps_init(void); + +typedef enum ccu_hps_ram_region_e { + ccu_hps_ram_region_ramspace0 = 0, + ccu_hps_ram_region_ramspace1 = 1, + ccu_hps_ram_region_ramspace2 = 2, + ccu_hps_ram_region_ramspace3 = 3, + ccu_hps_ram_region_ramspace4 = 4, + ccu_hps_ram_region_ramspace5 = 5, +} ccu_hps_ram_region_t; + +// Disables a RAM (OCRAM) region with the given ID. +int ccu_hps_ram_region_disable(int id); + +// Enables a RAM (OCRAM) region with the given ID. +int ccu_hps_ram_region_enable(int id); + +// Attempts to remap a RAM (OCRAM) region with the given ID to span the given +// start and end address. It also assigns the security and privilege policy. +// Regions must be a power-of-two size with a minimum size of 64B. +int ccu_hps_ram_region_remap(int id, uintptr_t start, uintptr_t end, +CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege); + +// Verifies that all enabled RAM (OCRAM) regions does not overlap. +int ccu_hps_ram_validate(void); + +typedef enum ccu_hps_mem_region_e { + ccu_hps_mem_region_ddrspace0 = 0, + ccu_hps_mem_region_memspace0 = 1, + ccu_hps_mem_region_memspace1a = 2, + ccu_hps_mem_region_memspace1b = 3, + ccu_hps_mem_region_memspace1c = 4, + ccu_hps_mem_region_memspace1d = 5, + ccu_hps_mem_region_memspace1e = 6, +} ccu_hps_mem_region_t; + +// Disables mem0 (DDR) region with the given ID. +int ccu_hps_mem0_region_disable(int id); + +// Enables mem0 (DDR) region with the given ID. +int ccu_hps_mem0_region_enable(int id); + +// Attempts to remap mem0 (DDR) region with the given ID to span the given +// start and end address. It also assigns the security nad privlege policy. +// Regions must be a power-of-two in size with a minimum size of 64B. +int ccu_hps_mem0_region_remap(int id, uintptr_t start, uintptr_t end, +CCU_REGION_SECURITY_t security, CCU_REGION_PRIVILEGE_t privilege); + +// Verifies that all enabled mem0 (DDR) regions does not overlap. +int ccu_hps_mem0_validate(void); + +typedef enum ccu_hps_ios_region_e { + ccu_hps_ios_region_iospace0a = 0, + ccu_hps_ios_region_iospace0b = 1, + ccu_hps_ios_region_iospace1a = 2, + ccu_hps_ios_region_iospace1b = 3, + ccu_hps_ios_region_iospace1c = 4, + ccu_hps_ios_region_iospace1d = 5, + ccu_hps_ios_region_iospace1e = 6, + ccu_hps_ios_region_iospace1f = 7, + ccu_hps_ios_region_iospace1g = 8, + ccu_hps_ios_region_iospace2a = 9, + ccu_hps_ios_region_iospace2b = 10, + ccu_hps_ios_region_iospace2c = 11, +} ccu_hps_ios_region_t; + +// Disables the IOS (IO Slave) region with the given ID. +int ccu_hps_ios_region_disable(int id); + +// Enables the IOS (IO Slave) region with the given ID. +int ccu_hps_ios_region_enable(int id); + + +#define NCORE_CCU_OFFSET 0xf7000000 /* Coherent Sub-System Address Map */ -#define NCORE_CAIU_OFFSET 0x00000 -#define NCORE_CAIU_SIZE 0x01000 - -#define NCORE_NCBU_OFFSET 0x60000 -#define NCORE_NCBU_SIZE 0x01000 - -#define NCORE_DIRU_OFFSET 0x80000 -#define NCORE_DIRU_SIZE 0x01000 - -#define NCORE_CMIU_OFFSET 0xc0000 -#define NCORE_CMIU_SIZE 0x01000 - -#define NCORE_CSR_OFFSET 0xff000 -#define NCORE_CSADSERO 0x00040 -#define NCORE_CSUIDR 0x00ff8 -#define NCORE_CSIDR 0x00ffc - +#define NCORE_CAIU_OFFSET 0x00000 +#define NCORE_CAIU_SIZE 0x01000 +#define NCORE_NCBU_OFFSET 0x60000 +#define NCORE_NCBU_SIZE 0x01000 +#define NCORE_DIRU_OFFSET 0x80000 +#define NCORE_DIRU_SIZE 0x01000 +#define NCORE_CMIU_OFFSET 0xc0000 +#define NCORE_CMIU_SIZE 0x01000 +#define NCORE_CSR_OFFSET 0xff000 +#define NCORE_CSADSERO 0x00040 +#define NCORE_CSUIDR 0x00ff8 +#define NCORE_CSIDR 0x00ffc /* Directory Unit Register Map */ -#define NCORE_DIRUSFER 0x00010 -#define NCORE_DIRUMRHER 0x00070 -#define NCORE_DIRUSFMCR 0x00080 -#define NCORE_DIRUSFMAR 0x00084 - +#define NCORE_DIRUSFER 0x00010 +#define NCORE_DIRUMRHER 0x00070 +#define NCORE_DIRUSFMCR 0x00080 +#define NCORE_DIRUSFMAR 0x00084 /* Coherent Agent Interface Unit Register Map */ -#define NCORE_CAIUIDR 0x00ffc - +#define NCORE_CAIUIDR 0x00ffc /* Snoop Enable Register */ -#define NCORE_DIRUCASER0 0x00040 -#define NCORE_DIRUCASER1 0x00044 -#define NCORE_DIRUCASER2 0x00048 -#define NCORE_DIRUCASER3 0x0004c - -#define NCORE_CSADSER0 0x00040 -#define NCORE_CSADSER1 0x00044 -#define NCORE_CSADSER2 0x00048 -#define NCORE_CSADSER3 0x0004c - +#define NCORE_DIRUCASER0 0x00040 +#define NCORE_DIRUCASER1 0x00044 +#define NCORE_DIRUCASER2 0x00048 +#define NCORE_DIRUCASER3 0x0004c +#define NCORE_CSADSER0 0x00040 +#define NCORE_CSADSER1 0x00044 +#define NCORE_CSADSER2 0x00048 +#define NCORE_CSADSER3 0x0004c /* Protocols Definition */ -#define ACE_W_DVM 0 -#define ACE_L_W_DVM 1 -#define ACE_WO_DVM 2 -#define ACE_L_WO_DVM 3 - +#define ACE_W_DVM 0 +#define ACE_L_W_DVM 1 +#define ACE_WO_DVM 2 +#define ACE_L_WO_DVM 3 /* Bypass OC Ram Firewall */ -#define NCORE_FW_OCRAM_BLK_BASE 0x100200 -#define NCORE_FW_OCRAM_BLK_CGF1 0x04 -#define NCORE_FW_OCRAM_BLK_CGF2 0x08 -#define NCORE_FW_OCRAM_BLK_CGF3 0x0c -#define NCORE_FW_OCRAM_BLK_CGF4 0x10 - -#define OCRAM_PRIVILEGED_MASK BIT(29) -#define OCRAM_SECURE_MASK BIT(30) - +#define NCORE_FW_OCRAM_BLK_BASE 0x100200 +#define NCORE_FW_OCRAM_BLK_CGF1 0x04 +#define NCORE_FW_OCRAM_BLK_CGF2 0x08 +#define NCORE_FW_OCRAM_BLK_CGF3 0x0c +#define NCORE_FW_OCRAM_BLK_CGF4 0x10 +#define OCRAM_PRIVILEGED_MASK BIT(29) +#define OCRAM_SECURE_MASK BIT(30) /* Macros */ -#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base)) -#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\ +#define NCORE_CCU_REG(base) (NCORE_CCU_OFFSET + (base)) +#define NCORE_CCU_CSR(reg) (NCORE_CCU_REG(NCORE_CSR_OFFSET)\ + (reg)) -#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\ +#define NCORE_CCU_DIR(reg) (NCORE_CCU_REG(NCORE_DIRU_OFFSET)\ + (reg)) -#define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\ +#define NCORE_CCU_CAI(reg) (NCORE_CCU_REG(NCORE_CAIU_OFFSET)\ + (reg)) - -#define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ +#define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ + NCORE_DIRU_SIZE * (x)) -#define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ +#define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ + NCORE_CAIU_SIZE * (x)) - -#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\ +#define COH_CPU0_BYPASS_REG(reg) (NCORE_CCU_REG(NCORE_FW_OCRAM_BLK_BASE)\ + (reg)) - -#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24) -#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16) -#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8) -#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0) - -#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18) - -#define SNOOP_FILTER_ID(x) (((x) << 16)) - -#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) -#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16) - +#define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24) +#define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16) +#define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8) +#define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0) +#define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18) +#define SNOOP_FILTER_ID(x) (((x) << 16)) +#define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) +#define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16) typedef struct coh_ss_id { uint8_t num_coh_mem; @@ -105,5 +426,6 @@ uint32_t init_ncore_ccu(void); void ncore_enable_ocram_firewall(void); +void setup_smmu_stream_id(void); #endif
diff --git a/plat/intel/soc/common/drivers/combophy/combophy.c b/plat/intel/soc/common/drivers/combophy/combophy.c new file mode 100644 index 0000000..6c53bc1 --- /dev/null +++ b/plat/intel/soc/common/drivers/combophy/combophy.c
@@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +#include "combophy.h" +#include "sdmmc/sdmmc.h" + +/* Temp assigned handoff data, need to remove when SDM up and run. */ +void config_nand(handoff *hoff_ptr) +{ + /* This is hardcoded input value for Combo PHY and SD host controller. */ + hoff_ptr->peripheral_pwr_gate_array = 0x40; + +} + +/* DFI configuration */ +int dfi_select(handoff *hoff_ptr) +{ + uint32_t data = 0; + + /* Temp assigned handoff data, need to remove when SDM up and run. */ + handoff reverse_handoff_ptr; + + /* Temp assigned handoff data, need to remove when SDM up and run. */ + config_nand(&reverse_handoff_ptr); + + if (((reverse_handoff_ptr.peripheral_pwr_gate_array) & PERIPHERAL_SDMMC_MASK) == 0U) { + ERROR("SDMMC/NAND is not set properly\n"); + return -ENXIO; + } + + mmio_setbits_32(SOCFPGA_SYSMGR(DFI_INTF), + (((reverse_handoff_ptr.peripheral_pwr_gate_array) & + PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)); + data = mmio_read_32(SOCFPGA_SYSMGR(DFI_INTF)); + if ((data & DFI_INTF_MASK) != (((reverse_handoff_ptr.peripheral_pwr_gate_array) & + PERIPHERAL_SDMMC_MASK) >> PERIPHERAL_SDMMC_OFFSET)) { + ERROR("DFI is not set properly\n"); + return -ENXIO; + } + + return 0; +} + +int combo_phy_init(handoff *hoff_ptr) +{ + /* SDMMC/NAND DFI selection based on system manager DFI register */ + int ret = dfi_select(hoff_ptr); + + if (ret != 0U) { + ERROR("DFI configuration failed\n"); + return ret; + } + + return 0; +}
diff --git a/plat/intel/soc/common/drivers/combophy/combophy.h b/plat/intel/soc/common/drivers/combophy/combophy.h new file mode 100644 index 0000000..ca571f7 --- /dev/null +++ b/plat/intel/soc/common/drivers/combophy/combophy.h
@@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef COMBOPHY_H +#define COMBOPHY_H + +#include <lib/mmio.h> + +#include "socfpga_handoff.h" + +#define PERIPHERAL_SDMMC_MASK 0x60 +#define PERIPHERAL_SDMMC_OFFSET 6 +#define DFI_INTF_MASK 0x1 + +/* FUNCTION DEFINATION */ +/* + * @brief Nand controller initialization function + * + * @hoff_ptr: Pointer to the hand-off data + * Return: 0 on success, a negative errno on failure + */ +int combo_phy_init(handoff *hoff_ptr); +int dfi_select(handoff *hoff_ptr); + +#endif
diff --git a/plat/intel/soc/common/drivers/ddr/ddr.c b/plat/intel/soc/common/drivers/ddr/ddr.c new file mode 100644 index 0000000..188302f --- /dev/null +++ b/plat/intel/soc/common/drivers/ddr/ddr.c
@@ -0,0 +1,342 @@ +/* + * Copyright (c) 2022, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <common/debug.h> +#include "ddr.h" +#include <lib/mmio.h> +#include "socfpga_handoff.h" + +int ddr_calibration_check(void) +{ + // DDR calibration check + int status = 0; + uint32_t u32data_read = 0; + + NOTICE("DDR: Access address 0x%x:...\n", IO96B_0_REG_BASE); + u32data_read = mmio_read_32(IO96B_0_REG_BASE); + NOTICE("DDR: Access address 0x%x: read 0x%04x\n", IO96B_0_REG_BASE, u32data_read); + + if (u32data_read == -EPERM) { + status = -EPERM; + assert(u32data_read); + } + + u32data_read = 0x0; + NOTICE("DDR: Access address 0x%x: ...\n", IO96B_1_REG_BASE); + u32data_read = mmio_read_32(IO96B_1_REG_BASE); + NOTICE("DDR: Access address 0x%x: read 0x%04x\n", IO96B_1_REG_BASE, u32data_read); + + if (u32data_read == -EPERM) { + status = -EPERM; + assert(u32data_read); + } + + return status; +} + +int iossm_mb_init(void) +{ + // int status; + + // Update according to IOSSM mailbox spec + + // if (status) { + // return status; + // } + + return 0; +} + +int wait_respond(uint16_t timeout) +{ + uint32_t status = 0; + uint32_t count = 0; + uint32_t data = 0; + + /* Wait status command response ready */ + do { + data = mmio_read_32(IO96B_CSR_REG(CMD_RESPONSE_STATUS)); + count++; + if (count >= timeout) { + return -ETIMEDOUT; + } + + } while (STATUS_COMMAND_RESPONSE(data) != STATUS_COMMAND_RESPONSE_READY); + + status = (data & STATUS_GENERAL_ERROR_MASK) >> STATUS_GENERAL_ERROR_OFFSET; + if (status != 0) { + return status; + } + + status = (data & STATUS_CMD_RESPONSE_ERROR_MASK) >> STATUS_CMD_RESPONSE_ERROR_OFFSET; + if (status != 0) { + return status; + } + + return status; +} + +int iossm_mb_read_response(void) +{ + uint32_t status = 0; + unsigned int i; + uint32_t resp_data[IOSSM_RESP_MAX_WORD_SIZE]; + uint32_t resp_param_reg; + + // Check STATUS_CMD_RESPONSE_DATA_PTR_VALID in + // STATUS_COMMAND_RESPONSE to ensure data pointer response + + /* Read CMD_RESPONSE_STATUS and CMD_RESPONSE_DATA_* */ + resp_data[0] = mmio_read_32(IO96B_CSR_REG(CMD_RESPONSE_STATUS)); + resp_data[0] = (resp_data[0] & CMD_RESPONSE_DATA_SHORT_MASK) >> + CMD_RESPONSE_DATA_SHORT_OFFSET; + resp_param_reg = CMD_RESPONSE_STATUS; + for (i = 1; i < IOSSM_RESP_MAX_WORD_SIZE; i++) { + resp_param_reg = resp_param_reg - CMD_RESPONSE_OFFSET; + resp_data[i] = mmio_read_32(IO96B_CSR_REG(resp_param_reg)); + } + + /* Wait for STATUS_COMMAND_RESPONSE_READY*/ + status = wait_respond(1000); + + /* Read CMD_RESPONSE_STATUS and CMD_RESPONSE_DATA_* */ + mmio_setbits_32(STATUS_COMMAND_RESPONSE(IO96B_CSR_REG( + CMD_RESPONSE_STATUS)), + STATUS_COMMAND_RESPONSE_READY_CLEAR); + + return status; +} + +int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id, + uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args, + unsigned int len) +{ + unsigned int i; + uint32_t status = 0; + uint32_t cmd_req; + uint32_t cmd_param_reg; + + cmd_target_ip_type = (cmd_target_ip_type & CMD_TARGET_IP_TYPE_MASK) << + CMD_TARGET_IP_TYPE_OFFSET; + cmd_target_ip_instance_id = (cmd_target_ip_instance_id & + CMD_TARGET_IP_INSTANCE_ID_MASK) << + CMD_TARGET_IP_INSTANCE_ID_OFFSET; + cmd_type = (cmd_type & CMD_TYPE_MASK) << CMD_TYPE_OFFSET; + cmd_opcode = (cmd_opcode & CMD_OPCODE_MASK) << CMD_OPCODE_OFFSET; + cmd_req = cmd_target_ip_type | cmd_target_ip_instance_id | cmd_type | + cmd_opcode; + + /* send mailbox request */ + IOSSM_MB_WRITE(IO96B_CSR_REG(CMD_REQ), cmd_req); + if (len != 0) { + cmd_param_reg = CMD_REQ; + for (i = 0; i < len; i++) { + cmd_param_reg = cmd_param_reg - CMD_PARAM_OFFSET; + IOSSM_MB_WRITE(IO96B_CSR_REG(cmd_param_reg), args[i]); + } + } + + status = iossm_mb_read_response(); + if (status != 0) { + return status; + } + + return status; +} + +int ddr_iossm_mailbox_cmd(uint32_t cmd_opcode) +{ + // IOSSM + uint32_t status = 0; + unsigned int i = 0; + uint32_t payload[IOSSM_CMD_MAX_WORD_SIZE] = {0U}; + + switch (cmd_opcode) { + case CMD_INIT: + status = iossm_mb_init(); + break; + + case OPCODE_GET_MEM_INTF_INFO: + status = iossm_mb_send(0, 0, MBOX_CMD_GET_SYS_INFO, + OPCODE_GET_MEM_INTF_INFO, payload, i); + break; + + case OPCODE_GET_MEM_TECHNOLOGY: + status = iossm_mb_send(0, 0, MBOX_CMD_GET_MEM_INFO, + OPCODE_GET_MEM_TECHNOLOGY, payload, i); + break; + + case OPCODE_GET_MEM_WIDTH_INFO: + status = iossm_mb_send(0, 0, MBOX_CMD_GET_MEM_INFO, + OPCODE_GET_MEM_WIDTH_INFO, payload, i); + break; + + case OPCODE_ECC_ENABLE_STATUS: + status = iossm_mb_send(0, 0, + MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_ENABLE_STATUS, + payload, i); + break; + + case OPCODE_ECC_INTERRUPT_MASK: + // payload[i] = CMD_PARAM_0 [16:0]: ECC_INTERRUPT_MASK + status = iossm_mb_send(0, 0, + MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_INTERRUPT_MASK, + payload, i); + break; + + case OPCODE_ECC_SCRUB_MODE_0_START: + // payload[i] = CMD_PARAM_0 [15:0]: ECC_SCRUB_INTERVAL + //i++; + // payload[i] = CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN + //i++; + // payload[i] = CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM + //i++; + // payload[i]= CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0] + //i++; + // payload[i] = CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32] + //i++; + // payload[i] = CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0] + //i++; + // payload[i] = CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32] + //i++; + status = iossm_mb_send(0, 0, + MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_SCRUB_MODE_0_START, + payload, i); + break; + + case OPCODE_ECC_SCRUB_MODE_1_START: + // payload[i] = CMD_PARAM_0 [15:0]: ECC_SCRUB_IDLE_CNT + //i++; + // payload[i] = CMD_PARAM_1 [11:0]: ECC_SCRUB_LEN + //i++; + // payload[i] = CMD_PARAM_2 [0:0]: ECC_SCRUB_FULL_MEM + //i++; + // payload[i] = CMD_PARAM_3 [31:0]: ECC_SCRUB_START_ADDR [31:0] + //i++; + // payload[i] = CMD_PARAM_4 [5:0]: ECC_SCRUB_START_ADDR [36:32] + //i++; + // payload[i] = CMD_PARAM_5 [31:0]: ECC_SCRUB_END_ADDR [31:0] + //i++; + // payload[i] = CMD_PARAM_6 [5:0]: ECC_SCRUB_END_ADDR [36:32] + //i++; + status = iossm_mb_send(0, 0, + MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_ECC_SCRUB_MODE_1_START, + payload, i); + break; + + case OPCODE_BIST_RESULTS_STATUS: + status = iossm_mb_send(0, 0, + MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_BIST_RESULTS_STATUS, + payload, i); + break; + + case OPCODE_BIST_MEM_INIT_START: + status = iossm_mb_send(0, 0, + MBOX_CMD_TRIG_CONTROLLER_OP, OPCODE_BIST_MEM_INIT_START, + payload, i); + break; + + case OPCODE_TRIG_MEM_CAL: + status = iossm_mb_send(0, 0, MBOX_CMD_TRIG_MEM_CAL_OP, + OPCODE_TRIG_MEM_CAL, payload, i); + break; + + default: + break; + } + + if (status == -EPERM) { + assert(status); + } + + return status; +} + +int ddr_config_handoff(handoff *hoff_ptr) +{ + /* Populate DDR handoff data */ + /* TODO: To add in DDR handoff configuration once available */ + return 0; +} + +// DDR firewall and non secure access +void ddr_enable_ns_access(void) +{ + /* Please set the ddr non secure registers accordingly */ + + mmio_setbits_32(CCU_REG(DMI0_DMIUSMCTCR), + CCU_DMI_ALLOCEN | CCU_DMI_LOOKUPEN); + mmio_setbits_32(CCU_REG(DMI1_DMIUSMCTCR), + CCU_DMI_ALLOCEN | CCU_DMI_LOOKUPEN); + + /* TODO: To add in CCU NCORE OCRAM bypass mask for non secure registers */ + NOTICE("DDR non secure configured\n"); +} + +void ddr_enable_firewall(void) +{ + /* Please set the ddr firewall registers accordingly */ + /* TODO: To add in CCU NCORE OCRAM bypass mask for firewall registers */ + NOTICE("DDR firewall enabled\n"); +} + +bool is_ddr_init_in_progress(void) +{ + uint32_t reg = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0)); + + if (reg & SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK) { + return true; + } + return false; +} + +int ddr_init(void) +{ + // DDR driver initialization + int status = -EPERM; + uint32_t cmd_opcode = 0; + + // Check and set Boot Scratch Register + if (is_ddr_init_in_progress()) { + return status; + } + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), 0x01); + + // Populate DDR handoff data + handoff reverse_handoff_ptr; + + if (!socfpga_get_handoff(&reverse_handoff_ptr)) { + assert(status); + } + status = ddr_config_handoff(&reverse_handoff_ptr); + if (status == -EPERM) { + assert(status); + } + + // CCU and firewall setup + ddr_enable_ns_access(); + ddr_enable_firewall(); + + // DDR calibration check + status = ddr_calibration_check(); + if (status == -EPERM) { + assert(status); + } + + // DDR mailbox command + status = ddr_iossm_mailbox_cmd(cmd_opcode); + if (status != 0) { + assert(status); + } + + // Check and set Boot Scratch Register + mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_0), 0x00); + + NOTICE("DDR init successfully\n"); + return status; +}
diff --git a/plat/intel/soc/common/drivers/ddr/ddr.h b/plat/intel/soc/common/drivers/ddr/ddr.h new file mode 100644 index 0000000..416b64e --- /dev/null +++ b/plat/intel/soc/common/drivers/ddr/ddr.h
@@ -0,0 +1,112 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDR_H +#define DDR_H + +#include <lib/mmio.h> +#include "socfpga_handoff.h" + +/* MACRO DEFINATION */ +#define IO96B_0_REG_BASE 0x18400000 +#define IO96B_1_REG_BASE 0x18800000 +#define IO96B_CSR_BASE 0x05000000 +#define IO96B_CSR_REG(reg) (IO96B_CSR_BASE + reg) + +#define IOSSM_CMD_MAX_WORD_SIZE 7U +#define IOSSM_RESP_MAX_WORD_SIZE 4U + +#define CCU_REG_BASE 0x1C000000 +#define DMI0_DMIUSMCTCR 0x7300 +#define DMI1_DMIUSMCTCR 0x8300 +#define CCU_DMI_ALLOCEN BIT(1) +#define CCU_DMI_LOOKUPEN BIT(2) +#define CCU_REG(reg) (CCU_REG_BASE + reg) + +// CMD_RESPONSE_STATUS Register +#define CMD_RESPONSE_STATUS 0x45C +#define CMD_RESPONSE_OFFSET 0x4 +#define CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define CMD_RESPONSE_DATA_SHORT_OFFSET 16 +#define STATUS_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define STATUS_CMD_RESPONSE_ERROR_OFFSET 5 +#define STATUS_GENERAL_ERROR_MASK GENMASK(4, 1) +#define STATUS_GENERAL_ERROR_OFFSET 1 +#define STATUS_COMMAND_RESPONSE_READY 0x1 +#define STATUS_COMMAND_RESPONSE_READY_CLEAR 0x0 +#define STATUS_COMMAND_RESPONSE_READY_MASK 0x1 +#define STATUS_COMMAND_RESPONSE_READY_OFFSET 0 +#define STATUS_COMMAND_RESPONSE(x) (((x) & \ + STATUS_COMMAND_RESPONSE_READY_MASK) >> \ + STATUS_COMMAND_RESPONSE_READY_OFFSET) + +// CMD_REQ Register +#define CMD_STATUS 0x400 +#define CMD_PARAM 0x438 +#define CMD_REQ 0x43C +#define CMD_PARAM_OFFSET 0x4 +#define CMD_TARGET_IP_TYPE_MASK GENMASK(31, 29) +#define CMD_TARGET_IP_TYPE_OFFSET 29 +#define CMD_TARGET_IP_INSTANCE_ID_MASK GENMASK(28, 24) +#define CMD_TARGET_IP_INSTANCE_ID_OFFSET 24 +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_TYPE_OFFSET 16 +#define CMD_OPCODE_MASK GENMASK(15, 0) +#define CMD_OPCODE_OFFSET 0 + +#define CMD_INIT 0 + +#define OPCODE_GET_MEM_INTF_INFO 0x0001 +#define OPCODE_GET_MEM_TECHNOLOGY 0x0002 +#define OPCODE_GET_MEM_WIDTH_INFO 0x0004 +#define OPCODE_TRIG_MEM_CAL 0x000A +#define OPCODE_ECC_ENABLE_STATUS 0x0102 +#define OPCODE_ECC_INTERRUPT_MASK 0x0105 +#define OPCODE_ECC_SCRUB_MODE_0_START 0x0202 +#define OPCODE_ECC_SCRUB_MODE_1_START 0x0203 +#define OPCODE_BIST_RESULTS_STATUS 0x0302 +#define OPCODE_BIST_MEM_INIT_START 0x0303 +// Please update according to IOSSM mailbox spec +#define MBOX_ID_IOSSM 0x00 +#define MBOX_CMD_GET_SYS_INFO 0x01 +// Please update according to IOSSM mailbox spec +#define MBOX_CMD_GET_MEM_INFO 0x02 +#define MBOX_CMD_TRIG_CONTROLLER_OP 0x04 +#define MBOX_CMD_TRIG_MEM_CAL_OP 0x05 +#define MBOX_CMD_POKE_REG 0xFD +#define MBOX_CMD_PEEK_REG 0xFE +#define MBOX_CMD_GET_DEBUG_LOG 0xFF +// Please update according to IOSSM mailbox spec +#define MBOX_CMD_DIRECT 0x00 + +#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0_MASK 0x01 + +#define IOSSM_MB_WRITE(addr, data) mmio_write_32(addr, data) + +/* FUNCTION DEFINATION */ +int ddr_calibration_check(void); + +int iossm_mb_init(void); + +int iossm_mb_read_response(void); + +int iossm_mb_send(uint32_t cmd_target_ip_type, uint32_t cmd_target_ip_instance_id, + uint32_t cmd_type, uint32_t cmd_opcode, uint32_t *args, + unsigned int len); + +int ddr_iossm_mailbox_cmd(uint32_t cmd); + +int ddr_init(void); + +int ddr_config_handoff(handoff *hoff_ptr); + +void ddr_enable_ns_access(void); + +void ddr_enable_firewall(void); + +bool is_ddr_init_in_progress(void); + +#endif
diff --git a/plat/intel/soc/common/drivers/nand/nand.c b/plat/intel/soc/common/drivers/nand/nand.c new file mode 100644 index 0000000..c6acbe3 --- /dev/null +++ b/plat/intel/soc/common/drivers/nand/nand.c
@@ -0,0 +1,57 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_nand.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> +#include "nand.h" + +#include "agilex5_pinmux.h" +#include "combophy/combophy.h" + +/* Pinmux configuration */ +static void nand_pinmux_config(void) +{ + mmio_write_32(SOCFPGA_PINMUX(PIN0SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN1SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN2SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN3SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN4SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN5SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN6SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN7SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN8SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN9SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN10SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN11SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN12SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN13SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN14SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN16SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN17SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN18SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN19SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN20SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN21SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN22SEL), SOCFPGA_PINMUX_SEL_NAND); + mmio_write_32(SOCFPGA_PINMUX(PIN23SEL), SOCFPGA_PINMUX_SEL_NAND); +} + +int nand_init(handoff *hoff_ptr) +{ + /* NAND pin mux configuration */ + nand_pinmux_config(); + + return cdns_nand_host_init(); +}
diff --git a/plat/intel/soc/common/drivers/nand/nand.h b/plat/intel/soc/common/drivers/nand/nand.h new file mode 100644 index 0000000..b060a72 --- /dev/null +++ b/plat/intel/soc/common/drivers/nand/nand.h
@@ -0,0 +1,22 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef DDR_H +#define DDR_H + +#include <lib/mmio.h> +#include "socfpga_handoff.h" + +/* FUNCTION DEFINATION */ +/* + * @brief Nand controller initialization function + * + * @hoff_ptr: Pointer to the hand-off data + * Return: 0 on success, a negative errno on failure + */ +int nand_init(handoff *hoff_ptr); + +#endif
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c index cecf560..da8a8bd 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.c +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.c
@@ -13,6 +13,7 @@ #include <drivers/console.h> #include "cadence_qspi.h" +#include "socfpga_plat_def.h" #define LESS(a, b) (((a) < (b)) ? (a) : (b)) #define MORE(a, b) (((a) > (b)) ? (a) : (b))
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h index cfef585..104ab5f 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h
@@ -10,8 +10,6 @@ #define CAD_QSPI_MICRON_N25Q_SUPPORT 1 -#define CAD_QSPI_OFFSET 0xff8d2000 - #define CAD_INVALID -1 #define CAD_QSPI_ERROR -2 @@ -38,8 +36,6 @@ #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb #define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd -#define CAD_QSPIDATA_OFST 0xff900000 - #define CAD_QSPI_DELAY 0xc #define CAD_QSPI_DELAY_CSSOT(x) (((x) & 0xff) << 0) #define CAD_QSPI_DELAY_CSEOT(x) (((x) & 0xff) << 8)
diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.c b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c new file mode 100644 index 0000000..8666f54 --- /dev/null +++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.c
@@ -0,0 +1,769 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <errno.h> +#include <stdbool.h> +#include <string.h> + +#include <arch_helpers.h> +#include <common/debug.h> +#include <drivers/cadence/cdns_combo_phy.h> +#include <drivers/cadence/cdns_sdmmc.h> +#include <drivers/delay_timer.h> +#include <lib/mmio.h> +#include <lib/utils.h> + +#include "agilex5_pinmux.h" +#include "sdmmc.h" + +static const struct mmc_ops *ops; +static unsigned int mmc_ocr_value; +static struct mmc_csd_emmc mmc_csd; +static struct sd_switch_status sd_switch_func_status; +static unsigned char mmc_ext_csd[512] __aligned(16); +static unsigned int mmc_flags; +static struct mmc_device_info *mmc_dev_info; +static unsigned int rca; +static unsigned int scr[2]__aligned(16) = { 0 }; + +extern const struct mmc_ops cdns_sdmmc_ops; +extern struct cdns_sdmmc_params cdns_params; +extern struct cdns_sdmmc_combo_phy sdmmc_combo_phy_reg; +extern struct cdns_sdmmc_sdhc sdmmc_sdhc_reg; + +static bool is_cmd23_enabled(void) +{ + return ((mmc_flags & MMC_FLAG_CMD23) != 0U); +} + +static bool is_sd_cmd6_enabled(void) +{ + return ((mmc_flags & MMC_FLAG_SD_CMD6) != 0U); +} + +/* TODO: Will romove once ATF driver is developed */ +void sdmmc_pin_config(void) +{ + /* temp use base + addr. Official must change to common method */ + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x00, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x04, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x08, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x0C, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x10, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x14, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x18, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x1C, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x20, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x24, 0x0); + mmio_write_32(AGX5_PINMUX_PIN0SEL+0x28, 0x0); +} + +static int sdmmc_send_cmd(unsigned int idx, unsigned int arg, + unsigned int r_type, unsigned int *r_data) +{ + struct mmc_cmd cmd; + int ret; + + zeromem(&cmd, sizeof(struct mmc_cmd)); + + cmd.cmd_idx = idx; + cmd.cmd_arg = arg; + cmd.resp_type = r_type; + + ret = ops->send_cmd(&cmd); + + if ((ret == 0) && (r_data != NULL)) { + int i; + + for (i = 0; i < 4; i++) { + *r_data = cmd.resp_data[i]; + r_data++; + } + } + + if (ret != 0) { + VERBOSE("Send command %u error: %d\n", idx, ret); + } + + return ret; +} + +static int sdmmc_device_state(void) +{ + int retries = DEFAULT_SDMMC_MAX_RETRIES; + unsigned int resp_data[4]; + + do { + int ret; + + if (retries == 0) { + ERROR("CMD13 failed after %d retries\n", + DEFAULT_SDMMC_MAX_RETRIES); + return -EIO; + } + + ret = sdmmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, &resp_data[0]); + if (ret != 0) { + retries--; + continue; + } + + if ((resp_data[0] & STATUS_SWITCH_ERROR) != 0U) { + return -EIO; + } + + retries--; + } while ((resp_data[0] & STATUS_READY_FOR_DATA) == 0U); + + return MMC_GET_STATE(resp_data[0]); +} + +static int sdmmc_set_ext_csd(unsigned int ext_cmd, unsigned int value) +{ + int ret; + + ret = sdmmc_send_cmd(MMC_CMD(6), + EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) | + EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL, + MMC_RESPONSE_R1B, NULL); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret == MMC_STATE_PRG); + + return 0; +} + +static int sdmmc_mmc_sd_switch(unsigned int bus_width) +{ + int ret; + int retries = DEFAULT_SDMMC_MAX_RETRIES; + unsigned int bus_width_arg = 0; + + /* CMD55: Application Specific Command */ + ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R5, NULL); + if (ret != 0) { + return ret; + } + + ret = ops->prepare(0, (uintptr_t)&scr, sizeof(scr)); + if (ret != 0) { + return ret; + } + + /* ACMD51: SEND_SCR */ + do { + ret = sdmmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL); + if ((ret != 0) && (retries == 0)) { + ERROR("ACMD51 failed after %d retries (ret=%d)\n", + DEFAULT_SDMMC_MAX_RETRIES, ret); + return ret; + } + + retries--; + } while (ret != 0); + + ret = ops->read(0, (uintptr_t)&scr, sizeof(scr)); + if (ret != 0) { + return ret; + } + + if (((scr[0] & SD_SCR_BUS_WIDTH_4) != 0U) && + (bus_width == MMC_BUS_WIDTH_4)) { + bus_width_arg = 2; + } + + /* CMD55: Application Specific Command */ + ret = sdmmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R5, NULL); + if (ret != 0) { + return ret; + } + + /* ACMD6: SET_BUS_WIDTH */ + ret = sdmmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret == MMC_STATE_PRG); + + return 0; +} + +static int sdmmc_set_ios(unsigned int clk, unsigned int bus_width) +{ + int ret; + unsigned int width = bus_width; + + if (mmc_dev_info->mmc_dev_type != MMC_IS_EMMC) { + if (width == MMC_BUS_WIDTH_8) { + WARN("Wrong bus config for SD-card, force to 4\n"); + width = MMC_BUS_WIDTH_4; + } + ret = sdmmc_mmc_sd_switch(width); + if (ret != 0) { + return ret; + } + } else if (mmc_csd.spec_vers == 4U) { + ret = sdmmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, + (unsigned int)width); + if (ret != 0) { + return ret; + } + } else { + VERBOSE("Wrong MMC type or spec version\n"); + } + + return ops->set_ios(clk, width); +} + +static int sdmmc_fill_device_info(void) +{ + unsigned long long c_size; + unsigned int speed_idx; + unsigned int nb_blocks; + unsigned int freq_unit; + int ret = 0; + struct mmc_csd_sd_v2 *csd_sd_v2; + + switch (mmc_dev_info->mmc_dev_type) { + case MMC_IS_EMMC: + mmc_dev_info->block_size = MMC_BLOCK_SIZE; + + ret = ops->prepare(0, (uintptr_t)&mmc_ext_csd, + sizeof(mmc_ext_csd)); + if (ret != 0) { + return ret; + } + + /* MMC CMD8: SEND_EXT_CSD */ + ret = sdmmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + ret = ops->read(0, (uintptr_t)&mmc_ext_csd, + sizeof(mmc_ext_csd)); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret != MMC_STATE_TRAN); + + nb_blocks = (mmc_ext_csd[CMD_EXTCSD_SEC_CNT] << 0) | + (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 1] << 8) | + (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 2] << 16) | + (mmc_ext_csd[CMD_EXTCSD_SEC_CNT + 3] << 24); + + mmc_dev_info->device_size = (unsigned long long)nb_blocks * + mmc_dev_info->block_size; + + break; + + case MMC_IS_SD: + /* + * Use the same mmc_csd struct, as required fields here + * (READ_BL_LEN, C_SIZE, CSIZE_MULT) are common with eMMC. + */ + mmc_dev_info->block_size = BIT_32(mmc_csd.read_bl_len); + + c_size = ((unsigned long long)mmc_csd.c_size_high << 2U) | + (unsigned long long)mmc_csd.c_size_low; + assert(c_size != 0xFFFU); + + mmc_dev_info->device_size = (c_size + 1U) * + BIT_64(mmc_csd.c_size_mult + 2U) * + mmc_dev_info->block_size; + + break; + + case MMC_IS_SD_HC: + assert(mmc_csd.csd_structure == 1U); + + mmc_dev_info->block_size = MMC_BLOCK_SIZE; + + /* Need to use mmc_csd_sd_v2 struct */ + csd_sd_v2 = (struct mmc_csd_sd_v2 *)&mmc_csd; + c_size = ((unsigned long long)csd_sd_v2->c_size_high << 16) | + (unsigned long long)csd_sd_v2->c_size_low; + + mmc_dev_info->device_size = (c_size + 1U) << SDMMC_MULT_BY_512K_SHIFT; + + break; + + default: + ret = -EINVAL; + break; + } + + if (ret < 0) { + return ret; + } + + speed_idx = (mmc_csd.tran_speed & CSD_TRAN_SPEED_MULT_MASK) >> + CSD_TRAN_SPEED_MULT_SHIFT; + + assert(speed_idx > 0U); + + if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { + mmc_dev_info->max_bus_freq = tran_speed_base[speed_idx]; + } else { + mmc_dev_info->max_bus_freq = sd_tran_speed_base[speed_idx]; + } + + freq_unit = mmc_csd.tran_speed & CSD_TRAN_SPEED_UNIT_MASK; + while (freq_unit != 0U) { + mmc_dev_info->max_bus_freq *= 10U; + --freq_unit; + } + + mmc_dev_info->max_bus_freq *= 10000U; + + return 0; +} + +static int sdmmc_sd_switch(unsigned int mode, unsigned char group, + unsigned char func) +{ + unsigned int group_shift = (group - 1U) * 4U; + unsigned int group_mask = GENMASK(group_shift + 3U, group_shift); + unsigned int arg; + int ret; + + ret = ops->prepare(0, (uintptr_t)&sd_switch_func_status, + sizeof(sd_switch_func_status)); + if (ret != 0) { + return ret; + } + + /* MMC CMD6: SWITCH_FUNC */ + arg = mode | SD_SWITCH_ALL_GROUPS_MASK; + arg &= ~group_mask; + arg |= func << group_shift; + ret = sdmmc_send_cmd(MMC_CMD(6), arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + return ops->read(0, (uintptr_t)&sd_switch_func_status, + sizeof(sd_switch_func_status)); +} + +static int sdmmc_sd_send_op_cond(void) +{ + int n; + unsigned int resp_data[4]; + + for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) { + int ret; + + /* CMD55: Application Specific Command */ + ret = sdmmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + /* ACMD41: SD_SEND_OP_COND */ + ret = sdmmc_send_cmd(MMC_ACMD(41), OCR_HCS | + mmc_dev_info->ocr_voltage, MMC_RESPONSE_R3, + &resp_data[0]); + if (ret != 0) { + return ret; + } + + if ((resp_data[0] & OCR_POWERUP) != 0U) { + mmc_ocr_value = resp_data[0]; + + if ((mmc_ocr_value & OCR_HCS) != 0U) { + mmc_dev_info->mmc_dev_type = MMC_IS_SD_HC; + } else { + mmc_dev_info->mmc_dev_type = MMC_IS_SD; + } + + return 0; + } + + mdelay(10); + } + + ERROR("ACMD41 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES); + + return -EIO; +} + +static int sdmmc_reset_to_idle(void) +{ + int ret; + + /* CMD0: reset to IDLE */ + ret = sdmmc_send_cmd(MMC_CMD(0), 0, 0, NULL); + if (ret != 0) { + return ret; + } + + mdelay(2); + + return 0; +} + +static int sdmmc_send_op_cond(void) +{ + int ret, n; + unsigned int resp_data[4]; + + ret = sdmmc_reset_to_idle(); + if (ret != 0) { + return ret; + } + + for (n = 0; n < SEND_SDMMC_OP_COND_MAX_RETRIES; n++) { + ret = sdmmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE | + OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7, + MMC_RESPONSE_R3, &resp_data[0]); + if (ret != 0) { + return ret; + } + + if ((resp_data[0] & OCR_POWERUP) != 0U) { + mmc_ocr_value = resp_data[0]; + return 0; + } + + mdelay(10); + } + + ERROR("CMD1 failed after %d retries\n", SEND_SDMMC_OP_COND_MAX_RETRIES); + + return -EIO; +} + +static int sdmmc_enumerate(unsigned int clk, unsigned int bus_width) +{ + int ret; + unsigned int resp_data[4]; + + ops->init(); + + ret = sdmmc_reset_to_idle(); + if (ret != 0) { + return ret; + } + + if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { + ret = sdmmc_send_op_cond(); + } else { + /* CMD8: Send Interface Condition Command */ + ret = sdmmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN, + MMC_RESPONSE_R5, &resp_data[0]); + + if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) { + ret = sdmmc_sd_send_op_cond(); + } + } + if (ret != 0) { + return ret; + } + + /* CMD2: Card Identification */ + ret = sdmmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL); + if (ret != 0) { + return ret; + } + + /* CMD3: Set Relative Address */ + if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) { + rca = MMC_FIX_RCA; + ret = sdmmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + } else { + ret = sdmmc_send_cmd(MMC_CMD(3), 0, + MMC_RESPONSE_R6, &resp_data[0]); + if (ret != 0) { + return ret; + } + + rca = (resp_data[0] & 0xFFFF0000U) >> 16; + } + + /* CMD9: CSD Register */ + ret = sdmmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R2, &resp_data[0]); + if (ret != 0) { + return ret; + } + + memcpy(&mmc_csd, &resp_data, sizeof(resp_data)); + + /* CMD7: Select Card */ + ret = sdmmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return ret; + } + + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return ret; + } + } while (ret != MMC_STATE_TRAN); + + ret = sdmmc_set_ios(clk, bus_width); + if (ret != 0) { + return ret; + } + + ret = sdmmc_fill_device_info(); + if (ret != 0) { + return ret; + } + + if (is_sd_cmd6_enabled() && + (mmc_dev_info->mmc_dev_type == MMC_IS_SD_HC)) { + /* Try to switch to High Speed Mode */ + ret = sdmmc_sd_switch(SD_SWITCH_FUNC_CHECK, 1U, 1U); + if (ret != 0) { + return ret; + } + + if ((sd_switch_func_status.support_g1 & BIT(9)) == 0U) { + /* High speed not supported, keep default speed */ + return 0; + } + + ret = sdmmc_sd_switch(SD_SWITCH_FUNC_SWITCH, 1U, 1U); + if (ret != 0) { + return ret; + } + + if ((sd_switch_func_status.sel_g2_g1 & 0x1U) == 0U) { + /* Cannot switch to high speed, keep default speed */ + return 0; + } + + mmc_dev_info->max_bus_freq = 50000000U; + ret = ops->set_ios(clk, bus_width); + } + + return ret; +} + +size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size) +{ + int ret; + unsigned int cmd_idx, cmd_arg; + + assert((ops != NULL) && + (ops->read != NULL) && + (size != 0U) && + ((size & MMC_BLOCK_MASK) == 0U)); + + ret = ops->prepare(lba, buf, size); + if (ret != 0) { + return 0; + } + + if (is_cmd23_enabled()) { + /* Set block count */ + ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + cmd_idx = MMC_CMD(18); + } else { + if (size > MMC_BLOCK_SIZE) { + cmd_idx = MMC_CMD(18); + } else { + cmd_idx = MMC_CMD(17); + } + } + + if (((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) && + (mmc_dev_info->mmc_dev_type != MMC_IS_SD_HC)) { + cmd_arg = lba * MMC_BLOCK_SIZE; + } else { + cmd_arg = lba; + } + + ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + ret = ops->read(lba, buf, size); + if (ret != 0) { + return 0; + } + + /* Wait buffer empty */ + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return 0; + } + } while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA)); + + if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) { + ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL); + if (ret != 0) { + return 0; + } + } + + return size; +} + +size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size) +{ + int ret; + unsigned int cmd_idx, cmd_arg; + + assert((ops != NULL) && + (ops->write != NULL) && + (size != 0U) && + ((buf & MMC_BLOCK_MASK) == 0U) && + ((size & MMC_BLOCK_MASK) == 0U)); + + ret = ops->prepare(lba, buf, size); + if (ret != 0) { + return 0; + } + + if (is_cmd23_enabled()) { + /* Set block count */ + ret = sdmmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE, + MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + cmd_idx = MMC_CMD(25); + } else { + if (size > MMC_BLOCK_SIZE) { + cmd_idx = MMC_CMD(25); + } else { + cmd_idx = MMC_CMD(24); + } + } + + if ((mmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) { + cmd_arg = lba * MMC_BLOCK_SIZE; + } else { + cmd_arg = lba; + } + + ret = sdmmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL); + if (ret != 0) { + return 0; + } + + ret = ops->write(lba, buf, size); + if (ret != 0) { + return 0; + } + + /* Wait buffer empty */ + do { + ret = sdmmc_device_state(); + if (ret < 0) { + return 0; + } + } while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_RCV)); + + if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) { + ret = sdmmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL); + if (ret != 0) { + return 0; + } + } + + return size; +} + +int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, + unsigned int width, unsigned int flags, + struct mmc_device_info *device_info) +{ + assert((ops_ptr != NULL) && + (ops_ptr->init != NULL) && + (ops_ptr->send_cmd != NULL) && + (ops_ptr->set_ios != NULL) && + (ops_ptr->prepare != NULL) && + (ops_ptr->read != NULL) && + (ops_ptr->write != NULL) && + (device_info != NULL) && + (clk != 0) && + ((width == MMC_BUS_WIDTH_1) || + (width == MMC_BUS_WIDTH_4) || + (width == MMC_BUS_WIDTH_8) || + (width == MMC_BUS_WIDTH_DDR_4) || + (width == MMC_BUS_WIDTH_DDR_8))); + + ops = ops_ptr; + mmc_flags = flags; + mmc_dev_info = device_info; + + return sdmmc_enumerate(clk, width); +} + +int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, struct mmc_device_info *info) +{ + int result = 0; + + /* SDMMC pin mux configuration */ + sdmmc_pin_config(); + cdns_set_sdmmc_var(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + result = cdns_sd_host_init(&sdmmc_combo_phy_reg, &sdmmc_sdhc_reg); + if (result < 0) { + return result; + } + + assert((params != NULL) && + ((params->reg_base & MMC_BLOCK_MASK) == 0) && + ((params->desc_base & MMC_BLOCK_MASK) == 0) && + ((params->desc_size & MMC_BLOCK_MASK) == 0) && + ((params->reg_pinmux & MMC_BLOCK_MASK) == 0) && + ((params->reg_phy & MMC_BLOCK_MASK) == 0) && + (params->desc_size > 0) && + (params->clk_rate > 0) && + ((params->bus_width == MMC_BUS_WIDTH_1) || + (params->bus_width == MMC_BUS_WIDTH_4) || + (params->bus_width == MMC_BUS_WIDTH_8))); + + memcpy(&cdns_params, params, sizeof(struct cdns_sdmmc_params)); + cdns_params.cdn_sdmmc_dev_type = info->mmc_dev_type; + cdns_params.cdn_sdmmc_dev_mode = SD_DS; + + result = sd_or_mmc_init(&cdns_sdmmc_ops, params->clk_rate, params->bus_width, + params->flags, info); + + return result; +}
diff --git a/plat/intel/soc/common/drivers/sdmmc/sdmmc.h b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h new file mode 100644 index 0000000..16c6b04 --- /dev/null +++ b/plat/intel/soc/common/drivers/sdmmc/sdmmc.h
@@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SDMMC_H +#define SDMMC_H + +#include <lib/mmio.h> +#include "socfpga_handoff.h" + +#define PERIPHERAL_SDMMC_MASK 0x60 +#define PERIPHERAL_SDMMC_OFFSET 6 + +#define DEFAULT_SDMMC_MAX_RETRIES 5 +#define SEND_SDMMC_OP_COND_MAX_RETRIES 100 +#define SDMMC_MULT_BY_512K_SHIFT 19 + +static const unsigned char tran_speed_base[16] = { + 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 +}; + +static const unsigned char sd_tran_speed_base[16] = { + 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 +}; + + +/* FUNCTION DEFINATION */ +/* + * @brief SDMMC controller initialization function + * + * @hoff_ptr: Pointer to the hand-off data + * Return: 0 on success, a negative errno on failure + */ +int sdmmc_init(handoff *hoff_ptr, struct cdns_sdmmc_params *params, + struct mmc_device_info *info); +int sd_or_mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, + unsigned int width, unsigned int flags, + struct mmc_device_info *device_info); +void sdmmc_pin_config(void); +#endif
diff --git a/plat/intel/soc/common/drivers/wdt/watchdog.h b/plat/intel/soc/common/drivers/wdt/watchdog.h index 2c72463..4ee4cff 100644 --- a/plat/intel/soc/common/drivers/wdt/watchdog.h +++ b/plat/intel/soc/common/drivers/wdt/watchdog.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,11 @@ #ifndef CAD_WATCHDOG_H #define CAD_WATCHDOG_H +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +#define WDT_BASE (0x10D00200) +#else #define WDT_BASE (0xFFD00200) +#endif #define WDT_REG_SIZE_OFFSET (0x4) #define WDT_MIN_CYCLES (65536) #define WDT_PERIOD (20)
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 4e50156..49fc567 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h
@@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,28 +12,37 @@ #include <common/interrupt_props.h> #include <common/tbbr/tbbr_img_def.h> #include <plat/common/common_def.h> +#include "socfpga_plat_def.h" /* Platform Type */ #define PLAT_SOCFPGA_STRATIX10 1 #define PLAT_SOCFPGA_AGILEX 2 #define PLAT_SOCFPGA_N5X 3 -#define PLAT_SOCFPGA_EMULATOR 0 +#define PLAT_SOCFPGA_AGILEX5 4 +#define SIMICS_RUN 1 +#define MAX_IO_MTD_DEVICES U(1) /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ #define PLAT_CPU_RELEASE_ADDR 0xffd12210 -/* - * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset - * is done and HPS should trigger warm reset via RMR_EL3. - */ -#define L2_RESET_DONE_REG 0xFFD12218 - /* Magic word to indicate L2 reset is completed */ #define L2_RESET_DONE_STATUS 0x1228E5E7 /* Define next boot image name and offset */ +/* Get non-secure image entrypoint for BL33. Zephyr and Linux */ +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + +#ifndef PRELOADED_BL33_BASE +#define PLAT_NS_IMAGE_OFFSET 0x80200000 +#else +#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE +#endif +#define PLAT_HANDOFF_OFFSET 0x0003F000 + +#else #define PLAT_NS_IMAGE_OFFSET 0x10000000 #define PLAT_HANDOFF_OFFSET 0xFFE3F000 +#endif /******************************************************************************* * Platform binary types for linking @@ -49,7 +58,6 @@ /******************************************************************************* * Generic platform constants ******************************************************************************/ -#define PLAT_PRIMARY_CPU 0 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 /* Size of cacheable stacks */ @@ -64,49 +72,27 @@ #define PLATFORM_CLUSTER_COUNT U(1) #define PLATFORM_CLUSTER0_CORE_COUNT U(4) #define PLATFORM_CLUSTER1_CORE_COUNT U(0) -#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ - PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) /* Interrupt related constant */ #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 -#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 +#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 -#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER -#define TSP_SEC_MEM_BASE BL32_BASE -#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) -/******************************************************************************* - * Platform memory map related constants - ******************************************************************************/ -#define DRAM_BASE (0x0) -#define DRAM_SIZE (0x80000000) +#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) -#define OCRAM_BASE (0xFFE00000) -#define OCRAM_SIZE (0x00040000) - -#define MEM64_BASE (0x0100000000) -#define MEM64_SIZE (0x1F00000000) - -#define DEVICE1_BASE (0x80000000) -#define DEVICE1_SIZE (0x60000000) - -#define DEVICE2_BASE (0xF7000000) -#define DEVICE2_SIZE (0x08E00000) - -#define DEVICE3_BASE (0xFFFC0000) -#define DEVICE3_SIZE (0x00008000) - -#define DEVICE4_BASE (0x2000000000) -#define DEVICE4_SIZE (0x0100000000) /******************************************************************************* * BL31 specific defines. @@ -117,33 +103,28 @@ * little space for growth. */ +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" -#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#define BL1_RO_BASE (0xffe00000) +#define BL1_RO_LIMIT (0xffe0f000) +#define BL1_RW_BASE (0xffe10000) +#define BL1_RW_LIMIT (0xffe1ffff) +#define BL1_RW_SIZE (0x14000) -#define BL1_RO_BASE (0xffe00000) -#define BL1_RO_LIMIT (0xffe0f000) -#define BL1_RW_BASE (0xffe10000) -#define BL1_RW_LIMIT (0xffe1ffff) -#define BL1_RW_SIZE (0x14000) +#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET -#define BL2_BASE (0xffe00000) -#define BL2_LIMIT (0xffe1b000) +#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) +#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) -#define BL31_BASE (0x1000) -#define BL31_LIMIT (0x81000) +#define CMP_ENTRY 0xFFE3EFF8 -#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET - -#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) -#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) - -#define PLAT_SEC_WARM_ENTRY 0 +#define PLAT_SEC_WARM_ENTRY 0 /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define MAX_XLAT_TABLES 8 -#define MAX_MMAP_REGIONS 16 +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 /******************************************************************************* * Declarations and constants to access the mailboxes safely. Each mailbox is @@ -155,46 +136,34 @@ * a valid mailbox address. ******************************************************************************/ #define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) - -#define PLAT_GIC_BASE (0xFFFC0000) -#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000) -#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000) -#define PLAT_GICR_BASE 0 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) /******************************************************************************* * UART related constants ******************************************************************************/ -#define PLAT_UART0_BASE (0xFFC02000) -#define PLAT_UART1_BASE (0xFFC02100) +#define CRASH_CONSOLE_BASE PLAT_UART0_BASE +#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE -#define CRASH_CONSOLE_BASE PLAT_UART0_BASE -#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE - -#if PLAT_SOCFPGA_EMULATOR -#define PLAT_BAUDRATE (4800) -#define PLAT_UART_CLOCK (76800) -#else -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) -#endif +#define PLAT_BAUDRATE (115200) +#define PLAT_UART_CLOCK (100000000) /******************************************************************************* * PHY related constants ******************************************************************************/ -#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII -#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII -#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII +#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII +#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII +#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII + +/******************************************************************************* + * GIC related constants + ******************************************************************************/ +#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE +#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE /******************************************************************************* * System counter frequency related constants ******************************************************************************/ -#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000) -#define PLAT_HZ_CONVERT_TO_MHZ (1000000) - -#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE -#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE /* * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 @@ -223,9 +192,9 @@ #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) -#define MAX_IO_HANDLES 4 -#define MAX_IO_DEVICES 4 -#define MAX_IO_BLOCK_DEVICES 2 +#define MAX_IO_HANDLES 4 +#define MAX_IO_DEVICES 4 +#define MAX_IO_BLOCK_DEVICES 2 #ifndef __ASSEMBLER__ struct socfpga_bl31_params { @@ -239,4 +208,3 @@ #endif #endif /* PLATFORM_DEF_H */ -
diff --git a/plat/intel/soc/common/include/socfpga_f2sdram_manager.h b/plat/intel/soc/common/include/socfpga_f2sdram_manager.h index b30a11e..1bebfc9 100644 --- a/plat/intel/soc/common/include/socfpga_f2sdram_manager.h +++ b/plat/intel/soc/common/include/socfpga_f2sdram_manager.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,7 @@ #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTCLR0 0x54 #define SOCFPGA_F2SDRAMMGR_SIDEBANDMGR_FLAGOUTSET0 0x50 +#define FLAGOUTCLR0_F2SDRAM0_ENABLE (BIT(8)) #define FLAGOUTSETCLR_F2SDRAM0_ENABLE (BIT(1)) #define FLAGOUTSETCLR_F2SDRAM1_ENABLE (BIT(4)) #define FLAGOUTSETCLR_F2SDRAM2_ENABLE (BIT(7))
diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h index 8a8f348..6bb70e0 100644 --- a/plat/intel/soc/common/include/socfpga_fcs.h +++ b/plat/intel/soc/common/include/socfpga_fcs.h
@@ -72,6 +72,9 @@ #define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */ #define FCS_AES_CMD_MAX_WORD_SIZE 15U +#define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */ +#define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */ + #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U
diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h index ba0f7f3..b2913c7 100644 --- a/plat/intel/soc/common/include/socfpga_handoff.h +++ b/plat/intel/soc/common/include/socfpga_handoff.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,13 +7,15 @@ #ifndef HANDOFF_H #define HANDOFF_H -#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ -#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ -#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ -#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ -#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ -#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ -#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ +#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */ +#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */ +#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */ +#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */ +#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */ +#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */ +#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */ +#define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */ +#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */ #include <socfpga_plat_def.h> @@ -39,8 +41,9 @@ uint32_t pinmux_fpga_magic; uint32_t pinmux_fpga_length; uint32_t _pad_0x338_0x340[2]; - uint32_t pinmux_fpga_array[42]; /* offset, value */ - uint32_t _pad_0x3e8_0x3f0[2]; + uint32_t pinmux_fpga_array[44]; /* offset, value */ + /* TODO: Temp remove due to add in extra handoff data */ + // uint32_t _pad_0x3e8_0x3f0[2]; /* pinmux configuration - io delay */ uint32_t pinmux_delay_magic; @@ -49,7 +52,6 @@ uint32_t pinmux_iodelay_array[96]; /* offset, value */ /* clock configuration */ - #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 uint32_t clock_magic; uint32_t clock_length; @@ -120,16 +122,68 @@ uint32_t hps_osc_clk_h; uint32_t fpga_clk_hz; uint32_t _pad_0x604_0x610[3]; +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + uint32_t clock_magic; + uint32_t clock_length; + uint32_t _pad_0x588_0x590[2]; + uint32_t main_pll_nocclk; + uint32_t main_pll_nocdiv; + uint32_t main_pll_pllglob; + uint32_t main_pll_fdbck; + uint32_t main_pll_pllc0; + uint32_t main_pll_pllc1; + uint32_t main_pll_pllc2; + uint32_t main_pll_pllc3; + uint32_t main_pll_pllm; + uint32_t per_pll_emacctl; + uint32_t per_pll_gpiodiv; + uint32_t per_pll_pllglob; + uint32_t per_pll_fdbck; + uint32_t per_pll_pllc0; + uint32_t per_pll_pllc1; + uint32_t per_pll_pllc2; + uint32_t per_pll_pllc3; + uint32_t per_pll_pllm; + uint32_t alt_emacactr; + uint32_t alt_emacbctr; + uint32_t alt_emacptpctr; + uint32_t alt_gpiodbctr; + uint32_t alt_sdmmcctr; + uint32_t alt_s2fuser0ctr; + uint32_t alt_s2fuser1ctr; + uint32_t alt_psirefctr; + /* TODO: Temp added for clk manager. */ + uint32_t qspi_clk_khz; + uint32_t hps_osc_clk_hz; + uint32_t fpga_clk_hz; + /* TODO: Temp added for clk manager. */ + uint32_t ddr_reset_type; + /* TODO: Temp added for clk manager. */ + uint32_t hps_status_coldreset; + /* TODO: Temp remove due to add in extra handoff data */ + //uint32_t _pad_0x604_0x610[3]; #endif /* misc configuration */ uint32_t misc_magic; uint32_t misc_length; uint32_t _pad_0x618_0x620[2]; + +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + /* peripheral configuration - select */ + uint32_t peripheral_pwr_gate_magic; + uint32_t peripheral_pwr_gate_length; + uint32_t _pad_0x08_0x0C[2]; + uint32_t peripheral_pwr_gate_array; /* offset, value */ + + /* ddr configuration - select */ + uint32_t ddr_magic; + uint32_t ddr_length; + uint32_t _pad_0x1C_0x20[2]; + uint32_t ddr_array[4]; /* offset, value */ +#endif } handoff; int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr); int socfpga_get_handoff(handoff *hoff_ptr); #endif - -
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h index 3abf39d..77d3af9 100644 --- a/plat/intel/soc/common/include/socfpga_mailbox.h +++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +9,11 @@ #include <lib/utils_def.h> - +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +#define MBOX_OFFSET 0x10a30000 +#else #define MBOX_OFFSET 0xffa30000 +#endif #define MBOX_ATF_CLIENT_ID 0x1U #define MBOX_MAX_JOB_ID 0xFU @@ -63,6 +66,9 @@ #define MBOX_CMD_QSPI_SET_CS 0x34 #define MBOX_CMD_QSPI_DIRECT 0x3B +/* SEU Commands */ +#define MBOX_CMD_SEU_ERR_READ 0x3C + /* RSU Commands */ #define MBOX_GET_SUBPARTITION_TABLE 0x5A #define MBOX_RSU_STATUS 0x5B @@ -190,9 +196,9 @@ #define RSU_VERSION_ACMF_MASK 0xff00 /* Config Status Macros */ -#define CONFIG_STATUS_WORD_SIZE 16U -#define CONFIG_STATUS_FW_VER_OFFSET 1 -#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF +#define CONFIG_STATUS_WORD_SIZE 16U +#define CONFIG_STATUS_FW_VER_OFFSET 1 +#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF /* Data structure */ @@ -230,6 +236,7 @@ unsigned int *resp_len); void mailbox_reset_cold(void); +void mailbox_reset_warm(uint32_t reset_type); void mailbox_clear_response(void); int intel_mailbox_get_config_status(uint32_t cmd, bool init_done); @@ -241,5 +248,6 @@ int mailbox_hps_stage_notify(uint32_t execution_stage); int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf); int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf); +int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len); #endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_noc.h b/plat/intel/soc/common/include/socfpga_noc.h index e3c0f73..3fc3f81 100644 --- a/plat/intel/soc/common/include/socfpga_noc.h +++ b/plat/intel/soc/common/include/socfpga_noc.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,6 +74,10 @@ #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG4 0x007c +#define SOCFPGA_NOC_FW_L4_SYS_SCR_PWRMGR 0x0080 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_RXECC 0x0084 +#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_TXECC 0x0088 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094
diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h index cce16ab..9d06a3d 100644 --- a/plat/intel/soc/common/include/socfpga_reset_manager.h +++ b/plat/intel/soc/common/include/socfpga_reset_manager.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,10 @@ #include "socfpga_plat_def.h" +/* Status Response */ +#define RSTMGR_RET_OK 0 +#define RSTMGR_RET_ERROR -1 + #define SOCFPGA_BRIDGE_ENABLE BIT(0) #define SOCFPGA_BRIDGE_HAS_MASK BIT(1) @@ -22,28 +26,51 @@ /* Register Mapping */ #define SOCFPGA_RSTMGR_STAT 0x000 +#define SOCFPGA_RSTMGR_MISCSTAT 0x008 #define SOCFPGA_RSTMGR_HDSKEN 0x010 #define SOCFPGA_RSTMGR_HDSKREQ 0x014 #define SOCFPGA_RSTMGR_HDSKACK 0x018 +#define SOCFPGA_RSTMGR_HDSKSTALL 0x01C +#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 #define SOCFPGA_RSTMGR_MPUMODRST 0x020 +#endif #define SOCFPGA_RSTMGR_PER0MODRST 0x024 #define SOCFPGA_RSTMGR_PER1MODRST 0x028 -#define SOCFPGA_RSTMGR_BRGMODRST 0x02c +#define SOCFPGA_RSTMGR_BRGMODRST 0x02C +#if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 #define SOCFPGA_RSTMGR_COLDMODRST 0x034 +#endif +#define SOCFPGA_RSTMGR_DBGMODRST 0x03C +#define SOCFPGA_RSTMGR_BRGWARMMASK 0x04C +#define SOCFPGA_RSTMGR_TSTSTA 0x05C #define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 +#define SOCFPGA_RSTMGR_DBGHDSKTIMEOUT 0x06C +#define SOCFPGA_RSTMGR_DBGRSTCMPLT 0x070 +#define SOCFPGA_RSTMGR_HPSRSTCMPLT 0x080 +#define SOCFPGA_RSTMGR_CPUINREST 0x090 +#define SOCFPGA_RSTMGR_CPURSTRELEASE 0x094 +#define SOCFPGA_RSTMGR_CPUBASELOW_0 0x098 +#define SOCFPGA_RSTMGR_CPUBASEHIGH_0 0x09C +#define SOCFPGA_RSTMGR_CPUBASELOW_1 0x0A0 +#define SOCFPGA_RSTMGR_CPUBASEHIGH_1 0x0A4 +#define SOCFPGA_RSTMGR_CPUBASELOW_2 0x0A8 +#define SOCFPGA_RSTMGR_CPUBASEHIGH_2 0x0AC +#define SOCFPGA_RSTMGR_CPUBASELOW_3 0x0B0 +#define SOCFPGA_RSTMGR_CPUBASEHIGH_3 0x0B4 /* Field Mapping */ - -#define RSTMGR_PER0MODRST_EMAC0 0x00000001 -#define RSTMGR_PER0MODRST_EMAC1 0x00000002 -#define RSTMGR_PER0MODRST_EMAC2 0x00000004 +/* PER0MODRST */ +#define RSTMGR_PER0MODRST_EMAC0 0x00000001 //TSN0 +#define RSTMGR_PER0MODRST_EMAC1 0x00000002 //TSN1 +#define RSTMGR_PER0MODRST_EMAC2 0x00000004 //TSN2 #define RSTMGR_PER0MODRST_USB0 0x00000008 #define RSTMGR_PER0MODRST_USB1 0x00000010 #define RSTMGR_PER0MODRST_NAND 0x00000020 +#define RSTMGR_PER0MODRST_SOFTPHY 0x00000040 #define RSTMGR_PER0MODRST_SDMMC 0x00000080 -#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 -#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 -#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 +#define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 //TSN0ECC +#define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 //TSN1ECC +#define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 //TSN2ECC #define RSTMGR_PER0MODRST_USB0OCP 0x00000800 #define RSTMGR_PER0MODRST_USB1OCP 0x00001000 #define RSTMGR_PER0MODRST_NANDOCP 0x00002000 @@ -64,6 +91,7 @@ #define RSTMGR_PER0MODRST_DMAIF6 0x40000000 #define RSTMGR_PER0MODRST_DMAIF7 0x80000000 +/* PER1MODRST */ #define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 #define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 #define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 @@ -77,31 +105,121 @@ #define RSTMGR_PER1MODRST_I2C2 0x00000400 #define RSTMGR_PER1MODRST_I2C3 0x00000800 #define RSTMGR_PER1MODRST_I2C4 0x00001000 +#define RSTMGR_PER1MODRST_I3C0 0x00002000 +#define RSTMGR_PER1MODRST_I3C1 0x00004000 #define RSTMGR_PER1MODRST_UART0 0x00010000 #define RSTMGR_PER1MODRST_UART1 0x00020000 #define RSTMGR_PER1MODRST_GPIO0 0x01000000 #define RSTMGR_PER1MODRST_GPIO1 0x02000000 +#define RSTMGR_PER1MODRST_WATCHDOG4 0x04000000 +/* HDSKEN */ +#define RSTMGR_HDSKEN_EMIF_FLUSH 0x00000001 #define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 #define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 -#define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 +#define RSTMGR_HDSKEN_LWS2F_FLUSH 0x00000200 +#define RSTMGR_HDSKEN_S2F_FLUSH 0x00000400 +#define RSTMGR_HDSKEN_F2SDRAM_FLUSH 0x00000800 +#define RSTMGR_HDSKEN_F2S_FLUSH 0x00001000 #define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 #define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 -#define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 -#define RSTMGR_HDSKEQ_FPGAHSREQ 0x4 +/* HDSKREQ */ +#define RSTMGR_HDSKREQ_EMIFFLUSHREQ 0x00000001 +#define RSTMGR_HDSKREQ_ETRSTALLREQ 0x00000008 +#define RSTMGR_HDSKREQ_LWS2F_FLUSH 0x00000200 +#define RSTMGR_HDSKREQ_S2F_FLUSH 0x00000400 +#define RSTMGR_HDSKREQ_F2SDRAM_FLUSH 0x00000800 +#define RSTMGR_HDSKREQ_F2S_FLUSH 0x00001000 +#define RSTMGR_HDSKREQ_L3NOC_DBG 0x00010000 +#define RSTMGR_HDSKREQ_DEBUG_L3NOC 0x00020000 +#define RSTMGR_HDSKREQ_FPGAHSREQ 0x00000004 +#define RSTMGR_HDSKREQ_LWSOC2FPGAREQ 0x00000200 +#define RSTMGR_HDSKREQ_SOC2FPGAREQ 0x00000400 +#define RSTMGR_HDSKREQ_F2SDRAM0REQ 0x00000800 +#define RSTMGR_HDSKREQ_FPGA2SOCREQ 0x00001000 -#define RSTMGR_BRGMODRST_SOC2FPGA 0x1 -#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 -#define RSTMGR_BRGMODRST_FPGA2SOC 0x4 -#define RSTMGR_BRGMODRST_F2SSDRAM0 0x8 +/* HDSKACK */ +#define RSTMGR_HDSKACK_EMIFFLUSHREQ 0x00000001 +#define RSTMGR_HDSKACK_FPGAHSREQ 0x00000004 +#define RSTMGR_HDSKACK_ETRSTALLREQ 0x00000008 +#define RSTMGR_HDSKACK_LWS2F_FLUSH 0x00000200 +#define RSTMGR_HDSKACK_S2F_FLUSH 0x00000400 +#define RSTMGR_HDSKACK_F2SDRAM_FLUSH 0x00000800 +#define RSTMGR_HDSKACK_F2S_FLUSH 0x00001000 +#define RSTMGR_HDSKACK_L3NOC_DBG 0x00010000 +#define RSTMGR_HDSKACK_DEBUG_L3NOC 0x00020000 +#define RSTMGR_HDSKACK_FPGAHSACK 0x00000004 +#define RSTMGR_HDSKACK_LWSOC2FPGAACK 0x00000200 +#define RSTMGR_HDSKACK_SOC2FPGAACK 0x00000400 +#define RSTMGR_HDSKACK_F2SDRAM0ACK 0x00000800 +#define RSTMGR_HDSKACK_FPGA2SOCACK 0x00001000 +#define RSTMGR_HDSKACK_FPGAHSACK_DASRT 0x00000000 +#define RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT 0x00000000 +#define RSTMGR_HDSKACK_FPGA2SOCACK_DASRT 0x00000000 + +/* HDSKSTALL */ +#define RSTMGR_HDSKACK_ETRSTALLWARMRST 0x00000001 + +/* BRGMODRST */ +#define RSTMGR_BRGMODRST_SOC2FPGA 0x00000001 +#define RSTMGR_BRGMODRST_LWHPS2FPGA 0x00000002 +#define RSTMGR_BRGMODRST_FPGA2SOC 0x00000004 +#define RSTMGR_BRGMODRST_F2SSDRAM0 0x00000008 +#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10 #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 -#define RSTMGR_BRGMODRST_MPFE 0x40 #define RSTMGR_BRGMODRST_DDRSCH 0x40 +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +#define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 +#define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 +#endif -#define RSTMGR_HDSKREQ_FPGAHSREQ (BIT(2)) -#define RSTMGR_HDSKACK_FPGAHSACK_MASK (BIT(2)) +#define RSTMGR_BRGMODRST_MPFE 0x40 + +/* DBGMODRST */ +#define RSTMGR_DBGMODRST_DBG_RST 0x00000001 + +/* BRGMODRSTMASK */ +#define RSTMGR_BRGMODRSTMASK_SOC2FPGA 0x00000001 +#define RSTMGR_BRGMODRSTMASK_LWHPS2FPGA 0x00000002 +#define RSTMGR_BRGMODRSTMASK_FPGA2SOC 0x00000004 +#define RSTMGR_BRGMODRSTMASK_F2SDRAM0 0x00000008 +#define RSTMGR_BRGMODRSTMASK_MPFE 0x00000040 + +/* TSTSTA */ +#define RSTMGR_TSTSTA_RSTST 0x0000001F + +/* HDSKTIMEOUT */ +#define RSTMGR_HDSKTIMEOUT_VAL 0xFFFFFFFF + +/* DBGHDSKTIMEOUT */ +#define RSTMGR_DBGHDSKTIMEOUT_VAL 0xFFFFFFFF + +/* DBGRSTCMPLT */ +#define RSTMGR_DBGRSTCMPLT_VAL 0xFFFFFFFF + +/* HPSRSTCMPLT */ +#define RSTMGR_DBGRSTCMPLT_VAL 0xFFFFFFFF + +/* CPUINRESET */ +#define RSTMGR_CPUINRESET_CPU0 0x00000001 +#define RSTMGR_CPUINRESET_CPU1 0x00000002 +#define RSTMGR_CPUINRESET_CPU2 0x00000004 +#define RSTMGR_CPUINRESET_CPU3 0x00000008 + +/* CPUSTRELEASE */ +#define RSTMGR_CPUSTRELEASE_CPUx 0x10D11094 + +/* CPUxRESETBASE */ +#define RSTMGR_CPUxRESETBASELOW_CPU0 0x10D11098 +#define RSTMGR_CPUxRESETBASEHIGH_CPU0 0x10D1109C +#define RSTMGR_CPUxRESETBASELOW_CPU1 0x10D110A0 +#define RSTMGR_CPUxRESETBASEHIGH_CPU1 0x10D110A4 +#define RSTMGR_CPUxRESETBASELOW_CPU2 0x10D110A8 +#define RSTMGR_CPUxRESETBASEHIGH_CPU2 0x10D110AC +#define RSTMGR_CPUxRESETBASELOW_CPU3 0x10D110B0 +#define RSTMGR_CPUxRESETBASEHIGH_CPU3 0x10D110B4 /* Definitions */ @@ -109,17 +227,28 @@ #define RSTMGR_HDSKEN_SET 0x010D /* Macros */ +#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE + (SOCFPGA_RSTMGR_##_reg)) +#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) -#define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \ - + (SOCFPGA_RSTMGR_##_reg)) -#define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) +/* Reset type to SDM from PSCI */ +// Temp add macro here for reset type +#define SOCFPGA_RESET_TYPE_COLD 0 +#define SOCFPGA_RESET_TYPE_WARM 1 /* Function Declarations */ void deassert_peripheral_reset(void); void config_hps_hs_before_warm_reset(void); +int socfpga_bridges_reset(uint32_t mask); int socfpga_bridges_enable(uint32_t mask); int socfpga_bridges_disable(uint32_t mask); +int socfpga_cpurstrelease(unsigned int cpu_id); +int socfpga_cpu_reset_base(unsigned int cpu_id); + +/* SMP: Func proto */ +void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id); +void bl31_plat_set_secondary_cpu_off(void); + #endif /* SOCFPGA_RESETMANAGER_H */
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index 21169f7..0668301 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -15,6 +15,7 @@ #define INTEL_SIP_SMC_STATUS_NO_RESPONSE 0x3 #define INTEL_SIP_SMC_STATUS_ERROR 0x4 #define INTEL_SIP_SMC_RSU_ERROR 0x7 +#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR 0x8 /* SiP mailbox error code */ #define GENERIC_RESPONSE_ERROR 0x3FF @@ -138,6 +139,9 @@ #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT 0xC200008C #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE 0xC200008E +/* SEU ERR */ +#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099 + #define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF #define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U @@ -163,6 +167,7 @@ #define INTEL_SIP_SMC_V2_REG_WRITE 0xC2000402 #define INTEL_SIP_SMC_V2_REG_UPDATE 0xC2000403 #define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES 0xC2000404 +#define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR 0xC2000405 /* V2: Mailbox function identifier */ #define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND 0xC2000420 @@ -181,7 +186,7 @@ /* * Increase if there is new SMC function ID being added */ -#define SIP_SVC_VERSION_MINOR 1 +#define SIP_SVC_VERSION_MINOR 2 /* Structure Definitions */ @@ -215,6 +220,9 @@ uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, uint32_t val, uint32_t *retval); +/* Set RSU update address*/ +uint32_t intel_rsu_update(uint64_t update_address); + /* Miscellaneous HPS services */ uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask);
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h index 69ee6d3..f860f57 100644 --- a/plat/intel/soc/common/include/socfpga_system_manager.h +++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,26 +13,6 @@ #define SOCFPGA_SYSMGR_SDMMC 0x28 -#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c - -#define SOCFPGA_SYSMGR_EMAC_0 0x44 -#define SOCFPGA_SYSMGR_EMAC_1 0x48 -#define SOCFPGA_SYSMGR_EMAC_2 0x4c -#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 - -#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 -#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 -#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 -#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc -#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 -#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 - -#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 -#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 -#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 -#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 -#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 - /* Field Masking */ #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
diff --git a/plat/intel/soc/common/include/socfpga_vab.h b/plat/intel/soc/common/include/socfpga_vab.h new file mode 100644 index 0000000..f6081df --- /dev/null +++ b/plat/intel/soc/common/include/socfpga_vab.h
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2020-2023, Intel Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SOCFPGA_VAB_H +#define SOCFPGA_VAB_H + + +#include <stdlib.h> +#include "socfpga_fcs.h" + +struct fcs_hps_vab_certificate_data { + uint32_t vab_cert_magic_num; /* offset 0x10 */ + uint32_t flags; + uint8_t rsvd0_1[8]; + uint8_t fcs_sha384[FCS_SHA384_WORD_SIZE]; /* offset 0x20 */ +}; + +struct fcs_hps_vab_certificate_header { + uint32_t cert_magic_num; /* offset 0 */ + uint32_t cert_data_sz; + uint32_t cert_ver; + uint32_t cert_type; + struct fcs_hps_vab_certificate_data d; /* offset 0x10 */ + /* keychain starts at offset 0x50 */ +}; + +/* Macros */ +#define IS_BYTE_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) +#define BYTE_ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) +#define VAB_CERT_HEADER_SIZE sizeof(struct fcs_hps_vab_certificate_header) +#define VAB_CERT_MAGIC_OFFSET offsetof(struct fcs_hps_vab_certificate_header, d) +#define VAB_CERT_FIT_SHA384_OFFSET offsetof(struct fcs_hps_vab_certificate_data, fcs_sha384[0]) +#define SDM_CERT_MAGIC_NUM 0x25D04E7F +#define CHUNKSZ_PER_WD_RESET (256 * 1024) + +/* SHA related return Macro */ +#define ENOVABIMG 1 /* VAB certificate not available */ +#define EIMGERR 2 /* Image format/size not valid */ +#define ETIMEOUT 3 /* Execution timeout */ +#define EPROCESS 4 /* Process error */ +#define EKEYREJECTED 5/* Key was rejected by service */ + +/* Function Definitions */ +static size_t get_img_size(uint8_t *img_buf, size_t img_buf_sz); +int socfpga_vendor_authentication(void **p_image, size_t *p_size); +static uint32_t get_unaligned_le32(const void *p); +void sha384_csum_wd(const unsigned char *input, unsigned int ilen, +unsigned char *output, unsigned int chunk_sz); + +#endif
diff --git a/plat/intel/soc/common/sip/socfpga_sip_ecc.c b/plat/intel/soc/common/sip/socfpga_sip_ecc.c index c4e06a6..c444d48 100644 --- a/plat/intel/soc/common/sip/socfpga_sip_ecc.c +++ b/plat/intel/soc/common/sip/socfpga_sip_ecc.c
@@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. */ #include <assert.h> @@ -11,10 +11,12 @@ #include "socfpga_fcs.h" #include "socfpga_mailbox.h" +#include "socfpga_plat_def.h" #include "socfpga_reset_manager.h" #include "socfpga_sip_svc.h" #include "socfpga_system_manager.h" + uint32_t intel_ecc_dbe_notification(uint64_t dbe_value) { dbe_value &= WARM_RESET_WFI_FLAG;
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c index d99026b..beaa720 100644 --- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c +++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -1073,6 +1073,7 @@ uint32_t resp_len; uint32_t payload[FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE] = {0U}; uintptr_t mac_offset; + uint32_t dst_size_check = 0; if (dst_size == NULL || mbox_error == NULL) { return INTEL_SIP_SMC_STATUS_REJECTED; @@ -1097,6 +1098,14 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare crypto header */ @@ -1149,6 +1158,12 @@ FCS_CS_FIELD_FLAG_FINALIZE) { /* Copy mac data to command */ mac_offset = src_addr + data_size; + + if ((i + ((src_size - data_size) / MBOX_WORD_BYTE)) > + FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) mac_offset, src_size - data_size); @@ -1189,7 +1204,7 @@ uint32_t resp_len; uint32_t payload[FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE] = {0U}; uintptr_t mac_offset; - + uint32_t dst_size_check = 0; /* * Source data must be 4 bytes aligned * User data must be 8 bytes aligned @@ -1214,6 +1229,14 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare crypto header */ @@ -1269,6 +1292,12 @@ * mac_offset = MAC data */ mac_offset = dst_addr; + + if ((i + ((src_size - data_size) / MBOX_WORD_BYTE)) > + FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) mac_offset, src_size - data_size); @@ -1316,6 +1345,7 @@ uint32_t payload[FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE] = {0U}; uint32_t resp_len; uintptr_t hash_data_addr; + uint32_t dst_size_check = 0; if ((dst_size == NULL) || (mbox_error == NULL)) { return INTEL_SIP_SMC_STATUS_REJECTED; @@ -1331,6 +1361,14 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare command payload */ @@ -1357,6 +1395,12 @@ /* Hash Data */ i++; hash_data_addr = src_addr; + + if ((i + ((src_size) / MBOX_WORD_BYTE)) > + FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) hash_data_addr, src_size); @@ -1400,6 +1444,7 @@ uint32_t payload[FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE] = {0U}; uint32_t resp_len; uintptr_t hash_sig_pubkey_addr; + uint32_t dst_size_check = 0; if ((dst_size == NULL) || (mbox_error == NULL)) { return INTEL_SIP_SMC_STATUS_REJECTED; @@ -1415,6 +1460,14 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare command payload */ @@ -1443,6 +1496,12 @@ /* Hash Data Word, Signature Data Word and Public Key Data word */ i++; hash_sig_pubkey_addr = src_addr; + + if ((i + ((src_size) / MBOX_WORD_BYTE)) > + FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) hash_sig_pubkey_addr, src_size); @@ -1690,6 +1749,7 @@ uint32_t payload[FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE] = {0U}; uint32_t resp_len; uintptr_t sig_pubkey_offset; + uint32_t dst_size_check = 0; if ((dst_size == NULL) || (mbox_error == NULL)) { return INTEL_SIP_SMC_STATUS_REJECTED; @@ -1700,6 +1760,10 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + if (data_size > src_size) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + if (!is_size_4_bytes_aligned(src_size)) { return INTEL_SIP_SMC_STATUS_REJECTED; } @@ -1714,6 +1778,14 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare crypto header */ @@ -1761,6 +1833,12 @@ FCS_CS_FIELD_FLAG_FINALIZE) { /* Signature + Public Key Data */ sig_pubkey_offset = src_addr + data_size; + + if ((i + ((src_size - data_size) / MBOX_WORD_BYTE)) > + FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) sig_pubkey_offset, src_size - data_size); @@ -1801,6 +1879,7 @@ uint32_t payload[FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE] = {0U}; uint32_t resp_len; uintptr_t sig_pubkey_offset; + uint32_t dst_size_check = 0; /* * Source data must be 4 bytes aligned @@ -1819,11 +1898,23 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + if (data_size > src_size) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + if (!is_address_in_ddr_range(src_addr, src_size) || !is_address_in_ddr_range(dst_addr, *dst_size)) { return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare crypto header */ @@ -1874,6 +1965,12 @@ * sig_pubkey_offset is Signature + Public Key Data */ sig_pubkey_offset = dst_addr; + + if ((i + ((src_size - data_size) / MBOX_WORD_BYTE)) > + FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) sig_pubkey_offset, src_size - data_size); @@ -1990,11 +2087,13 @@ uint32_t payload[FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE] = {0U}; uint32_t resp_len; uintptr_t pubkey; + uint32_t dst_size_check = 0; if ((dst_size == NULL) || (mbox_error == NULL)) { return INTEL_SIP_SMC_STATUS_REJECTED; } + if (fcs_ecdh_request_param.session_id != session_id || fcs_ecdh_request_param.context_id != context_id) { return INTEL_SIP_SMC_STATUS_REJECTED; @@ -2005,6 +2104,14 @@ return INTEL_SIP_SMC_STATUS_REJECTED; } + dst_size_check = *dst_size; + if ((dst_size_check > FCS_MAX_DATA_SIZE || + dst_size_check < FCS_MIN_DATA_SIZE) || + (src_size > FCS_MAX_DATA_SIZE || + src_size < FCS_MIN_DATA_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + resp_len = *dst_size / MBOX_WORD_BYTE; /* Prepare command payload */ @@ -2028,6 +2135,12 @@ i++; /* Public key data */ pubkey = src_addr; + + if ((i + ((src_size) / MBOX_WORD_BYTE)) > + FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &payload[i], (uint8_t *) pubkey, src_size); i += src_size / MBOX_WORD_BYTE; @@ -2162,6 +2275,11 @@ fcs_aes_crypt_payload[i] = fcs_aes_init_payload.key_id; i++; + if ((i + ((fcs_aes_init_payload.param_size) / MBOX_WORD_BYTE)) > + FCS_AES_CMD_MAX_WORD_SIZE) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + memcpy((uint8_t *) &fcs_aes_crypt_payload[i], (uint8_t *) fcs_aes_init_payload.crypto_param, fcs_aes_init_payload.param_size);
diff --git a/plat/intel/soc/common/soc/socfpga_emac.c b/plat/intel/soc/common/soc/socfpga_emac.c index cacfd53..49c92c3 100644 --- a/plat/intel/soc/common/soc/socfpga_emac.c +++ b/plat/intel/soc/common/soc/socfpga_emac.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Intel Corporation. All rights reserved. + * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include <platform_def.h> #include "socfpga_emac.h" +#include "socfpga_plat_def.h" #include "socfpga_reset_manager.h" #include "socfpga_system_manager.h"
diff --git a/plat/intel/soc/common/soc/socfpga_firewall.c b/plat/intel/soc/common/soc/socfpga_firewall.c index fc3889c..6247df3 100644 --- a/plat/intel/soc/common/soc/socfpga_firewall.c +++ b/plat/intel/soc/common/soc/socfpga_firewall.c
@@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,11 @@ void enable_ns_peripheral_access(void) { mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL); +#if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \ + (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \ + (PLATFORM_MODEL == PLAT_SOCFPGA_N5X)) mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL); +#endif mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL); mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL); @@ -87,9 +91,19 @@ mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG1), DISABLE_L4_FIREWALL); mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG2), DISABLE_L4_FIREWALL); mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG3), DISABLE_L4_FIREWALL); +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG4), DISABLE_L4_FIREWALL); +#endif mmio_write_32(SOCFPGA_L4_SYS_SCR(DAP), DISABLE_L4_FIREWALL); +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + mmio_write_32(SOCFPGA_L4_SYS_SCR(PWRMGR), DISABLE_L4_FIREWALL); + + mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_RXECC), DISABLE_L4_FIREWALL); + mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_TXECC), DISABLE_L4_FIREWALL); +#endif + mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_PROBES), DISABLE_L4_FIREWALL); mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL);
diff --git a/plat/intel/soc/common/soc/socfpga_handoff.c b/plat/intel/soc/common/soc/socfpga_handoff.c index 4bb3a96..526c6e1 100644 --- a/plat/intel/soc/common/soc/socfpga_handoff.c +++ b/plat/intel/soc/common/soc/socfpga_handoff.c
@@ -1,9 +1,10 @@ /* - * Copyright (c) 2019, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <errno.h> #include <string.h> #include "socfpga_handoff.h" @@ -17,6 +18,10 @@ uint32_t *buffer; handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET; + if (sizeof(*handoff_ptr) > sizeof(handoff)) { + return -EOVERFLOW; + } + memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff)); buffer = (uint32_t *)reverse_hoff_ptr; @@ -24,16 +29,34 @@ for (i = 0; i < sizeof(handoff) / 4; i++) buffer[i] = SWAP_UINT32(buffer[i]); - if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) + if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) { return -1; - if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) + } + if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) { return -1; - if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) + } + if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) { return -1; - if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) + } + if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) { return -1; - if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) + } + if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) { return -1; + } + if (reverse_hoff_ptr->clock_magic != HANDOFF_MAGIC_CLOCK) { + return -1; + } + +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + if (reverse_hoff_ptr->peripheral_pwr_gate_magic != HANDOFF_MAGIC_PERIPHERAL) { + return -1; + } + + if (reverse_hoff_ptr->ddr_magic != HANDOFF_MAGIC_DDR) { + return -1; + } +#endif return 0; }
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c index 7010d81..d93fc8a 100644 --- a/plat/intel/soc/common/soc/socfpga_mailbox.c +++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -7,8 +7,10 @@ #include <lib/mmio.h> #include <common/debug.h> #include <drivers/delay_timer.h> +#include <platform_def.h> #include "socfpga_mailbox.h" +#include "socfpga_plat_def.h" #include "socfpga_sip_svc.h" #include "socfpga_system_manager.h" @@ -183,6 +185,7 @@ uint32_t resp_data; uint32_t ret_resp_len = 0; uint8_t is_done = 0; + uint32_t resp_len_check = 0; if ((mailbox_resp_ctr.flag & MBOX_PAYLOAD_FLAG_BUSY) != 0) { ret_resp_len = MBOX_RESP_LEN( @@ -242,6 +245,12 @@ *resp_len = ret_resp_len; } + resp_len_check = (uint32_t) *resp_len; + + if (resp_len_check > MBOX_DATA_MAX_LEN) { + return MBOX_RET_ERROR; + } + memcpy((uint8_t *) response, (uint8_t *) mailbox_resp_ctr.payload->data, *resp_len * MBOX_WORD_BYTE); @@ -514,8 +523,18 @@ void mailbox_reset_cold(void) { mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); - mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, NULL, 0U, - CMD_CASUAL, NULL, NULL); + + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0U, 0U, + CMD_CASUAL, NULL, NULL); +} + +void mailbox_reset_warm(uint32_t reset_type) +{ + mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE); + + reset_type = 0x01; // Warm reset header data must be 1 + mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, &reset_type, 1U, + CMD_CASUAL, NULL, NULL); } int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, unsigned int resp_buf_len) @@ -669,3 +688,11 @@ CMD_CASUAL, resp_buf, &resp_len); } + +int mailbox_seu_err_status(uint32_t *resp_buf, unsigned int resp_buf_len) +{ + + return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SEU_ERR_READ, NULL, 0U, + CMD_CASUAL, resp_buf, + &resp_buf_len); +}
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c index 77d9a73..7db86c7 100644 --- a/plat/intel/soc/common/soc/socfpga_reset_manager.c +++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -1,16 +1,19 @@ /* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <assert.h> #include <errno.h> #include <common/debug.h> #include <drivers/delay_timer.h> #include <lib/mmio.h> +#include <platform_def.h> #include "socfpga_f2sdram_manager.h" #include "socfpga_mailbox.h" +#include "socfpga_plat_def.h" #include "socfpga_reset_manager.h" #include "socfpga_system_manager.h" @@ -21,6 +24,7 @@ RSTMGR_FIELD(PER1, WATCHDOG1) | RSTMGR_FIELD(PER1, WATCHDOG2) | RSTMGR_FIELD(PER1, WATCHDOG3) | + RSTMGR_FIELD(PER1, WATCHDOG4) | RSTMGR_FIELD(PER1, L4SYSTIMER0) | RSTMGR_FIELD(PER1, L4SYSTIMER1) | RSTMGR_FIELD(PER1, SPTIMER0) | @@ -30,12 +34,15 @@ RSTMGR_FIELD(PER1, I2C2) | RSTMGR_FIELD(PER1, I2C3) | RSTMGR_FIELD(PER1, I2C4) | + RSTMGR_FIELD(PER1, I3C0) | + RSTMGR_FIELD(PER1, I3C1) | RSTMGR_FIELD(PER1, UART0) | RSTMGR_FIELD(PER1, UART1) | RSTMGR_FIELD(PER1, GPIO0) | RSTMGR_FIELD(PER1, GPIO1)); mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST), + RSTMGR_FIELD(PER0, SOFTPHY) | RSTMGR_FIELD(PER0, EMAC0OCP) | RSTMGR_FIELD(PER0, EMAC1OCP) | RSTMGR_FIELD(PER0, EMAC2OCP) | @@ -78,10 +85,10 @@ { uint32_t or_mask = 0; - or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN; + or_mask |= RSTMGR_HDSKEN_EMIF_FLUSH; or_mask |= RSTMGR_HDSKEN_FPGAHSEN; or_mask |= RSTMGR_HDSKEN_ETRSTALLEN; - or_mask |= RSTMGR_HDSKEN_L2FLUSHEN; + or_mask |= RSTMGR_HDSKEN_LWS2F_FLUSH; or_mask |= RSTMGR_HDSKEN_L3NOC_DBG; or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC; @@ -102,6 +109,27 @@ return -ETIMEDOUT; } +#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 +static int poll_idle_status_by_counter(uint32_t addr, uint32_t mask, + uint32_t match, uint32_t delay_ms) +{ + int time_out = delay_ms; + + while (time_out-- > 0) { + + if ((mmio_read_32(addr) & mask) == match) { + return 0; + } + + /* ToDo: Shall use udelay for product release */ + for (int i = 0; i < 2000; i++) { + /* dummy delay */ + } + } + return -ETIMEDOUT; +} +#endif + static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_clk_cycles) { @@ -183,6 +211,39 @@ *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY; *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM2_CMDIDLE; } +#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 + if (mask & FPGA2SOC_MASK) { + *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC); + *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ; + *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN; + *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE; + *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK; + *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY; + } + if (mask & F2SDRAM0_MASK) { + *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0); + *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ; + *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN; + *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE; + *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK; + *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY; + } + if (mask & F2SDRAM1_MASK) { + *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1); + *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ; + *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN; + *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE; + *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK; + *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY; + } + if (mask & F2SDRAM2_MASK) { + *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2); + *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ; + *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN; + *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE; + *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK; + *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY; + } #else if ((mask & FPGA2SOC_MASK) != 0U) { *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC); @@ -196,6 +257,153 @@ #endif } +int socfpga_bridges_reset(uint32_t mask) +{ + int ret = 0; + int timeout = 300; + uint32_t brg_mask = 0; + uint32_t noc_mask = 0; + uint32_t f2s_idlereq = 0; + uint32_t f2s_force_drain = 0; + uint32_t f2s_en = 0; + uint32_t f2s_idleack = 0; + uint32_t f2s_respempty = 0; + uint32_t f2s_cmdidle = 0; + + /* Reset s2f bridge */ + socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask); + if (brg_mask) { + if (mask & SOC2FPGA_MASK) { + /* Request handshake with SOC2FPGA bridge to clear traffic */ + mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), + RSTMGR_HDSKREQ_S2F_FLUSH); + + /* Wait for bridge to idle status */ + ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK), + RSTMGR_HDSKACK_S2F_FLUSH, + RSTMGR_HDSKACK_S2F_FLUSH, 300); + } + + if (mask & LWHPS2FPGA_MASK) { + /* Request handshake with LWSOC2FPGA bridge to clear traffic */ + mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), + RSTMGR_HDSKREQ_LWS2F_FLUSH); + + /* Wait for bridge to idle status */ + ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK), + RSTMGR_HDSKACK_LWS2F_FLUSH, + RSTMGR_HDSKACK_LWS2F_FLUSH, 300); + } + + if (ret < 0) { + ERROR("S2F Bridge reset: Timeout waiting for idle ack\n"); + assert(false); + } + + /* Assert reset to bridge */ + mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), + brg_mask); + + /* Clear idle requests to bridge */ + if (mask & SOC2FPGA_MASK) { + mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), + RSTMGR_HDSKREQ_S2F_FLUSH); + } + + if (mask & LWHPS2FPGA_MASK) { + mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), + RSTMGR_HDSKREQ_LWS2F_FLUSH); + } + + /* When FPGA reconfig is complete */ + mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask); + } + + /* Reset f2s bridge */
