| Gavin Liu | a65fadf | 2024-10-21 14:22:19 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2024, Mediatek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| 10 | #include <arch.h> |
| 11 | #include <plat/common/common_def.h> |
| 12 | |
| 13 | #include <arch_def.h> |
| 14 | |
| 15 | #define PLAT_PRIMARY_CPU (0x0) |
| 16 | |
| 17 | #define MT_GIC_BASE (0x0C400000) |
| 18 | #define MCUCFG_BASE (0x0C000000) |
| 19 | #define MCUCFG_REG_SIZE (0x50000) |
| 20 | #define IO_PHYS (0x10000000) |
| 21 | |
| 22 | /* Aggregate of all devices for MMU mapping */ |
| 23 | #define MTK_DEV_RNG1_BASE (IO_PHYS) |
| 24 | #define MTK_DEV_RNG1_SIZE (0x10000000) |
| 25 | |
| 26 | #define TOPCKGEN_BASE (IO_PHYS) |
| 27 | |
| 28 | /******************************************************************************* |
| 29 | * AUDIO related constants |
| 30 | ******************************************************************************/ |
| 31 | #define AUDIO_BASE (IO_PHYS + 0x0a110000) |
| 32 | |
| 33 | /******************************************************************************* |
| 34 | * SPM related constants |
| 35 | ******************************************************************************/ |
| 36 | #define SPM_BASE (IO_PHYS + 0x0C004000) |
| 37 | |
| 38 | /******************************************************************************* |
| Cathy Xu | 4cb9f2a | 2024-02-27 17:07:31 +0800 | [diff] [blame] | 39 | * GPIO related constants |
| 40 | ******************************************************************************/ |
| 41 | #define GPIO_BASE (IO_PHYS + 0x0002D000) |
| 42 | #define RGU_BASE (IO_PHYS + 0x0C00B000) |
| 43 | #define DRM_BASE (IO_PHYS + 0x0000D000) |
| 44 | #define IOCFG_RT_BASE (IO_PHYS + 0x02000000) |
| 45 | #define IOCFG_RM1_BASE (IO_PHYS + 0x02020000) |
| 46 | #define IOCFG_RM2_BASE (IO_PHYS + 0x02040000) |
| 47 | #define IOCFG_RB_BASE (IO_PHYS + 0x02060000) |
| 48 | #define IOCFG_BM1_BASE (IO_PHYS + 0x02820000) |
| 49 | #define IOCFG_BM2_BASE (IO_PHYS + 0x02840000) |
| 50 | #define IOCFG_BM3_BASE (IO_PHYS + 0x02860000) |
| 51 | #define IOCFG_LT_BASE (IO_PHYS + 0x03000000) |
| 52 | #define IOCFG_LM1_BASE (IO_PHYS + 0x03020000) |
| 53 | #define IOCFG_LM2_BASE (IO_PHYS + 0x03040000) |
| 54 | #define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000) |
| 55 | #define IOCFG_LB2_BASE (IO_PHYS + 0x03110000) |
| 56 | #define IOCFG_TM1_BASE (IO_PHYS + 0x03800000) |
| 57 | #define IOCFG_TM2_BASE (IO_PHYS + 0x03820000) |
| 58 | #define IOCFG_TM3_BASE (IO_PHYS + 0x03860000) |
| 59 | |
| 60 | /******************************************************************************* |
| Gavin Liu | a65fadf | 2024-10-21 14:22:19 +0800 | [diff] [blame] | 61 | * UART related constants |
| 62 | ******************************************************************************/ |
| 63 | #define UART0_BASE (IO_PHYS + 0x06000000) |
| 64 | #define UART_BAUDRATE (115200) |
| 65 | |
| 66 | /******************************************************************************* |
| 67 | * Infra IOMMU related constants |
| 68 | ******************************************************************************/ |
| 69 | #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) |
| 70 | #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) |
| 71 | #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) |
| 72 | #define PERICFG_AO_REG_SIZE (0x1000) |
| 73 | |
| 74 | /******************************************************************************* |
| 75 | * GIC-600 & interrupt handling related constants |
| 76 | ******************************************************************************/ |
| 77 | /* Base MTK_platform compatible GIC memory map */ |
| 78 | #define BASE_GICD_BASE (MT_GIC_BASE) |
| 79 | #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) |
| 80 | #define MTK_GIC_REG_SIZE 0x400000 |
| 81 | |
| 82 | /******************************************************************************* |
| 83 | * MM IOMMU & SMI related constants |
| 84 | ******************************************************************************/ |
| 85 | #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) |
| 86 | #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) |
| 87 | #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) |
| 88 | #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) |
| 89 | #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) |
| 90 | #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) |
| 91 | #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) |
| 92 | #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) |
| 93 | #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) |
| 94 | #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) |
| 95 | #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) |
| 96 | #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) |
| 97 | #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) |
| 98 | #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) |
| 99 | #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) |
| 100 | #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) |
| 101 | #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) |
| 102 | #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) |
| 103 | #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) |
| 104 | #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) |
| 105 | #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) |
| 106 | #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) |
| 107 | #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) |
| 108 | #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) |
| 109 | #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) |
| 110 | #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) |
| 111 | #define SMI_LARB_REG_RNG_SIZE (0x1000) |
| 112 | |
| 113 | /******************************************************************************* |
| 114 | * APMIXEDSYS related constants |
| 115 | ******************************************************************************/ |
| 116 | #define APMIXEDSYS (IO_PHYS + 0x0000C000) |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * VPPSYS related constants |
| 120 | ******************************************************************************/ |
| 121 | #define VPPSYS0_BASE (IO_PHYS + 0x04000000) |
| 122 | #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) |
| 123 | |
| 124 | /******************************************************************************* |
| 125 | * VDOSYS related constants |
| 126 | ******************************************************************************/ |
| 127 | #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) |
| 128 | #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) |
| 129 | |
| 130 | /******************************************************************************* |
| Mac Shen | 3e43d1d | 2024-12-10 14:15:20 +0800 | [diff] [blame] | 131 | * DP related constants |
| 132 | ******************************************************************************/ |
| 133 | #define EDP_SEC_BASE (IO_PHYS + 0x2EC50000) |
| 134 | #define DP_SEC_BASE (IO_PHYS + 0x2EC10000) |
| 135 | #define EDP_SEC_SIZE (0x1000) |
| 136 | #define DP_SEC_SIZE (0x1000) |
| 137 | |
| 138 | /******************************************************************************* |
| Gavin Liu | a65fadf | 2024-10-21 14:22:19 +0800 | [diff] [blame] | 139 | * EMI MPU related constants |
| 140 | *******************************************************************************/ |
| 141 | #define EMI_MPU_BASE (IO_PHYS + 0x00428000) |
| 142 | #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) |
| 143 | |
| 144 | /******************************************************************************* |
| 145 | * System counter frequency related constants |
| 146 | ******************************************************************************/ |
| 147 | #define SYS_COUNTER_FREQ_IN_HZ (13000000) |
| 148 | #define SYS_COUNTER_FREQ_IN_MHZ (13) |
| 149 | |
| 150 | /******************************************************************************* |
| 151 | * Generic platform constants |
| 152 | ******************************************************************************/ |
| 153 | #define PLATFORM_STACK_SIZE (0x800) |
| 154 | #define SOC_CHIP_ID U(0x8196) |
| 155 | |
| 156 | /******************************************************************************* |
| 157 | * Platform memory map related constants |
| 158 | ******************************************************************************/ |
| 159 | #define TZRAM_BASE (0x94600000) |
| 160 | #define TZRAM_SIZE (0x00200000) |
| 161 | |
| 162 | /******************************************************************************* |
| 163 | * BL31 specific defines. |
| 164 | ******************************************************************************/ |
| 165 | /* |
| 166 | * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if |
| 167 | * present). BL31_BASE is calculated using the current BL3-1 debug size plus a |
| 168 | * little space for growth. |
| 169 | */ |
| 170 | #define BL31_BASE (TZRAM_BASE + 0x1000) |
| 171 | #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) |
| 172 | |
| 173 | /******************************************************************************* |
| 174 | * Platform specific page table and MMU setup constants |
| 175 | ******************************************************************************/ |
| 176 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) |
| 177 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) |
| 178 | #define MAX_XLAT_TABLES (128) |
| 179 | #define MAX_MMAP_REGIONS (512) |
| 180 | |
| 181 | /******************************************************************************* |
| 182 | * CPU PM definitions |
| 183 | *******************************************************************************/ |
| 184 | #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) |
| 185 | #define PLAT_CPU_PM_ILDO_ID (6) |
| 186 | #define CPU_IDLE_SRAM_BASE (0x11B000) |
| 187 | #define CPU_IDLE_SRAM_SIZE (0x1000) |
| 188 | |
| 189 | /******************************************************************************* |
| 190 | * SYSTIMER related definitions |
| 191 | ******************************************************************************/ |
| 192 | #define SYSTIMER_BASE (0x1C400000) |
| 193 | |
| 194 | #endif /* PLATFORM_DEF_H */ |