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Soby Mathewb48349e2015-06-29 16:30:12 +01001/*
Soby Mathew4067dc32015-05-05 16:33:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Soby Mathewb48349e2015-06-29 16:30:12 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl_common.h>
35#include <context.h>
36#include <context_mgmt.h>
37#include <platform.h>
38#include <stddef.h>
39#include "psci_private.h"
40
41/*******************************************************************************
42 * Per cpu non-secure contexts used to program the architectural state prior
43 * return to the normal world.
44 * TODO: Use the memory allocator to set aside memory for the contexts instead
Soby Mathew4067dc32015-05-05 16:33:16 +010045 * of relying on platform defined constants. Using PSCI_NUM_PWR_DOMAINS will be
46 * an overkill.
Soby Mathewb48349e2015-06-29 16:30:12 +010047 ******************************************************************************/
48static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
49
50/*******************************************************************************
Soby Mathew4067dc32015-05-05 16:33:16 +010051 * In a system, a certain number of power domain instances are present at a
52 * power level. The cumulative number of instances across all levels are
53 * stored in 'psci_pwr_domain_map'. The topology tree has been flattenned into
54 * this array. To retrieve nodes, information about the extents of each power
55 * level i.e. start index and end index needs to be present.
56 * 'psci_pwr_lvl_limits' stores this information.
Soby Mathewb48349e2015-06-29 16:30:12 +010057 ******************************************************************************/
Soby Mathew4067dc32015-05-05 16:33:16 +010058pwr_lvl_limits_node_t psci_pwr_lvl_limits[MPIDR_MAX_AFFLVL + 1];
Soby Mathewb48349e2015-06-29 16:30:12 +010059
60/******************************************************************************
61 * Define the psci capability variable.
62 *****************************************************************************/
63uint32_t psci_caps;
64
65
66/*******************************************************************************
Soby Mathew4067dc32015-05-05 16:33:16 +010067 * Routines for retrieving the node corresponding to a power domain instance
Soby Mathewb48349e2015-06-29 16:30:12 +010068 * in the mpidr. The first one uses binary search to find the node corresponding
Soby Mathew4067dc32015-05-05 16:33:16 +010069 * to the mpidr (key) at a particular power level. The second routine decides
70 * extents of the binary search at each power level.
Soby Mathewb48349e2015-06-29 16:30:12 +010071 ******************************************************************************/
Soby Mathew4067dc32015-05-05 16:33:16 +010072static int psci_pwr_domain_map_get_idx(unsigned long key,
Soby Mathewb48349e2015-06-29 16:30:12 +010073 int min_idx,
74 int max_idx)
75{
76 int mid;
77
78 /*
79 * Terminating condition: If the max and min indices have crossed paths
80 * during the binary search then the key has not been found.
81 */
82 if (max_idx < min_idx)
83 return PSCI_E_INVALID_PARAMS;
84
85 /*
86 * Make sure we are within array limits.
87 */
Soby Mathew4067dc32015-05-05 16:33:16 +010088 assert(min_idx >= 0 && max_idx < PSCI_NUM_PWR_DOMAINS);
Soby Mathewb48349e2015-06-29 16:30:12 +010089
90 /*
91 * Bisect the array around 'mid' and then recurse into the array chunk
92 * where the key is likely to be found. The mpidrs in each node in the
Soby Mathew4067dc32015-05-05 16:33:16 +010093 * 'psci_pwr_domain_map' for a given power level are stored in an
94 * ascending order which makes the binary search possible.
Soby Mathewb48349e2015-06-29 16:30:12 +010095 */
96 mid = min_idx + ((max_idx - min_idx) >> 1); /* Divide by 2 */
97
Soby Mathew4067dc32015-05-05 16:33:16 +010098 if (psci_pwr_domain_map[mid].mpidr > key)
99 return psci_pwr_domain_map_get_idx(key, min_idx, mid - 1);
100 else if (psci_pwr_domain_map[mid].mpidr < key)
101 return psci_pwr_domain_map_get_idx(key, mid + 1, max_idx);
Soby Mathewb48349e2015-06-29 16:30:12 +0100102 else
103 return mid;
104}
105
Soby Mathew4067dc32015-05-05 16:33:16 +0100106pwr_map_node_t *psci_get_pwr_map_node(unsigned long mpidr, int pwr_lvl)
Soby Mathewb48349e2015-06-29 16:30:12 +0100107{
108 int rc;
109
Soby Mathew4067dc32015-05-05 16:33:16 +0100110 if (pwr_lvl > PLAT_MAX_PWR_LVL)
Soby Mathewb48349e2015-06-29 16:30:12 +0100111 return NULL;
112
Soby Mathew4067dc32015-05-05 16:33:16 +0100113 /* Right shift the mpidr to the required power level */
114 mpidr = mpidr_mask_lower_afflvls(mpidr, pwr_lvl);
Soby Mathewb48349e2015-06-29 16:30:12 +0100115
Soby Mathew4067dc32015-05-05 16:33:16 +0100116 rc = psci_pwr_domain_map_get_idx(mpidr,
117 psci_pwr_lvl_limits[pwr_lvl].min,
118 psci_pwr_lvl_limits[pwr_lvl].max);
Soby Mathewb48349e2015-06-29 16:30:12 +0100119 if (rc >= 0)
Soby Mathew4067dc32015-05-05 16:33:16 +0100120 return &psci_pwr_domain_map[rc];
Soby Mathewb48349e2015-06-29 16:30:12 +0100121 else
122 return NULL;
123}
124
125/*******************************************************************************
126 * This function populates an array with nodes corresponding to a given range of
Soby Mathew4067dc32015-05-05 16:33:16 +0100127 * power levels in an mpidr. It returns successfully only when the power
128 * levels are correct, the mpidr is valid i.e. no power level is absent from
129 * the topology tree & the power domain instance at level 0 is not absent.
Soby Mathewb48349e2015-06-29 16:30:12 +0100130 ******************************************************************************/
Soby Mathew4067dc32015-05-05 16:33:16 +0100131int psci_get_pwr_map_nodes(unsigned long mpidr,
132 int start_pwrlvl,
133 int end_pwrlvl,
134 pwr_map_node_t *mpidr_nodes[])
Soby Mathewb48349e2015-06-29 16:30:12 +0100135{
136 int rc = PSCI_E_INVALID_PARAMS, level;
Soby Mathew4067dc32015-05-05 16:33:16 +0100137 pwr_map_node_t *node;
Soby Mathewb48349e2015-06-29 16:30:12 +0100138
Soby Mathew4067dc32015-05-05 16:33:16 +0100139 rc = psci_check_pwrlvl_range(start_pwrlvl, end_pwrlvl);
Soby Mathewb48349e2015-06-29 16:30:12 +0100140 if (rc != PSCI_E_SUCCESS)
141 return rc;
142
Soby Mathew4067dc32015-05-05 16:33:16 +0100143 for (level = start_pwrlvl; level <= end_pwrlvl; level++) {
Soby Mathewb48349e2015-06-29 16:30:12 +0100144
145 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100146 * Grab the node for each power level. No power level
Soby Mathewb48349e2015-06-29 16:30:12 +0100147 * can be missing as that would mean that the topology tree
148 * is corrupted.
149 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100150 node = psci_get_pwr_map_node(mpidr, level);
Soby Mathewb48349e2015-06-29 16:30:12 +0100151 if (node == NULL) {
152 rc = PSCI_E_INVALID_PARAMS;
153 break;
154 }
155
156 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100157 * Skip absent power levels unless it's power level 0.
Soby Mathewb48349e2015-06-29 16:30:12 +0100158 * An absent cpu means that the mpidr is invalid. Save the
Soby Mathew4067dc32015-05-05 16:33:16 +0100159 * pointer to the node for the present power level
Soby Mathewb48349e2015-06-29 16:30:12 +0100160 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100161 if (!(node->state & PSCI_PWR_DOMAIN_PRESENT)) {
Soby Mathewb48349e2015-06-29 16:30:12 +0100162 if (level == MPIDR_AFFLVL0) {
163 rc = PSCI_E_INVALID_PARAMS;
164 break;
165 }
166
167 mpidr_nodes[level] = NULL;
168 } else
169 mpidr_nodes[level] = node;
170 }
171
172 return rc;
173}
174
175/*******************************************************************************
Soby Mathew4067dc32015-05-05 16:33:16 +0100176 * Function which initializes the 'pwr_map_node' corresponding to a power
177 * domain instance. Each node has a unique mpidr, level and bakery lock.
Soby Mathewb48349e2015-06-29 16:30:12 +0100178 ******************************************************************************/
Soby Mathew4067dc32015-05-05 16:33:16 +0100179static void psci_init_pwr_map_node(unsigned long mpidr,
Soby Mathewb48349e2015-06-29 16:30:12 +0100180 int level,
181 unsigned int idx)
182{
183 unsigned char state;
184 uint32_t linear_id;
Soby Mathew4067dc32015-05-05 16:33:16 +0100185 psci_pwr_domain_map[idx].mpidr = mpidr;
186 psci_pwr_domain_map[idx].level = level;
187 psci_lock_init(psci_pwr_domain_map, idx);
Soby Mathewb48349e2015-06-29 16:30:12 +0100188
189 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100190 * If an power domain instance is present then mark it as OFF
191 * to begin with.
Soby Mathewb48349e2015-06-29 16:30:12 +0100192 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100193 state = plat_get_pwr_domain_state(level, mpidr);
194 psci_pwr_domain_map[idx].state = state;
Soby Mathewb48349e2015-06-29 16:30:12 +0100195
196 if (level == MPIDR_AFFLVL0) {
197
198 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100199 * Mark the cpu as OFF. Higher power level reference counts
Soby Mathewb48349e2015-06-29 16:30:12 +0100200 * have already been memset to 0
201 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100202 if (state & PSCI_PWR_DOMAIN_PRESENT)
203 psci_set_state(&psci_pwr_domain_map[idx],
204 PSCI_STATE_OFF);
Soby Mathewb48349e2015-06-29 16:30:12 +0100205
206 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100207 * Associate a non-secure context with this power
Soby Mathewb48349e2015-06-29 16:30:12 +0100208 * instance through the context management library.
209 */
210 linear_id = platform_get_core_pos(mpidr);
211 assert(linear_id < PLATFORM_CORE_COUNT);
212
213 /* Invalidate the suspend context for the node */
214 set_cpu_data_by_index(linear_id,
215 psci_svc_cpu_data.power_state,
216 PSCI_INVALID_DATA);
217
Soby Mathewb48349e2015-06-29 16:30:12 +0100218 flush_cpu_data_by_index(linear_id, psci_svc_cpu_data);
219
220 cm_set_context_by_mpidr(mpidr,
221 (void *) &psci_ns_context[linear_id],
222 NON_SECURE);
223 }
224
225 return;
226}
227
228/*******************************************************************************
229 * Core routine used by the Breadth-First-Search algorithm to populate the
Soby Mathew4067dc32015-05-05 16:33:16 +0100230 * power domain tree. Each level in the tree corresponds to a power level. This
231 * routine's aim is to traverse to the target power level and populate nodes
232 * in the 'psci_pwr_domain_map' for all the siblings at that level. It uses the
233 * current power level to keep track of how many levels from the root of the
234 * tree have been traversed. If the current power level != target power level,
Soby Mathewb48349e2015-06-29 16:30:12 +0100235 * then the platform is asked to return the number of children that each
Soby Mathew4067dc32015-05-05 16:33:16 +0100236 * power domain instance has at the current power level. Traversal is then done
237 * for each child at the next lower level i.e. current power level - 1.
Soby Mathewb48349e2015-06-29 16:30:12 +0100238 *
Soby Mathew4067dc32015-05-05 16:33:16 +0100239 * CAUTION: This routine assumes that power domain instance ids are allocated
240 * in a monotonically increasing manner at each power level in a mpidr starting
Soby Mathewb48349e2015-06-29 16:30:12 +0100241 * from 0. If the platform breaks this assumption then this code will have to
242 * be reworked accordingly.
243 ******************************************************************************/
Soby Mathew4067dc32015-05-05 16:33:16 +0100244static unsigned int psci_init_pwr_map(unsigned long mpidr,
245 unsigned int pwrmap_idx,
246 int cur_pwrlvl,
247 int tgt_pwrlvl)
Soby Mathewb48349e2015-06-29 16:30:12 +0100248{
Soby Mathew4067dc32015-05-05 16:33:16 +0100249 unsigned int ctr, pwr_inst_count;
Soby Mathewb48349e2015-06-29 16:30:12 +0100250
Soby Mathew4067dc32015-05-05 16:33:16 +0100251 assert(cur_pwrlvl >= tgt_pwrlvl);
Soby Mathewb48349e2015-06-29 16:30:12 +0100252
253 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100254 * Find the number of siblings at the current power level &
Soby Mathewb48349e2015-06-29 16:30:12 +0100255 * assert if there are none 'cause then we have been invoked with
256 * an invalid mpidr.
257 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100258 pwr_inst_count = plat_get_pwr_domain_count(cur_pwrlvl, mpidr);
259 assert(pwr_inst_count);
Soby Mathewb48349e2015-06-29 16:30:12 +0100260
Soby Mathew4067dc32015-05-05 16:33:16 +0100261 if (tgt_pwrlvl < cur_pwrlvl) {
262 for (ctr = 0; ctr < pwr_inst_count; ctr++) {
263 mpidr = mpidr_set_pwr_domain_inst(mpidr, ctr,
264 cur_pwrlvl);
265 pwrmap_idx = psci_init_pwr_map(mpidr,
266 pwrmap_idx,
267 cur_pwrlvl - 1,
268 tgt_pwrlvl);
Soby Mathewb48349e2015-06-29 16:30:12 +0100269 }
270 } else {
Soby Mathew4067dc32015-05-05 16:33:16 +0100271 for (ctr = 0; ctr < pwr_inst_count; ctr++, pwrmap_idx++) {
272 mpidr = mpidr_set_pwr_domain_inst(mpidr, ctr,
273 cur_pwrlvl);
274 psci_init_pwr_map_node(mpidr, cur_pwrlvl, pwrmap_idx);
Soby Mathewb48349e2015-06-29 16:30:12 +0100275 }
276
Soby Mathew4067dc32015-05-05 16:33:16 +0100277 /* pwrmap_idx is 1 greater than the max index of cur_pwrlvl */
278 psci_pwr_lvl_limits[cur_pwrlvl].max = pwrmap_idx - 1;
Soby Mathewb48349e2015-06-29 16:30:12 +0100279 }
280
Soby Mathew4067dc32015-05-05 16:33:16 +0100281 return pwrmap_idx;
Soby Mathewb48349e2015-06-29 16:30:12 +0100282}
283
284/*******************************************************************************
285 * This function initializes the topology tree by querying the platform. To do
Soby Mathew4067dc32015-05-05 16:33:16 +0100286 * so, it's helper routines implement a Breadth-First-Search. At each power
287 * level the platform conveys the number of power domain instances that exist
288 * i.e. the power instance count. The algorithm populates the
289 * psci_pwr_domain_map* recursively using this information. On a platform that
290 * implements two clusters of 4 cpus each, the populated pwr_map_array would
291 * look like this:
Soby Mathewb48349e2015-06-29 16:30:12 +0100292 *
293 * <- cpus cluster0 -><- cpus cluster1 ->
294 * ---------------------------------------------------
295 * | 0 | 1 | 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 |
296 * ---------------------------------------------------
297 * ^ ^
298 * cluster __| cpu __|
299 * limit limit
300 *
301 * The first 2 entries are of the cluster nodes. The next 4 entries are of cpus
302 * within cluster 0. The last 4 entries are of cpus within cluster 1.
Soby Mathew4067dc32015-05-05 16:33:16 +0100303 * The 'psci_pwr_lvl_limits' array contains the max & min index of each power
304 * level within the 'psci_pwr_domain_map' array. This allows restricting search
305 * of a node at a power level between the indices in the limits array.
Soby Mathewb48349e2015-06-29 16:30:12 +0100306 ******************************************************************************/
307int32_t psci_setup(void)
308{
309 unsigned long mpidr = read_mpidr();
Soby Mathew4067dc32015-05-05 16:33:16 +0100310 int pwrlvl, pwrmap_idx, max_pwrlvl;
311 pwr_map_node_t *node;
Soby Mathewb48349e2015-06-29 16:30:12 +0100312
313 psci_plat_pm_ops = NULL;
314
Soby Mathew4067dc32015-05-05 16:33:16 +0100315 /* Find out the maximum power level that the platform implements */
316 max_pwrlvl = PLAT_MAX_PWR_LVL;
317 assert(max_pwrlvl <= MPIDR_MAX_AFFLVL);
Soby Mathewb48349e2015-06-29 16:30:12 +0100318
319 /*
320 * This call traverses the topology tree with help from the platform and
Soby Mathew4067dc32015-05-05 16:33:16 +0100321 * populates the power map using a breadth-first-search recursively.
322 * We assume that the platform allocates power domain instance ids from
323 * 0 onwards at each power level in the mpidr. FIRST_MPIDR = 0.0.0.0
Soby Mathewb48349e2015-06-29 16:30:12 +0100324 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100325 pwrmap_idx = 0;
326 for (pwrlvl = max_pwrlvl; pwrlvl >= MPIDR_AFFLVL0; pwrlvl--) {
327 pwrmap_idx = psci_init_pwr_map(FIRST_MPIDR,
328 pwrmap_idx,
329 max_pwrlvl,
330 pwrlvl);
Soby Mathewb48349e2015-06-29 16:30:12 +0100331 }
332
333#if !USE_COHERENT_MEM
334 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100335 * The psci_pwr_domain_map only needs flushing when it's not allocated
336 * in coherent memory.
Soby Mathewb48349e2015-06-29 16:30:12 +0100337 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100338 flush_dcache_range((uint64_t) &psci_pwr_domain_map,
339 sizeof(psci_pwr_domain_map));
Soby Mathewb48349e2015-06-29 16:30:12 +0100340#endif
341
342 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100343 * Set the bounds for number of instances of each level in the map. Also
Soby Mathewb48349e2015-06-29 16:30:12 +0100344 * flush out the entire array so that it's visible to subsequent power
Soby Mathew4067dc32015-05-05 16:33:16 +0100345 * management operations. The 'psci_pwr_lvl_limits' array is allocated
346 * in normal memory. It will be accessed when the mmu is off e.g. after
Soby Mathewb48349e2015-06-29 16:30:12 +0100347 * reset. Hence it needs to be flushed.
348 */
Soby Mathew4067dc32015-05-05 16:33:16 +0100349 for (pwrlvl = MPIDR_AFFLVL0; pwrlvl < max_pwrlvl; pwrlvl++) {
350 psci_pwr_lvl_limits[pwrlvl].min =
351 psci_pwr_lvl_limits[pwrlvl + 1].max + 1;
Soby Mathewb48349e2015-06-29 16:30:12 +0100352 }
353
Soby Mathew4067dc32015-05-05 16:33:16 +0100354 flush_dcache_range((unsigned long) psci_pwr_lvl_limits,
355 sizeof(psci_pwr_lvl_limits));
Soby Mathewb48349e2015-06-29 16:30:12 +0100356
357 /*
Soby Mathew4067dc32015-05-05 16:33:16 +0100358 * Mark the power domain instances in our mpidr as ON. No need to lock
359 * as this is the primary cpu.
Soby Mathewb48349e2015-06-29 16:30:12 +0100360 */
361 mpidr &= MPIDR_AFFINITY_MASK;
Soby Mathew4067dc32015-05-05 16:33:16 +0100362 for (pwrlvl = MPIDR_AFFLVL0; pwrlvl <= max_pwrlvl; pwrlvl++) {
Soby Mathewb48349e2015-06-29 16:30:12 +0100363
Soby Mathew4067dc32015-05-05 16:33:16 +0100364 node = psci_get_pwr_map_node(mpidr, pwrlvl);
Soby Mathewb48349e2015-06-29 16:30:12 +0100365 assert(node);
366
367 /* Mark each present node as ON. */
Soby Mathew4067dc32015-05-05 16:33:16 +0100368 if (node->state & PSCI_PWR_DOMAIN_PRESENT)
Soby Mathewb48349e2015-06-29 16:30:12 +0100369 psci_set_state(node, PSCI_STATE_ON);
370 }
371
372 platform_setup_pm(&psci_plat_pm_ops);
373 assert(psci_plat_pm_ops);
374
375 /* Initialize the psci capability */
376 psci_caps = PSCI_GENERIC_CAP;
377
Soby Mathew4067dc32015-05-05 16:33:16 +0100378 if (psci_plat_pm_ops->pwr_domain_off)
Soby Mathewb48349e2015-06-29 16:30:12 +0100379 psci_caps |= define_psci_cap(PSCI_CPU_OFF);
Soby Mathew4067dc32015-05-05 16:33:16 +0100380 if (psci_plat_pm_ops->pwr_domain_on &&
381 psci_plat_pm_ops->pwr_domain_on_finish)
Soby Mathewb48349e2015-06-29 16:30:12 +0100382 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
Soby Mathew4067dc32015-05-05 16:33:16 +0100383 if (psci_plat_pm_ops->pwr_domain_suspend &&
384 psci_plat_pm_ops->pwr_domain_suspend_finish) {
Soby Mathewb48349e2015-06-29 16:30:12 +0100385 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
386 if (psci_plat_pm_ops->get_sys_suspend_power_state)
387 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
388 }
389 if (psci_plat_pm_ops->system_off)
390 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
391 if (psci_plat_pm_ops->system_reset)
392 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
393
394 return 0;
395}