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review.trustedfirmware.org / TF-A / trusted-firmware-a / 22d74da7cd0132b3b40c2289a3cbd152e548632c / . / plat / mediatek / mt8196 / include / platform_def.h
blob: 83370d6c5fb37fd0bb326dbd5c07adb11463f9aa [file] [log] [blame]
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]1/*
Kai Liang4ba679d2024-12-28 21:25:21 +0800[diff] [blame]2 * Copyright (c) 2025, Mediatek Inc. All rights reserved.
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
11#include <plat/common/common_def.h>
12
13#include <arch_def.h>
14
15#define PLAT_PRIMARY_CPU (0x0)
16
17#define MT_GIC_BASE (0x0C400000)
18#define MCUCFG_BASE (0x0C000000)
19#define MCUCFG_REG_SIZE (0x50000)
20#define IO_PHYS (0x10000000)
21
Kai Liang4ba679d2024-12-28 21:25:21 +0800[diff] [blame]22#define MT_UTILITYBUS_BASE (0x0C800000)
23#define MT_UTILITYBUS_SIZE (0x800000)
24
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]25/* Aggregate of all devices for MMU mapping */
26#define MTK_DEV_RNG1_BASE (IO_PHYS)
27#define MTK_DEV_RNG1_SIZE (0x10000000)
28
29#define TOPCKGEN_BASE (IO_PHYS)
30
31/*******************************************************************************
32 * AUDIO related constants
33 ******************************************************************************/
34#define AUDIO_BASE (IO_PHYS + 0x0a110000)
35
36/*******************************************************************************
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]37 * APUSYS related constants
38 ******************************************************************************/
39#define APUSYS_BASE (IO_PHYS + 0x09000000)
Karl Li5e5c57d2024-11-14 20:21:31 +0800[diff] [blame]40#define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000)
41#define APU_MD32_WDT (IO_PHYS + 0x09002000)
42#define APU_LOGTOP (IO_PHYS + 0x09024000)
Karl Lif31932b2024-11-14 20:26:04 +0800[diff] [blame]43#define APUSYS_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09030000)
Karl Li5e5c57d2024-11-14 20:21:31 +0800[diff] [blame]44#define APU_REVISER (IO_PHYS + 0x0903C000)
Karl Lie534d4f2024-11-15 11:01:03 +0800[diff] [blame]45#define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000)
46#define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000)
47#define APU_CMU_TOP (IO_PHYS + 0x09067000)
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]48#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
Karl Li5e5c57d2024-11-14 20:21:31 +0800[diff] [blame]49#define APU_ARE_REG_BASE (IO_PHYS + 0x090B0000)
Karl Lie534d4f2024-11-15 11:01:03 +0800[diff] [blame]50#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000)
Karl Li83f836c2024-11-14 16:18:54 +0800[diff] [blame]51#define APU_AO_CTRL (IO_PHYS + 0x090F2000)
Karl Li9059a372024-11-14 16:04:49 +0800[diff] [blame]52#define APU_SEC_CON (IO_PHYS + 0x090F5000)
Karl Li31a0b872024-11-14 15:56:00 +0800[diff] [blame]53#define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000)
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]54
55#define APU_MBOX0 (0x4C200000)
Karl Li5e5c57d2024-11-14 20:21:31 +0800[diff] [blame]56#define APU_MD32_TCM (0x4D000000)
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]57
Karl Li5e5c57d2024-11-14 20:21:31 +0800[diff] [blame]58#define APU_MD32_TCM_SZ (0x50000)
Karl Li83f836c2024-11-14 16:18:54 +0800[diff] [blame]59#define APU_MBOX0_SZ (0x100000)
60#define APU_INFRA_BASE (0x1002C000)
61#define APU_INFRA_SZ (0x1000)
62
Karl Li5e5c57d2024-11-14 20:21:31 +0800[diff] [blame]63#define APU_RESERVE_MEMORY (0x95000000)
64#define APU_SEC_INFO_OFFSET (0x100000)
65#define APU_RESERVE_SIZE (0x1400000)
66
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]67/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]68 * SPM related constants
69 ******************************************************************************/
70#define SPM_BASE (IO_PHYS + 0x0C004000)
Kai Liang4ba679d2024-12-28 21:25:21 +0800[diff] [blame]71#define SPM_REG_SIZE (0x1000)
72#define SPM_SRAM_BASE (IO_PHYS + 0x0C00C000)
73#define SPM_SRAM_REG_SIZE (0x1000)
74#define SPM_PBUS_BASE (IO_PHYS + 0x0C00D000)
75#define SPM_PBUS_REG_SIZE (0x1000)
76
77#ifdef SPM_BASE
78#define SPM_EXT_INT_WAKEUP_REQ (SPM_BASE + 0x210)
79#define SPM_EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x214)
80#define SPM_EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x218)
81#define SPM_CPU_BUCK_ISO_CON (SPM_BASE + 0xEF8)
82#define SPM_CPU_BUCK_ISO_DEFAUT (0x0)
83#define SPM_AUDIO_PWR_CON (SPM_BASE + 0xE4C)
84#endif
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]85
86/*******************************************************************************
Cathy Xu4cb9f2a2024-02-27 17:07:31 +0800[diff] [blame]87 * GPIO related constants
88 ******************************************************************************/
89#define GPIO_BASE (IO_PHYS + 0x0002D000)
Yidi Lin22d74da2024-04-19 11:59:24 +0800[diff] [blame^]90#define RGU_BASE (IO_PHYS + 0x0C010000)
Cathy Xu4cb9f2a2024-02-27 17:07:31 +0800[diff] [blame]91#define DRM_BASE (IO_PHYS + 0x0000D000)
92#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
93#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)
94#define IOCFG_RM2_BASE (IO_PHYS + 0x02040000)
95#define IOCFG_RB_BASE (IO_PHYS + 0x02060000)
96#define IOCFG_BM1_BASE (IO_PHYS + 0x02820000)
97#define IOCFG_BM2_BASE (IO_PHYS + 0x02840000)
98#define IOCFG_BM3_BASE (IO_PHYS + 0x02860000)
99#define IOCFG_LT_BASE (IO_PHYS + 0x03000000)
100#define IOCFG_LM1_BASE (IO_PHYS + 0x03020000)
101#define IOCFG_LM2_BASE (IO_PHYS + 0x03040000)
102#define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000)
103#define IOCFG_LB2_BASE (IO_PHYS + 0x03110000)
104#define IOCFG_TM1_BASE (IO_PHYS + 0x03800000)
105#define IOCFG_TM2_BASE (IO_PHYS + 0x03820000)
106#define IOCFG_TM3_BASE (IO_PHYS + 0x03860000)
107
108/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]109 * UART related constants
110 ******************************************************************************/
111#define UART0_BASE (IO_PHYS + 0x06000000)
112#define UART_BAUDRATE (115200)
113
114/*******************************************************************************
Hope Wangadf73ae2024-12-13 16:21:01 +0800[diff] [blame]115 * PMIF address
116 ******************************************************************************/
117#define PMIF_SPMI_M_BASE (IO_PHYS + 0x0C01A000)
118#define PMIF_SPMI_P_BASE (IO_PHYS + 0x0C018000)
119#define PMIF_SPMI_SIZE 0x1000
120
121/*******************************************************************************
122 * SPMI address
123 ******************************************************************************/
124#define SPMI_MST_M_BASE (IO_PHYS + 0x0C01C000)
125#define SPMI_MST_P_BASE (IO_PHYS + 0x0C01C800)
126#define SPMI_MST_SIZE 0x1000
127
128/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]129 * Infra IOMMU related constants
130 ******************************************************************************/
131#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
132#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000)
133#define PERICFG_AO_BASE (IO_PHYS + 0x06630000)
134#define PERICFG_AO_REG_SIZE (0x1000)
135
136/*******************************************************************************
137 * GIC-600 & interrupt handling related constants
138 ******************************************************************************/
139/* Base MTK_platform compatible GIC memory map */
140#define BASE_GICD_BASE (MT_GIC_BASE)
141#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
142#define MTK_GIC_REG_SIZE 0x400000
Runyang Chend905b3d2024-12-19 19:53:22 +0800[diff] [blame]143#define SGI_MASK 0xffff
144#define DEV_IRQ_ID 982
145
146#define PLATFORM_G1S_PROPS(grp) \
147 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
148 GIC_INTR_CFG_LEVEL)
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]149
150/*******************************************************************************
ot_chhao.chang49d8c112024-12-02 17:30:58 +0800[diff] [blame]151 * CIRQ related constants
152 ******************************************************************************/
153#define SYS_CIRQ_BASE (IO_PHYS + 0x1CB000)
154#define MD_WDT_IRQ_BIT_ID (397)
155#define CIRQ_REG_NUM (26)
156#define CIRQ_SPI_START (128)
157#define CIRQ_IRQ_NUM (831)
158
159/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]160 * MM IOMMU & SMI related constants
161 ******************************************************************************/
162#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
163#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
164#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
165#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
166#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
167#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
168#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
169#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
170#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
171#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
172#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
173#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
174#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
175#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
176#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
177#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
178#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
179#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
180#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
181#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
182#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
183#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
184#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
185#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
186#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
187#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
188#define SMI_LARB_REG_RNG_SIZE (0x1000)
189
190/*******************************************************************************
191 * APMIXEDSYS related constants
192 ******************************************************************************/
193#define APMIXEDSYS (IO_PHYS + 0x0000C000)
194
195/*******************************************************************************
196 * VPPSYS related constants
197 ******************************************************************************/
198#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
199#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
200
201/*******************************************************************************
202 * VDOSYS related constants
203 ******************************************************************************/
204#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
205#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
206
207/*******************************************************************************
Mac Shen3e43d1d2024-12-10 14:15:20 +0800[diff] [blame]208 * DP related constants
209 ******************************************************************************/
210#define EDP_SEC_BASE (IO_PHYS + 0x2EC50000)
211#define DP_SEC_BASE (IO_PHYS + 0x2EC10000)
212#define EDP_SEC_SIZE (0x1000)
213#define DP_SEC_SIZE (0x1000)
214
215/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]216 * EMI MPU related constants
217 *******************************************************************************/
Gavin Liu39f5e272024-12-31 14:34:00 +0800[diff] [blame]218#define EMI_MPU_BASE (IO_PHYS + 0x00428000)
219#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000)
220#define EMI_SLB_BASE (IO_PHYS + 0x0042e000)
221#define SUB_EMI_SLB_BASE (IO_PHYS + 0x0052e000)
222#define CHN0_EMI_APB_BASE (IO_PHYS + 0x00201000)
223#define CHN1_EMI_APB_BASE (IO_PHYS + 0x00205000)
224#define CHN2_EMI_APB_BASE (IO_PHYS + 0x00209000)
225#define CHN3_EMI_APB_BASE (IO_PHYS + 0x0020D000)
226#define EMI_APB_BASE (IO_PHYS + 0x00429000)
227#define INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00425000)
228#define NEMI_SMPU_BASE (IO_PHYS + 0x0042f000)
229#define SEMI_SMPU_BASE (IO_PHYS + 0x0052f000)
230#define SUB_EMI_APB_BASE (IO_PHYS + 0x00529000)
231#define SUB_INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00525000)
232#define SUB_INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00504000)
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]233
234/*******************************************************************************
235 * System counter frequency related constants
236 ******************************************************************************/
237#define SYS_COUNTER_FREQ_IN_HZ (13000000)
238#define SYS_COUNTER_FREQ_IN_MHZ (13)
239
240/*******************************************************************************
241 * Generic platform constants
242 ******************************************************************************/
243#define PLATFORM_STACK_SIZE (0x800)
244#define SOC_CHIP_ID U(0x8196)
245
246/*******************************************************************************
247 * Platform memory map related constants
248 ******************************************************************************/
249#define TZRAM_BASE (0x94600000)
250#define TZRAM_SIZE (0x00200000)
251
252/*******************************************************************************
253 * BL31 specific defines.
254 ******************************************************************************/
255/*
256 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
257 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
258 * little space for growth.
259 */
260#define BL31_BASE (TZRAM_BASE + 0x1000)
261#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
262
263/*******************************************************************************
264 * Platform specific page table and MMU setup constants
265 ******************************************************************************/
266#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
267#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
268#define MAX_XLAT_TABLES (128)
269#define MAX_MMAP_REGIONS (512)
270
271/*******************************************************************************
Kai Liang4ba679d2024-12-28 21:25:21 +0800[diff] [blame]272 * CPU_EB TCM handling related constants
273 ******************************************************************************/
274#define CPU_EB_TCM_BASE 0x0C2CF000
275#define CPU_EB_TCM_SIZE 0x1000
Kai Liang4ba679d2024-12-28 21:25:21 +0800[diff] [blame]276#define CPU_EB_TCM_CNT_BASE 0x0C2CC000
277
278/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]279 * CPU PM definitions
Kai Liang4ba679d2024-12-28 21:25:21 +0800[diff] [blame]280 ******************************************************************************/
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]281#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
282#define PLAT_CPU_PM_ILDO_ID (6)
283#define CPU_IDLE_SRAM_BASE (0x11B000)
284#define CPU_IDLE_SRAM_SIZE (0x1000)
285
286/*******************************************************************************
287 * SYSTIMER related definitions
288 ******************************************************************************/
289#define SYSTIMER_BASE (0x1C400000)
290
Wenzhen Yufb57af72024-12-20 14:37:26 +0800[diff] [blame]291/*******************************************************************************
292 * CKSYS related constants
293 ******************************************************************************/
294#define CKSYS_BASE (IO_PHYS)
295
296/*******************************************************************************
297 * VLP AO related constants
298 ******************************************************************************/
299#define VLPCFG_BUS_BASE (IO_PHYS + 0x0C001000)
300#define VLPCFG_BUS_SIZE (0x1000)
301#define VLP_AO_DEVAPC_APB_BASE (IO_PHYS + 0x0C550000)
302#define VLP_AO_DEVAPC_APB_SIZE (0x1000)
303
304/*******************************************************************************
305 * SCP registers
306 ******************************************************************************/
307#define SCP_CLK_CTRL_BASE (IO_PHYS + 0x0CF21000)
308#define SCP_CLK_CTRL_SIZE (0x1000)
309
310#define SCP_CFGREG_BASE (IO_PHYS + 0x0CF24000)
311#define SCP_CFGREG_SIZE (0x1000)
312
313/*******************************************************************************
314 * VLP CKSYS related constants
315 ******************************************************************************/
316#define VLP_CKSYS_BASE (IO_PHYS + 0x0C016000)
317#define VLP_CKSYS_SIZE 0x1000
318
319/*******************************************************************************
320 * PERI related constants use PERI secure address to garuantee access
321 ******************************************************************************/
322#define PERICFG_AO_SIZE 0x1000
323#define PERI_CG0_STA (PERICFG_AO_BASE + 0x10)
324#define PERI_CLK_CON (PERICFG_AO_BASE + 0x20)
325#define PERI_CG1_CLR (PERICFG_AO_BASE + 0x30)
326
327/******************************************************************************
328 * LPM syssram related constants
329 *****************************************************************************/
330#define MTK_LPM_SRAM_BASE 0x11B000
331#define MTK_LPM_SRAM_MAP_SIZE 0x1000
332
333/*******************************************************************************
334 * SSPM_MBOX_3 related constants
335 ******************************************************************************/
336#define SSPM_MBOX_3_BASE (IO_PHYS + 0x0C380000)
337#define SSPM_MBOX_3_SIZE 0x1000
338
339/*******************************************************************************
340 * SSPM related constants
341 ******************************************************************************/
342#define SSPM_REG_OFFSET (0x40000)
343#define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET)
344#define SSPM_CFGREG_SIZE (0x1000)
345
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]346#endif /* PLATFORM_DEF_H */