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review.trustedfirmware.org / TF-A / trusted-firmware-a / d9cc9372e12a9a814bb5ec18202f68748bb20fe3 / . / include / plat / arm / common / arm_spm_def.h
blob: 3d7ded23c3460ce94237b1813597279f24e6ed2b [file] [log] [blame]
Antonio Nino Diaze29efeb2017-11-09 11:34:09 +0000[diff] [blame]1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef __ARM_SPM_DEF_H__
7#define __ARM_SPM_DEF_H__
8
9#include <arm_def.h>
Antonio Nino Diaze29efeb2017-11-09 11:34:09 +0000[diff] [blame]10#include <utils_def.h>
11#include <xlat_tables_defs.h>
12
13/*
14 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
15 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
16 * at the base of DRAM.
17 */
18#define ARM_SP_IMAGE_BASE BL32_BASE
19#define ARM_SP_IMAGE_LIMIT BL32_LIMIT
20/* The maximum size of the S-EL0 payload can be 3MB */
21#define ARM_SP_IMAGE_SIZE ULL(0x300000)
22
23#ifdef IMAGE_BL2
24/* SPM Payload memory. Mapped as RW in BL2. */
25#define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \
26 ARM_SP_IMAGE_BASE, \
27 ARM_SP_IMAGE_SIZE, \
28 MT_MEMORY | MT_RW | MT_SECURE)
29#endif
30#ifdef IMAGE_BL31
31/* SPM Payload memory. Mapped as code in S-EL1 */
32#define ARM_SP_IMAGE_MMAP MAP_REGION2( \
33 ARM_SP_IMAGE_BASE, \
34 ARM_SP_IMAGE_BASE, \
35 ARM_SP_IMAGE_SIZE, \
36 MT_CODE | MT_SECURE | MT_USER, \
37 PAGE_SIZE)
38#endif
39
40/*
41 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into
42 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission
43 * from S-EL0. Placed after SPM Payload memory.
44 */
45#define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE)
46#define PLAT_SPM_BUF_SIZE ULL(0x100000)
47
48#define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \
49 PLAT_SPM_BUF_BASE, \
50 PLAT_SPM_BUF_SIZE, \
51 MT_RW_DATA | MT_SECURE)
52#define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \
53 PLAT_SPM_BUF_BASE, \
54 PLAT_SPM_BUF_BASE, \
55 PLAT_SPM_BUF_SIZE, \
56 MT_RO_DATA | MT_SECURE | MT_USER,\
57 PAGE_SIZE)
58
59/*
60 * Memory shared between Normal world and S-EL0 for passing data during service
61 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and
62 * S-EL0.
63 */
64#define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
65#define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
66#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
67 ARM_SP_IMAGE_NS_BUF_BASE, \
68 ARM_SP_IMAGE_NS_BUF_BASE, \
69 ARM_SP_IMAGE_NS_BUF_SIZE, \
70 MT_RW_DATA | MT_NS | MT_USER, \
71 PAGE_SIZE)
72
73/*
74 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory
75 * shared between Secure and Non-secure worlds. First there is the stack memory
76 * for all CPUs and then there is the common heap memory. Both are mapped with
77 * RW permissions.
78 */
79#define PLAT_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
80 ARM_SP_IMAGE_NS_BUF_SIZE)
81#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
82#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
83 PLAT_SP_IMAGE_STACK_PCPU_SIZE)
84
85#define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \
86 ARM_SP_IMAGE_STACK_TOTAL_SIZE)
87#define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE)
88
89#define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \
90 PLAT_SP_IMAGE_STACK_BASE, \
91 PLAT_SP_IMAGE_STACK_BASE, \
92 (ARM_SP_IMAGE_LIMIT - \
93 PLAT_SP_IMAGE_STACK_BASE), \
94 MT_RW_DATA | MT_SECURE | MT_USER,\
95 PAGE_SIZE)
96
97/* Total number of memory regions with distinct properties */
98#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
99
Antonio Nino Diaze29efeb2017-11-09 11:34:09 +0000[diff] [blame]100/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
101#define PLAT_SPM_COOKIE_0 ULL(0)
102#define PLAT_SPM_COOKIE_1 ULL(0)
103
104#endif /* __ARM_SPM_DEF_H__ */