blob: 13b447a170ef49432e69fc5761900574727aab0f [file] [log] [blame]
Dan Handley4def07d2018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillard6f625742017-06-28 15:23:03 +01002=============================
3
Douglas Raillard6f625742017-06-28 15:23:03 +01004This document describes the various build options present in the CPU specific
5operations framework to enable errata workarounds and to enable optimizations
6for a specific CPU on a platform.
7
Dimitris Papastamosf62ad322017-11-30 14:53:53 +00008Security Vulnerability Workarounds
9----------------------------------
10
Dan Handley4def07d2018-03-01 18:44:00 +000011TF-A exports a series of build flags which control which security
12vulnerability workarounds should be applied at runtime.
Dimitris Papastamosf62ad322017-11-30 14:53:53 +000013
14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos59dc4ef2018-03-28 12:06:40 +010015 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
16 of the PEs in the system need the workaround. Setting this flag to 0 provides
17 no performance benefit for non-affected platforms, it just helps to comply
18 with the recommendation in the spec regarding workaround discovery.
19 Defaults to 1.
Dimitris Papastamosf62ad322017-11-30 14:53:53 +000020
Dimitris Papastamosb8a25bb2018-04-05 14:38:26 +010021- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
23 the default value of 1 even on platforms that are unaffected by
24 CVE-2018-3639, in order to comply with the recommendation in the spec
25 regarding workaround discovery.
26
Dimitris Papastamosfe007b22018-05-16 11:36:14 +010027- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
30 Defaults to 0.
31
Bipin Ravi1fe4a9d2022-01-18 01:59:06 -060032- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_.
33 This build option should be set to 1 if the target platform contains at
34 least 1 CPU that requires this mitigation. Defaults to 1.
35
Paul Beesley34760952019-04-12 14:19:42 +010036.. _arm_cpu_macros_errata_workarounds:
37
Douglas Raillard6f625742017-06-28 15:23:03 +010038CPU Errata Workarounds
39----------------------
40
Dan Handley4def07d2018-03-01 18:44:00 +000041TF-A exports a series of build flags which control the errata workarounds that
42are applied to each CPU by the reset handler. The errata details can be found
43in the CPU specific errata documents published by Arm:
Douglas Raillard6f625742017-06-28 15:23:03 +010044
45- `Cortex-A53 MPCore Software Developers Errata Notice`_
46- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnici6de9b332017-08-02 18:33:41 +010047- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillard6f625742017-06-28 15:23:03 +010048
49The errata workarounds are implemented for a particular revision or a set of
50processor revisions. This is checked by the reset handler at runtime. Each
51errata workaround is identified by its ``ID`` as specified in the processor's
52errata notice document. The format of the define used to enable/disable the
53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
54is for example ``A57`` for the ``Cortex_A57`` CPU.
55
Paul Beesley34760952019-04-12 14:19:42 +010056Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
57write errata workaround functions.
Douglas Raillard6f625742017-06-28 15:23:03 +010058
59All workarounds are disabled by default. The platform is responsible for
60enabling these workarounds according to its requirement by defining the
61errata workaround build flags in the platform specific makefile. In case
62these workarounds are enabled for the wrong CPU revision then the errata
63workaround is not applied. In the DEBUG build, this is indicated by
64printing a warning to the crash console.
65
66In the current implementation, a platform which has more than 1 variant
67with different revisions of a processor has no runtime mechanism available
68for it to specify which errata workarounds should be enabled or not.
69
John Tsichritzis8a677182018-07-23 09:11:59 +010070The value of the build flags is 0 by default, that is, disabled. A value of 1
71will enable it.
Douglas Raillard6f625742017-06-28 15:23:03 +010072
Joel Huttondd4cf2c2019-04-10 12:52:52 +010073For Cortex-A9, the following errata build flags are defined :
74
Louis Mayencourtb4e9ab92019-04-18 12:11:25 +010075- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Huttondd4cf2c2019-04-10 12:52:52 +010076 CPU. This needs to be enabled for all revisions of the CPU.
77
Ambroise Vincent75a1ada2019-03-04 16:56:26 +000078For Cortex-A15, the following errata build flags are defined :
79
80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
82
Ambroise Vincent5f2c6902019-03-05 09:54:21 +000083- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
85
Ambroise Vincent0b64c192019-02-28 16:23:53 +000086For Cortex-A17, the following errata build flags are defined :
87
88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
90
Ambroise Vincentbe10dcd2019-03-04 13:20:56 +000091- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
93
Louis Mayencourtcba71b72019-04-05 16:25:25 +010094For Cortex-A35, the following errata build flags are defined :
95
96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
98
John Tsichritzis8a677182018-07-23 09:11:59 +010099For Cortex-A53, the following errata build flags are defined :
Douglas Raillard6f625742017-06-28 15:23:03 +0100100
Ambroise Vincentbd393702019-02-21 14:16:24 +0000101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
103
104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
106
Douglas Raillard6f625742017-06-28 15:23:03 +0100107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
109
Ambroise Vincentbd393702019-02-21 14:16:24 +0000110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
112
Douglas Raillardca6b1cb2017-07-17 14:14:52 +0100113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
115 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
116 sections.
117
Douglas Raillard6f625742017-06-28 15:23:03 +0100118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
120 r0p4 and onwards, this errata is enabled by default in hardware.
121
Douglas Raillardca6b1cb2017-07-17 14:14:52 +0100122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
125 which are 4kB aligned.
126
Douglas Raillard6f625742017-06-28 15:23:03 +0100127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
128 CPUs. Though the erratum is present in every revision of the CPU,
129 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillard6f625742017-06-28 15:23:03 +0100131 Earlier revisions of the CPU have other errata which require the same
132 workaround in software, so they should be covered anyway.
133
Manish V Badarkhee008a292020-07-31 08:38:49 +0100134- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
135 revisions of Cortex-A53 CPU.
136
Ambroise Vincent1afeee92019-02-21 16:20:43 +0000137For Cortex-A55, the following errata build flags are defined :
138
139- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
140 CPU. This needs to be enabled only for revision r0p0 of the CPU.
141
Ambroise Vincenta6cc6612019-02-21 16:25:37 +0000142- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
143 CPU. This needs to be enabled only for revision r0p0 of the CPU.
144
Ambroise Vincent6ab87d22019-02-21 16:27:34 +0000145- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
146 CPU. This needs to be enabled only for revision r0p0 of the CPU.
147
Ambroise Vincent6e789732019-02-21 16:29:16 +0000148- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
150
Ambroise Vincent47949f32019-02-21 16:29:50 +0000151- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
152 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
153
Ambroise Vincent9af07df2019-05-28 09:52:48 +0100154- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
155 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
156
Manish V Badarkhee008a292020-07-31 08:38:49 +0100157- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
158 revisions of Cortex-A55 CPU.
159
John Tsichritzis8a677182018-07-23 09:11:59 +0100160For Cortex-A57, the following errata build flags are defined :
Douglas Raillard6f625742017-06-28 15:23:03 +0100161
162- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
163 CPU. This needs to be enabled only for revision r0p0 of the CPU.
164
165- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
166 CPU. This needs to be enabled only for revision r0p0 of the CPU.
167
168- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
169 CPU. This needs to be enabled only for revision r0p0 of the CPU.
170
Ambroise Vincent0f6fbbd2019-02-21 16:35:07 +0000171- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
172 CPU. This needs to be enabled only for revision r0p0 of the CPU.
173
Ambroise Vincent5bd2c242019-02-21 16:35:49 +0000174- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
175 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
176
Douglas Raillard6f625742017-06-28 15:23:03 +0100177- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
178 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
179
180- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
181 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
182
183- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
185
186- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
187 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
188
189- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
190 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
191
Eleanor Bonnici45b52c22017-08-02 16:35:04 +0100192- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
193 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
194
Manish V Badarkhee008a292020-07-31 08:38:49 +0100195- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
196 revisions of Cortex-A57 CPU.
Eleanor Bonnici6de9b332017-08-02 18:33:41 +0100197
John Tsichritzis8a677182018-07-23 09:11:59 +0100198For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnici6de9b332017-08-02 18:33:41 +0100199
200- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
201 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
202
Manish V Badarkhee008a292020-07-31 08:38:49 +0100203- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
204 revisions of Cortex-A72 CPU.
205
Louis Mayencourte6cab152019-02-21 16:38:16 +0000206For Cortex-A73, the following errata build flags are defined :
207
Louis Mayencourt25278ea2019-02-27 14:24:16 +0000208- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
209 CPU. This needs to be enabled only for revision r0p0 of the CPU.
210
Louis Mayencourte6cab152019-02-21 16:38:16 +0000211- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
212 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
213
Louis Mayencourt5f5d1ed2019-02-20 12:11:41 +0000214For Cortex-A75, the following errata build flags are defined :
215
216- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
217 CPU. This needs to be enabled only for revision r0p0 of the CPU.
218
Louis Mayencourt98551592019-02-25 14:57:57 +0000219- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
220 CPU. This needs to be enabled only for revision r0p0 of the CPU.
221
Louis Mayencourt508d7112019-02-21 17:35:07 +0000222For Cortex-A76, the following errata build flags are defined :
223
Louis Mayencourt5c6aa012019-02-25 15:17:44 +0000224- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
225 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
226
Louis Mayencourt508d7112019-02-21 17:35:07 +0000227- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
228 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
229
Louis Mayencourt5cc8c7b2019-02-25 11:37:38 +0000230- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
231 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
232
Soby Mathewe6e1d0a2019-05-01 09:43:18 +0100233- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
234 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
235
236- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
237 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
238
239- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
241
242- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
244
johpow01d7b08e62020-05-29 14:17:38 -0500245- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
246 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
247
Manish V Badarkhee008a292020-07-31 08:38:49 +0100248- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
249 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
250 limitation of errata framework this errata is applied to all revisions
251 of Cortex-A76 CPU.
252
johpow0155ff05f2020-09-29 17:19:09 -0500253- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
254 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
255
johpow013f0d8362020-12-15 19:02:18 -0600256- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
257 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
258
johpow0162bbfe82020-06-03 15:23:31 -0500259For Cortex-A77, the following errata build flags are defined :
260
laurenw-armaa3efe32020-07-14 14:18:34 -0500261- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
262 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
263
johpow0135c75372020-09-10 13:39:26 -0500264- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
265 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
266
laurenw-arma492edc42021-03-23 13:09:35 -0500267- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
268 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
269
johpow013f0bec72021-05-03 13:37:13 -0500270- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
271 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
272
Jimmy Brisson3f357092020-06-01 10:18:22 -0500273For Cortex-A78, the following errata build flags are defined :
Madhukar Pappireddy83e95522019-12-18 15:56:27 -0600274
Jimmy Brisson3f357092020-06-01 10:18:22 -0500275- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
276 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
Madhukar Pappireddy83e95522019-12-18 15:56:27 -0600277
johpow01e26c59d2020-10-06 17:55:25 -0500278- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
279 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
280
johpow013a2710d2020-10-07 15:08:01 -0500281- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
282 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
283 issue but there is no workaround for that revision.
284
johpow011a691452021-04-30 18:08:52 -0500285- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
286 CPU. This needs to be enabled for revisions r0p0 and r1p0.
287
nayanpatel-arm00bee992021-08-11 13:33:00 -0700288- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
289 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
290
nayanpatel-armb36fe212021-09-28 17:31:50 -0700291- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
292 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
293 is still open.
294
johpow011ea91902021-09-02 17:53:30 -0500295- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
296 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
297 is present in r0p0 but there is no workaround. It is still open.
298
Varun Wadekar89130472021-07-27 00:39:40 -0700299For Cortex-A78 AE, the following errata build flags are defined :
300
Varun Wadekar92e87082022-03-09 22:04:00 +0000301- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
302 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
303 This erratum is still open.
Varun Wadekar47d6f5f2021-07-27 02:32:29 -0700304
Varun Wadekar92e87082022-03-09 22:04:00 +0000305- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
306 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
307 erratum is still open.
308
309- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
310 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
311 erratum is still open.
Varun Wadekar89130472021-07-27 00:39:40 -0700312
lauwal01a601afe2019-06-24 11:23:50 -0500313For Neoverse N1, the following errata build flags are defined :
314
315- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
316 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
317
lauwal01e34606f2019-06-24 11:28:34 -0500318- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
319 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
320
lauwal012017ab22019-06-24 11:32:40 -0500321- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
322 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
323
lauwal01ef5fa7d2019-06-24 11:35:37 -0500324- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
325 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
326
lauwal019eceb022019-06-24 11:38:53 -0500327- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
328 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
329
lauwal01335b3c72019-06-24 11:42:02 -0500330- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
331 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
332
lauwal01411f4952019-06-24 11:44:58 -0500333- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
334 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
335
lauwal0111c48372019-06-24 11:47:30 -0500336- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
337 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
338
lauwal014d8801f2019-06-24 11:49:01 -0500339- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
340 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
341
Andre Przywara5f5d0762019-05-20 14:57:06 +0100342- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
343 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
344
laurenw-arm80942622019-08-20 15:51:24 -0500345- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
346 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
347
johpow0161f0ffc2020-08-05 12:27:12 -0500348- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
349 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
350
johpow01263ee782020-10-07 14:33:15 -0500351- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
352 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
353 revisions r0p0, r1p0, and r2p0 there is no workaround.
354
johpow0133e3e922021-05-03 15:33:39 -0500355For Neoverse V1, the following errata build flags are defined :
356
laurenw-arm4789cf62021-08-02 13:22:32 -0500357- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
358 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
359 in r1p1.
360
johpow0133e3e922021-05-03 15:33:39 -0500361- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
362 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
363 in r1p1.
364
laurenw-arm143b1962021-08-02 14:40:08 -0500365- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
366 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
367 in r1p1.
368
laurenw-arm741dd042021-08-02 15:00:15 -0500369- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
370 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
371
johpow01182ce102020-10-07 16:38:37 -0500372- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
373 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
374 CPU.
375
johpow011a8804c2021-08-02 18:59:08 -0500376- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
377 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
378 issue is present in r0p0 as well but there is no workaround for that
379 revision. It is still open.
380
johpow01100d4022021-08-03 14:35:20 -0500381- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
382 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
383 CPU. It is still open.
384
nayanpatel-arm8e140272021-09-28 13:41:03 -0700385- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
386 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
387 It is still open.
388
johpow014c8fe6b2021-09-02 18:29:17 -0500389- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
390 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
391 issue is present in r0p0 as well but there is no workaround for that
392 revision. It is still open.
393
nayanpatel-armfbcf54a2021-08-06 16:39:48 -0700394For Cortex-A710, the following errata build flags are defined :
395
396- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
397 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
398 r2p0 of the CPU. It is still open.
399
nayanpatel-arma64bcc22021-08-25 17:35:15 -0700400- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
401 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
402 r2p0 of the CPU. It is still open.
403
Bipin Ravi213afde2021-03-31 16:45:40 -0500404- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
405 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
406 and is still open.
407
Bipin Raviafc2ed62021-03-31 18:45:55 -0500408- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
409 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
410 of the CPU and is still open.
411
nayanpatel-arm95fe1952021-09-16 15:27:53 -0700412- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
413 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
414 is still open.
415
nayanpatel-arm744bdbf2021-09-22 12:35:03 -0700416- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
417 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
418 of the CPU and is still open.
419
Bipin Ravicfe1a8f2022-02-06 02:32:54 -0600420- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
421 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
422 of the CPU and is fixed in r2p1.
423
Bipin Ravi8a855bd2022-02-06 03:11:44 -0600424- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
425 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
426 of the CPU and is fixed in r2p1.
427
johpow01ef934cd2022-02-28 18:34:04 -0600428- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
429 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
430 of the CPU and is fixed in r2p1.
431
Bipin Ravi65e04f22021-03-30 16:08:32 -0500432For Neoverse N2, the following errata build flags are defined :
433
nayanpatel-arm5819e232021-10-06 15:31:24 -0700434- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
435 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
436
Bipin Ravi65e04f22021-03-30 16:08:32 -0500437- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
438 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
439
Bipin Ravi4618b2b2021-03-31 10:10:27 -0500440- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
441 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
442
Bipin Ravi7cfae932021-08-30 13:02:51 -0500443- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
Bipin Ravi1cafb082021-09-01 01:36:43 -0500444 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
445
446- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
447 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
Bipin Ravi7cfae932021-08-30 13:02:51 -0500448
nayanpatel-armef8f0c52021-09-28 09:46:45 -0700449- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
450 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
451
nayanpatel-arm5819e232021-10-06 15:31:24 -0700452- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
453 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
454
nayanpatel-armc9481852021-10-20 18:28:58 -0700455- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
456 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
457
nayanpatel-arm603806d2021-10-07 17:59:33 -0700458- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
459 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
460
nayanpatel-arm0d2d9992021-10-20 17:30:46 -0700461- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
462 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
463
johpow011db6cd62021-12-01 17:40:39 -0600464For Cortex-X2, the following errata build flags are defined :
465
johpow0134ee76d2021-12-02 13:25:50 -0600466- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
467 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
468 it is still open.
469
johpow01e16045d2021-12-03 11:27:33 -0600470- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
471 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
472 it is still open.
473
johpow011db6cd62021-12-01 17:40:39 -0600474- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
475 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
476
Bipin Ravie7ca4432022-01-20 00:01:04 -0600477- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
478 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
479 r2p0 of the CPU, it is fixed in r2p1.
480
Bipin Ravic060b532022-01-20 00:42:05 -0600481- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
482 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
483 r2p0 of the CPU, it is fixed in r2p1.
484
Bipin Ravi4dff7592022-02-06 01:29:31 -0600485- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
486 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
487 r2p0 of the CPU, it is fixed in r2p1.
488
johpow0183435632022-01-04 16:15:18 -0600489For Cortex-A510, the following errata build flags are defined :
490
491- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
492 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
493 fixed in r0p1.
494
johpow01d5e25122022-01-06 14:54:49 -0600495- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to
496 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
497 r0p2, r0p3 and r1p0, it is fixed in r1p1.
498
johpow01d48088a2022-01-07 17:12:31 -0600499- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
500 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
501 r0p2, it is fixed in r0p3.
502
johpow01e72bbe42022-01-11 17:54:41 -0600503- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
504 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
505 in r0p3. The issue is also present in r0p0 and r0p1 but there is no
506 workaround for those revisions.
507
johpow017f304b02022-02-13 21:00:10 -0600508- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
509 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
510 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
511 ENABLE_MPMM=1.
512
johpow01cc790182022-02-14 20:19:08 -0600513- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
514 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
515 r0p3 and r1p0, it is fixed in r1p1.
516
johpow01c0959d22022-02-15 22:55:22 -0600517- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
518 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
519 r0p3 and r1p0, it is fixed in r1p1.
520
John Tsichritzis8a677182018-07-23 09:11:59 +0100521DSU Errata Workarounds
522----------------------
523
524Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
525Shared Unit) errata. The DSU errata details can be found in the respective Arm
526documentation:
527
528- `Arm DSU Software Developers Errata Notice`_.
529
530Each erratum is identified by an ``ID``, as defined in the DSU errata notice
531document. Thus, the build flags which enable/disable the errata workarounds
532have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
533of DSU errata workarounds are similar to `CPU errata workarounds`_.
534
535For DSU errata, the following build flags are defined:
536
Louis Mayencourt0e985d72019-04-09 16:29:01 +0100537- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
538 affected DSU configurations. This errata applies only for those DSUs that
539 revision is r0p0 (on r0p1 it is fixed). However, please note that this
540 workaround results in increased DSU power consumption on idle.
541
John Tsichritzis8a677182018-07-23 09:11:59 +0100542- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
543 affected DSU configurations. This errata applies only for those DSUs that
544 contain the ACP interface **and** the DSU revision is older than r2p0 (on
545 r2p0 it is fixed). However, please note that this workaround results in
546 increased DSU power consumption on idle.
547
Douglas Raillard6f625742017-06-28 15:23:03 +0100548CPU Specific optimizations
549--------------------------
550
551This section describes some of the optimizations allowed by the CPU micro
552architecture that can be enabled by the platform as desired.
553
554- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
555 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
556 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
557 of the L2 by set/way flushes any dirty lines from the L1 as well. This
558 is a known safe deviation from the Cortex-A57 TRM defined power down
559 sequence. Each Cortex-A57 based platform must make its own decision on
560 whether to use the optimization.
561
562- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
563 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
564 in a way most programmers expect, and will most probably result in a
Dan Handley4def07d2018-03-01 18:44:00 +0000565 significant speed degradation to any code that employs them. The Armv8-A
566 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillard6f625742017-06-28 15:23:03 +0100567 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
568 flag enforces this behaviour. This needs to be enabled only for revisions
569 <= r0p3 of the CPU and is enabled by default.
570
571- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
572 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
573 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
574 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
575 `Cortex-A57 Software Optimization Guide`_.
576
Varun Wadekarcd0ea182018-06-12 16:49:12 -0700577- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
578 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
579 this bit only if their memory system meets the requirement that cache
580 line fill requests from the Cortex-A57 processor are atomic. Each
581 Cortex-A57 based platform must make its own decision on whether to use
582 the optimization. This flag is disabled by default.
583
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100584- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
Manish Pandeyf2d6b4e2020-01-24 11:54:44 +0000585 level cache(LLC) is present in the system, and that the DataSource field
586 on the master CHI interface indicates when data is returned from the LLC.
587 This is used to control how the LL_CACHE* PMU events count.
Javier Almansa Sobrino25bbbd22020-10-23 13:22:07 +0100588 Default value is 0 (Disabled).
Manish Pandeyf2d6b4e2020-01-24 11:54:44 +0000589
Douglas Raillard6f625742017-06-28 15:23:03 +0100590--------------
591
laurenw-arma492edc42021-03-23 13:09:35 -0500592*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
Douglas Raillard6f625742017-06-28 15:23:03 +0100593
John Tsichritzisaf45d642018-09-04 10:56:53 +0100594.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
595.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Bipin Ravi1fe4a9d2022-01-18 01:59:06 -0600596.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960
Paul Beesleydd4e9a72019-02-08 16:43:05 +0000597.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
598.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnici6de9b332017-08-02 18:33:41 +0100599.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillard6f625742017-06-28 15:23:03 +0100600.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleuxf3cacad2019-02-08 15:26:36 +0100601.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html