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Yann Gautierc9d75b32019-02-14 11:13:25 +01001/*
Lionel Debieveae3ce8b2019-11-04 14:31:38 +01002 * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
Yann Gautierc9d75b32019-02-14 11:13:25 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP_COMMON_H
8#define STM32MP_COMMON_H
9
Yann Gautier3f9c9782019-02-14 11:13:39 +010010#include <stdbool.h>
11
Yann Gautier1e919522019-04-19 10:48:36 +020012#include <platform_def.h>
13
Yann Gautier3d201782021-03-08 15:03:35 +010014#define JEDEC_ST_BKID U(0x0)
15#define JEDEC_ST_MFID U(0x20)
16
Yann Gautierc9d75b32019-02-14 11:13:25 +010017/* Functions to save and get boot context address given by ROM code */
Yann Gautier3f9c9782019-02-14 11:13:39 +010018void stm32mp_save_boot_ctx_address(uintptr_t address);
19uintptr_t stm32mp_get_boot_ctx_address(void);
Yann Gautier7e87ba22020-08-27 18:28:57 +020020uint16_t stm32mp_get_boot_itf_selected(void);
Yann Gautierc9d75b32019-02-14 11:13:25 +010021
Yann Gautierb2182cd2019-06-04 18:23:10 +020022bool stm32mp_is_single_core(void);
Lionel Debievef7004232019-09-16 12:17:09 +020023bool stm32mp_is_closed_device(void);
Yann Gautierb2182cd2019-06-04 18:23:10 +020024
Yann Gautier7ae58c62019-02-14 11:01:20 +010025/* Return the base address of the DDR controller */
26uintptr_t stm32mp_ddrctrl_base(void);
27
28/* Return the base address of the DDR PHY */
29uintptr_t stm32mp_ddrphyc_base(void);
30
31/* Return the base address of the PWR peripheral */
32uintptr_t stm32mp_pwr_base(void);
33
34/* Return the base address of the RCC peripheral */
35uintptr_t stm32mp_rcc_base(void);
36
Yann Gautiere463d3f2019-05-22 19:13:51 +020037/* Check MMU status to allow spinlock use */
38bool stm32mp_lock_available(void);
39
Lionel Debieveae3ce8b2019-11-04 14:31:38 +010040int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
41 uint32_t *otp_len);
42int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val);
43int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val);
44
Yann Gautier73680c22019-06-04 18:06:34 +020045/* Get IWDG platform instance ID from peripheral IO memory base address */
46uint32_t stm32_iwdg_get_instance(uintptr_t base);
47
48/* Return bitflag mask for expected IWDG configuration from OTP content */
49uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
50
51#if defined(IMAGE_BL2)
52/* Update OTP shadow registers with IWDG configuration from device tree */
53uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
54#endif
55
Yann Gautieracf28c22021-10-18 16:06:22 +020056#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
Patrick Delaunay9083fa12021-10-28 13:48:52 +020057/* Get the UART address from its instance number */
58uintptr_t get_uart_address(uint32_t instance_nb);
59#endif
60
Yann Gautier53612f72021-10-18 15:26:33 +020061/* Setup the UART console */
62int stm32mp_uart_console_setup(void);
63
Yann Gautierc9d75b32019-02-14 11:13:25 +010064/*
65 * Platform util functions for the GPIO driver
66 * @bank: Target GPIO bank ID as per DT bindings
67 *
68 * Platform shall implement these functions to provide to stm32_gpio
69 * driver the resource reference for a target GPIO bank. That are
70 * memory mapped interface base address, interface offset (see below)
71 * and clock identifier.
72 *
73 * stm32_get_gpio_bank_offset() returns a bank offset that is used to
74 * check DT configuration matches platform implementation of the banks
75 * description.
76 */
77uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
78unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
79uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
Yann Gautier737ad292021-06-11 10:54:56 +020080bool stm32_gpio_is_secure_at_reset(unsigned int bank);
Yann Gautierc9d75b32019-02-14 11:13:25 +010081
Etienne Carriereccc199e2020-04-25 11:14:45 +020082/* Return node offset for target GPIO bank ID @bank or a FDT error code */
83int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
84
Yann Gautier92661e02021-05-10 16:05:18 +020085/* Get the chip revision */
86uint32_t stm32mp_get_chip_version(void);
87/* Get the chip device ID */
88uint32_t stm32mp_get_chip_dev_id(void);
89
90/* Get SOC name */
91#define STM32_SOC_NAME_SIZE 20
92void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]);
93
Yann Gautierdec286d2019-06-04 18:02:37 +020094/* Print CPU information */
95void stm32mp_print_cpuinfo(void);
96
Yann Gautier10e7a9e2019-05-13 18:34:48 +020097/* Print board information */
98void stm32mp_print_boardinfo(void);
99
Yann Gautierc9d75b32019-02-14 11:13:25 +0100100/* Initialise the IO layer and register platform IO devices */
Yann Gautier3f9c9782019-02-14 11:13:39 +0100101void stm32mp_io_setup(void);
Yann Gautierc9d75b32019-02-14 11:13:25 +0100102
Yann Gautier1d204ee2021-05-19 18:48:16 +0200103#if STM32MP_USE_STM32IMAGE
Yann Gautier1e919522019-04-19 10:48:36 +0200104/*
105 * Check that the STM32 header of a .stm32 binary image is valid
106 * @param header: pointer to the stm32 image header
107 * @param buffer: address of the binary image (payload)
108 * @return: 0 on success, negative value in case of error
109 */
110int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
Yann Gautier1d204ee2021-05-19 18:48:16 +0200111#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautier1e919522019-04-19 10:48:36 +0200112
Yann Gautier84686ba2020-01-10 18:18:59 +0100113/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
114int stm32mp_map_ddr_non_cacheable(void);
115int stm32mp_unmap_ddr(void);
116
Yann Gautiera6bfa752020-12-16 12:04:06 +0100117/* Functions to save and get boot peripheral info */
Yann Gautier4dc77a32021-12-10 17:04:40 +0100118void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
Yann Gautiera6bfa752020-12-16 12:04:06 +0100119void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
Yann Gautier4dc77a32021-12-10 17:04:40 +0100120
Sughosh Ganuba02add2021-12-01 15:56:27 +0530121#if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
122void stm32mp1_fwu_set_boot_idx(void);
123#endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
124
Yann Gautierc9d75b32019-02-14 11:13:25 +0100125#endif /* STM32MP_COMMON_H */