blob: 2702c30f31fe8fbeea85232f18b45f4a58df2d90 [file] [log] [blame]
David Cunado1a853372017-10-20 11:30:57 +01001/*
Max Shvetsov0c5e7d12021-03-22 11:59:37 +00002 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
David Cunado1a853372017-10-20 11:30:57 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +00007#include <stdbool.h>
8
David Cunado1a853372017-10-20 11:30:57 +01009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaz09d40e02018-12-14 00:18:21 +000011#include <lib/el3_runtime/pubsub.h>
12#include <lib/extensions/sve.h>
David Cunado1a853372017-10-20 11:30:57 +010013
Max Shvetsov0c5e7d12021-03-22 11:59:37 +000014/*
15 * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
16 * VECTOR_SIZE = (LEN+1) * 128
17 */
18#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
19
20static bool sve_supported(void)
David Cunado1a853372017-10-20 11:30:57 +010021{
22 uint64_t features;
23
24 features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
Antonio Nino Diaz40daecc2018-10-25 16:52:26 +010025 return (features & ID_AA64PFR0_SVE_MASK) == 1U;
Dimitris Papastamos2ff8fbf2018-02-19 14:52:19 +000026}
David Cunado1a853372017-10-20 11:30:57 +010027
Max Shvetsov0c5e7d12021-03-22 11:59:37 +000028void sve_enable(cpu_context_t *context)
Dimitris Papastamos2ff8fbf2018-02-19 14:52:19 +000029{
Arunachalam Ganapathy68ac5ed2021-07-08 09:35:57 +010030 u_register_t cptr_el3;
31
Max Shvetsov0c5e7d12021-03-22 11:59:37 +000032 if (!sve_supported()) {
Dimitris Papastamos2ff8fbf2018-02-19 14:52:19 +000033 return;
David Cunado1a853372017-10-20 11:30:57 +010034 }
David Cunado1a853372017-10-20 11:30:57 +010035
Arunachalam Ganapathy68ac5ed2021-07-08 09:35:57 +010036 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
Max Shvetsov0c5e7d12021-03-22 11:59:37 +000037
38 /* Enable access to SVE functionality for all ELs. */
39 cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
40 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
41
42 /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */
43 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
44 (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512)));
45}