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review.trustedfirmware.org / TF-A / trusted-firmware-a / 9059a375eeb20c08cdcd5e604b9fd68b47a31e7e / . / plat / mediatek / mt8196 / include / platform_def.h
blob: 402d23e4fc9725b57b32f8046ccf1ad2d3749ad8 [file] [log] [blame]
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]1/*
2 * Copyright (c) 2024, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
9
10#include <arch.h>
11#include <plat/common/common_def.h>
12
13#include <arch_def.h>
14
15#define PLAT_PRIMARY_CPU (0x0)
16
17#define MT_GIC_BASE (0x0C400000)
18#define MCUCFG_BASE (0x0C000000)
19#define MCUCFG_REG_SIZE (0x50000)
20#define IO_PHYS (0x10000000)
21
22/* Aggregate of all devices for MMU mapping */
23#define MTK_DEV_RNG1_BASE (IO_PHYS)
24#define MTK_DEV_RNG1_SIZE (0x10000000)
25
26#define TOPCKGEN_BASE (IO_PHYS)
27
28/*******************************************************************************
29 * AUDIO related constants
30 ******************************************************************************/
31#define AUDIO_BASE (IO_PHYS + 0x0a110000)
32
33/*******************************************************************************
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]34 * APUSYS related constants
35 ******************************************************************************/
36#define APUSYS_BASE (IO_PHYS + 0x09000000)
37#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
Karl Li9059a372024-11-14 16:04:49 +0800[diff] [blame^]38#define APU_SEC_CON (IO_PHYS + 0x090F5000)
Karl Li31a0b872024-11-14 15:56:00 +0800[diff] [blame]39#define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000)
Karl Li0781f782024-11-14 15:46:27 +0800[diff] [blame]40
41#define APU_MBOX0 (0x4C200000)
42
43/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]44 * SPM related constants
45 ******************************************************************************/
46#define SPM_BASE (IO_PHYS + 0x0C004000)
47
48/*******************************************************************************
Cathy Xu4cb9f2a2024-02-27 17:07:31 +0800[diff] [blame]49 * GPIO related constants
50 ******************************************************************************/
51#define GPIO_BASE (IO_PHYS + 0x0002D000)
52#define RGU_BASE (IO_PHYS + 0x0C00B000)
53#define DRM_BASE (IO_PHYS + 0x0000D000)
54#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
55#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)
56#define IOCFG_RM2_BASE (IO_PHYS + 0x02040000)
57#define IOCFG_RB_BASE (IO_PHYS + 0x02060000)
58#define IOCFG_BM1_BASE (IO_PHYS + 0x02820000)
59#define IOCFG_BM2_BASE (IO_PHYS + 0x02840000)
60#define IOCFG_BM3_BASE (IO_PHYS + 0x02860000)
61#define IOCFG_LT_BASE (IO_PHYS + 0x03000000)
62#define IOCFG_LM1_BASE (IO_PHYS + 0x03020000)
63#define IOCFG_LM2_BASE (IO_PHYS + 0x03040000)
64#define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000)
65#define IOCFG_LB2_BASE (IO_PHYS + 0x03110000)
66#define IOCFG_TM1_BASE (IO_PHYS + 0x03800000)
67#define IOCFG_TM2_BASE (IO_PHYS + 0x03820000)
68#define IOCFG_TM3_BASE (IO_PHYS + 0x03860000)
69
70/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]71 * UART related constants
72 ******************************************************************************/
73#define UART0_BASE (IO_PHYS + 0x06000000)
74#define UART_BAUDRATE (115200)
75
76/*******************************************************************************
77 * Infra IOMMU related constants
78 ******************************************************************************/
79#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
80#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000)
81#define PERICFG_AO_BASE (IO_PHYS + 0x06630000)
82#define PERICFG_AO_REG_SIZE (0x1000)
83
84/*******************************************************************************
85 * GIC-600 & interrupt handling related constants
86 ******************************************************************************/
87/* Base MTK_platform compatible GIC memory map */
88#define BASE_GICD_BASE (MT_GIC_BASE)
89#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
90#define MTK_GIC_REG_SIZE 0x400000
91
92/*******************************************************************************
93 * MM IOMMU & SMI related constants
94 ******************************************************************************/
95#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
96#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
97#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
98#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
99#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
100#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
101#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
102#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
103#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
104#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
105#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
106#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
107#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
108#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
109#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
110#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
111#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
112#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
113#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
114#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
115#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
116#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
117#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
118#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
119#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
120#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
121#define SMI_LARB_REG_RNG_SIZE (0x1000)
122
123/*******************************************************************************
124 * APMIXEDSYS related constants
125 ******************************************************************************/
126#define APMIXEDSYS (IO_PHYS + 0x0000C000)
127
128/*******************************************************************************
129 * VPPSYS related constants
130 ******************************************************************************/
131#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
132#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
133
134/*******************************************************************************
135 * VDOSYS related constants
136 ******************************************************************************/
137#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
138#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
139
140/*******************************************************************************
Mac Shen3e43d1d2024-12-10 14:15:20 +0800[diff] [blame]141 * DP related constants
142 ******************************************************************************/
143#define EDP_SEC_BASE (IO_PHYS + 0x2EC50000)
144#define DP_SEC_BASE (IO_PHYS + 0x2EC10000)
145#define EDP_SEC_SIZE (0x1000)
146#define DP_SEC_SIZE (0x1000)
147
148/*******************************************************************************
Gavin Liua65fadf2024-10-21 14:22:19 +0800[diff] [blame]149 * EMI MPU related constants
150 *******************************************************************************/
151#define EMI_MPU_BASE (IO_PHYS + 0x00428000)
152#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000)
153
154/*******************************************************************************
155 * System counter frequency related constants
156 ******************************************************************************/
157#define SYS_COUNTER_FREQ_IN_HZ (13000000)
158#define SYS_COUNTER_FREQ_IN_MHZ (13)
159
160/*******************************************************************************
161 * Generic platform constants
162 ******************************************************************************/
163#define PLATFORM_STACK_SIZE (0x800)
164#define SOC_CHIP_ID U(0x8196)
165
166/*******************************************************************************
167 * Platform memory map related constants
168 ******************************************************************************/
169#define TZRAM_BASE (0x94600000)
170#define TZRAM_SIZE (0x00200000)
171
172/*******************************************************************************
173 * BL31 specific defines.
174 ******************************************************************************/
175/*
176 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
177 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
178 * little space for growth.
179 */
180#define BL31_BASE (TZRAM_BASE + 0x1000)
181#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
182
183/*******************************************************************************
184 * Platform specific page table and MMU setup constants
185 ******************************************************************************/
186#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
187#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
188#define MAX_XLAT_TABLES (128)
189#define MAX_MMAP_REGIONS (512)
190
191/*******************************************************************************
192 * CPU PM definitions
193 *******************************************************************************/
194#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
195#define PLAT_CPU_PM_ILDO_ID (6)
196#define CPU_IDLE_SRAM_BASE (0x11B000)
197#define CPU_IDLE_SRAM_SIZE (0x1000)
198
199/*******************************************************************************
200 * SYSTIMER related definitions
201 ******************************************************************************/
202#define SYSTIMER_BASE (0x1C400000)
203
204#endif /* PLATFORM_DEF_H */