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Sumit Gargc35d59a2018-06-15 13:41:59 +05301/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <common_def.h>
11
12#define CACHE_WRITEBACK_SHIFT 6
13#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
14
15#define PLATFORM_STACK_SIZE 0x400
16
17#define BL31_BASE 0x04000000
18#define BL31_SIZE 0x00080000
19#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
20
Sumit Garg85427de2018-06-15 13:48:11 +053021#define SQ_BOOT_CFG_ADDR 0x45410000
22#define PLAT_SQ_PRIMARY_CPU_SHIFT 8
23#define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6
24
Sumit Gargc35d59a2018-06-15 13:41:59 +053025#endif /* __PLATFORM_DEF_H__ */