blob: 194c59551c791fdc86dc1c82d3ef77d4c1ff7f41 [file] [log] [blame]
Oliver Swede536d9062019-11-11 11:11:06 +00001#
2# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7RESET_TO_BL31 := 1
8ifeq (${RESET_TO_BL31}, 0)
9$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
10endif
11
Oliver Swedee726c752019-12-16 14:08:27 +000012ifeq (${ENABLE_PIE}, 1)
13override SEPARATE_CODE_AND_RODATA := 1
14endif
15
Oliver Swede536d9062019-11-11 11:11:06 +000016CTX_INCLUDE_AARCH32_REGS := 0
17ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
18$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
19endif
20
21ifeq (${TRUSTED_BOARD_BOOT}, 1)
22$(error "TRUSTED_BOARD_BOOT must be disabled")
23endif
24
25ifndef PRELOADED_BL33_BASE
26$(error "PRELOADED_BL33_BASE is not set")
27endif
28
29ifndef FPGA_PRELOADED_DTB_BASE
30$(error "FPGA_PRELOADED_DTB_BASE is not set")
31else
32$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
33endif
34
35# Treating this as a memory-constrained port for now
36USE_COHERENT_MEM := 0
37
38# The CPU in the initial image makes use of this feature
39HW_ASSISTED_COHERENCY := 1
40
41FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S \
42 lib/cpus/aarch64/neoverse_zeus.S
43
Oliver Swede87762bc2019-12-03 14:08:21 +000044FPGA_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
45 drivers/arm/gic/v3/gicdv3_helpers.c \
46 drivers/arm/gic/v3/gicrv3_helpers.c \
47 drivers/arm/gic/v3/gicv3_main.c \
48 drivers/arm/gic/v3/gic600.c \
49 drivers/arm/gic/common/gic_common.c \
50 plat/common/plat_gicv3.c \
51 plat/arm/board/arm_fpga/fpga_gicv3.c
Oliver Swede536d9062019-11-11 11:11:06 +000052
53PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
54
55PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
56
57BL31_SOURCES += drivers/delay_timer/delay_timer.c \
58 drivers/delay_timer/generic_delay_timer.c \
59 drivers/arm/pl011/${ARCH}/pl011_console.S \
60 plat/common/plat_psci_common.c \
61 plat/arm/board/arm_fpga/fpga_pm.c \
62 plat/arm/board/arm_fpga/fpga_topology.c \
63 plat/arm/board/arm_fpga/fpga_console.c \
64 plat/arm/board/arm_fpga/fpga_bl31_setup.c \
65 ${FPGA_CPU_LIBS} \
66 ${FPGA_GIC_SOURCES}
67
68all: bl31