)]}' { "log": [ { "commit": "10198eab3aa7b0eeba10d9667197816b052ba3e4", "tree": "8a66db4b6e9b700031ecbcd7708ea8f0f064b5b3", "parents": [ "34a87d74d9fbbe8037431ea5101110a9f1cf30e1" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Fri Aug 20 20:53:34 2021 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Tue Sep 07 14:38:02 2021 +0100" }, "message": "feat(tc): Enable SVE for both secure and non-secure world\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nChange-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091\n" }, { "commit": "34a87d74d9fbbe8037431ea5101110a9f1cf30e1", "tree": "c416e28e0f2a02296a7abee247e087df2d810a1d", "parents": [ "acfe3be2828735fa07868c117315a5ea43cb3853" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Tue Aug 17 17:57:10 2021 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Tue Sep 07 14:37:53 2021 +0100" }, "message": "feat(tc): populate HW_CONFIG in BL31\n\nBL2 passes FW_CONFIG to BL31 which contains information\nabout different DTBs present. BL31 then uses FW_CONFIG\nto get the base address of HW_CONFIG and populate fconf.\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nChange-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616\n" }, { "commit": "acfe3be2828735fa07868c117315a5ea43cb3853", "tree": "e23df2bac1da4c7b15bec07e3d1a972d0fe2083b", "parents": [ "3b15e9ad11949fb6f7029bf69e3db9feab052d6f", "578f468ac058bbb60b08f78e2aa2c20cdc601620" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 21:42:19 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 21:42:19 2021 +0200" }, "message": "Merge changes I976aef15,I11ae679f into integration\n\n* changes:\n feat(plat/xilinx/zynqmp): add support for runtime feature config\n feat(plat/xilinx/zynqmp): sync IOCTL IDs\n" }, { "commit": "3b15e9ad11949fb6f7029bf69e3db9feab052d6f", "tree": "bbb2c6db59472bc06b91a1a17380b879a48b09ab", "parents": [ "f8bcfa8b76fb03ad8c6a1242ac8ce7fb05a47f4a", "b4f8d44597faf641177134ee08db7c3fcef5aa14" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 18:22:51 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 18:22:51 2021 +0200" }, "message": "Merge \"fix(el3_runtime): correct CASSERT for pauth\" into integration" }, { "commit": "f8bcfa8b76fb03ad8c6a1242ac8ce7fb05a47f4a", "tree": "5847efc5fe8034d9214e4ac848c00012c284b8ea", "parents": [ "15405fccae1f2a9f2a1cf9a466653144c9373209", "325716c97b7835b8d249f12c1461556bab8c53a0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 18:07:24 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 18:07:24 2021 +0200" }, "message": "Merge \"fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit\" into integration" }, { "commit": "15405fccae1f2a9f2a1cf9a466653144c9373209", "tree": "055136cdb41fc309747d0e277c93046cfb7d42c3", "parents": [ "bd4b4b03c2cc8d05bb670ad80e277c48f2b2750e", "99080bd1273331007f0b2d6f64fed51ac6861bcd" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 16:33:57 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 16:33:57 2021 +0200" }, "message": "Merge \"fix(plat/st): apply security at the end of BL2\" into integration" }, { "commit": "bd4b4b03c2cc8d05bb670ad80e277c48f2b2750e", "tree": "ae2ded5da5b87eca8165558a1cfb42883d1c93fb", "parents": [ "9fcefe38d54bdfd86648248854944d95bb99a92a", "3af9b3f0f0afeab5ea5080e97ca1b985505ad1a5" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Aug 20 10:20:03 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 10:20:03 2021 +0200" }, "message": "Merge \"docs(spmc): threat model document\" into integration" }, { "commit": "9fcefe38d54bdfd86648248854944d95bb99a92a", "tree": "494dd8c602d6625b78a0d82be3e4bb9d97e9c2df", "parents": [ "0ed87212a9c1d21c7fb116bb606c64381d6b897b", "d810e30dd6b47e0725dccbcb42ca0a0c5215ee34" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Thu Aug 19 16:43:45 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 19 16:43:45 2021 +0200" }, "message": "Merge \"fix(plat/arm_fpga): enable AMU extension\" into integration" }, { "commit": "b4f8d44597faf641177134ee08db7c3fcef5aa14", "tree": "b07a271ebca79e1a0ee1ca0d4d859cc17ad600e3", "parents": [ "459b24451a0829460783ce8dfa15561e36d901d8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Aug 19 11:36:26 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Aug 19 11:42:09 2021 +0200" }, "message": "fix(el3_runtime): correct CASSERT for pauth\n\nclang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR\u003d1)\nand CRASH_REPORTING (DEBUG\u003d1) options are enabled:\n\ninclude/lib/el3_runtime/cpu_data.h:135:2: error: redefinition of typedef\n\u0027assert_cpu_data_crash_stack_offset_mismatch\u0027 is a C11 feature [-Werror,\n-Wtypedef-redefinition]\n assert_cpu_data_crash_stack_offset_mismatch);\n ^\ninclude/lib/el3_runtime/cpu_data.h:128:2: note: previous definition is here\n assert_cpu_data_crash_stack_offset_mismatch);\n ^\n1 error generated.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I22c8c45a94a64620007979d55412dbb57b11b813\n" }, { "commit": "3af9b3f0f0afeab5ea5080e97ca1b985505ad1a5", "tree": "7ef303b430f73aae4fe4da979e2b9a5c3e1ba255", "parents": [ "459b24451a0829460783ce8dfa15561e36d901d8" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jun 01 15:37:16 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Aug 19 10:37:59 2021 +0200" }, "message": "docs(spmc): threat model document\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ib5f443a6997239d6ba4655d7df6c3fc61d45f991\n" }, { "commit": "0ed87212a9c1d21c7fb116bb606c64381d6b897b", "tree": "9db0c981fe07d08ec83556965720aca3f9675353", "parents": [ "459b24451a0829460783ce8dfa15561e36d901d8", "8913047a52e646877812617a2d98cff99494487b" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Aug 19 09:58:52 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 19 09:58:52 2021 +0200" }, "message": "Merge \"feat(cpus): workaround for Cortex A78 AE erratum 1951502\" into integration" }, { "commit": "578f468ac058bbb60b08f78e2aa2c20cdc601620", "tree": "6aed6413380339bc797add74a572c8e80106e5c4", "parents": [ "38c0b2521a0ea0951f4e1ee678ccdbce5fc07a98" ], "author": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Aug 11 00:26:28 2021 -0700" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Aug 18 22:27:05 2021 -0700" }, "message": "feat(plat/xilinx/zynqmp): add support for runtime feature config\n\nAdd support for runtime feature configuration which are running on the\n firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and\n IOCTL_GET_FEATURE_CONFIG for configuring the features.\n\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: I976aef15932783a25396b2adeb4c8f140cc87e79\n" }, { "commit": "38c0b2521a0ea0951f4e1ee678ccdbce5fc07a98", "tree": "5d34630d0b6fe169c50b65a6f8d4aca920ce2eee", "parents": [ "be3a51ce18499947b13b847a31552f52359375eb" ], "author": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Sun Jun 27 22:31:20 2021 -0700" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Aug 18 22:23:29 2021 -0700" }, "message": "feat(plat/xilinx/zynqmp): sync IOCTL IDs\n\nSync IOCTL IDs in order to avoid conflict with other components like,\n Linux and firmware. Hence assigning value to IDs to make it more\n specific.\n\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: I11ae679fbd0a953290306b62d661cc142f50dc28\n" }, { "commit": "325716c97b7835b8d249f12c1461556bab8c53a0", "tree": "969908b808ad0b0d3d859a0c680a3f49786fe0e1", "parents": [ "391828923fdd846ebc41745b72343b2a0b6a7204" ], "author": { "name": "lwpDarren", "email": "lwp513@qq.com", "time": "Wed Aug 18 00:54:19 2021 +0800" }, "committer": { "name": "lwp513", "email": "lwp513@qq.com", "time": "Wed Aug 18 16:13:22 2021 +0100" }, "message": "fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit\n\nafter this commit: If15cf3b9d3e2e7876c40ce888f22e887893fe696\nplat/qemu/common/qemu_pm.c:116:\t (entrypoint \u003c (NS_DRAM0_BASE + NS_DRAM0_SIZE)))\nthe above line (NS_DRAM0_BASE + NS_DRAM0_SIZE) \u003d 0x100000000, which will\noverflow 32bit and cause ERROR\nSO add ULL to fix it\n\ntested on compiler:\ngcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))\n\nSigned-off-by: Darren Liang \u003clwp513@qq.com\u003e\nChange-Id: I1d769b0803142d37bd2968d765ab04a9c7c5c21a\n" }, { "commit": "459b24451a0829460783ce8dfa15561e36d901d8", "tree": "391137c614b2d668ac93dec5dde54c0663d65b04", "parents": [ "391828923fdd846ebc41745b72343b2a0b6a7204", "c7e4f1cfb84136a7521f26e403a6635ffdce4a2b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 18 16:08:53 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 18 16:08:53 2021 +0200" }, "message": "Merge \"feat: enabling stack protector for diphda\" into integration" }, { "commit": "d810e30dd6b47e0725dccbcb42ca0a0c5215ee34", "tree": "e15087136139bb53cd55d389161051115965a53e", "parents": [ "be3a51ce18499947b13b847a31552f52359375eb" ], "author": { "name": "Tom Cosgrove", "email": "tom.cosgrove@arm.com", "time": "Tue Aug 17 08:50:53 2021 +0100" }, "committer": { "name": "Tom Cosgrove", "email": "tom.cosgrove@arm.com", "time": "Tue Aug 17 08:50:53 2021 +0100" }, "message": "fix(plat/arm_fpga): enable AMU extension\n\nAs done recently for plat/tc0 in b5863cab9, enable AMU explicitly.\nThis is necessary as the recent changes that enable SVE for the secure\nworld disable AMU by default in the CPTR_EL3 reset value.\n\nChange-Id: Ie3abf1dee8a4e1c8c39f934da8e32d67891f5f09\nSigned-off-by: Tom Cosgrove \u003ctom.cosgrove@arm.com\u003e\n" }, { "commit": "99080bd1273331007f0b2d6f64fed51ac6861bcd", "tree": "7e3002a2eabc4e0a91cf146b9fb30be2ae4c4925", "parents": [ "391828923fdd846ebc41745b72343b2a0b6a7204" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Aug 16 11:58:01 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Aug 17 09:10:51 2021 +0200" }, "message": "fix(plat/st): apply security at the end of BL2\n\nNow that the DDR is mapped secured, the security settings (TZC400\nfirewall) have to be applied at the end of BL2 for the OP-TEE case.\nThis is required to avoid checskum computation error on U-Boot binary,\nfor which MMU and TZC400 would not be aligned.\n\nChange-Id: I4a364f7117960e8fae1b579f341b9f140b766ea6\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "391828923fdd846ebc41745b72343b2a0b6a7204", "tree": "791917d5041164661612df492b0baec91ca7b654", "parents": [ "485d1f8003f7a05049bf770b676d46cc31e799cb", "d4ad3da06ac310de0502dfff3a827de91d094fd1" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 16 21:54:07 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 16 21:54:07 2021 +0200" }, "message": "Merge \"refactor(tegra132): deprecate platform\" into integration" }, { "commit": "8913047a52e646877812617a2d98cff99494487b", "tree": "c546101c98abbba6e6696d2741ab0ef9fe7afdc9", "parents": [ "c87f2c1dd38ac7b87aae30c82e66ee2d7741621a" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Tue Jul 27 00:39:40 2021 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Aug 16 20:23:07 2021 +0100" }, "message": "feat(cpus): workaround for Cortex A78 AE erratum 1951502\n\nCortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions\n\u003c\u003d r0p1. It is still open. This erratum is avoided by inserting a DMB ST\nbefore acquire atomic instructions without release semantics through a series\nof writes to implementation defined system registers.\n\nSDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900\n\nChange-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\n" }, { "commit": "d4ad3da06ac310de0502dfff3a827de91d094fd1", "tree": "791917d5041164661612df492b0baec91ca7b654", "parents": [ "485d1f8003f7a05049bf770b676d46cc31e799cb" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Fri Apr 23 22:26:18 2021 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Mon Aug 16 11:58:24 2021 -0700" }, "message": "refactor(tegra132): deprecate platform\n\nThe Tegra132 platforms have reached their end of life and are\nno longer used in the field. Internally and externally, all\nknown programs have removed support for this legacy platform.\n\nThis change removes this platform from the Tegra tree as a result.\n\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\nChange-Id: I72edb689293e23b63290cdcaef60468b90687a5a\n" }, { "commit": "485d1f8003f7a05049bf770b676d46cc31e799cb", "tree": "442bafc13ff89ca3207e63d7a78c064e22778057", "parents": [ "be3a51ce18499947b13b847a31552f52359375eb", "30e8fa7e779851aeb8a2bae990bf090b8bc06b3e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 16 18:04:10 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 16 18:04:10 2021 +0200" }, "message": "Merge \"refactor(plat/ea_handler): Use default ea handler implementation for panic\" into integration" }, { "commit": "be3a51ce18499947b13b847a31552f52359375eb", "tree": "8fce2d8b4e6bb45048a29f64b324852409744e4a", "parents": [ "d6449d2927ce7cebb7bdf335ee9d9308a2da4656", "302b4dfb8fb0041959b8593a098ccae6c61e3238" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 13 17:22:12 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 13 17:22:12 2021 +0200" }, "message": "Merge \"feat(plat/versal): add support for SLS mitigation\" into integration" }, { "commit": "d6449d2927ce7cebb7bdf335ee9d9308a2da4656", "tree": "57d6e733190e36272cef9f17da11a02282fc3009", "parents": [ "c87f2c1dd38ac7b87aae30c82e66ee2d7741621a", "30a8f422bafb2c19a69001b0924d593f8521b674" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Aug 13 12:10:05 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 13 12:10:05 2021 +0200" }, "message": "Merge \"build(deps): bump path-parse from 1.0.6 to 1.0.7\" into integration" }, { "commit": "30e8fa7e779851aeb8a2bae990bf090b8bc06b3e", "tree": "a684378a800e9e88b453affd215c41bc4c429e77", "parents": [ "c87f2c1dd38ac7b87aae30c82e66ee2d7741621a" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Mon Jun 21 17:22:27 2021 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 13 11:12:11 2021 +0200" }, "message": "refactor(plat/ea_handler): Use default ea handler implementation for panic\n\nPut default ea handler implementation into function plat_default_ea_handler()\nwhich just print verbose information and panic, so it can be called also\nfrom overwritten / weak function plat_ea_handler() implementation.\n\nReplace every custom implementation of printing verbose error message of\nexternal aborts in custom plat_ea_handler() functions by a common\nimplementation from plat_default_ea_handler() function.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98\n" }, { "commit": "30a8f422bafb2c19a69001b0924d593f8521b674", "tree": "f1a33fe83995757c991511e7a6fb37d93762af60", "parents": [ "abde216dc8ac95c43ad4b477a669b1249be6e289" ], "author": { "name": "dependabot[bot]", "email": "49699333+dependabot[bot]@users.noreply.github.com", "time": "Fri Aug 13 01:17:53 2021 +0000" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Fri Aug 13 10:12:00 2021 +0100" }, "message": "build(deps): bump path-parse from 1.0.6 to 1.0.7\n\nBumps [path-parse](https://github.com/jbgutierrez/path-parse) from\n1.0.6 to 1.0.7.\n\n- [Release notes](https://github.com/jbgutierrez/path-parse/releases)\n- [Commits](https://github.com/jbgutierrez/path-parse/commits/v1.0.7)\n\n---\nupdated-dependencies:\n- dependency-name: path-parse\n dependency-type: indirect\n...\n\nChange-Id: Ic51c94f3c90d4eab91aeb3b477622358bf74c636\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\nSigned-off-by: dependabot[bot] \u003csupport@github.com\u003e\n" }, { "commit": "c87f2c1dd38ac7b87aae30c82e66ee2d7741621a", "tree": "1ee4c770723aa643e4c97f5c51644ae107aab225", "parents": [ "e528bc22ebb7cf66fa79250514bdac519b2b1c61", "12c75c8886a0ee69d7e279a48cbeb8d1602826b3" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Aug 13 10:16:20 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 13 10:16:20 2021 +0200" }, "message": "Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration\n\n* changes:\n feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked\n feat(plat/rcar3): add a DRAM size setting for M3N\n feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0\n feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB\n feat(drivers/rcar3): ddr: add function to judge a DDR rank\n fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N\n fix(drivers/rcar3): i2c_dvfs: fix I2C operation\n fix(drivers/rcar3): fix CPG registers redefinition\n fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition\n fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0\n refactor(plat/rcar3): factor out DT memory node generation\n feat(plat/rcar3): add optional support for gzip-compressed BL33\n" }, { "commit": "e528bc22ebb7cf66fa79250514bdac519b2b1c61", "tree": "cf58b1b50e10037d481b7172152cf21e0ae2b46c", "parents": [ "5360449b61ccfe8c2e70c4d533e01b62d0199154", "9a9ea82948fd2f1459b6351cb0641f3f77b4e6de" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Aug 13 00:22:55 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 13 00:22:55 2021 +0200" }, "message": "Merge changes from topic \"st_fip_fconf\" into integration\n\n* changes:\n feat(io_mtd): offset management for FIP usage\n feat(nand): count bad blocks before a given offset\n feat(plat/st): add helper to save boot interface\n fix(plat/st): improve DDR get size function\n refactor(plat/st): map DDR secure at boot\n refactor(plat/st): rework TZC400 configuration\n" }, { "commit": "c7e4f1cfb84136a7521f26e403a6635ffdce4a2b", "tree": "cfcec0036b645f2d95e72e0820a67deb0a0fed80", "parents": [ "5360449b61ccfe8c2e70c4d533e01b62d0199154" ], "author": { "name": "Abdellatif El Khlifi", "email": "abdellatif.elkhlifi@arm.com", "time": "Wed Aug 11 12:04:41 2021 +0100" }, "committer": { "name": "Abdellatif El Khlifi", "email": "abdellatif.elkhlifi@arm.com", "time": "Thu Aug 12 16:49:52 2021 +0100" }, "message": "feat: enabling stack protector for diphda\n\nThis commit activates the stack protector feature for the diphda\nplatform.\n\nChange-Id: Ib16b74871c62b67e593a76ecc12cd3634d212614\nSigned-off-by: Abdellatif El Khlifi \u003cabdellatif.elkhlifi@arm.com\u003e\n" }, { "commit": "5360449b61ccfe8c2e70c4d533e01b62d0199154", "tree": "e4068e8da81877a784dfd31e626c801f239c9899", "parents": [ "ae5cfc5fe01e2629ff3663a42fb2c585b4d3e7cc", "d53c9dbf9ff9c435552b62f47fb95bfe86d025e3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Aug 12 15:47:53 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 12 15:47:53 2021 +0200" }, "message": "Merge \"feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP\" into integration" }, { "commit": "ae5cfc5fe01e2629ff3663a42fb2c585b4d3e7cc", "tree": "c7883a512591a49f11a1fedbb14bcb941f2fb046", "parents": [ "8ce073e420db827dbc074a50626126de0543669a", "6ec0c65b09745fd0f4cee44ee3aa99870303f448" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Aug 11 23:51:45 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 11 23:51:45 2021 +0200" }, "message": "Merge \"feat(plat/arm): Introduce TC1 platform\" into integration" }, { "commit": "6ec0c65b09745fd0f4cee44ee3aa99870303f448", "tree": "c7883a512591a49f11a1fedbb14bcb941f2fb046", "parents": [ "8ce073e420db827dbc074a50626126de0543669a" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Fri Apr 09 17:07:41 2021 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Wed Aug 11 11:36:50 2021 +0100" }, "message": "feat(plat/arm): Introduce TC1 platform\n\nThis renames tc0 platform folder and files to tc, and introduces\nTARGET_PLATFORM variable to account for the differences between\nTC0 and TC1.\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nChange-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd\n" }, { "commit": "8ce073e420db827dbc074a50626126de0543669a", "tree": "b89c1a65d7feed1e7eaa4a8506a34b9cc991472e", "parents": [ "0d6aff206022ae5040791c8709c05ca51a2f940f", "5183e637a0496ad8dfbd8c892bc874ac6a1531bf" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Aug 11 00:46:12 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 11 00:46:12 2021 +0200" }, "message": "Merge \"feat(plat/mdeiatek/mt8192): add DFD control in SiP service\" into integration" }, { "commit": "0d6aff206022ae5040791c8709c05ca51a2f940f", "tree": "a62ca829edaa2bcfe71a6df80b348d78ac500455", "parents": [ "9aacfb6fff20f2c85afb0d5861929b042b26e3d7", "100d4029a926a7d0df28072d9674787c09e37d85" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Aug 10 21:43:00 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 21:43:00 2021 +0200" }, "message": "Merge \"errata: workaround for Neoverse V1 errata 2139242\" into integration" }, { "commit": "9aacfb6fff20f2c85afb0d5861929b042b26e3d7", "tree": "fa6a4c1698f17853b3f58ebfda5a094b7c1a3816", "parents": [ "e5c7a92b5066c4456a4f748ac9a75edfe3fe25c8", "1a8804c3834966f8177eb9211bb24f546420ba9b" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Aug 10 21:42:50 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 21:42:50 2021 +0200" }, "message": "Merge \"errata: workaround for Neoverse V1 errata 1966096\" into integration" }, { "commit": "100d4029a926a7d0df28072d9674787c09e37d85", "tree": "a62ca829edaa2bcfe71a6df80b348d78ac500455", "parents": [ "1a8804c3834966f8177eb9211bb24f546420ba9b" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Aug 03 14:35:20 2021 -0500" }, "committer": { "name": "John", "email": "john.powell@arm.com", "time": "Tue Aug 10 17:23:01 2021 +0200" }, "message": "errata: workaround for Neoverse V1 errata 2139242\n\nNeoverse V1 erratum 2139242 is a Cat B erratum present in the V1\nprocessor core. This issue is present in revisions r0p0, r1p0,\nand r1p1, and it is still open.\n\nSDEN can be found here:\nhttps://documentation-service.arm.com/static/60d499080320e92fa40b4625\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe\n" }, { "commit": "1a8804c3834966f8177eb9211bb24f546420ba9b", "tree": "fa6a4c1698f17853b3f58ebfda5a094b7c1a3816", "parents": [ "e5c7a92b5066c4456a4f748ac9a75edfe3fe25c8" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Mon Aug 02 18:59:08 2021 -0500" }, "committer": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Aug 10 10:22:00 2021 -0500" }, "message": "errata: workaround for Neoverse V1 errata 1966096\n\nNeoverse V1 erratum 1966096 is a Cat B erratum present in the V1\nprocessor core. This issue is present in revisions r0p0, r1p0,\nand r1p1, but the workaround only applies to r1p0 and r1p1, it is still\nopen.\n\nSDEN can be found here:\nhttps://documentation-service.arm.com/static/60d499080320e92fa40b4625\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ic0b9a931e38da8a7000648e221481e17c253563b\n" }, { "commit": "e5c7a92b5066c4456a4f748ac9a75edfe3fe25c8", "tree": "935feccb295eb7ff6ba7737208e27473f2c00364", "parents": [ "abde216dc8ac95c43ad4b477a669b1249be6e289", "62f9134de08041322c8e970b19b7bd3d4f176275" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Aug 10 15:58:11 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 15:58:11 2021 +0200" }, "message": "Merge \"revert(plat/xilinx): add timeout while waiting for IPI Ack\" into integration" }, { "commit": "abde216dc8ac95c43ad4b477a669b1249be6e289", "tree": "15c467710c51f37b5e5aee15d5e5d51feb4a64ad", "parents": [ "d1987f4c8f07192cb5f80289c809f88298759193", "e1c732d46fa91231b39209621ead1e5a5fb2c497" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Aug 10 11:14:44 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 11:14:44 2021 +0200" }, "message": "Merge \"feat(ff-a): update FF-A version to v1.1\" into integration" }, { "commit": "62f9134de08041322c8e970b19b7bd3d4f176275", "tree": "6e802402ca7e0fa65ed71cfa895e5311811864ff", "parents": [ "87311b4c16730b884c7e4ff01e3faea83f2731be" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed Aug 04 21:33:15 2021 -0600" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Mon Aug 09 23:20:39 2021 -0600" }, "message": "revert(plat/xilinx): add timeout while waiting for IPI Ack\n\nThis reverts commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01.\n\nTimeout in IPI ack was added for functional safety reason.\nFunctional safety is not criteria for ATF. However, this\ncreates issues for APIs that take long or non-deterministic\nduration like FPGA load. So revert this patch for now to fix\nFPGA loading issue. Need to add support for non-blocking API\nfor FPGA loading with callback when API completes.\n\nSigned-off-by: Rajan Vaja \u003crajan.vaja@xilinx.com\u003e\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I940e798f1e2f7d0dfca1da5caaf8b94036d440c6\n" }, { "commit": "5183e637a0496ad8dfbd8c892bc874ac6a1531bf", "tree": "dd43e1d24e3b09d94bebf137ea5e907909c9eaa7", "parents": [ "d1987f4c8f07192cb5f80289c809f88298759193" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.com", "time": "Mon Jul 05 20:42:09 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Tue Aug 10 09:41:15 2021 +0800" }, "message": "feat(plat/mdeiatek/mt8192): add DFD control in SiP service\n\nDFD (Design for Debug) is a debugging tool, which scans\nflip-flops and dumps to internal RAM on the WDT reset.\nAfter system reboots, those values could be showed for\ndebugging.\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I9c7af9a4f75216ed2c6b44458d121a352bef4b95\n" }, { "commit": "d1987f4c8f07192cb5f80289c809f88298759193", "tree": "f8874314dc2eff8a1a068784b4230f21bb5fe29e", "parents": [ "55120f9ca64fa0ed3f3f7120a421b6522d2b7a77", "741dd04c812f0bd3015f8e934cb9da84e068040e" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Aug 10 00:32:05 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 00:32:05 2021 +0200" }, "message": "Merge \"errata: workaround for Neoverse V1 errata 1925756\" into integration" }, { "commit": "55120f9ca64fa0ed3f3f7120a421b6522d2b7a77", "tree": "9c832c243d58ff60244eba090275f8466800f5ae", "parents": [ "1d24eb33c567acc858cfd5329929297aa2b4c60e", "143b19651bd7f4ff00757436fcd768b20aaf3eb7" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Aug 10 00:31:44 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 00:31:44 2021 +0200" }, "message": "Merge \"errata: workaround for Neoverse V1 errata 1852267\" into integration" }, { "commit": "1d24eb33c567acc858cfd5329929297aa2b4c60e", "tree": "86e8316f882d059739034a4fcb69cd32db05d8da", "parents": [ "ddbc09abef3af359b12b6f516868db8d0f540dd3", "4789cf66af0560900b088e03968bc2fc83d1f330" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Aug 10 00:31:25 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 10 00:31:25 2021 +0200" }, "message": "Merge \"errata: workaround for Neoverse V1 errata 1774420\" into integration" }, { "commit": "ddbc09abef3af359b12b6f516868db8d0f540dd3", "tree": "0cde3f2088b07bf424af953471a147ca9bbfb87f", "parents": [ "87311b4c16730b884c7e4ff01e3faea83f2731be", "f34322c1cea1e355aeb4133df6aa601d719be5a3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 09 17:23:00 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 09 17:23:00 2021 +0200" }, "message": "Merge \"fix: avoid redefinition of \u0027efi_guid\u0027 structure\" into integration" }, { "commit": "f34322c1cea1e355aeb4133df6aa601d719be5a3", "tree": "0cde3f2088b07bf424af953471a147ca9bbfb87f", "parents": [ "87311b4c16730b884c7e4ff01e3faea83f2731be" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Aug 04 16:32:53 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Aug 06 12:54:11 2021 +0100" }, "message": "fix: avoid redefinition of \u0027efi_guid\u0027 structure\n\nFixed the build error by removing the local definition of \u0027efi_guid\u0027\nstructure in \u0027sgi_ras.c\u0027 file as this structure definition is already\npopulated in \u0027sgi_ras.c\u0027 file via \u0027uuid.h\u0027 header.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I57687336863f2a0761c09b6c1aa00b4aa82a6a12\n" }, { "commit": "e1c732d46fa91231b39209621ead1e5a5fb2c497", "tree": "d21d37aff9fd70c6ccb306f781fe18c35bf67590", "parents": [ "87311b4c16730b884c7e4ff01e3faea83f2731be" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Thu Mar 11 17:46:47 2021 +0000" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Aug 06 11:16:39 2021 +0200" }, "message": "feat(ff-a): update FF-A version to v1.1\n\nBump the required FF-A version in framework and manifests to v1.1 as\nupstream feature development goes.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I89b2bd3828a13fc4344ccd53bc3ac9c0c22ab29f\n" }, { "commit": "741dd04c812f0bd3015f8e934cb9da84e068040e", "tree": "795e28fdd9f12e85ed5e377c4d440faea00c2aed", "parents": [ "143b19651bd7f4ff00757436fcd768b20aaf3eb7" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Mon Aug 02 15:00:15 2021 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Aug 05 12:17:04 2021 -0500" }, "message": "errata: workaround for Neoverse V1 errata 1925756\n\nNeoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,\nand r1p1 of the V1 processor core, and it is still open.\n\nSDEN can be found here:\nhttps://documentation-service.arm.com/static/60d499080320e92fa40b4625\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52\n" }, { "commit": "143b19651bd7f4ff00757436fcd768b20aaf3eb7", "tree": "7de35b6109838b8bc03a22878b1b6c2ee3cf23fc", "parents": [ "4789cf66af0560900b088e03968bc2fc83d1f330" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Mon Aug 02 14:40:08 2021 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Aug 03 09:49:09 2021 -0500" }, "message": "errata: workaround for Neoverse V1 errata 1852267\n\nNeoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and\nr1p0 of the V1 processor core. It is fixed in r1p1.\n\nSDEN can be found here:\nhttps://documentation-service.arm.com/static/60d499080320e92fa40b4625\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe\n" }, { "commit": "4789cf66af0560900b088e03968bc2fc83d1f330", "tree": "c2a8bdd38cc33364339c0072a9211d598e90ba2d", "parents": [ "6ea1a75df34c9beed4609b84544d473b8d5690e7" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Mon Aug 02 13:22:32 2021 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Aug 03 09:46:12 2021 -0500" }, "message": "errata: workaround for Neoverse V1 errata 1774420\n\nNeoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and\nr1p0 of the V1 processor core. It is fixed in r1p1.\n\nSDEN can be found here:\nhttps://documentation-service.arm.com/static/60d499080320e92fa40b4625\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123\n" }, { "commit": "87311b4c16730b884c7e4ff01e3faea83f2731be", "tree": "e5d17d5e53e025d9f24662d31531c500d453e20a", "parents": [ "5e4e13e173444e526123dfa2542b5e49e9b7d624", "050a99a62f1df4de589be077b5b5fffe3c93afc7" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Aug 03 13:50:31 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 03 13:50:31 2021 +0200" }, "message": "Merge \"refactor: moved drivers hdr files to include/drivers/nxp\" into integration" }, { "commit": "050a99a62f1df4de589be077b5b5fffe3c93afc7", "tree": "e5d17d5e53e025d9f24662d31531c500d453e20a", "parents": [ "5e4e13e173444e526123dfa2542b5e49e9b7d624" ], "author": { "name": "Pankaj Gupta", "email": "pankaj.gupta@nxp.com", "time": "Thu Mar 25 15:15:52 2021 +0530" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Aug 03 12:19:56 2021 +0200" }, "message": "refactor: moved drivers hdr files to include/drivers/nxp\n\nNXP drivers header files are moved:\n - from: drivers/nxp/\u003cxx\u003e/*.h\n - to : include/drivers/nxp/\u003cxx\u003e/*.h\n\nTo accommodate these changes each drivers makefiles\ndrivers/nxp/\u003cxx\u003e/xx.mk, are updated.\n\nSigned-off-by: Pankaj Gupta \u003cpankaj.gupta@nxp.com\u003e\nChange-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21\n" }, { "commit": "5e4e13e173444e526123dfa2542b5e49e9b7d624", "tree": "b364e326c0a81b902764fccc0e811f028e81bcfc", "parents": [ "c7e39dcf6881426d7eee590b357e73ccaaf8992e", "f21693704a7bac275e12b44ae30fd210bc317175" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Aug 02 22:53:50 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 02 22:53:50 2021 +0200" }, "message": "Merge changes from topic \"fw-update-2\" into integration\n\n* changes:\n feat(sw_crc32): add software CRC32 support\n refactor(hw_crc32): renamed hw_crc32 to tf_crc32\n feat(fwu): avoid booting with an alternate boot source\n docs(fwu): add firmware update documentation\n feat(fwu): avoid NV counter upgrade in trial run state\n feat(plat/arm): add FWU support in Arm platforms\n feat(fwu): initialize FWU driver in BL2\n feat(fwu): add FWU driver\n feat(fwu): introduce FWU platform-specific functions declarations\n docs(fwu_metadata): add FWU metadata build options\n feat(fwu_metadata): add FWU metadata header and build options\n" }, { "commit": "f21693704a7bac275e12b44ae30fd210bc317175", "tree": "56e0c18861d3c8c3aa5967431ca582c3a8da622c", "parents": [ "c885d5c84d94cd82a80e074b2d6e6b5c04796cde" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jul 02 20:18:57 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:41 2021 +0100" }, "message": "feat(sw_crc32): add software CRC32 support\n\nAdded software CRC32 support in case platform doesn\u0027t support\nhardware CRC32.\n\nPlatform must include necessary Zlib source files for compilation\nto use software CRC32 implementation.\n\nChange-Id: Iecb649b2edf951944b1a7e4c250c40fe7a3bde25\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "c885d5c84d94cd82a80e074b2d6e6b5c04796cde", "tree": "9b12759afd4f9750b436ba72f348b664e526ebe6", "parents": [ "4b48f7b56577a78cdc9a2b47280cb62cbae0f7c3" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jul 02 20:29:56 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:41 2021 +0100" }, "message": "refactor(hw_crc32): renamed hw_crc32 to tf_crc32\n\nRenamed hw_crc32 to tf_crc32 to make the file and function\nname more generic so that the same name can be used in upcoming\nsoftware CRC32 implementation.\n\nChange-Id: Idff8f70c50ca700a4328a27b49d5e1f14d2095eb\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "4b48f7b56577a78cdc9a2b47280cb62cbae0f7c3", "tree": "0c2dbbda80f3e09f57a3704503ce7191ac8d84f5", "parents": [ "0f20e50b26f29db7c6ae033446e6b4c9ae9f2c86" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jul 01 21:32:31 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:41 2021 +0100" }, "message": "feat(fwu): avoid booting with an alternate boot source\n\nAll firmware banks should be part of the same non-volatile storage\nas per PSA FWU specification, hence avoid checking for any alternate\nboot source when PSA FWU is enabled.\n\nChange-Id: I5b016e59e87f1cbfc73f4cd29fce6017c24f88b3\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "0f20e50b26f29db7c6ae033446e6b4c9ae9f2c86", "tree": "44cabd1077ea3b0cadfbbc71dab3e7c315cf445a", "parents": [ "c0bfc88f8e8e03974834cbcacbbfbd5f202a2857" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Sun Jun 20 21:14:46 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:41 2021 +0100" }, "message": "docs(fwu): add firmware update documentation\n\nAdded firmware update documentation for:\n1. PSA firmware update build flag\n2. Porting guidelines to set the addresses of FWU metadata image\n and updated components in I/O policy\n\nChange-Id: Iad3eb68b4be01a0b5850b69a067c60fcb464f54b\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "c0bfc88f8e8e03974834cbcacbbfbd5f202a2857", "tree": "61c1d7c174f7177ebc596aee7d8ceb7a89dda074", "parents": [ "2f1177b2b9ebec3b2fe92607cd771bda1dc9cbfc" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Sun Jun 20 22:29:22 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:40 2021 +0100" }, "message": "feat(fwu): avoid NV counter upgrade in trial run state\n\nAvoided NV counter update when the system is running in\ntrial run state.\n\nChange-Id: I5da6a6760f8a9faff777f2ff879156e9c3c76726\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "2f1177b2b9ebec3b2fe92607cd771bda1dc9cbfc", "tree": "6238a52ba6771873adb0e1f669e538ed60dd0396", "parents": [ "396b339dc20b97ddd75146e03467a255e28f31b9" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 25 23:43:33 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:40 2021 +0100" }, "message": "feat(plat/arm): add FWU support in Arm platforms\n\nAdded firmware update support in Arm platforms by using\nFWU platform hooks and compiling FWU driver in BL2\ncomponent.\n\nChange-Id: I71af06c09d95c2c58e3fd766c4a61c5652637151\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "396b339dc20b97ddd75146e03467a255e28f31b9", "tree": "d48c4ca8b4f0a1d9cfec890f249d205739a74fe1", "parents": [ "0ec3ac60d86b75d132e7a63fc09ea47e67f90bbd" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 25 23:28:59 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:40 2021 +0100" }, "message": "feat(fwu): initialize FWU driver in BL2\n\nInitialized FWU driver module in BL2 component under\nbuild flag PSA_FWU_SUPPORT.\n\nChange-Id: I08b191599835925c355981d695667828561b9a21\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "0ec3ac60d86b75d132e7a63fc09ea47e67f90bbd", "tree": "a02d5a34c7fef69a210661404a9dc4899d69ee38", "parents": [ "efb2ced256dacbab71ca11cbc87f70f413ca6729" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Sun Jun 20 20:35:25 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:40 2021 +0100" }, "message": "feat(fwu): add FWU driver\n\nImplemented FWU metadata load and verification APIs.\nAlso, exported below APIs to the platform:\n1. fwu_init - Load FWU metadata in a structure. Also, set the\n\t addresses of updated components in I/O policy\n2. fwu_is_trial_run_state - To detect trial run or regular run\n\t\t\t state\n\nChange-Id: I67eeabb52d9275ac83be635306997b7c353727cd\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "efb2ced256dacbab71ca11cbc87f70f413ca6729", "tree": "ee1f3a1b2dd636e4260d8b5a50e274d0fddcb2d5", "parents": [ "34f702d5db1d95960a86329af4e1c119c4e406db" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Sun Jun 20 21:04:49 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 17:15:32 2021 +0100" }, "message": "feat(fwu): introduce FWU platform-specific functions declarations\n\nAdded FWU platform specific functions declarations in common\nplatform header.\n\nChange-Id: I637e61753ea3dc7f7e7f3159ae1b43ab6780aef2\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "c7e39dcf6881426d7eee590b357e73ccaaf8992e", "tree": "0f8dba150f178eb792b368bb8bc091bce7a68637", "parents": [ "6881f7be465a60a6bda54da2a07bd68aacf816b2", "bb320dbc4751f7ea0c37ffba07d14628e58081d0" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Aug 02 18:14:54 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Aug 02 18:14:54 2021 +0200" }, "message": "Merge \"feat(ff-a): change manifest messaging method\" into integration" }, { "commit": "34f702d5db1d95960a86329af4e1c119c4e406db", "tree": "9e834076883c3e004d8e7e0730eb132c99348f27", "parents": [ "5357f83d4ee89fb831d7e4f6149ae2f652e1b9af" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Mar 16 11:14:19 2021 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 14:39:41 2021 +0100" }, "message": "docs(fwu_metadata): add FWU metadata build options\n\nAdded the build options used in defining the firmware update metadata\nstructure.\n\nChange-Id: Idd40ea629e643e775083f283b75c80f6c026b127\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "5357f83d4ee89fb831d7e4f6149ae2f652e1b9af", "tree": "3d87ac080cf4984baf3f57e8bde02d099888afd5", "parents": [ "6881f7be465a60a6bda54da2a07bd68aacf816b2" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Mar 16 10:01:27 2021 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Aug 02 14:39:41 2021 +0100" }, "message": "feat(fwu_metadata): add FWU metadata header and build options\n\nAdded a firmware update metadata structure as per section 4.1\nin the specification document[1].\n\nAlso, added the build options used in defining the firmware\nupdate metadata structure.\n\n[1]: https://developer.arm.com/documentation/den0118/a/\n\nChange-Id: I8f43264a46fde777ceae7fd2a5bb0326f1711928\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "6881f7be465a60a6bda54da2a07bd68aacf816b2", "tree": "eef68e62946df5fe2e9cd54ddda0053b9f5129ab", "parents": [ "6ea1a75df34c9beed4609b84544d473b8d5690e7", "a5fea8105887d0dd15edf94aebd591b1b6b5ef05" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 30 17:58:22 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 30 17:58:22 2021 +0200" }, "message": "Merge changes Ic7579b60,I05414ca1 into integration\n\n* changes:\n fix(plat/ea_handler): print newline before fatal abort error message\n feat(common/debug): add new macro ERROR_NL() to print just a newline\n" }, { "commit": "a5fea8105887d0dd15edf94aebd591b1b6b5ef05", "tree": "e92ddf5ce8a10c9be38ecd53c094f7c9d1fe98ac", "parents": [ "fd1360a339e84ccd49f8a2d8a42e4c131a681b3c" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Jun 22 20:23:38 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Thu Jul 29 16:30:40 2021 +0100" }, "message": "fix(plat/ea_handler): print newline before fatal abort error message\n\nExternal Abort may happen also during printing of some messages by\nU-Boot or kernel. So print newline before fatal abort error message.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: Ic7579b605e695c2e4cb9a4f5cdc2d0b3e5083e49\n" }, { "commit": "6ea1a75df34c9beed4609b84544d473b8d5690e7", "tree": "6c29307177b992ee088bf73cd984160d78a0c9de", "parents": [ "20ceff34c3e563ed69b20fd67efd4b4f3bb36761", "92024f81a673734512e83c5573f7d8f398d17aa4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jul 29 10:55:44 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jul 29 10:55:44 2021 +0200" }, "message": "Merge \"refactor(plat/marvell): move doc platform build options into own subsections\" into integration" }, { "commit": "20ceff34c3e563ed69b20fd67efd4b4f3bb36761", "tree": "7175b31283055c8edf4cc39190a1ab3dc591646e", "parents": [ "81bbb9216bf4df0e73e3863a06f9ffbbdbd5d768", "d21f1ddb71fc9e13f4f352f34e2a707a5b7df301" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Jul 28 21:25:53 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 28 21:25:53 2021 +0200" }, "message": "Merge \"services: Fix pmr_el1 rewrote issue in sdei_disaptch_event()\" into integration" }, { "commit": "81bbb9216bf4df0e73e3863a06f9ffbbdbd5d768", "tree": "794b54fbf846873ba2530b6d0d8258c233a468dc", "parents": [ "fe1021f1a13e1c02c42bb80de74a096ccb8d49da", "749d0fa80d1c7ca30b4092a381a06deeeaf1747f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 28 13:23:39 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 28 13:23:39 2021 +0200" }, "message": "Merge \"fix(plat/fvp): provide boot files via semihosting\" into integration" }, { "commit": "749d0fa80d1c7ca30b4092a381a06deeeaf1747f", "tree": "794b54fbf846873ba2530b6d0d8258c233a468dc", "parents": [ "fe1021f1a13e1c02c42bb80de74a096ccb8d49da" ], "author": { "name": "Stas Sergeev", "email": "stsp@users.sourceforge.net", "time": "Mon Jul 26 13:19:39 2021 +0300" }, "committer": { "name": "Stas Sergeev", "email": "stsp@users.sourceforge.net", "time": "Wed Jul 28 14:16:55 2021 +0300" }, "message": "fix(plat/fvp): provide boot files via semihosting\n\nThese files are needed during boot, but they were missing\nfor semihosting.\nWith this patch, the list of files is complete enough to\nboot on ATF platform via semihosting.\n\nChange-Id: I2f0ca25983a6e18096f040780776f19f8040ea79\nSigned-off-by: stsp@users.sourceforge.net\n" }, { "commit": "fe1021f1a13e1c02c42bb80de74a096ccb8d49da", "tree": "b09770adcb8e8b79961dd240078fb0af3f3ca1ef", "parents": [ "d985cb743bde7ddf61f85b0ff83930d459120288", "6e63cdc55e3b8b75396f42b2a6ad9951a9b8332b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 28 13:01:35 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 28 13:01:35 2021 +0200" }, "message": "Merge \"rpi4: enable RPi4 PCI SMC conduit\" into integration" }, { "commit": "d985cb743bde7ddf61f85b0ff83930d459120288", "tree": "8d7a2393205026e0af0dcee039ec3cc001508293", "parents": [ "7bfec3adf3e01b7c5cd1f023e614687e564ec796", "5a5e0aac398989536dc4be790820af89da3d093a" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jul 28 11:29:32 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 28 11:29:32 2021 +0200" }, "message": "Merge \"fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif\" into integration" }, { "commit": "7bfec3adf3e01b7c5cd1f023e614687e564ec796", "tree": "4e111efc824313be31c43b32ef6f7c7ba0b97f74", "parents": [ "743e3b4147a74ebedf9d59058537c1729955c0b0", "ab061eb732dcd2ee711b6960c37c4b25c44f3f9d" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Jul 28 11:19:53 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jul 28 11:19:53 2021 +0200" }, "message": "Merge \"rpi4: SMCCC PCI implementation\" into integration" }, { "commit": "d21f1ddb71fc9e13f4f352f34e2a707a5b7df301", "tree": "ed376ad8e71fa156886b56ae6e19c49edd5ee196", "parents": [ "743e3b4147a74ebedf9d59058537c1729955c0b0" ], "author": { "name": "Ming Huang", "email": "huangming@linux.alibaba.com", "time": "Fri Apr 23 15:06:17 2021 +0800" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Jul 28 11:12:44 2021 +0200" }, "message": "services: Fix pmr_el1 rewrote issue in sdei_disaptch_event()\n\nConsider a RAS scenario:\nEnter EL3 by sync exception, then call spm_mm_sp_call() enter\nEL0s to handle this error, then call sdei_dispatch_event() to\ninform OS. Finally, return back to OS from sync exception flow.\nSimilar flow is sgi_ras_intr_handler() in sgi_ras.c.\n\nThe icc_pmr_el1 register will be change in above flow:\n1 cm_el1_sysregs_context_save(NON_SECURE);\n -\u003e ehf_exited_normal_world();\n ##icc_pmr_el1: 0xf8 \u003d\u003e 0x80\n2 spm_mm_sp_call();\n3 sdei_dispatch_event();\n4 ehf_activate_priority(sdei_event_priority(map));\n ##icc_pmr_el1: 0x80 \u003d\u003e 0x60\n5 restore_and_resume_ns_context();\n -\u003e ehf_exited_normal_world();\n ##return due to has_valid_pri_activations(pe_data) \u003d\u003d 1\n6 ehf_deactivate_priority(sdei_event_priority(map));\n ##icc_pmr_el1: 0x60 \u003d\u003e 0x80\nThe icc_pmr_el1 was rewrote from 0xf8 to 0x80. This issue will\nresult in OS hang when eret to OS from RAS flow.\n\nMove ehf_activate_priority(sdei_event_priority(map)) after\nrestore_and_resume_ns_context() can fix this issue.\n\nSigned-off-by: Ming Huang \u003chuangming@linux.alibaba.com\u003e\nChange-Id: If01ec55cf0aabf1594dece1ad50d3ec3406cdabc\n" }, { "commit": "ab061eb732dcd2ee711b6960c37c4b25c44f3f9d", "tree": "4e111efc824313be31c43b32ef6f7c7ba0b97f74", "parents": [ "743e3b4147a74ebedf9d59058537c1729955c0b0" ], "author": { "name": "Jeremy Linton", "email": "jeremy.linton@arm.com", "time": "Wed Nov 18 10:11:33 2020 -0600" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Jul 28 09:41:55 2021 +0200" }, "message": "rpi4: SMCCC PCI implementation\n\nThe rpi4 has a single nonstandard ECAM. It is broken\ninto two pieces, the root port registers, and a window\nto a single device\u0027s config space which can be moved\nbetween devices. Now that we have widened the page\ntables/MMIO window, we can create a read/write acces\nfunctions that are called by the SMCCC/PCI API.\n\nAs an example platform, the rpi4 single device ECAM\nregion quirk is pretty straightforward. The assumption\nhere is that a lower level (uefi) has configured and\ninitialized the PCI root to match the values we are\nusing here.\n\nSigned-off-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\nChange-Id: Ie1ffa8fe9aa1d3c62e6aa84746a949c1009162e0\n" }, { "commit": "6e63cdc55e3b8b75396f42b2a6ad9951a9b8332b", "tree": "e9cbea4eae95dd8fb81fdb7609b8d81bdd5ea02d", "parents": [ "743e3b4147a74ebedf9d59058537c1729955c0b0" ], "author": { "name": "Jeremy Linton", "email": "jeremy.linton@arm.com", "time": "Wed Nov 18 10:13:30 2020 -0600" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Jul 28 09:41:05 2021 +0200" }, "message": "rpi4: enable RPi4 PCI SMC conduit\n\nNow that we have adjusted the address map, added the\nSMC conduit code, and the RPi4 PCI callbacks, lets\nadd the flags to enable everything in the build.\n\nBy default this service is disabled because the\nexpectation is that its only useful in a UEFI+ACPI\nenvironment.\n\nSigned-off-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\nChange-Id: I2a3cac6d63ba8119d3b711db121185816b89f8a2\n" }, { "commit": "743e3b4147a74ebedf9d59058537c1729955c0b0", "tree": "aaa833d4a719e856c101506f83d0036fdd018aa4", "parents": [ "7fb82d82863d94eb5938119f149299558deeca46", "59c2a027400d6b5a2853efdfa085052fcc11bd64" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jul 27 21:35:11 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 27 21:35:11 2021 +0200" }, "message": "Merge \"plat/sgi: tag dmc620 MM communicate messages with a guid\" into integration" }, { "commit": "92024f81a673734512e83c5573f7d8f398d17aa4", "tree": "63bb7d537b2ae98ec016b90d6d912b6cfda605c2", "parents": [ "e18f4aaf5ea36c3df3d83a0ba11af3247597ab74" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Jul 20 17:42:24 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Jul 27 19:31:36 2021 +0100" }, "message": "refactor(plat/marvell): move doc platform build options into own subsections\n\nUpdate documentation and group platform specific build options into\ntheir own subsections.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I05927d8abf9f811493c49b856f06329220e7d8bb\n" }, { "commit": "7fb82d82863d94eb5938119f149299558deeca46", "tree": "23dd5be582bd5892df4068c3973b92b2c998510b", "parents": [ "048fe1916cdd139e8fa9bc22a8d0f88cc3f8e148", "2c4b0c05c6546e24eb7209ffb3bb465d4feed164" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jul 27 17:01:40 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 27 17:01:40 2021 +0200" }, "message": "Merge \"fix(rk3399/suspend): correct LPDDR4 resume sequence\" into integration" }, { "commit": "048fe1916cdd139e8fa9bc22a8d0f88cc3f8e148", "tree": "f72d29436532e27187b8efc500bf122a9e652b2b", "parents": [ "d31f319492fb328b170cb89316f5f0cfab490cae", "d0d642450f1f3a0f43e0e156ef57a0c460dd48cf" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Jul 27 16:06:30 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jul 27 16:06:30 2021 +0200" }, "message": "Merge \"fix(fdt): fix OOB write in uuid parsing function\" into integration" }, { "commit": "d0d642450f1f3a0f43e0e156ef57a0c460dd48cf", "tree": "8f0d28da8f47a6d58363ac5efb2888da40f1b9b6", "parents": [ "f98c0bea9c31630fce4895b8ae2fc50e399fe9ec" ], "author": { "name": "David Horstmann", "email": "david.horstmann@arm.com", "time": "Mon Jul 26 16:31:42 2021 +0100" }, "committer": { "name": "David Horstmann", "email": "david.horstmann@arm.com", "time": "Mon Jul 26 16:42:25 2021 +0100" }, "message": "fix(fdt): fix OOB write in uuid parsing function\n\nThe function read_uuid() zeroes the UUID destination buffer\non error. However, it mistakenly uses the dest pointer\nthat has been incremented many times during the parsing,\nleading to an out-of-bounds write.\n\nTo fix this, retain a pointer to the start of the buffer,\nand use this when clearing it instead.\n\nSigned-off-by: David Horstmann \u003cdavid.horstmann@arm.com\u003e\nChange-Id: Iee8857be5d3f383ca2eab86cde99a43bf606f306\n" }, { "commit": "d31f319492fb328b170cb89316f5f0cfab490cae", "tree": "4e0e797b32e5ad351a4005ee92f2dadd05e59548", "parents": [ "81e63f25ff2414385cb7ce24db47d5f39a0ccbb3", "99d37c8cb8196a7296311fb4f97f80f086021c74" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jul 26 17:39:59 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 26 17:39:59 2021 +0200" }, "message": "Merge \"fix(plat/imx): do not keep mmc_device_info in stack\" into integration" }, { "commit": "81e63f25ff2414385cb7ce24db47d5f39a0ccbb3", "tree": "647d8f50d0f2267f50ca5031688379bbe6daa0df", "parents": [ "f98c0bea9c31630fce4895b8ae2fc50e399fe9ec", "0e54a7899dcab939e5204bbe52dc29b9674cfd13" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Mon Jul 26 17:29:30 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 26 17:29:30 2021 +0200" }, "message": "Merge changes from topic \"allwinner_mmap\" into integration\n\n* changes:\n refactor(plat/allwinner): clean up platform definitions\n refactor(plat/allwinner): do not map BL32 DRAM at EL3\n refactor(plat/allwinner): map SRAM as device memory by default\n refactor(plat/allwinner): rename static mmap region constant\n feat(bl_common): import BL_NOBITS_{BASE,END} when defined\n" }, { "commit": "f98c0bea9c31630fce4895b8ae2fc50e399fe9ec", "tree": "30765562d600f9e247ffdd1d5c815eac0f031792", "parents": [ "a52c52477aa797e6a261215e9b3536533590b334", "37596fcb43e34ed4bcf1bd3e86d8dec1011edab8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jul 26 11:15:30 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 26 11:15:30 2021 +0200" }, "message": "Merge \"fix(sdei): set SPSR for SDEI based on TakeException\" into integration" }, { "commit": "a52c52477aa797e6a261215e9b3536533590b334", "tree": "fe42b1908403e23192da125bef7ef05afb9534a0", "parents": [ "76cce57108d782b35a66e8ee5f3baf51193be352", "b5863cab9adb3fed0c1e4dfb92cf906794e7bdb4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jul 26 11:05:39 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jul 26 11:05:39 2021 +0200" }, "message": "Merge changes from topic \"sve+amu\" into integration\n\n* changes:\n fix(plat/tc0): enable AMU extension\n fix(el3_runtime): fix SVE and AMU extension enablement flags\n" }, { "commit": "76cce57108d782b35a66e8ee5f3baf51193be352", "tree": "3b58d4cbf6855df5343bc45f4af633d92a28ad71", "parents": [ "e73d9d0fa8ffb843775956499d8a221eebf76ca2", "7b514399e999047a9652d084cfa10a016884fc43" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Sun Jul 25 15:02:03 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Jul 25 15:02:03 2021 +0200" }, "message": "Merge \"docs(maintainers): update imx8 entry\" into integration" }, { "commit": "e73d9d0fa8ffb843775956499d8a221eebf76ca2", "tree": "76554ad67c76f0a314dcc5e98e0db6c57734724c", "parents": [ "d55d83090ef65d134c9974f8c02491919263acc8", "4429b47165eeee81fb8300c60a6832898c31db42" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Sat Jul 24 18:38:19 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Jul 24 18:38:19 2021 +0200" }, "message": "Merge \"refactor(aarch64): remove `FEAT_BTI` architecture check\" into integration" }, { "commit": "7b514399e999047a9652d084cfa10a016884fc43", "tree": "efd2553e34420e6b3b58212353bafc4ab4922352", "parents": [ "52eb322919017b4230fb0f9580020375db56466b" ], "author": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Fri Jul 23 18:18:53 2021 +0800" }, "committer": { "name": "Peng Fan", "email": "peng.fan@nxp.com", "time": "Sat Jul 24 21:16:13 2021 +0800" }, "message": "docs(maintainers): update imx8 entry\n\nAdd myself as i.MX8 maintainer.\n\nSigned-off-by: Peng Fan \u003cpeng.fan@nxp.com\u003e\nChange-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58\n" }, { "commit": "d55d83090ef65d134c9974f8c02491919263acc8", "tree": "8853ab8f62309e9d59c139eb0ad1e2214d301893", "parents": [ "52eb322919017b4230fb0f9580020375db56466b", "7f70cd29235cc5e96ff6b5f509c7e4260bec5610" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jul 23 19:24:07 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jul 23 19:24:07 2021 +0200" }, "message": "Merge changes from topic \"diphda\" into integration\n\n* changes:\n feat: disabling non volatile counters in diphda\n feat: adding the diphda platform\n" }, { "commit": "37596fcb43e34ed4bcf1bd3e86d8dec1011edab8", "tree": "94ea867d568914b1960a831b3b96da8f799ded95", "parents": [ "c791113776c91e13c930d7b3e1081a3902e4c856" ], "author": { "name": "Daniel Boulby", "email": "danielboulby@arm.com", "time": "Wed Nov 25 16:36:46 2020 +0000" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Jul 23 13:20:28 2021 +0100" }, "message": "fix(sdei): set SPSR for SDEI based on TakeException\n\nThe SDEI specification now says that during an SDEI\nevent handler dispatch the SPSR should be set according\nto the TakeException() pseudocode function defined in\nthe Arm Architecture Reference Manual. This patch sets\nthe SPSR according to the function given in\nARM DDI 0487F.c page J1-7635\n\nChange-Id: Id2f8f2464fd69c701d81626162827e5c4449b658\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\n" }, { "commit": "b5863cab9adb3fed0c1e4dfb92cf906794e7bdb4", "tree": "a8aaa271be7382aed67e73ca96fd625dad1b7469", "parents": [ "68ac5ed0493b24e6a0a178171a47db75a31cc423" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Jul 09 13:43:01 2021 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Jul 23 10:33:59 2021 +0100" }, "message": "fix(plat/tc0): enable AMU extension\n\nRecent changes to enable SVE for the secure world have disabled AMU\nextension by default in the reset value of CPTR_EL3 register. So the\nplatform has to enable this extension explicitly.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I7d930d96ec22d7c3db961411370564bece0ce272\n" }, { "commit": "68ac5ed0493b24e6a0a178171a47db75a31cc423", "tree": "9034048bd8ec2cc7abc7f1b8e2b541a194be9602", "parents": [ "52eb322919017b4230fb0f9580020375db56466b" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Jul 08 09:35:57 2021 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Fri Jul 23 10:33:59 2021 +0100" }, "message": "fix(el3_runtime): fix SVE and AMU extension enablement flags\n\nIf SVE are enabled for both Non-secure and Secure world along with AMU\nextension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit\nfrom bl31. This restricts access to the AMU register set in normal\nworld. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT\nby saving and restoring CPTR_EL3 register from EL3 context.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: Id76ce1d27ee48bed65eb32392036377716aff087\n" }, { "commit": "5a5e0aac398989536dc4be790820af89da3d093a", "tree": "8bd27563aeb13f3baeee3b9fa00fac9298254371", "parents": [ "c791113776c91e13c930d7b3e1081a3902e4c856" ], "author": { "name": "Ming Huang", "email": "huangming@linux.alibaba.com", "time": "Fri Jun 04 16:23:22 2021 +0800" }, "committer": { "name": "Ming Huang", "email": "huangming@linux.alibaba.com", "time": "Fri Jul 23 10:48:00 2021 +0800" }, "message": "fix(gicv3): add dsb in both disable and enable function of gicv3_cpuif\n\nA RAS error may be triggered while offline core in OS. Error:\nUncorrected software error in the Distributor, with IERR\u003d9,SERR\u003df.\nCore put to sleep before its Group enables were cleared.\n\ngicv3_cpuif_disable() will be called in offline core flow.\nAccording to GIC architecture version 3 and version 4:\nArchitectural execution of a DSB instruction guarantees that\nthe last value written to ICC_IGRPEN0_EL1, ICC_IGRPEN1_EL1,\nICC_IGRPEN1_EL3 or GICC_CTLR.{EnableGrp0, EnableGrp1}is observed\nby the associated Redistributor.\nAn ISB or other context synchronization operation must precede\nthe DSB to ensure visibility of System register writes.\n\nSigned-off-by: Ming Huang \u003chuangming@linux.alibaba.com\u003e\nChange-Id: Iff1475657f401374c761b5e8f2f5b3a4b2040e9d\n" }, { "commit": "0e54a7899dcab939e5204bbe52dc29b9674cfd13", "tree": "db66b54ffc5454ee3df98236bbf91c9473bc950d", "parents": [ "8d9efdf8a8885e8520c80692c3ffc36ff2c4b363" ], "author": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Sun Apr 04 15:54:17 2021 -0500" }, "committer": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Thu Jul 22 20:50:30 2021 -0500" }, "message": "refactor(plat/allwinner): clean up platform definitions\n\nGroup the SCP base/size definitions in a more logical location.\n\nSigned-off-by: Samuel Holland \u003csamuel@sholland.org\u003e\nChange-Id: Id43f9b468d7d855a2413173d674a5ee666527808\n" }, { "commit": "8d9efdf8a8885e8520c80692c3ffc36ff2c4b363", "tree": "42f96b86fcac29fa67b85d0ee9df9c176bfc8743", "parents": [ "ab74206b605eb6e8d573de15161bb14971556714" ], "author": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Sun Dec 13 20:22:42 2020 -0600" }, "committer": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Thu Jul 22 20:50:27 2021 -0500" }, "message": "refactor(plat/allwinner): do not map BL32 DRAM at EL3\n\nBL31 does not appear to ever access the DRAM allocated to BL32,\nso there is no need to map it at EL3.\n\nSigned-off-by: Samuel Holland \u003csamuel@sholland.org\u003e\nChange-Id: Ie8727b793e53ea14517894942266f6da0333eb74\n" }, { "commit": "ab74206b605eb6e8d573de15161bb14971556714", "tree": "50ddcf1716d05614c391fe30523ed56370f18626", "parents": [ "bc135624efdfffab220b032f7f3542541195c15c" ], "author": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Sun Dec 13 20:45:49 2020 -0600" }, "committer": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Thu Jul 22 20:50:24 2021 -0500" }, "message": "refactor(plat/allwinner): map SRAM as device memory by default\n\nThe SRAM on Allwinner platforms is shared between BL31 and coprocessor\nfirmware. Previously, SRAM was mapped as normal memory by default.\nThis scheme requires carveouts and cache maintenance code for proper\nsynchronization with the coprocessor.\n\nA better scheme is to only map pages owned by BL31 as normal memory,\nand leave everything else as device memory. This removes the need for\ncache maintenance, and it makes the mapping for BL31 RW data explicit\ninstead of magic.\n\nSigned-off-by: Samuel Holland \u003csamuel@sholland.org\u003e\nChange-Id: I820ddeba2dfa2396361c2322308c0db51b55c348\n" }, { "commit": "bc135624efdfffab220b032f7f3542541195c15c", "tree": "c932a395e46d8d05ca1dae590968a4df28f619f5", "parents": [ "9aedca021d917c7435aa2a0405972aa9d44493a2" ], "author": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Sun Dec 13 21:26:36 2020 -0600" }, "committer": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Thu Jul 22 20:50:21 2021 -0500" }, "message": "refactor(plat/allwinner): rename static mmap region constant\n\nThis constant specifically refers to the number of static mmap regions.\nRename it to make that clear.\n\nSigned-off-by: Samuel Holland \u003csamuel@sholland.org\u003e\nChange-Id: I475c037777ce2a10db2631ec0e7446bb73590a36\n" }, { "commit": "9aedca021d917c7435aa2a0405972aa9d44493a2", "tree": "0d016d072a7cf54e6633e2b29815e3d1f9e822fa", "parents": [ "e2a16044ad8ef33c7ce6e2c72c882d05583e1c38" ], "author": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Sun Dec 13 20:42:22 2020 -0600" }, "committer": { "name": "Samuel Holland", "email": "samuel@sholland.org", "time": "Thu Jul 22 20:50:17 2021 -0500" }, "message": "feat(bl_common): import BL_NOBITS_{BASE,END} when defined\n\nIf SEPARATE_NOBITS_REGION is enabled, the platform may need to map\nmemory specifically for that region. Import the symbols from the linker\nscript to allow the platform to do so.\n\nSigned-off-by: Samuel Holland \u003csamuel@sholland.org\u003e\nChange-Id: Iaec4dee94a6735b22f58f7b61f18d53e7bc6ca8d\n" }, { "commit": "7f70cd29235cc5e96ff6b5f509c7e4260bec5610", "tree": "8853ab8f62309e9d59c139eb0ad1e2214d301893", "parents": [ "bf3ce9937182e5d8d91e058baabb8213acedacdb" ], "author": { "name": "Abdellatif El Khlifi", "email": "abdellatif.elkhlifi@arm.com", "time": "Mon May 10 12:38:41 2021 +0100" }, "committer": { "name": "Abdellatif El Khlifi", "email": "abdellatif.elkhlifi@arm.com", "time": "Thu Jul 22 18:01:43 2021 +0100" }, "message": "feat: disabling non volatile counters in diphda\n\nAt this stage of development Non Volatile counters are not implemented\nin the Diphda platform.\n\nThis commit disables their use during the Trusted Board Boot by\noverriding the NV counters get/set functions.\n\nChange-Id: I8dcbebe0281cc4d0837c283ff637e20b850988ef\nSigned-off-by: Abdellatif El Khlifi \u003cabdellatif.elkhlifi@arm.com\u003e\n" }, { "commit": "bf3ce9937182e5d8d91e058baabb8213acedacdb", "tree": "751d6140edd4e2768e6aedb66e0529583f106ec4", "parents": [ "52eb322919017b4230fb0f9580020375db56466b" ], "author": { "name": "Abdellatif El Khlifi", "email": "abdellatif.elkhlifi@arm.com", "time": "Wed Apr 21 17:20:43 2021 +0100" }, "committer": { "name": "Abdellatif El Khlifi", "email": "abdellatif.elkhlifi@arm.com", "time": "Thu Jul 22 18:01:39 2021 +0100" }, "message": "feat: adding the diphda platform\n\nThis commit enables trusted-firmware-a with Trusted Board Boot support\nfor the Diphda 64-bit platform.\n\nDiphda uses a FIP image located in the flash. The FIP contains the\nfollowing components:\n\n- BL2\n- BL31\n- BL32\n- BL32 SPMC manifest\n- BL33\n- The TBB certificates\n\nThe board boot relies on CoT (chain of trust). The trusted-firmware-a\nBL2 is extracted from the FIP and verified by the Secure Enclave\nprocessor. BL2 verification relies on the signature area at the\nbeginning of the BL2 image. This area is needed by the SecureEnclave\nbootloader.\n\nThen, the application processor is released from reset and starts by\nexecuting BL2.\n\nBL2 performs the actions described in the trusted-firmware-a TBB design\ndocument.\n\nSigned-off-by: Rui Miguel Silva \u003crui.silva@arm.com\u003e\nSigned-off-by: Abdellatif El Khlifi \u003cabdellatif.elkhlifi@arm.com\u003e\nChange-Id: Iddb1cb9c2a0324a9635e23821c210ac81dfc305d\n" } ], "next": "52eb322919017b4230fb0f9580020375db56466b" }