)]}' { "log": [ { "commit": "15ca2c5e14abe415e70d08fb595973dd3e3b0af9", "tree": "64787d168d0246f2d4d82dc1f8a8f3db60f41541", "parents": [ "e1c018e8072385414c1cd120d3c474ac0228992b" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 19 14:15:48 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 19 15:13:18 2022 +0100" }, "message": "fix(st-ddr): add missing debug.h\n\nIn a later patch, the stm32mp1_def.h will be reworked. The inclusion\nof common/debug.h may not be done there through another included file.\nAdd this header inclusion in the files that need it.\n\nChange-Id: I83687f7910032ca38c0856796580a650e1e41a68\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "e1c018e8072385414c1cd120d3c474ac0228992b", "tree": "15b2168a985caf2875918ae465d4e81a71116100", "parents": [ "1c87d60b55097eeb3f0c8e3e77c74ebc43023f06", "32d5042204e8b41caa4c0c1ed5b48bad9f1cb1b5" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jan 19 12:02:33 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 19 12:02:33 2022 +0100" }, "message": "Merge \"fix(imx8mp): change the BL31 physical load address\" into integration" }, { "commit": "1c87d60b55097eeb3f0c8e3e77c74ebc43023f06", "tree": "04cc2ea6855be55ae646406194bfd9074e41d48d", "parents": [ "97c911478718ac6e789b3a863970ed80e18be9e5", "8bbb1d80a58dbdf96fcabbdebbfbd21d2d5344a4" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Mon Jan 17 18:37:53 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 17 18:37:53 2022 +0100" }, "message": "Merge \"feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1\" into integration" }, { "commit": "97c911478718ac6e789b3a863970ed80e18be9e5", "tree": "42dca2acc5f72ad92bb9ad470e6d00220ba3d71e", "parents": [ "1f4adc3a34f80249d40bfc7033a65f4217d7ee04", "d958d10eb360024e15f3c921dc3863a0cee98830" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jan 13 23:10:48 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 13 23:10:48 2022 +0100" }, "message": "Merge changes from topic \"st_mapping_update\" into integration\n\n* changes:\n feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections\n refactor(stm32mp1): reduce MMU memory regions and split XLAT by context\n feat(st): map 2MB for ROM code\n fix(stm32mp1): restrict DEVICE2 mapping in BL2\n" }, { "commit": "1f4adc3a34f80249d40bfc7033a65f4217d7ee04", "tree": "ba13ba0e6a1eb212f690d0af441e3676e1cfecc1", "parents": [ "e537bcdedb16907ecab911e851c1dc4f35411b49", "635e6b108e773daf37c00f46e6fbb1cae4e78f96" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jan 13 18:30:49 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 13 18:30:49 2022 +0100" }, "message": "Merge changes I52b241b2,I25b4b97c into integration\n\n* changes:\n feat(mt8186): add Vcore DVFS driver\n feat(mt8186): add SPM suspend driver\n" }, { "commit": "8bbb1d80a58dbdf96fcabbdebbfbd21d2d5344a4", "tree": "ee9d7fb1729d3ad2bd194599afe32b36788459d7", "parents": [ "e537bcdedb16907ecab911e851c1dc4f35411b49" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Oct 21 15:02:08 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 13 18:00:46 2022 +0800" }, "message": "feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1\n\nAdd L1PCTL field definiton in register CPUACTLR_EL1.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: Iebfb240ac58aa8f3dc870804bf4390dfbdfa9b95\n" }, { "commit": "635e6b108e773daf37c00f46e6fbb1cae4e78f96", "tree": "ba13ba0e6a1eb212f690d0af441e3676e1cfecc1", "parents": [ "7ac6a76c47d429778723aa804b64c48220a10f11" ], "author": { "name": "jason-ch chen", "email": "jason-ch.chen@mediatek.corp-partner.google.com", "time": "Tue Nov 16 10:18:46 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Thu Jan 13 10:11:39 2022 +0800" }, "message": "feat(mt8186): add Vcore DVFS driver\n\nAdd Vcore DVFS to SPM driver.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Jason-ch Chen \u003cjason-ch.chen@mediatek.com\u003e\nChange-Id: I52b241b2cdb792be74390cbaa09a728ddbe6593a\n" }, { "commit": "7ac6a76c47d429778723aa804b64c48220a10f11", "tree": "0abed8ab9ba4c18bc81ca3f5ccf66c86ea7b5268", "parents": [ "e537bcdedb16907ecab911e851c1dc4f35411b49" ], "author": { "name": "jason-ch chen", "email": "jason-ch.chen@mediatek.corp-partner.google.com", "time": "Tue Nov 16 09:48:20 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Thu Jan 13 10:10:56 2022 +0800" }, "message": "feat(mt8186): add SPM suspend driver\n\nAdd SPM suspend driver for suspend/resume features.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Jason-ch Chen \u003cjason-ch.chen@mediatek.com\u003e\nChange-Id: I25b4b97cd3138a7b347385539e47ccfa884d64fc\n" }, { "commit": "d958d10eb360024e15f3c921dc3863a0cee98830", "tree": "570d836fd4b914941a1a7acbf052b04dac8e4a51", "parents": [ "ac1b24d58a391cfe1d79a93f1012da3d278d2d56" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Sep 15 11:30:25 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 12 09:21:14 2022 +0100" }, "message": "feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections\n\nBecause the BL2 is not relocated, the usage of BL2_IN_XIP_MEM\ncan be used. It reduces the binary size by removing all relocation\nsections. XIP will not be used when STM32MP_USE_STM32IMAGE is\ndefined. Introduce new definitions for SEPARATE_CODE_AND_RODATA.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nChange-Id: Ifd76f14e5bc98990bf84e0bfd4ee0b4e49a9a293\n" }, { "commit": "ac1b24d58a391cfe1d79a93f1012da3d278d2d56", "tree": "4105c9323bec065aaa5ac6541f78e7f530a3e34d", "parents": [ "1697ad8cc81307972d31cec3b27d58f589eeeb3f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Jan 16 18:50:51 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 12 09:21:14 2022 +0100" }, "message": "refactor(stm32mp1): reduce MMU memory regions and split XLAT by context\n\nSimplify the BL2 MMU mapping and reduce the memory regions\nnumber. Split the XLAT define between BL2 and BL32 as binaries\ndo not share the same tables anymore.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nChange-Id: Iaf09e72b4cc29acbe376f6f1cd2a8116c793ba26\n" }, { "commit": "1697ad8cc81307972d31cec3b27d58f589eeeb3f", "tree": "3cf544f3a9d8e5a6faf352c8458c8ae3754fda2d", "parents": [ "db3e0ece7157181a3529d14172368003eb63dc30" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Sep 15 15:12:57 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 12 09:21:14 2022 +0100" }, "message": "feat(st): map 2MB for ROM code\n\nThis allows reducing MMU tables, and as there is nothing after ROM code\nin memory mapping, this has no impact.\n\nChange-Id: If51facb96a523770465cb06eb1ab400f75d26db3\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "db3e0ece7157181a3529d14172368003eb63dc30", "tree": "7ccee499b4982f67ea3f9d010ed4c590b92d48e9", "parents": [ "e537bcdedb16907ecab911e851c1dc4f35411b49" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 17 11:38:09 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 12 09:21:14 2022 +0100" }, "message": "fix(stm32mp1): restrict DEVICE2 mapping in BL2\n\nOnly NAND memory map area can be of interest for BL2 in the\nDEVICE2 area. Map DEVICE2 under STM32MP_RAW_NAND flag.\n\nChange-Id: I7e3b39579e4a2525b25cb1987d6ec38038d0de2b\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "32d5042204e8b41caa4c0c1ed5b48bad9f1cb1b5", "tree": "e0d5a4ca58658b6e50abae84050331af601af166", "parents": [ "e537bcdedb16907ecab911e851c1dc4f35411b49" ], "author": { "name": "Ying-Chun Liu (PaulLiu)", "email": "paul.liu@linaro.org", "time": "Wed Dec 15 16:03:17 2021 +0800" }, "committer": { "name": "Ying-Chun Liu (PaulLiu)", "email": "paulliu@debian.org", "time": "Wed Jan 12 10:33:27 2022 +0800" }, "message": "fix(imx8mp): change the BL31 physical load address\n\nChange BL31 load address to 0x970000. This was done by Change-Id\nI96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.\nHowever, 0x970000 is the correct value thus we change it back again.\n\nSigned-off-by: Ying-Chun Liu (PaulLiu) \u003cpaul.liu@linaro.org\u003e\nChange-Id: Ia0db4877123b89072f723d18e2bcce25ef38f47d\n" }, { "commit": "e537bcdedb16907ecab911e851c1dc4f35411b49", "tree": "be79865e5c3db9781c6aa6e969091aa3dda8f1a3", "parents": [ "f7a92518f66d5b5aa51f9effad0494b1a2405a8f", "c21a736d6f3fa9fb0647bff404b0174ebf1acd91" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 11 00:25:01 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 11 00:25:01 2022 +0100" }, "message": "Merge \"feat(mt8195): apply erratas of CA78 for MT8195\" into integration" }, { "commit": "f7a92518f66d5b5aa51f9effad0494b1a2405a8f", "tree": "c0cb9f520611ba1aa8a3ba957ca6ef637bb3ebd8", "parents": [ "32de790f02dc440cac78af688154c72328b05af0", "63d215984691e8b2de46e7b725ca2abf7f8ae304" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jan 07 17:24:54 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 07 17:24:54 2022 +0100" }, "message": "Merge changes from topic \"st_ddr_updates\" into integration\n\n* changes:\n refactor(st-ddr): move basic tests in a dedicated file\n refactor(st-ddr): reorganize generic and specific elements\n feat(stm32mp1): allow configuration of DDR AXI ports number\n refactor(st-ddr): update parameter array initialization\n feat(st-ddr): add read valid training support\n refactor(stm32mp1): remove the support of calibration result\n fix(st-ddr): correct DDR warnings\n" }, { "commit": "32de790f02dc440cac78af688154c72328b05af0", "tree": "31c1819563d4ee1741c795aacec6ac2bced2093b", "parents": [ "4230998741c2f2e41348c73ac0fd052d27ced223", "9e52d45fdf619561e0a7a833b77aaacc947a4dfd" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jan 07 17:09:53 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 07 17:09:53 2022 +0100" }, "message": "Merge \"fix(st): manage UART clock and reset only in BL2\" into integration" }, { "commit": "4230998741c2f2e41348c73ac0fd052d27ced223", "tree": "bb3383e8661f69d7043f8ecfdf5eb49dd288ac42", "parents": [ "cbbcf9b1185d127a97ca3b6a6f3463de69db33c8", "f2b2cc146e5be18daef3ae9752699e9422f7070d" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Thu Jan 06 19:14:29 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 06 19:14:29 2022 +0100" }, "message": "Merge changes Icf5e3045,Ie5fb0b72 into integration\n\n* changes:\n docs(allwinner): update SoC list and build options\n docs(allwinner): add SUNXI_SETUP_REGULATORS build option\n" }, { "commit": "cbbcf9b1185d127a97ca3b6a6f3463de69db33c8", "tree": "13e0b69926150648d241df5f462b1ef9de140339", "parents": [ "5b0962833a9aabe14e4dcf9ba33b0551e8cd8365", "f94c84baa2a2bad75397b0ec6a0922fe8a475847" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 06 12:01:41 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 06 12:01:41 2022 +0100" }, "message": "Merge changes Ifea8148e,I73559522 into integration\n\n* changes:\n fix(morello): include errata workaround for 1868343\n fix(errata): workaround for Rainier erratum 1868343\n" }, { "commit": "9e52d45fdf619561e0a7a833b77aaacc947a4dfd", "tree": "7afd751466ca6eb9b61a8b9ea9aa9b0a10d82713", "parents": [ "5b0962833a9aabe14e4dcf9ba33b0551e8cd8365" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Jan 05 18:02:46 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 18:54:59 2022 +0100" }, "message": "fix(st): manage UART clock and reset only in BL2\n\nAs the UART is already initialized, no need to check for UART clock\nor reset in next BL. An issue can appear if the next BL device tree\n(e.g HW_CONFIG) doesn\u0027t use the same clocks or resets (like SCMI ones).\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I044ef2386abe2d3dba5a53c3685440d64ca50a4f\n" }, { "commit": "f94c84baa2a2bad75397b0ec6a0922fe8a475847", "tree": "d9fd52a4257ce31a6a8c0bef4f18dc0e5343e317", "parents": [ "a72144fb7a30c2782a583a3b0064e741d1fe2c9f" ], "author": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Wed Jan 05 14:38:44 2022 +0000" }, "committer": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Wed Jan 05 17:16:42 2022 +0000" }, "message": "fix(morello): include errata workaround for 1868343\n\nThis patch includes the errata workaround for erratum\n1868343 for the Morello platform.\n\nSigned-off-by: Manoj Kumar \u003cmanoj.kumar3@arm.com\u003e\nChange-Id: Ifea8148e10946db2276560f90bf2f32bf12b9dcc\n" }, { "commit": "a72144fb7a30c2782a583a3b0064e741d1fe2c9f", "tree": "4d5b7cad399a3303e7a26a97edefd51dcabd7b00", "parents": [ "f8183f4df15dcebfbd974c1609c7c2bffa47e4e5" ], "author": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Wed Jan 05 14:33:52 2022 +0000" }, "committer": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Wed Jan 05 17:16:19 2022 +0000" }, "message": "fix(errata): workaround for Rainier erratum 1868343\n\nRainier CPU is based on Neoverse N1 R4P0 version which exhibits\nthe erratum 1868343. This patch inherits the workaround from\nneoverse_n1.S file into rainier.S file for erratum 1868343.\n\nSigned-off-by: Manoj Kumar \u003cmanoj.kumar3@arm.com\u003e\nChange-Id: I735595229716a77d26369943086de08384cafa70\n" }, { "commit": "5b0962833a9aabe14e4dcf9ba33b0551e8cd8365", "tree": "54cb0bb1765ad1a7cac1e1cd5bbef2d4cc929935", "parents": [ "f8183f4df15dcebfbd974c1609c7c2bffa47e4e5", "14d9727e334300b3f5f57e76a9f6e21431e6c6b5" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jan 05 17:28:13 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 05 17:28:13 2022 +0100" }, "message": "Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration\n\n* changes:\n feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3\n feat(plat/rcar3): modify type for Internal function argument\n feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53\n fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53\n" }, { "commit": "f8183f4df15dcebfbd974c1609c7c2bffa47e4e5", "tree": "989dd1877799870c3a511fefaabf1b24fde04d3a", "parents": [ "64fc535972e6ac7b1b6df842689065139942fb89", "c5ee8588bf9a36075723e5aacceefa93fd2de8c9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jan 05 12:08:14 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 05 12:08:14 2022 +0100" }, "message": "Merge \"fix(ufs): delete call to inv_dcache_range for utrd\" into integration" }, { "commit": "63d215984691e8b2de46e7b725ca2abf7f8ae304", "tree": "d9408971155a6f0b1136056dd977bf32b248efac", "parents": [ "06e55dc8424277f7d6325949c4cd6ebe7fabb173" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@foss.st.com", "time": "Tue Mar 02 11:19:36 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 11:47:46 2022 +0100" }, "message": "refactor(st-ddr): move basic tests in a dedicated file\n\nThese basic tests are generic and should be used independently of the\ndriver, depending on the plaftorm characteristics.\n\nChange-Id: I38161b659ef2a23fd30a56e1c9b1bd98461a2fe4\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@foss.st.com\u003e\n" }, { "commit": "06e55dc8424277f7d6325949c4cd6ebe7fabb173", "tree": "6d60ff7ed6f316ea44212e0b75e260738f1eba22", "parents": [ "88f4fb8fa759b1761954067346ee674b454bdfde" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Tue May 18 10:01:30 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 11:09:59 2022 +0100" }, "message": "refactor(st-ddr): reorganize generic and specific elements\n\nstm32mp_ddrctl structure contains DDRCTRL registers definitions.\nstm32mp_ddr_info contains general DDR information extracted from DT.\nstm32mp_ddr_size moves to the generic side.\nstm32mp1_ddr_priv contains platform private data.\n\nstm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to\nretrieve data from DT. They are located in new generic c/h files in\nwhich stm32mp_ddr_param structure is declared. Platform makefile\nis updated.\n\nAdapt driver with this new classification.\n\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\nChange-Id: I4187376c9fff1a30e7a94407d188391547107997\n" }, { "commit": "88f4fb8fa759b1761954067346ee674b454bdfde", "tree": "1df70dde8b9a05d90e07b0b32d169dfe83940b0c", "parents": [ "ba7d2e2698c42df85b5c32d5b49008870da43bc6" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 17 12:42:46 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 11:09:59 2022 +0100" }, "message": "feat(stm32mp1): allow configuration of DDR AXI ports number\n\nA new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.\nIt will allow choosing single or dual AXI ports for DDR.\n\nChange-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "ba7d2e2698c42df85b5c32d5b49008870da43bc6", "tree": "e8330c36e6c8d57a05ed0281c972a9839f3f5a10", "parents": [ "5def13eb01ebac5656031bdc388a215d012fdaf8" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 25 13:44:27 2019 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 11:09:59 2022 +0100" }, "message": "refactor(st-ddr): update parameter array initialization\n\nForce alignment of the size of parameters array with the expected\nvalue by the binding.\nThe registers dynamic structs are removed as not used in TF-A.\n\nChange-Id: I7a41f355a435f54fbf23f468cca87c7f8f7e69e8\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "5def13eb01ebac5656031bdc388a215d012fdaf8", "tree": "aaace281a4ffdfb37ee2a36d7eecc56234fdf7a0", "parents": [ "26cf5cf6d62eae599a9173217a221bf552b4cc06" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Fri Sep 10 12:03:38 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 11:09:59 2022 +0100" }, "message": "feat(st-ddr): add read valid training support\n\nAdd the read data eye training \u003d training for optimal read valid placement\n(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.\n\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\nChange-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2\n" }, { "commit": "26cf5cf6d62eae599a9173217a221bf552b4cc06", "tree": "6b8d37b48379f5a67962ac95e3d24587604fc2db", "parents": [ "a078134e2305ca5695731bc275a5ca892cc38880" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Fri Apr 30 17:31:52 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 11:09:59 2022 +0100" }, "message": "refactor(stm32mp1): remove the support of calibration result\n\nThe support of a predefined DDR PHY tuning result is removed for\nSTM32MP1 driver because it is not needed at the supported frequency\nwhen built-in calibration is executed.\n\nThe calibration parameters were provided in the device tree by the\noptional node \"st,phy-cal\", activated in ddr helper file by the\ncompilation flag DDR_PHY_CAL_SKIP and filled with values generated\nby CubeMX.\n\nThis patch\n- updates the binding file to remove \"st,phy-cal\" support\n- updates the device trees and remove the associated defines\n- simplifies the STM32MP1 DDR driver and remove the support of\n the optional \"st,phy-cal\"\n\nAfter this patch the built-in calibration is always executed.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\nChange-Id: I3fc445520c259f7f05730aefc25e64b328bf7159\n" }, { "commit": "c21a736d6f3fa9fb0647bff404b0174ebf1acd91", "tree": "de0a5111ee2c9a8301a37d76b6765ab7fb7edeeb", "parents": [ "64fc535972e6ac7b1b6df842689065139942fb89" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Jan 05 14:51:57 2022 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Jan 05 17:10:44 2022 +0800" }, "message": "feat(mt8195): apply erratas of CA78 for MT8195\n\nMT8195 uses Cortex A78 CPU, so we apply these erratas.\n\nTEST\u003dbuild pass\nBUG\u003dnone\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I5ce3d5c490a12226bff4eb5a2d55687da0f74f0e\n" }, { "commit": "a078134e2305ca5695731bc275a5ca892cc38880", "tree": "4b97444ca25886aa76f58217f98449657b203b4b", "parents": [ "64fc535972e6ac7b1b6df842689065139942fb89" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:07:35 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 05 09:19:05 2022 +0100" }, "message": "fix(st-ddr): correct DDR warnings\n\nReplace %d with %u in logs, to avoid warning when\n-Wformat-signedness is enabled.\nAnd correct the order of includes.\n\nChange-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "64fc535972e6ac7b1b6df842689065139942fb89", "tree": "d318f7f7fd117ea2b766a46255d93d810ae9e936", "parents": [ "9b75d94718ad59069672fd260df95b1b5ba45227", "ab45305062f50f81e5c3f800ef4c6cef5097cb04" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 04 20:10:25 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 04 20:10:25 2022 +0100" }, "message": "Merge \"feat(plat/mediatek/mt8195): improve SPM wakeup log\" into integration" }, { "commit": "9b75d94718ad59069672fd260df95b1b5ba45227", "tree": "8dc734ccd572da4f7d0f22a951fdd938af175bb7", "parents": [ "0ac23de9ce7cd5630dd55f3f8b4613faa021547e", "21cfa4531a76a7c3cad00e874400b97e2f68723c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jan 04 18:46:59 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 04 18:46:59 2022 +0100" }, "message": "Merge changes from topic \"st_fixes\" into integration\n\n* changes:\n fix(stm32mp1): do not reopen debug features\n refactor(stm32mp1): improve DGBMCU driver\n fix(stm32mp1): set reset pulse duration to 31ms\n" }, { "commit": "0ac23de9ce7cd5630dd55f3f8b4613faa021547e", "tree": "41e5dee547bf4b4c6078e5a9241ac66c7a32515a", "parents": [ "040b6f99dc8ca34f920fcbfb95011f18f36c7675", "9565962c37e1bb241a793f3fa27be7d971f90f54" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jan 04 18:26:57 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 04 18:26:57 2022 +0100" }, "message": "Merge \"refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication\" into integration" }, { "commit": "040b6f99dc8ca34f920fcbfb95011f18f36c7675", "tree": "15840ae329073d890c95786c7cc17e23dbdc7953", "parents": [ "e752fa4a4c01ad9a0196033a524b3da7c9697b1b", "d50e7a71cb5f8ecfbe2eb69c163d532bab82cbf0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jan 04 16:36:45 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 04 16:36:45 2022 +0100" }, "message": "Merge \"fix(st-sdmmc2): check regulator enable/disable return\" into integration" }, { "commit": "9565962c37e1bb241a793f3fa27be7d971f90f54", "tree": "8b971f751594880442ac8ea75866813a678aebc7", "parents": [ "e752fa4a4c01ad9a0196033a524b3da7c9697b1b" ], "author": { "name": "Jona Stubbe", "email": "tf-a@jona-stubbe.de", "time": "Tue Dec 22 13:06:10 2020 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jan 04 15:26:43 2022 +0100" }, "message": "refactor(plat/rockchip/rk3399/drivers/gpio): reduce code duplication\n\nRefactor the GPIO code to use a small lookup table instead of redundant or\nrepetitive code.\n\nSigned-off-by: Jona Stubbe \u003ctf-a@jona-stubbe.de\u003e\nChange-Id: Icf60385095efc1f506e4215d497b60f90e16edfd\nSigned-off-by: Jimmy Brisson \u003cjimmy.brisson@arm.com\u003e\n" }, { "commit": "d50e7a71cb5f8ecfbe2eb69c163d532bab82cbf0", "tree": "15840ae329073d890c95786c7cc17e23dbdc7953", "parents": [ "e752fa4a4c01ad9a0196033a524b3da7c9697b1b" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 04 15:25:04 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 04 15:25:04 2022 +0100" }, "message": "fix(st-sdmmc2): check regulator enable/disable return\n\nThe issue was reported by Coverity [1]. The return of the functions\nregulator_disable() and regulator_enable() was not checked.\nIf they fail, this means there is an issue either with PMIC or I2C.\nThe board should the stop booting with a panic().\n\n[1] https://scan4.scan.coverity.com/reports.htm#v47771/p11439/mergedDefectId\u003d374565\n\nChange-Id: If5dfd5643c210e03ae4b1f4cab0168c0db89f60e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "21cfa4531a76a7c3cad00e874400b97e2f68723c", "tree": "4bc90331c9df1755c82b2373798c1f2d3aba323f", "parents": [ "a24d5947af5921beab566e7f9e9d23e2f9dd9072" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Sep 15 14:49:48 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 04 13:30:53 2022 +0100" }, "message": "fix(stm32mp1): do not reopen debug features\n\nOn closed chips, it is not allowed to open debug. The BSEC debug\nregister can not be rewritten.\nOn open chips, the debug is already open, no need to rewrite this\nregister. This part of code is just removed.\nAn INFO message is displayed if debug is disabled.\nThe freeze of the watchdog during debug is also removed.\nIn case of debug, this must be managed by the software that enables\nthe debugger.\n\nChange-Id: I19fbd3c487bb1018db30fd599cfa94fe5090899f\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "a24d5947af5921beab566e7f9e9d23e2f9dd9072", "tree": "afee9d969c4926fe1d10ca7c25244e764816bff7", "parents": [ "9a73a56c353d32742e03b828647562bdbe2ddbb2" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Thu Sep 19 11:27:24 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 04 13:30:53 2022 +0100" }, "message": "refactor(stm32mp1): improve DGBMCU driver\n\nAdd function headers to improve readability.\nAdd asserts when required.\nUse RCC_BASE address.\n\nChange-Id: Ia545293f00167b6276331a986ea7aa08c006e004\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\n" }, { "commit": "9a73a56c353d32742e03b828647562bdbe2ddbb2", "tree": "2ab176147284214096dd1c3a8fc8a2aee71269da", "parents": [ "c8076a0e696243533b2e8f6673a5600dc90bd638" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Apr 27 18:19:13 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 04 13:30:53 2022 +0100" }, "message": "fix(stm32mp1): set reset pulse duration to 31ms\n\nAccording to ST Application note AN5256 [1], the minimum reset pulse\nduration should be set to 31ms on boards powered with discrete\nregulators.\n\n[1] https://www.st.com/resource/en/application_note/dm00561921.pdf\n\nChange-Id: Ib6ed029ee8a4b95f75a80948fdd2154b4ebe484f\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "e752fa4a4c01ad9a0196033a524b3da7c9697b1b", "tree": "15e5692e4865d4413209e49d08ee7b40f5acf196", "parents": [ "f72827b8428d0927a37dfe8f5176134b8e172d3d", "67412e4d7ae3defaac78ef5e351c63e06cfd907a" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Sat Jan 01 02:16:14 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Jan 01 02:16:14 2022 +0100" }, "message": "Merge \"feat(allwinner): allow to skip PMIC regulator setup\" into integration" }, { "commit": "f72827b8428d0927a37dfe8f5176134b8e172d3d", "tree": "a73ede10b399dd6dec3fa3fded634d1528f4f0df", "parents": [ "a006606f3c79a8835a15e4ba0c46ffc4547c68b7", "bc714bafe7ae8ca29075ba9bf3985c0e15ae0f64" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Dec 30 16:38:40 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Dec 30 16:38:40 2021 +0100" }, "message": "Merge \"fix(mt8186): remove unused files in drivers/mcdi\" into integration" }, { "commit": "bc714bafe7ae8ca29075ba9bf3985c0e15ae0f64", "tree": "a73ede10b399dd6dec3fa3fded634d1528f4f0df", "parents": [ "a006606f3c79a8835a15e4ba0c46ffc4547c68b7" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Thu Dec 30 13:04:29 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Thu Dec 30 17:21:33 2021 +0800" }, "message": "fix(mt8186): remove unused files in drivers/mcdi\n\nWe don\u0027t use mbox drivers which are implemented in these files for\nmcdi, so remove related files from mcdi folder.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: Idea5ebe5b25f91066ebd653cdcdafe65ca292b0f\n" }, { "commit": "c5ee8588bf9a36075723e5aacceefa93fd2de8c9", "tree": "257bca64558ec5ae86863da238d7eebd216bce5a", "parents": [ "c8076a0e696243533b2e8f6673a5600dc90bd638" ], "author": { "name": "Wing Li", "email": "wingers@google.com", "time": "Thu Dec 23 11:32:08 2021 -0800" }, "committer": { "name": "Wing Li", "email": "wingers@google.com", "time": "Tue Dec 28 10:41:14 2021 -0800" }, "message": "fix(ufs): delete call to inv_dcache_range for utrd\n\nThe utrd struct is allocated on the stack by ufs_check_resp\u0027s caller.\nInvalidating the utrd struct is unnecessary since it\u0027s only read from,\nand can cause other values stored on the stack (e.g. link register) to\nbe inadvertently invalidated.\n\nChange-Id: Icd455b52beb2677fafc083d68d0bfa0645b7194b\nSigned-off-by: Wing Li \u003cwingers@google.com\u003e\n" }, { "commit": "f2b2cc146e5be18daef3ae9752699e9422f7070d", "tree": "d01bdebe1a070da038f329fb048e64ae6f95a24f", "parents": [ "aa6169902790c9c027b0123d2b30944501977380" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Dec 27 15:10:49 2021 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Dec 27 15:32:22 2021 +0000" }, "message": "docs(allwinner): update SoC list and build options\n\nOur list of possible Allwinner build targets was missing the newly\nintroduced R329 support. Fix that by adding a table with maps the SoC\nnames to the build target names.\nAlso add some explanation about the recently introduced PSCI power\nmanagement providers.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nChange-Id: Icf5e304562c3082552bf08d7b26904caf9074936\n" }, { "commit": "67412e4d7ae3defaac78ef5e351c63e06cfd907a", "tree": "90ccebac4ed0552100bf29d16bc2745f42b23939", "parents": [ "c8076a0e696243533b2e8f6673a5600dc90bd638" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Nov 01 00:17:37 2021 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Dec 27 15:32:22 2021 +0000" }, "message": "feat(allwinner): allow to skip PMIC regulator setup\n\nFor somewhat historical reasons we are doing some initial PMIC regulator\nsetup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked\nfine so far, but there is at least one board (OrangePi 3) that gets upset,\nbecause the Ethernet PHY needs some *coordinated* bringup of *two*\nregulators.\n\nTo avoid custom hacks, let\u0027s introduce a build option to keep doing the\nregulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break\nsupport for some devices on some boards in U-Boot (Ethernet and HDMI),\nbut will allow to bring up the OrangePi 3 in Linux correctly. We keep\nthe default at 1 to not change the behaviour for all other boards.\n\nAfter U-Boot gained proper PMIC support at some point in the future, we\nwill probably change the default to 0, to get rid of the less optimal\nPMIC code in TF-A.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nChange-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7\n" }, { "commit": "aa6169902790c9c027b0123d2b30944501977380", "tree": "a42db9079b79160f34ddaa382cdc24fe6b8ba75a", "parents": [ "67412e4d7ae3defaac78ef5e351c63e06cfd907a" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Dec 27 15:09:53 2021 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Dec 27 15:32:22 2021 +0000" }, "message": "docs(allwinner): add SUNXI_SETUP_REGULATORS build option\n\nDocument the newly introduced SUNXI_SETUP_REGULATORS build option, that\nallows to disable PMIC regulator setup at build time.\n\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\nChange-Id: Ie5fb0b7220426b67cfffc95df4cabb31a6ec174a\n" }, { "commit": "a006606f3c79a8835a15e4ba0c46ffc4547c68b7", "tree": "e48a0929487fd40d8533741e31d100929beec661", "parents": [ "93b153b5bf3f76d482257a52b7a082b8c42f35d0", "d0ec1cc437c59e64ecba44710dbce82a04ff892d" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Dec 24 11:26:32 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 24 11:26:32 2021 +0100" }, "message": "Merge \"feat(ccidx): update the do_dcsw_op function to support FEAT_CCIDX\" into integration" }, { "commit": "93b153b5bf3f76d482257a52b7a082b8c42f35d0", "tree": "fd7fc91ac5fc5e15ac4bfb2e3a1468ad12e02bd6", "parents": [ "91a8bd660a7b560def28f1a220c2b975bd27571e", "258bef913aa76ead1b10c257d1695d9c0ef1c79d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Dec 24 00:13:50 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 24 00:13:50 2021 +0100" }, "message": "Merge changes from topic \"st_regulator\" into integration\n\n* changes:\n feat(st-sdmmc2): manage cards power cycle\n feat(stm32mp1): register fixed regulator\n feat(st-drivers): introduce fixed regulator driver\n refactor(st): update CPU and VDD voltage get\n refactor(stm32mp1-fdts): update regulator description\n refactor(st-pmic): use regulator framework for DDR init\n feat(st-pmic): register the PMIC to regulator framework\n refactor(st-pmic): split initialize_pmic()\n feat(stm32mp1): add regulator framework compilation\n feat(regulator): add a regulator framework\n feat(stpmic1): add new services\n feat(stpmic1): add USB OTG regulators\n refactor(st-pmic): improve driver usage\n refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean\n refactor(stm32mp1): re-order drivers init\n" }, { "commit": "91a8bd660a7b560def28f1a220c2b975bd27571e", "tree": "febf43b9a152f177fd51517a003e1dfbbd7536d1", "parents": [ "dd14d0f63f7d049cbcbfd3f8128f05e9a351bbe5", "24ab2c0af74be174acf755a36b3ebba867184e60" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 23:57:16 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 23:57:16 2021 +0100" }, "message": "Merge \"fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32\" into integration" }, { "commit": "dd14d0f63f7d049cbcbfd3f8128f05e9a351bbe5", "tree": "6d3046db1545d43da8706163be6e7abc27f5127c", "parents": [ "9697e4596c700f04e5c17a75e7224795bd70d3a2", "0a956f81805b46b1530f30dd79d16950dc491a7b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 22:24:44 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 22:24:44 2021 +0100" }, "message": "Merge \"fix(fiptool): respect OPENSSL_DIR\" into integration" }, { "commit": "9697e4596c700f04e5c17a75e7224795bd70d3a2", "tree": "f9211a3fd897531f13f63063231cc687edece134", "parents": [ "b3c410154153e423231fa9335d37108e029c4d36", "00e8113145aa12d89db72068bdd3157f08575d14" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Dec 22 21:13:03 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 21:13:03 2021 +0100" }, "message": "Merge \"fix(trp): Distinguish between cold and warm boot\" into integration" }, { "commit": "b3c410154153e423231fa9335d37108e029c4d36", "tree": "34136e909404cd55e5a9703e29782ea61c26a634", "parents": [ "0ca4b4b79edc898314cd6dbc7dde0f5f450e7517", "2c791499c26b40c31ce7f68c3bf0dca777fc62de" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 19:18:15 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 19:18:15 2021 +0100" }, "message": "Merge changes from topic \"uart1_console\" into integration\n\n* changes:\n feat(versal): add UART1 as console\n feat(zynqmp): add uart1 as console\n" }, { "commit": "0ca4b4b79edc898314cd6dbc7dde0f5f450e7517", "tree": "ce7e56906302def6002e6737826388c0b62a77e1", "parents": [ "ed780b0b40d5fe0dffffd277de835425f3064f78", "33667d299bd5398ca549f542345e0f321b483d17" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 19:17:57 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 19:17:57 2021 +0100" }, "message": "Merge changes from topic \"clock_framework\" into integration\n\n* changes:\n feat(st): use newly introduced clock framework\n feat(clk): add a minimal clock framework\n" }, { "commit": "ed780b0b40d5fe0dffffd277de835425f3064f78", "tree": "daa29c54aa1090381ec138c30d328bd97e5af9f6", "parents": [ "d76346b9406c5afd1b4567d1c98167e03390bed6", "24dd5a7b71544c503446e58cb23c0cfd09245a3c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 19:16:55 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 19:16:55 2021 +0100" }, "message": "Merge changes I41001484,Ic734696a,I84741535,I85aaaf3a,Ibd5423b7, ... into integration\n\n* changes:\n feat(plat/mediatek/mt8186): add reboot function for PSCI\n feat(plat/mdeiatek/mt8186): add power-off function for PSCI\n feat(plat/mediatek/mt8186): apply erratas for MT8186\n feat(plat/mediatek/mt8186): add MCDI drivers\n feat(plat/mediatek/mt8186): add CPU hotplug\n feat(plat/mediatek/mt8186): add RTC drivers\n fix(plat/mediatek/mt8186): extend MMU region size\n feat(plat/mediatek/mt8186): add DCM driver\n feat(plat/mediatek/mt8186): add pinctrl support\n feat(plat/mediatek/mt8186): add sys_cirq support\n feat(plat/mediatek/mt8186): initialize GIC\n feat(plat/mediatek/mt8186): add SiP service\n feat(plat/mediatek/mt8186): add pwrap and pmic driver\n feat(plat/mediatek/mt8186): initialize delay_timer\n feat(plat/mediatek/mt8186): initialize systimer\n feat(plat/mediatek/mt8186): add EMI MPU basic driver\n" }, { "commit": "d76346b9406c5afd1b4567d1c98167e03390bed6", "tree": "7ecce9cc8d9c174df894ad586b4c77051c9d776b", "parents": [ "b48121b6fd1d24a0842d61e79191d766eb696c11", "ab556c9c646f1b5f1b500449a5813a4eecdc0302" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 15:32:14 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 15:32:14 2021 +0100" }, "message": "Merge \"fix(fiptool): avoid packing the zero size images in the FIP\" into integration" }, { "commit": "b48121b6fd1d24a0842d61e79191d766eb696c11", "tree": "e9f2906b215f89d1a35476861572dcf743fcad0c", "parents": [ "47833abd7772a49aa1b591392584549fb5a2c28f", "e16045de50e8b430e6601ba0e1e47097d8310f3d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Dec 22 15:23:00 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 15:23:00 2021 +0100" }, "message": "Merge \"fix(errata): workaround for Cortex X2 erratum 2058056\" into integration" }, { "commit": "258bef913aa76ead1b10c257d1695d9c0ef1c79d", "tree": "7ff31330893d7ee9506118fbc4e732dad94cf7e7", "parents": [ "967a8e63c33822680e3a4631430dcd9a4a64becd" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 10 16:01:34 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(st-sdmmc2): manage cards power cycle\n\nTo correctly initialize the MMC devices, a power cycle is required.\nFor this we need to:\n- disable vmmc-supply regulator\n- make the power cycle required for SDMMC2 peripheral\n- enable regulators\n\nChange-Id: I2be6d9082d1cc4c864a82cf2c31ff8522e2d31a2\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "967a8e63c33822680e3a4631430dcd9a4a64becd", "tree": "05051230c4359da45e470b25be61f25c131406d0", "parents": [ "5d6a2646f7759a5a2b3daed0d8aef4588c552ba4" ], "author": { "name": "Pascal Paillet", "email": "p.paillet@st.com", "time": "Fri Jan 29 14:48:49 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(stm32mp1): register fixed regulator\n\nRegister fixed regulator in BL2.\n\nChange-Id: I24292f549b2cd24fb717fbb68eb95af7aa68e3b9\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "5d6a2646f7759a5a2b3daed0d8aef4588c552ba4", "tree": "8b1a66d645a01d6331c8d922477bdf357924f19c", "parents": [ "c39c658e75d98d10eefcc6a58055cc8937cfce4f" ], "author": { "name": "Pascal Paillet", "email": "p.paillet@st.com", "time": "Wed Jan 20 17:09:10 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(st-drivers): introduce fixed regulator driver\n\nFixed regulator is mainly used when no pmic is available\n\nChange-Id: Ib6a998684bcb055ba95a093bee563372d9051474\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\n" }, { "commit": "c39c658e75d98d10eefcc6a58055cc8937cfce4f", "tree": "5d01a8e073de4fbcd7a9dfbe2901947bb857d326", "parents": [ "67d95409baaeafed238ce617b7c16a4bf27b5fe2" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Sep 17 16:08:12 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(st): update CPU and VDD voltage get\n\nUse regulator framework to get CPU and VDD power supplies.\n\nChange-Id: Ice745fb21ff10e71ef811e747165499c2e19253e\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "67d95409baaeafed238ce617b7c16a4bf27b5fe2", "tree": "7e77b1ddac84129de92cb72bd1f3de54f552706d", "parents": [ "0ba71ac90149e91db5a3ebb8f82a0ab320b6067a" ], "author": { "name": "Pascal Paillet", "email": "p.paillet@st.com", "time": "Thu Jan 07 18:05:46 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(stm32mp1-fdts): update regulator description\n\nUpdate regulator description to match with pmic driver updates.\nvref_ddr does not support over-current protection.\nvtt_ddr is set to sink source mode.\n\nChange-Id: I725f35b091ca8c230994c2b5f81693ebc97bf4aa\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "0ba71ac90149e91db5a3ebb8f82a0ab320b6067a", "tree": "5efe2c807314599934b38e180198f9df1490f82a", "parents": [ "85fb175b5ef854bc4607db98a4cfb5f35d822cee" ], "author": { "name": "Pascal Paillet", "email": "p.paillet@st.com", "time": "Tue Dec 15 19:05:09 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(st-pmic): use regulator framework for DDR init\n\nUse regulator framework for DDR initialization.\n\nChange-Id: I9dffe499ca12cdc35904de7daf2dda821b267a31\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "85fb175b5ef854bc4607db98a4cfb5f35d822cee", "tree": "29213fb029d4473fa1ac43938547e6c0f75b5ef1", "parents": [ "ae7792e0583f83adc06eb3b14693539e95110490" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Sep 27 14:31:40 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(st-pmic): register the PMIC to regulator framework\n\nRegister the PMIC to the regulator framework.\n\nChange-Id: Ic825a8ef08505316db3dbd5944d62ea907f73c4a\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "ae7792e0583f83adc06eb3b14693539e95110490", "tree": "2c71bf38304638bea7a694144b56f15dd0a98b3b", "parents": [ "bba9fdee589fb9a7aca5963f53b7ce67c30520b3" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Mon Nov 18 13:13:36 2019 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(st-pmic): split initialize_pmic()\n\nprint_pmic_info_and_debug() prints the PMIC version ID and displays\nregulator information if debug is enabled.\nIt is under DEBUG flag and called after initialize_pmic() in BL2.\n\nChange-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\n" }, { "commit": "bba9fdee589fb9a7aca5963f53b7ce67c30520b3", "tree": "23ea12608bae6d6f2a387b42d1201e68f7c3c719", "parents": [ "d5b4a2c4e7fd0bcb9f08584b242e69a2e591fb71" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 15 13:16:15 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(stm32mp1): add regulator framework compilation\n\nAdd required macro PLAT_NB_RDEVS in platform code, and update\nplatform.mk to compile regulator framework.\n\nChange-Id: I9dc7a0a4c4f5a23d9bedda368d407612c9cd21cd\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "d5b4a2c4e7fd0bcb9f08584b242e69a2e591fb71", "tree": "ffbb15e29133206758e0327ce86f1669ee968333", "parents": [ "ea552bf5a57b573a6b09e396e3466b3c4af727f0" ], "author": { "name": "Pascal Paillet", "email": "p.paillet@st.com", "time": "Tue Dec 15 18:26:39 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(regulator): add a regulator framework\n\nAdd a regulator framework to:\n- provide an interface to consumers and drivers,\n- connect consumers with drivers,\n- handle most of devicetree-parsing,\n- handle always-on and boot-on regulators,\n- handle min/max voltages,\n\nChange-Id: I23c939fdef2c71a416c44c9de332f70db0d2aa53\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\n" }, { "commit": "ea552bf5a57b573a6b09e396e3466b3c4af727f0", "tree": "d1729572369c85014333280fa464ca8fb5779213", "parents": [ "13fbfe046e71393961d2c70a4f748a15f9c15f77" ], "author": { "name": "Pascal Paillet", "email": "p.paillet@st.com", "time": "Tue Dec 15 18:28:34 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(stpmic1): add new services\n\nAdd support for ICC, sink mode, bypass mode,\nactive discharge and list voltages.\nHandle LDO3 sink source mode in a different way to avoid\nsetting voltage while in sink source mode.\n\nChange-Id: Ib1b909fd8a153f542917f650e43e24317a570534\nSigned-off-by: Pascal Paillet \u003cp.paillet@st.com\u003e\n" }, { "commit": "13fbfe046e71393961d2c70a4f748a15f9c15f77", "tree": "7d9b76c70d677b79abb60a7db6c2a1b5e0bda60b", "parents": [ "c77c7d9e309b6c27ada533f887baf6506f587c4a" ], "author": { "name": "Etienne Carriere", "email": "etienne.carriere@st.com", "time": "Fri Jan 10 08:31:13 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "feat(stpmic1): add USB OTG regulators\n\nAdd regulators boost, pwr_sw1 and pwr_sw2 regulators related to\nUSB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are\nneeded since manipulated during the suspend/resume power sequence\nas per FDT description for stm32mp15x-xxx boards from\nSTMicroelectronics.\n\nChange-Id: I6217de707e49882bd5a9100db43e0d354908800d\nSigned-off-by: Etienne Carriere \u003cetienne.carriere@st.com\u003e\n" }, { "commit": "c77c7d9e309b6c27ada533f887baf6506f587c4a", "tree": "4f1b9fa482c14ad2514266fb72c5a0a0d1a5ed68", "parents": [ "16e56a75deb30fb18c43a94762a830fc94c71a16" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Fri Nov 15 15:56:06 2019 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(st-pmic): improve driver usage\n\nStore status of dt_pmic_status() as local static variable,\nthis avoids parsing DT several times.\nIn the same way, store nodes in dt_pmic_i2c_config() and\nin dt_get_pmic_node() as local static variables.\n\nChange-Id: I4585e9dfdde2847a369bffcc6f2b39ecc2b74de1\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\n" }, { "commit": "16e56a75deb30fb18c43a94762a830fc94c71a16", "tree": "60ba32dc0b5ebd086ba6e8b3c9e8c221aae628b8", "parents": [ "0c16e7d2fbb99fb546efd5303ec863742d99500e" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Thu Sep 19 11:24:50 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(stpmic1): set stpmic1_is_regulator_enabled() as boolean\n\nImprove use and readability.\n\nChange-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\n" }, { "commit": "0c16e7d2fbb99fb546efd5303ec863742d99500e", "tree": "10db1c45358e9480fc09f9dd1536fe0f6481e494", "parents": [ "47833abd7772a49aa1b591392584549fb5a2c28f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Sep 17 11:54:52 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:04:32 2021 +0100" }, "message": "refactor(stm32mp1): re-order drivers init\n\nSYSCFG can be initialized later, after console is up, to display the\nwarnings or messages it could issue.\nPMIC should be initialized earlier, before SYSCFG init.\n\nChange-Id: Icc3a1366083a1b1fde7f0e173645449b4c04c49b\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "24ab2c0af74be174acf755a36b3ebba867184e60", "tree": "4a3b7767531803d27fbe9b0faf15574c905b9222", "parents": [ "47833abd7772a49aa1b591392584549fb5a2c28f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Nov 19 11:35:46 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 14:03:19 2021 +0100" }, "message": "fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32\n\nWith patch [1], ENABLE_SVE_FOR_NS is always enable.\nDisable it for AARCH32 platforms, as the feature is not supported.\nThe warning message is replaced with an error, and the second override\nis removed.\n\n[1] dc78e62d80e6 (\"feat(sme): enable SME functionality\")\n\nChange-Id: Ic9c5e2612c9e00bd0d37ca3b59537e39270c9799\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "33667d299bd5398ca549f542345e0f321b483d17", "tree": "e4f0175eb1321050e8676a88a248ea0be9e24217", "parents": [ "847c6bc8e6d55b1c0f31a52407aa61515cd6c612" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Aug 30 15:06:54 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 13:08:09 2021 +0100" }, "message": "feat(st): use newly introduced clock framework\n\nReplace calls to stm32mp_clk_enable() / stm32mp_clk_disable() /\nstm32mp_clk_get_rate() with clk_enable() / clk_disable() /\nclk_get_rate().\n\nChange-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111\nSigned-off-by: Gabriel Fernandez \u003cgabriel.fernandez@st.com\u003e\n" }, { "commit": "847c6bc8e6d55b1c0f31a52407aa61515cd6c612", "tree": "578509e25e2e017c8240b1e50e60888f53a9fa0b", "parents": [ "47833abd7772a49aa1b591392584549fb5a2c28f" ], "author": { "name": "Gabriel Fernandez", "email": "gabriel.fernandez@st.com", "time": "Tue Oct 13 09:36:25 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Dec 22 13:07:23 2021 +0100" }, "message": "feat(clk): add a minimal clock framework\n\nThis is mainly a clock interface with clk_ops callbacks.\nThose callbacks are: enable, disable, get_rate, set_parent,\nand is_enabled.\nThis framework is compiled for STM32MP1.\n\nChange-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794\nSigned-off-by: Ludovic Barre \u003cludovic.barre@st.com\u003e\nSigned-off-by: Gabriel Fernandez \u003cgabriel.fernandez@st.com\u003e\n" }, { "commit": "2c791499c26b40c31ce7f68c3bf0dca777fc62de", "tree": "1693b589a81370c3a79cfc69efadda9810d04d78", "parents": [ "ea66e4af0baf5d5b905e72f824a672f16a6e0f98" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Sun Dec 19 21:36:23 2021 -0700" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed Dec 22 03:56:42 2021 -0700" }, "message": "feat(versal): add UART1 as console\n\nCurrently only UART0 is handled as console device, fix the\ncode to support UART1 as console also.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: Ifcd3c331cf6ce4afb0074357c92fc4addb9438b6\n" }, { "commit": "ea66e4af0baf5d5b905e72f824a672f16a6e0f98", "tree": "2208ea8647aef72c0259a034bcbadd752a5d5175", "parents": [ "f480c9c42b26841f7814aea81084d5a7d1605071" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Sun Dec 19 21:32:00 2021 -0700" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed Dec 22 03:56:16 2021 -0700" }, "message": "feat(zynqmp): add uart1 as console\n\nCurrently only UART0 is handled as console device, fix the\ncode to support UART1 as console also.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I08f69b65b78b967ceb7159f4a467aa5982b1f791\n" }, { "commit": "24dd5a7b71544c503446e58cb23c0cfd09245a3c", "tree": "2bb9095aeedbe8cd115ce216be6985af1d7df7fb", "parents": [ "a68346a772859ee6971ec14c6473d2a853e9c66f" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Mon Nov 22 18:14:38 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add reboot function for PSCI\n\nAdd system_reset function in PSCI operations.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I41001484f6244bd6ae7dedcfb6ce71cd6c035a1e\n" }, { "commit": "a68346a772859ee6971ec14c6473d2a853e9c66f", "tree": "eb1d9cac633cfc46bce6f247036177924321172b", "parents": [ "572f8adbb062c36835fbb82944dd2ed772134bfd" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Mon Nov 22 17:55:56 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mdeiatek/mt8186): add power-off function for PSCI\n\nAdd support for system-off.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: Ic734696aab1b71ae85bca6ed08e544a522ce5c95\n" }, { "commit": "572f8adbb062c36835fbb82944dd2ed772134bfd", "tree": "392490a9383e0c30ac1f6d91e2427d6db7a18404", "parents": [ "06cb65ef079941d0525dca75dd0e110e9330906d" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Thu Nov 25 18:55:04 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): apply erratas for MT8186\n\nMT8186 uses Cortex A76 CPU, so we apply these erratas.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I84741535fbe429f664092f624c2da653532204cd\n" }, { "commit": "06cb65ef079941d0525dca75dd0e110e9330906d", "tree": "86432fe86a364114f5815beb941d93fa97caf833", "parents": [ "1da57e54b2270b3b49710afa6fd947b01d61b261" ], "author": { "name": "Garmin.Chang", "email": "Garmin.Chang@mediatek.com", "time": "Sun Nov 14 10:14:45 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add MCDI drivers\n\nAdd MCDI related drivers to handle CPU powered on/off in CPU suspend.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nChange-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748\nSigned-off-by: Garmin.Chang \u003cGarmin.Chang@mediatek.com\u003e\n" }, { "commit": "1da57e54b2270b3b49710afa6fd947b01d61b261", "tree": "b577f0eea1fe4082e7c923679ea7dd5ea5a249e1", "parents": [ "6e5d76bac8786120d037953f5a6fd67aaff035c1" ], "author": { "name": "Garmin.Chang", "email": "Garmin.Chang@mediatek.com", "time": "Mon Nov 08 11:30:40 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add CPU hotplug\n\nImplement PSCI platform operations to support CPU hotplug and MCDI.\n\nTEST\u003dbringup 8 CPUs successfully on kernel stage.\nBUG\u003db:202871018\n\nChange-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510\nSigned-off-by: Garmin.Chang \u003cGarmin.Chang@mediatek.com\u003e\n" }, { "commit": "6e5d76bac8786120d037953f5a6fd67aaff035c1", "tree": "b6d25edc21e6de7e3b54a9226ad32874193cb77a", "parents": [ "0fe7ae9c64aa6f6d5b06a80de9c88081057d5dbe" ], "author": { "name": "Yuchen Huang", "email": "yuchen.huang@mediatek.corp-partner.google.com", "time": "Fri Nov 12 16:56:33 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add RTC drivers\n\nAdd RTC drivers for EOSC calibration.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Yuchen Huang \u003cyuchen.huang@mediatek.corp-partner.google.com\u003e\nChange-Id: Ib48c07204c4a614072ba710c042794b59e8a902a\n" }, { "commit": "0fe7ae9c64aa6f6d5b06a80de9c88081057d5dbe", "tree": "f65677e31d7efd8166529e8a9890c5997dc6844d", "parents": [ "95ea87ffc2445c77f070e6a2f78ffa424810faed" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Tue Nov 09 13:12:03 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "fix(plat/mediatek/mt8186): extend MMU region size\n\nIn mt8186 suspend/resume flow, ATF has to communicate with a subsys by\nread/write the subsys registers. However, the register region of subsys\ndoesn\u0027t include in the MMU mapping region. It triggers MMU faults.\n\nThis patch extends the MMU region 0 size to cover all mt8186 HW modules.\nThis patch also remove MMU region 1 because region 0 covers region 1.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I520c51338578bd68756cd02603ce6783f93daf51\n" }, { "commit": "95ea87ffc2445c77f070e6a2f78ffa424810faed", "tree": "117ab2bbd91c6a78647953b4322145088fc3714b", "parents": [ "af5a0c40aff21c4b8771365f19dcb01d6086b30d" ], "author": { "name": "Edward-JW Yang", "email": "edward-jw.yang@mediatek.corp-partner.google.com", "time": "Mon Nov 01 20:20:18 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add DCM driver\n\nDCM means dynamic clock management, and it can dynamically\nslow down or gate clocks during CPU or bus idle.\n\n1. Add MCUSYS related DCM drivers.\n2. Enable MCUSYS related DCM by default.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Edward-JW Yang \u003cedward-jw.yang@mediatek.corp-partner.google.com\u003e\nChange-Id: Idc669364c89cde0974d2940bd12987ee833d1965\n" }, { "commit": "af5a0c40aff21c4b8771365f19dcb01d6086b30d", "tree": "aa7cb7a565108f8e1ba4a6128e6023a682769a44", "parents": [ "109b91e38c8d4f73941c8574759560a1f1636d05" ], "author": { "name": "Guodong Liu", "email": "guodong.liu@mediatek.corp-partner.google.com", "time": "Fri Oct 15 16:52:18 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add pinctrl support\n\nAdd MT8186 pinctrl support.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Guodong Liu \u003cguodong.liu@mediatek.corp-partner.google.com\u003e\nChange-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f\n" }, { "commit": "109b91e38c8d4f73941c8574759560a1f1636d05", "tree": "f6c02f23aac41c606b90faef868b2c0d46534d48", "parents": [ "206f125cc177bc110eb87d40ffc7fa18b28c01ce" ], "author": { "name": "Zhengnan Chen", "email": "zhengnan.chen@mediatek.corp-partner.google.com", "time": "Tue Oct 12 17:05:49 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add sys_cirq support\n\nAdd 8186 sys_cirq info.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Zhengnan Chen \u003czhengnan.chen@mediatek.corp-partner.google.com\u003e\nChange-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787\n" }, { "commit": "206f125cc177bc110eb87d40ffc7fa18b28c01ce", "tree": "8bf4697e66429fc91f4d488856c87fc97faf0d35", "parents": [ "5aab27dc4294110a6c0b69bf5ec5343e7df883a7" ], "author": { "name": "Christine Zhu", "email": "christine.zhu@mediatek.corp-partner.google.com", "time": "Mon Oct 11 21:29:58 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): initialize GIC\n\nInitialize GIC for mt8186.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Christine Zhu \u003cchristine.zhu@mediatek.corp-partner.google.com\u003e\nChange-Id: I8d029983c7ce48fa116fafa7fa78c65349308014\n" }, { "commit": "5aab27dc4294110a6c0b69bf5ec5343e7df883a7", "tree": "efcd2e5c3fd80f3678611c9a93920c20a2f9de36", "parents": [ "5bc88ec61c75ed42b41d84817aa4d6ee68a2efc8" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Oct 06 19:25:50 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add SiP service\n\nAdd the basic SiP service.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I4dcc7383237bb6c1f2494920cde21197754f6367\n" }, { "commit": "5bc88ec61c75ed42b41d84817aa4d6ee68a2efc8", "tree": "47c0b1fd361ece8af1d8b98a13f822568302f5c4", "parents": [ "d73e15e66a33398c8fc51c83f975a3f35494faf5" ], "author": { "name": "James Lo", "email": "james.lo@mediatek.corp-partner.google.com", "time": "Wed Oct 06 18:12:30 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add pwrap and pmic driver\n\n1. Add 8186 pwrap driver to access pmic.\n2. Add 6366 pmic driver to support clean PWRHOLD.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: James Lo \u003cjames.lo@mediatek.corp-partner.google.com\u003e\nChange-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2\n" }, { "commit": "d73e15e66a33398c8fc51c83f975a3f35494faf5", "tree": "b574ec31ad99847c4726cf05e5428cc97139b644", "parents": [ "a6a0af57c3369dfc6fc2f25877d812a24e9be311" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Oct 06 19:00:13 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): initialize delay_timer\n\nInitialize delay_timer for delay functions.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: Ib8f52d1c674537795cc478015c83cca0f872df60\n" }, { "commit": "a6a0af57c3369dfc6fc2f25877d812a24e9be311", "tree": "fd1395d35b6a3e2eb06c9785e8fadc7d62874e61", "parents": [ "1b17e34c5d7740a357b2027d88aef7760b346616" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Oct 06 18:55:53 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:53 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): initialize systimer\n\nAdd systimer to support timer function.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I505f7d094410d178e4203e3a9294b851a30ba150\n" }, { "commit": "1b17e34c5d7740a357b2027d88aef7760b346616", "tree": "38b5b1c90541c41e420449dfb4bb5780bbfe6e31", "parents": [ "47833abd7772a49aa1b591392584549fb5a2c28f" ], "author": { "name": "Penny Jan", "email": "penny.jan@mediatek.corp-partner.google.com", "time": "Sun Oct 03 10:11:04 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Wed Dec 22 18:06:48 2021 +0800" }, "message": "feat(plat/mediatek/mt8186): add EMI MPU basic driver\n\nEMI MPU stands for external memory interface memory protect unit.\nMT8186 supports 32 regions and 16 domains.\nWe add basic driver currently, and will add more settings for\nEMI MPU in next patch.\n\nTEST\u003dbuild pass\nBUG\u003db:202871018\n\nSigned-off-by: Penny Jan \u003cpenny.jan@mediatek.corp-partner.google.com\u003e\nChange-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e\n" }, { "commit": "47833abd7772a49aa1b591392584549fb5a2c28f", "tree": "643e73922c6b49864068106c938c3cace3c1e033", "parents": [ "c2d75fa7a3f0c179f067058711f1aa1cbba7f1a8", "34ee76dbdfeee85f123cb903ea95dbee5e9a44a5" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Dec 22 01:12:32 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 01:12:32 2021 +0100" }, "message": "Merge \"fix(errata): workaround for Cortex X2 erratum 2002765\" into integration" }, { "commit": "c2d75fa7a3f0c179f067058711f1aa1cbba7f1a8", "tree": "599f6736aa6a64149448b869424b0daf42fb831d", "parents": [ "c8076a0e696243533b2e8f6673a5600dc90bd638", "1db6cd60279e2d082876692a65cf9c532f506a69" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Dec 22 01:10:54 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Dec 22 01:10:54 2021 +0100" }, "message": "Merge \"fix(errata): workaround for Cortex X2 erratum 2083908\" into integration" }, { "commit": "c8076a0e696243533b2e8f6673a5600dc90bd638", "tree": "07e45fe1776bb9fe382ac068e6c43c654c2f19c8", "parents": [ "f480c9c42b26841f7814aea81084d5a7d1605071", "3e80e840c1a09d363499dcaee0ba04865bcb62f6" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Tue Dec 21 19:08:44 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Dec 21 19:08:44 2021 +0100" }, "message": "Merge \"fix(doc): update TF-A v2.7 release date in the release information page\" into integration" }, { "commit": "e16045de50e8b430e6601ba0e1e47097d8310f3d", "tree": "531e27675c5d32678fd2e3978da246fea2e0a601", "parents": [ "34ee76dbdfeee85f123cb903ea95dbee5e9a44a5" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Dec 03 11:27:33 2021 -0600" }, "committer": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Dec 21 11:52:26 2021 -0600" }, "message": "fix(errata): workaround for Cortex X2 erratum 2058056\n\nCortex X2 erratum 2058056 is a Cat B erratum present in the X2 core.\nIt applies to revisions r0p0, r1p0, and r2p0 and is still open.\n\nThere are 2 ways this workaround can be accomplished, the first of\nwhich involves executing a few additional instructions around MSR\nwrites to CPUECTLR when disabling the prefetcher. (see SDEN for\ndetails)\n\nHowever, this patch implements the 2nd possible workaround which sets\nthe prefetcher into its most conservative mode, since this workaround\nis generic.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775100\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Idb20d9928c986616cd5bedf40bb29d46d384cfd3\n" }, { "commit": "3e80e840c1a09d363499dcaee0ba04865bcb62f6", "tree": "001906abd7d945b7f66d993c983fb5e51af2b19b", "parents": [ "714ca37dc70ae933724ffe42770f06b0e3447728" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Dec 21 09:14:48 2021 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Dec 21 09:14:48 2021 -0600" }, "message": "fix(doc): update TF-A v2.7 release date in the release information page\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Iae84f82518ab89edc204a23083d5f4168449c2bf\n" }, { "commit": "ab556c9c646f1b5f1b500449a5813a4eecdc0302", "tree": "691ac1b4b416c56f9e42a7b05b19a57757d8fc0e", "parents": [ "f480c9c42b26841f7814aea81084d5a7d1605071" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Sat Dec 18 11:26:25 2021 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Dec 20 13:31:38 2021 +0000" }, "message": "fix(fiptool): avoid packing the zero size images in the FIP\n\nUpdated the fiptool to avoid packing the zero size images in\nthe FIP.\nAlso, updated the commitlint-json file to cover the fiptool\nchanges under a separate scope.\n\nChange-Id: Id7ac3dcff0c7318546e49308d0f17b6cbd5eb24b\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "f480c9c42b26841f7814aea81084d5a7d1605071", "tree": "1a2765b1677c92339ae6cda06f6c2424228b0b23", "parents": [ "1d996e567cbcdf5c48c23c0519c2b4434fa26572", "ff7675ebf94999618dbde14bb59741cefb2b2edd" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Dec 17 20:04:33 2021 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Dec 17 20:04:33 2021 +0100" }, "message": "Merge \"fix(stm32mp1): correct include order\" into integration" } ], "next": "34ee76dbdfeee85f123cb903ea95dbee5e9a44a5" }