)]}' { "log": [ { "commit": "28645ebd706fe6ac9f34db9f7be5657fe4cffc1a", "tree": "0012f2cf2fbc61efdd664d308689941577d61022", "parents": [ "2d8e80c2a2104b7eca737fbc1e226572295c0d11" ], "author": { "name": "Rohit Ner", "email": "rohitner@google.com", "time": "Sat Jul 02 04:52:40 2022 -0700" }, "committer": { "name": "Rohit Ner", "email": "rohitner@google.com", "time": "Thu Jul 07 07:14:33 2022 -0700" }, "message": "fix(ufs): add retries to ufs_read_capacity\n\nThis change replaces the polling loop with fixed number of retries,\nreturns error values and handles them in ufs_enum.\n\nSigned-off-by: Rohit Ner \u003crohitner@google.com\u003e\nChange-Id: Ia769ef26703c7525091e55ff46aaae4637db933c\n" }, { "commit": "2d8e80c2a2104b7eca737fbc1e226572295c0d11", "tree": "34f42f9150cf403c9d331ee89ffcf62eeb49d480", "parents": [ "06526962434930c00ecdb76e39568d13adb06244", "054f0fe1361ba0cb339fb0902470988a82a24cf7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 30 16:47:49 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 30 16:47:49 2022 +0200" }, "message": "Merge changes from topics \"binary-format-sp\", \"od/meas-boot-spmc\" into integration\n\n* changes:\n feat(spm): add tpm event log node to spmc manifest\n fix(measured-boot): add SP entries to event_log_metadata\n" }, { "commit": "06526962434930c00ecdb76e39568d13adb06244", "tree": "b4e14067c93ab6a68e1151aba6e9632fb1deb623", "parents": [ "57ab749758dd0d4aa8a679420723101f321d7fe9", "722ca35ecc1c5de8682ca8df315a6369d0c21946" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jun 30 16:29:22 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 30 16:29:22 2022 +0200" }, "message": "Merge \"feat(stm32mp15): manage OP-TEE shared memory\" into integration" }, { "commit": "722ca35ecc1c5de8682ca8df315a6369d0c21946", "tree": "b4e14067c93ab6a68e1151aba6e9632fb1deb623", "parents": [ "57ab749758dd0d4aa8a679420723101f321d7fe9" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Jun 30 11:33:27 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Jun 30 14:19:45 2022 +0200" }, "message": "feat(stm32mp15): manage OP-TEE shared memory\n\nOn STM32MP15, there is currently an OP-TEE shared memory area at the end\nof the DDR. But this area will in term be removed. To allow a smooth\ntransition, a new flag is added (STM32MP15_OPTEE_RSV_SHM). It reflects\nthe OP-TEE flag: CFG_CORE_RESERVED_SHM. The flag is enabled by default\n(no behavior change). It will be set to 0 when OP-TEE is aligned, and\nthen later be removed.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I91146cd8a26a24be22143c212362294c1e880264\n" }, { "commit": "57ab749758dd0d4aa8a679420723101f321d7fe9", "tree": "8cb40fb8c04cb35961ddfb9f9ab23dd6229186ec", "parents": [ "cb666b39d8571348e7a5a1582f69aa3f5da5189b", "7b1a6a08ccc7522687f66e6e989bbc597d08ab06" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Thu Jun 30 00:36:46 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 30 00:36:46 2022 +0200" }, "message": "Merge changes from topic \"xlnx_zynqmp_misra_fix1\" into integration\n\n* changes:\n fix(zynqmp): resolve the misra 8.6 warnings\n fix(zynqmp): resolve the misra 4.6 warnings\n" }, { "commit": "cb666b39d8571348e7a5a1582f69aa3f5da5189b", "tree": "68744d7223815e29372447617861b29a1e864881", "parents": [ "e0061a22a59726dd6568b78c77f12821454077d0", "0aaa382fe2395c82c9491b199b6b82819afd368f" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 29 15:27:32 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 29 15:27:32 2022 +0200" }, "message": "Merge \"fix(sptool): fix concurrency issue for SP packages\" into integration" }, { "commit": "0aaa382fe2395c82c9491b199b6b82819afd368f", "tree": "84790775837e9afa20d45de2a22853b1f821a06a", "parents": [ "65a5e1c04df56dbc0feb270fbae13c884020a5b9" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Thu Jun 09 12:04:30 2022 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Tue Jun 28 12:27:20 2022 +0100" }, "message": "fix(sptool): fix concurrency issue for SP packages\n\nAdd dependency between rules to generate SP packages and their dtb files\nto ensure the dtb files are built before the sptool attempts to generate\nthe SP package.\n\nChange-Id: I071806f4aa09f39132e3e1990c91d71dc9acd728\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\n" }, { "commit": "e0061a22a59726dd6568b78c77f12821454077d0", "tree": "56970be94481c1207da8902d562c015903c0e8c7", "parents": [ "caca0e57b8c4cceafa6812f2351419744648b890", "8d76a4a687983bdc5f6ecdf10614bcb80fc50f48" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Jun 28 13:23:18 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 28 13:23:18 2022 +0200" }, "message": "Merge \"docs: add Manish Badarkhe to maintainer list\" into integration" }, { "commit": "caca0e57b8c4cceafa6812f2351419744648b890", "tree": "ff5aa3ee82255efc0642eaec04b4b4b1feb68712", "parents": [ "96f715eb842f5462daf843a85ef2978b986a2f34", "ab2b325c1ab895e626d4e11a9f26b9e7c968f8d8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 28 10:53:01 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 28 10:53:01 2022 +0200" }, "message": "Merge \"feat(stm32mp1): save boot auth status and partition info\" into integration" }, { "commit": "96f715eb842f5462daf843a85ef2978b986a2f34", "tree": "6ffa581acd15f5bde31daa88aed6697e3e7e75b2", "parents": [ "4bbdc3912bcc3f664e902ab3e2815b459615075f", "70b1c025003452602f68feb13402c705e44145aa" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Jun 28 09:33:44 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 28 09:33:44 2022 +0200" }, "message": "Merge \"fix(measured-boot): clear the entire digest array of Startup Locality event\" into integration" }, { "commit": "4bbdc3912bcc3f664e902ab3e2815b459615075f", "tree": "26db2929b988e9d14be9a16ec3bde3b17d020dcf", "parents": [ "24f51f214e538b92490d635010381865e70360ad", "a19382521c583b3dde89df14678b011960097f6c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 28 03:43:48 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 28 03:43:48 2022 +0200" }, "message": "Merge changes from topic \"HEAD\" into integration\n\n* changes:\n feat(synquacer): add FWU Multi Bank Update support\n feat(synquacer): add TBBR support\n feat(synquacer): add BL2 support\n refactor(synquacer): move common source files\n" }, { "commit": "a19382521c583b3dde89df14678b011960097f6c", "tree": "105a176ab46a728eaa13e8f926c83059a2d8367e", "parents": [ "19aaeea00bc4fba94af7aca508af878136930f4a" ], "author": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Mon May 23 13:16:01 2022 -0500" }, "committer": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Mon Jun 27 13:12:24 2022 -0500" }, "message": "feat(synquacer): add FWU Multi Bank Update support\n\nAdd FWU Multi Bank Update support. This reads the platform metadata\nand update the FIP base address so that BL2 can load correct BL3X\nbased on the boot index.\n\nCc: Sumit Garg \u003csumit.garg@linaro.org\u003e\nCc: Masahisa Kojima \u003cmasahisa.kojima@linaro.org\u003e\nCc: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nCc: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: I5d96972bc4b3b9a12a8157117e53a05da5ce89f6\nSigned-off-by: Masami Hiramatsu \u003cmasami.hiramatsu@linaro.org\u003e\nSigned-off-by: Jassi Brar \u003cjaswinder.singh@linaro.org\u003e\n" }, { "commit": "19aaeea00bc4fba94af7aca508af878136930f4a", "tree": "75edfb89e82e1c1c2b3e014ad908a9bc7db01ba1", "parents": [ "48ab390444e1dabb669430ace9b8e5a80348eed0" ], "author": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Thu Mar 03 15:24:31 2022 -0600" }, "committer": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Mon Jun 27 13:12:24 2022 -0500" }, "message": "feat(synquacer): add TBBR support\n\nenable Trusted-Boot for Synquacer platform.\n\nCc: Sumit Garg \u003csumit.garg@linaro.org\u003e\nCc: Masahisa Kojima \u003cmasahisa.kojima@linaro.org\u003e\nCc: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nCc: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: I2608b4d573d95d55da1fc5544333e0dbf3f763f2\nSigned-off-by: Jassi Brar \u003cjaswinder.singh@linaro.org\u003e\n" }, { "commit": "48ab390444e1dabb669430ace9b8e5a80348eed0", "tree": "2d34eec130e8944f010e27d52666eac93b1c853b", "parents": [ "3ba82d5ff1dd59a585af5434a4373e0ffd1212c2" ], "author": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Thu Mar 03 15:24:31 2022 -0600" }, "committer": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Mon Jun 27 13:12:24 2022 -0500" }, "message": "feat(synquacer): add BL2 support\n\nAdd BL2 support by default. Move the legacy mode behind the\nRESET_TO_BL31 define.\n\nCc: Sumit Garg \u003csumit.garg@linaro.org\u003e\nCc: Masahisa Kojima \u003cmasahisa.kojima@linaro.org\u003e\nCc: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nCc: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: Ic490745a7e8f6114172733428ebd6bd6adfcc1ec\nSigned-off-by: Jassi Brar \u003cjaswinder.singh@linaro.org\u003e\n" }, { "commit": "3ba82d5ff1dd59a585af5434a4373e0ffd1212c2", "tree": "9e9631d57c07c900b9c2611a41c676202b814f6d", "parents": [ "3f261a564ec82a6a7ecf443232372a2bf0356521" ], "author": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Thu Mar 03 15:24:31 2022 -0600" }, "committer": { "name": "Jassi Brar", "email": "jaswinder.singh@linaro.org", "time": "Mon Jun 27 13:12:24 2022 -0500" }, "message": "refactor(synquacer): move common source files\n\nPrepare for introduction of BL2 support by moving\nreusable files from BL31_SOURCES into PLAT_BL_COMMON_SOURCES\n\nCc: Sumit Garg \u003csumit.garg@linaro.org\u003e\nCc: Masahisa Kojima \u003cmasahisa.kojima@linaro.org\u003e\nCc: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nCc: Leonardo Sandoval \u003cleonardo.sandoval@linaro.org\u003e\nChange-Id: I21137cdd40d027cfa77f1dec3598ee85d4873581\nSigned-off-by: Jassi Brar \u003cjaswinder.singh@linaro.org\u003e\n" }, { "commit": "8d76a4a687983bdc5f6ecdf10614bcb80fc50f48", "tree": "234d8b0cdcd228d10991ce3de288b944206e7d19", "parents": [ "3f261a564ec82a6a7ecf443232372a2bf0356521" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 27 18:05:48 2022 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 27 18:08:15 2022 +0100" }, "message": "docs: add Manish Badarkhe to maintainer list\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I8fd116962bb9775e2f96faee37bbf73073e15512\n" }, { "commit": "24f51f214e538b92490d635010381865e70360ad", "tree": "bb25ca5eef9cc5cdfcf89870917ead1c528e3af7", "parents": [ "f95ddea6ced4e5fa2cac260940cc1e0412bf4708", "a4e485d7bf1c428d64e90e9821e4b1a109d10626" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 27 18:01:12 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 27 18:01:12 2022 +0200" }, "message": "Merge \"feat(auth): enable MBEDTLS_CHECK_RETURN_WARNING\" into integration" }, { "commit": "f95ddea6ced4e5fa2cac260940cc1e0412bf4708", "tree": "efabd2ebca8ddc31f7d7986912fe3a44d45dd5cd", "parents": [ "02450800bca438eac1da75f3a04d732f55c32f48", "c4dbcb885201c89a44df203661af007945782993" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 27 18:00:50 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 27 18:00:50 2022 +0200" }, "message": "Merge changes from topic \"st_optee_paged\" into integration\n\n* changes:\n feat(stm32mp1): optionally use paged OP-TEE\n feat(optee): check paged_image_info\n" }, { "commit": "ab2b325c1ab895e626d4e11a9f26b9e7c968f8d8", "tree": "4ef49616eb6f32002ee055ab9394e33e43844a8b", "parents": [ "3f261a564ec82a6a7ecf443232372a2bf0356521" ], "author": { "name": "Igor Opaniuk", "email": "igor.opaniuk@foundries.io", "time": "Thu Jun 23 21:19:26 2022 +0300" }, "committer": { "name": "Igor Opaniuk", "email": "igor.opaniuk@foundries.io", "time": "Mon Jun 27 18:56:55 2022 +0300" }, "message": "feat(stm32mp1): save boot auth status and partition info\n\nIntroduce a functionality for saving/restoring boot auth status\nand partition used for booting (FSBL partition on which the boot\nwas successful).\n\nSigned-off-by: Igor Opaniuk \u003cigor.opaniuk@foundries.io\u003e\nChange-Id: I4d7f153b70dfc49dad8c1c3fa71111a350caf1ee\n" }, { "commit": "02450800bca438eac1da75f3a04d732f55c32f48", "tree": "24627955ec1efb0f7a2ec82e05ff550607efb148", "parents": [ "6f614219c70fbfea2b8ea20351ed83a34e9612c9", "4ee91ba98f7b86aa27b1e14a524c4429bf13fd2f" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Mon Jun 27 17:32:59 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 27 17:32:59 2022 +0200" }, "message": "Merge changes from topic \"mb_hash\" into integration\n\n* changes:\n refactor(imx): update config of mbedtls support\n refactor(qemu): update configuring mbedtls support\n refactor(measured-boot): mb algorithm selection\n" }, { "commit": "6f614219c70fbfea2b8ea20351ed83a34e9612c9", "tree": "437c0287ea4df6372590599ef31213e3f5102449", "parents": [ "63d49c49c2943b82930d1303ac64aa3286832f23", "742c23aab79a21803472c5b4314b43057f1d3e84" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 27 15:46:58 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 27 15:46:58 2022 +0200" }, "message": "Merge \"fix(nxp-ddr): fix firmware buffer re-mapping issue\" into integration" }, { "commit": "a4e485d7bf1c428d64e90e9821e4b1a109d10626", "tree": "b89c882dbda2bb2f10b55081aa73b29385b20b7b", "parents": [ "299d38100a69b2730b76c5d3dde2633662ba5aec" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jun 15 15:31:52 2022 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jun 27 10:33:03 2022 +0200" }, "message": "feat(auth): enable MBEDTLS_CHECK_RETURN_WARNING\n\nDefine the MBEDTLS_CHECK_RETURN_WARNING macro in mbedTLS configuration\nfile to get compile-time warnings for mbedTLS functions we call and do\nnot check the return value of. Right now, this does not flag anything\nbut it could help catching bugs in the future.\n\nThis was a new feature introduced in mbed TLS 2.28.0 release.\n\nChange-Id: If26f3c83b6ccc8bc60e75c3e582ab20817d047aa\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "63d49c49c2943b82930d1303ac64aa3286832f23", "tree": "a9d995bca554fa4be5b4dd54a55a996718152125", "parents": [ "9316149ef8538ee0b7299700429ba0e7ff802630", "2abd317d27a26bbfa3da7fe3fe709da3fa0f09af" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Jun 27 09:37:39 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 27 09:37:39 2022 +0200" }, "message": "Merge \"fix(measured-boot): fix verbosity level of RSS digests traces\" into integration" }, { "commit": "9316149ef8538ee0b7299700429ba0e7ff802630", "tree": "d9af98db018c33e6ae43c019d7cc320dafbcef6e", "parents": [ "40366cb69dd337b3c3fc8f31db19ac474c1602ee", "389594dfa7e60a720d60f0d55296f91ba1610de5" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 24 13:43:41 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 24 13:43:41 2022 +0200" }, "message": "Merge \"fix(zynqmp): move bl31 with DEBUG\u003d1 back to OCM\" into integration" }, { "commit": "40366cb69dd337b3c3fc8f31db19ac474c1602ee", "tree": "5b373657daf4f68d8ae0135a46203bccb594a1cc", "parents": [ "f3249498217d88f3c1a6938d712dec256ce88c52", "1117a16e0379986ea68581c02fb2fee40937452b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 24 13:40:01 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 24 13:40:01 2022 +0200" }, "message": "Merge changes from topic \"xlnx_versal_misra_fix\" into integration\n\n* changes:\n fix(versal): resolve misra 15.6 warnings\n fix(zynqmp): resolve misra 8.13 warnings\n fix(versal): resolve misra 8.13 warnings\n fix(versal): resolve the misra 4.6 warnings\n" }, { "commit": "f3249498217d88f3c1a6938d712dec256ce88c52", "tree": "030b26049207e1c6fd6231bdb0f94ac79bc88b3b", "parents": [ "3f261a564ec82a6a7ecf443232372a2bf0356521", "50b449776df11cac06347e8ef1af5dae701a0e3a" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 24 12:44:06 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 24 12:44:06 2022 +0200" }, "message": "Merge changes from topic \"lw/cca_cot\" into integration\n\n* changes:\n feat(arm): retrieve the right ROTPK for cca\n feat(arm): add support for cca CoT\n feat(arm): provide some swd rotpk files\n build(tbbr): drive cert_create changes for cca CoT\n refactor(arm): add cca CoT certificates to fconf\n feat(fiptool): add cca, core_swd, plat cert in FIP\n feat(cert_create): define the cca chain of trust\n feat(cca): introduce new \"cca\" chain of trust\n build(changelog): add new scope for CCA\n refactor(fvp): increase bl2 size when bl31 in DRAM\n" }, { "commit": "3f261a564ec82a6a7ecf443232372a2bf0356521", "tree": "483514e45dafa14a93b85c1aa1ee9ad768584470", "parents": [ "0f93168c01d3971b340ed96559bb7f2a6141129e", "a62cc91aeedbdcfb3396983ed165eb35b8d4c3fa" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 22 17:45:45 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 22 17:45:45 2022 +0200" }, "message": "Merge changes from topic \"ns/cpu_info\" into integration\n\n* changes:\n feat(plat/arm/sgi): increase memory reserved for bl31 image\n feat(plat/arm/sgi): read isolated cpu mpid list from sds\n" }, { "commit": "0f93168c01d3971b340ed96559bb7f2a6141129e", "tree": "0e9ce8b875da8f2a7d0e2f3cf53d74b15ed396cb", "parents": [ "daa4df63c683698462429f1b7e56dea28f8d0502", "afa41571b856509c25c66c331737b895144b681b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 22 17:45:40 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 22 17:45:40 2022 +0200" }, "message": "Merge \"feat(board/rdn2): add a new \u0027isolated-cpu-list\u0027 property\" into integration" }, { "commit": "c4dbcb885201c89a44df203661af007945782993", "tree": "5741c5f14fb60cd7b12ab1a592a1c32ed430ba4a", "parents": [ "c0a11cd8698394e1d3d3d7c9cedb19846ba59223" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Jun 20 11:43:17 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jun 22 14:51:03 2022 +0200" }, "message": "feat(stm32mp1): optionally use paged OP-TEE\n\nSTM32MP13 can encrypt the DDR. OP-TEE is then fully in DDR, and there\nis no need for paged image on STM32MP13. The management of the paged\nOP-TEE is made conditional, and will be kept only for STM32MP15.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I85ac7aaf6a172c4ee529736113ed40fe66835fd7\n" }, { "commit": "c0a11cd8698394e1d3d3d7c9cedb19846ba59223", "tree": "a745a7140647e8ce08d7341ff7a3fb4a93bc807c", "parents": [ "daa4df63c683698462429f1b7e56dea28f8d0502" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Jun 20 11:24:22 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jun 22 14:48:35 2022 +0200" }, "message": "feat(optee): check paged_image_info\n\nFor OP-TEE without pager, the paged image may not be present in OP-TEE\nheader. We could then pass NULL for paged_image_info to the function\nparse_optee_header(). It avoids creating a useless struct for that\nnon existing image. But we should then avoid assigning header_ep args\nthat depend on paged_image_info.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I4fdb45a91ac1ba6f912d6130813f5215c7e28c8b\n" }, { "commit": "daa4df63c683698462429f1b7e56dea28f8d0502", "tree": "6cff38e2e66b187ef719643f63d02bf6c6e2298d", "parents": [ "84adb0519e96251bbd7b4a5dabe904b4a7f3a833", "56f895ede3a2a4a97c0e4f8270050aff20a167bc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 21 17:19:58 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 21 17:19:58 2022 +0200" }, "message": "Merge changes from topic \"st_clk_fixes\" into integration\n\n* changes:\n fix(st-clock): correct MISRA C2012 15.6\n fix(st-clock): correctly check ready bit\n" }, { "commit": "56f895ede3a2a4a97c0e4f8270050aff20a167bc", "tree": "6cff38e2e66b187ef719643f63d02bf6c6e2298d", "parents": [ "3b06a53044e754979cb0608fd93a137a5879a6a0" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jun 21 14:34:13 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jun 21 16:01:10 2022 +0200" }, "message": "fix(st-clock): correct MISRA C2012 15.6\n\nAdd braces to correct MISRA C2012 15.6 warning:\nThe body of an iteration-statement or a selection-statement shall be a\ncompound-statement.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: If26f3732d31df11bf389a16298ec9e9d8a4a2279\n" }, { "commit": "3b06a53044e754979cb0608fd93a137a5879a6a0", "tree": "88988213c99fb3b23d4dd95cf2380f65b94d8498", "parents": [ "84adb0519e96251bbd7b4a5dabe904b4a7f3a833" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Jun 21 15:12:27 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jun 21 16:01:06 2022 +0200" }, "message": "fix(st-clock): correctly check ready bit\n\nThe function clk_oscillator_wait_ready() was wrongly checking the set\nbit and not the ready bit. Correct that by using osc_data-\u003egate_rdy_id\nwhen calling _clk_stm32_gate_wait_ready().\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Ida58f14d7f0f326b580ae24b98d6b9f592d2d711\n" }, { "commit": "a62cc91aeedbdcfb3396983ed165eb35b8d4c3fa", "tree": "aabe0a9fafdf98a8155c63842b25e1de0641637d", "parents": [ "4243ef41d480fd8e870f74defe263156a6c02c8d" ], "author": { "name": "Nishant Sharma", "email": "nishant.sharma@arm.com", "time": "Thu Mar 31 17:16:21 2022 +0100" }, "committer": { "name": "Nishant Sharma", "email": "nishant.sharma@arm.com", "time": "Tue Jun 21 13:59:53 2022 +0100" }, "message": "feat(plat/arm/sgi): increase memory reserved for bl31 image\n\nIncrease the size of bl31 image by 52K to accomodate increased size of\nxlat table.\n\nSigned-off-by: Nishant Sharma \u003cnishant.sharma@arm.com\u003e\nChange-Id: Ic3a8d8be1104adf48d22aa829e2197f710b6b666\n" }, { "commit": "4243ef41d480fd8e870f74defe263156a6c02c8d", "tree": "6eb2eb0b1f26cbb0f2e3858567bf19ae61fa0821", "parents": [ "afa41571b856509c25c66c331737b895144b681b" ], "author": { "name": "Nishant Sharma", "email": "nishant.sharma@arm.com", "time": "Tue Nov 30 09:31:48 2021 +0000" }, "committer": { "name": "Nishant Sharma", "email": "nishant.sharma@arm.com", "time": "Tue Jun 21 13:59:39 2022 +0100" }, "message": "feat(plat/arm/sgi): read isolated cpu mpid list from sds\n\nAdd support to read the list of isolated CPUs from SDS and publish this\nlist via the non-trusted firmware configuration file for the next stages\nof boot software to use.\n\nIsolated CPUs are those that are not to be used on the platform for\nvarious reasons. The isolated CPU list is an array of MPID values of the\nCPUs that have to be isolated.\n\nSigned-off-by: Nishant Sharma \u003cnishant.sharma@arm.com\u003e\nChange-Id: I4313cf025f4c9e9feffebca2d35b259f5bafce69\n" }, { "commit": "84adb0519e96251bbd7b4a5dabe904b4a7f3a833", "tree": "bf7253b8a5fc075ca633d06867f3fa2c7b346563", "parents": [ "4e898483de5fc56dc271179d55dbaec69d7aad4c", "69a131d894dde9a6570877c7bf181fb60484342d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 21 14:11:47 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 21 14:11:47 2022 +0200" }, "message": "Merge changes from topic \"mb/gic600-errata\" into integration\n\n* changes:\n refactor(arm): update BL2 base address\n refactor(nxp): use DPG0 mask from Arm GICv3 header\n fix(gic600): implement workaround to forward highest priority interrupt\n" }, { "commit": "afa41571b856509c25c66c331737b895144b681b", "tree": "00c65abbb2cc631486b774f82f871b9c380fef35", "parents": [ "4e898483de5fc56dc271179d55dbaec69d7aad4c" ], "author": { "name": "Nishant Sharma", "email": "nishant.sharma@arm.com", "time": "Tue Nov 30 09:38:46 2021 +0000" }, "committer": { "name": "Nishant Sharma", "email": "nishant.sharma@arm.com", "time": "Tue Jun 21 12:41:54 2022 +0100" }, "message": "feat(board/rdn2): add a new \u0027isolated-cpu-list\u0027 property\n\nAdd a new property named \u0027isolated-cpu-list\u0027 to list the CPUs that are\nto be isolated and not used by the platform. The data represented by\nthis property is formatted as below.\n\n strutct isolated_cpu_mpid_list {\n uint64_t count;\n uint64_t mpid_list[MAX Number of PE];\n }\n\nAlso, the property is pre-initialized to 0 to reserve space for the\nproperty in the dtb. The data for this property is read from SDS and\nupdated during boot. The number of entries in this list is equal to the\nmaximum number of PEs present on the platform.\n\nSigned-off-by: Nishant Sharma \u003cnishant.sharma@arm.com\u003e\nChange-Id: I4119f899a273ccbf8259e0d711d3a25501c7ec64\n" }, { "commit": "4e898483de5fc56dc271179d55dbaec69d7aad4c", "tree": "331429b18f87cfd5883713f2d1006cc89207b6e2", "parents": [ "0938847fc70aac7a4354834ec5d82b7233ff7846", "2a7e080cc50be5739afcfb3b7db59e4d610a7d53" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 21 12:42:08 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 21 12:42:08 2022 +0200" }, "message": "Merge changes from topic \"uart_segregation_v2\" into integration\n\n* changes:\n feat(sgi): add page table translation entry for secure uart\n feat(sgi): route TF-A logs via secure uart\n feat(sgi): deviate from arm css common uart related definitions\n" }, { "commit": "742c23aab79a21803472c5b4314b43057f1d3e84", "tree": "fd210590be8f31e058ed6c4535f78a26ad0d0bcd", "parents": [ "0938847fc70aac7a4354834ec5d82b7233ff7846" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Apr 08 11:10:40 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Mon Jun 20 15:54:16 2022 +0800" }, "message": "fix(nxp-ddr): fix firmware buffer re-mapping issue\n\nFirmware buffer has already been mapped when loading 1D firmware,\nso the same buffer address will be re-mapped when loading 2D\nfirmware. Move the buffer mapping to be out of load_fw().\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: Idb29d504bc482a1e7ca58bc51bec09ffe6068324\n" }, { "commit": "054f0fe1361ba0cb339fb0902470988a82a24cf7", "tree": "4f20ed4aa7fbfa0c1e748821fb06f49ebf046380", "parents": [ "e637a5e19da72599229fd2c70e793c123aaf14ca" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Jun 15 11:18:48 2022 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Jun 17 17:22:28 2022 +0200" }, "message": "feat(spm): add tpm event log node to spmc manifest\n\nAdd the TPM event log node to the SPMC manifest such that the TF-A\nmeasured boot infrastructure fills the properties with event log address\nfor components measured by BL2 at boot time.\nFor a SPMC there is a particular interest with SP measurements.\nIn the particular case of Hafnium SPMC, the tpm event log node is not\nyet consumed, but the intent is later to pass this information to an\nattestation SP.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: Ic30b553d979532c5dad9ed6d419367595be5485e\n" }, { "commit": "2a7e080cc50be5739afcfb3b7db59e4d610a7d53", "tree": "f9d2febaf07aae800569823e43c32cf6e1097380", "parents": [ "0601083f0ce0045bd957c1343d2196be0887973b" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Mon Dec 13 15:33:04 2021 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Fri Jun 17 15:27:45 2022 +0100" }, "message": "feat(sgi): add page table translation entry for secure uart\n\nAdd page table translation entry for secure uart so that logs from\nsecure partition can be routed via the same.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I3416d114bcee13824a7d0861ee54fb799e154897\n" }, { "commit": "0601083f0ce0045bd957c1343d2196be0887973b", "tree": "e58ca258b8885d9176d0dc648ad432e96ff09d17", "parents": [ "173674ae428aa23e8f2a38d5542d0ea52eed7e80" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Mon Dec 13 15:40:25 2021 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Fri Jun 17 15:27:18 2022 +0100" }, "message": "feat(sgi): route TF-A logs via secure uart\n\nRoute the boot, runtime and crash stage logs via secure UART port\ninstead of the existing use of non-secure UART. This aligns with the\nsecurity state the PE is in when logs are put out. In addition to this,\nthis allows consolidation of the UART related macros across all the\nvariants of the Neoverse reference design platforms.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I417f5d16457b602c94da4c74b4d88bba03da7462\n" }, { "commit": "173674ae428aa23e8f2a38d5542d0ea52eed7e80", "tree": "0c61b64aaa4196fa9af6195c277a31aadc346f25", "parents": [ "453abc80b2eacbf2816c838e47e40f063227d934" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Mon Dec 13 13:50:15 2021 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Fri Jun 17 15:26:39 2022 +0100" }, "message": "feat(sgi): deviate from arm css common uart related definitions\n\nThe Neoverse reference design platforms will migrate to use different\nset of secure and non-secure UART ports. This implies that the board\nspecific macros defined in the common Arm platform code will no longer\nbe usable for Neoverse reference design platforms.\n\nIn preparation for migrating to a different set of UART ports, add a\nNeoverse reference design platform specific copy of the board\ndefinitions. The value of these definitions will be changed in\nsubsequent patches.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I1ab17a3f02c8180b63be24e9266f7129beee819f\n" }, { "commit": "70b1c025003452602f68feb13402c705e44145aa", "tree": "827d4d295f199ff57ca9d6f9a023dbb8ed022899", "parents": [ "0938847fc70aac7a4354834ec5d82b7233ff7846" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jun 09 22:39:32 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 17 15:18:01 2022 +0100" }, "message": "fix(measured-boot): clear the entire digest array of Startup Locality event\n\nAccording to TCG PC Client Platform Firmware Profile Specification\n(Section 10.2.2, TCG_PCR_EVENT2 Structure, and 10.4.5 EV_NO_ACTION Event\nTypes), all EV_NO_ACTION events shall set TCG_PCR_EVENT2.digests to all\n0x00\u0027s for each allocated Hash algorithm.\n\nRight now, this is not enforced. Only part of the buffer is zeroed due\nto the wrong macro being used for the size of the buffer in the clearing\noperation (TPM_ALG_ID instead of TCG_DIGEST_SIZE). This could confuse\na TPM event log parser.\n\nAlso, add an assertion to ensure that the Event Log size is large enough\nbefore writing the Event Log header.\n\nChange-Id: I6d4bc3fb28fd10c227e33c8c7bb4a40b08c3fd5e\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "0938847fc70aac7a4354834ec5d82b7233ff7846", "tree": "0d24d038e760b86ad2202ac093d6bad55d75caa0", "parents": [ "ffa3f9423b435154191057e0a662e8a0eb407bf4", "37200ae08b2cd91ca3c1104a597ba90cf6c3ba30" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 17 11:10:35 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 17 11:10:35 2022 +0200" }, "message": "Merge \"docs(security): update security advisory for CVE-2022-23960\" into integration" }, { "commit": "37200ae08b2cd91ca3c1104a597ba90cf6c3ba30", "tree": "65a8c255835c5829cb7c20ac1bfaf6906b0cc20e", "parents": [ "100da90ca84a3265d6312f24df16f920929234a6" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jun 16 16:32:22 2022 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jun 16 17:04:09 2022 -0500" }, "message": "docs(security): update security advisory for CVE-2022-23960\n\nUpdate advisory document following Spectre-BHB mitigation support for\nadditional CPUs.\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I4492397f18882f514beff4da06afe973acecf1f0\n" }, { "commit": "ffa3f9423b435154191057e0a662e8a0eb407bf4", "tree": "6838c899ce27625ef934c12e8c7aff5106ba3864", "parents": [ "75fb34d5f8fbad60a64efd0e0326b2591407ac9c", "57b73d553305d89da7098f9b53b0a2356ca7ff8b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 16 23:30:22 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 16 23:30:22 2022 +0200" }, "message": "Merge \"fix(errata): workaround for Neoverse-V1 erratum 2372203\" into integration" }, { "commit": "75fb34d5f8fbad60a64efd0e0326b2591407ac9c", "tree": "a08bcc1dfcb296dffe9dbba899791b78f63662b2", "parents": [ "100da90ca84a3265d6312f24df16f920929234a6", "7bf1a7aaaa41034587e43d5805b42da83090b85b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 16 22:06:40 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 16 22:06:40 2022 +0200" }, "message": "Merge \"fix(errata): workaround for Cortex-A77 erratum 2356587\" into integration" }, { "commit": "4ee91ba98f7b86aa27b1e14a524c4429bf13fd2f", "tree": "8bdcf36db4ec1c1bd0304710ce4138508a7443f6", "parents": [ "a58cfefb31a08e0dd7613c90543da3346daf2c24" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jun 16 13:40:48 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jun 16 13:42:25 2022 -0500" }, "message": "refactor(imx): update config of mbedtls support\n\nPull in MbedTLS support for sha512 when greater than sha256 is required\nbased on refactoring for hash algorithm selection for Measured Boot.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I489392133435436a16edced1d810bc5204ba608f\n" }, { "commit": "a58cfefb31a08e0dd7613c90543da3346daf2c24", "tree": "22b50d1e04a27e4c92aa44e9f149855828358712", "parents": [ "78da42a5f1f33ca55019dddf0890c0db1c2fa05f" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jun 16 13:36:52 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jun 16 13:42:19 2022 -0500" }, "message": "refactor(qemu): update configuring mbedtls support\n\nPull in MbedTLS support for sha512 when greater than sha256 is required\nbased on refactoring for hash algorithm selection for Measured Boot.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: Ib0ca5ecdee7906b41a0e1060339d43ce7a018d31\n" }, { "commit": "78da42a5f1f33ca55019dddf0890c0db1c2fa05f", "tree": "337bf94c98a1444e93aadab9a493dd7ad3c41e38", "parents": [ "100da90ca84a3265d6312f24df16f920929234a6" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue May 31 16:39:09 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Jun 16 13:42:19 2022 -0500" }, "message": "refactor(measured-boot): mb algorithm selection\n\nWith RSS now introduced, we have 2 Measured Boot backends. Both backends\ncan be used in the same firmware build with potentially different hash\nalgorithms, so now there can be more than one hash algorithm in a build.\nTherefore the logic for selecting the measured boot hash algorithm needs\nto be updated and the coordination of algorithm selection added. This is\ndone by:\n\n- Adding MBOOT_EL_HASH_ALG for Event Log to define the hash algorithm\nto replace TPM_HASH_ALG, removing reference to TPM.\n\n- Adding MBOOT_RSS_HASH_ALG for RSS to define the hash algorithm to\nreplace TPM_HASH_ALG.\n\n- Coordinating MBOOT_EL_HASH_ALG and MBOOT_RSS_HASH_ALG to define the\nMeasured Boot configuration macros through defining\nTF_MBEDTLS_MBOOT_USE_SHA512 to pull in SHA-512 support if either\nbackend requires a stronger algorithm than SHA-256.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I4ddf06ebdc3835beb4d1b6c7bab5a257ffc5c71a\n" }, { "commit": "7bf1a7aaaa41034587e43d5805b42da83090b85b", "tree": "bc1247da9e5ebc9afd38134a264673fbe01f1d73", "parents": [ "65a5e1c04df56dbc0feb270fbae13c884020a5b9" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Jun 08 15:27:00 2022 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jun 16 12:23:53 2022 -0500" }, "message": "fix(errata): workaround for Cortex-A77 erratum 2356587\n\nCortex-A77 erratum 2356587 is a cat B erratum that applies to revisions\nr0p0 - r1p1 and is still open. The workaround is to set bit[0] of\nCPUACTLR2_EL1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not\ncause invalidations to other PE caches.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1152370/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I243cfd587bca06ffd2a7be5bce28f8d2c5e68230\n" }, { "commit": "57b73d553305d89da7098f9b53b0a2356ca7ff8b", "tree": "77de1c1c87543a9c3c461ad76ccb3e9307263bb1", "parents": [ "299d38100a69b2730b76c5d3dde2633662ba5aec" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Jun 14 17:09:23 2022 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jun 16 12:09:01 2022 -0500" }, "message": "fix(errata): workaround for Neoverse-V1 erratum 2372203\n\nNeoverse-V1 erratum 2372203 is a cat B erratum that applies to revisions\nr0p0 - r1p1 and is still open. The workaround is to set bit[40] of\nCPUACTLR2_EL1 to disable folding of demand requests into older\nprefetches with L2 miss requests outstanding.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1401781/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ice8c2e5a0152972a35219c8245a2e07e646d0557\n" }, { "commit": "2abd317d27a26bbfa3da7fe3fe709da3fa0f09af", "tree": "5a97bc3787d34081a61aa6aa309b05149ee512fd", "parents": [ "100da90ca84a3265d6312f24df16f920929234a6" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Jun 15 14:21:17 2022 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Jun 16 14:29:41 2022 +0200" }, "message": "fix(measured-boot): fix verbosity level of RSS digests traces\n\nMost traces displayed by log_measurement() use the INFO verbosity\nlevel. Only the digests are unconditionally printed, regardless of\nthe verbosity level. As a result, when the verbosity level is set\nlower than INFO (typically in release mode), only the digests are\nprinted, which look weird and out of context.\n\nChange-Id: I0220977c35dcb636f1510d8a7a0a9e3d92548bdc\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "69a131d894dde9a6570877c7bf181fb60484342d", "tree": "07f0fbf696e47cbb6ad5a0f5548bf3fa25045500", "parents": [ "76398c02a6a9b069baf84e85a12f7f32e8cb1e56" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Jun 13 18:23:01 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jun 15 22:02:18 2022 +0100" }, "message": "refactor(arm): update BL2 base address\n\nBL2 base address updated to provide enough space for BL31 in\nTrusted SRAM when building with BL2_AT_EL3 and ENABLE_PIE options.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: Ieaba00d841648add855feb99b7923a4b0cccfb08\n" }, { "commit": "76398c02a6a9b069baf84e85a12f7f32e8cb1e56", "tree": "7442d162e0213748253d1a49cb53a7951ddaaabc", "parents": [ "e1b15b09a530f2a0b0edc4384e977452d6b389eb" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Jun 06 12:08:35 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jun 15 22:02:18 2022 +0100" }, "message": "refactor(nxp): use DPG0 mask from Arm GICv3 header\n\nRemoved GICR_CTLR_DPG0_MASK definition from platform GIC header file\nas Arm GICv3 header file added its definition.\n\nChange-Id: Ieec43aeef96b9b6c8a7f955a8d145be6e4b183c5\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "e1b15b09a530f2a0b0edc4384e977452d6b389eb", "tree": "1098bcb58684bbd8e8ab43548b3f3707584756b4", "parents": [ "938dfa29687a689c1499859be9d37dc849ada99d" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon May 09 21:55:19 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jun 15 22:02:13 2022 +0100" }, "message": "fix(gic600): implement workaround to forward highest priority interrupt\n\nIf the interrupt being targeted is released from the CPU before the\nCLEAR command is sent to the CPU then a subsequent SET command may not\nbe delivered in a finite time. To workaround this, issue an unblocking\nevent by toggling GICR_CTLR.DPG* bits after clearing the cpu group\nenable (EnableGrp* bits of GIC CPU interface register)\nThis fix is implemented as per the errata 2384374-part 2 workaround\nmentioned here:\nhttps://developer.arm.com/documentation/sden892601/latest/\n\nChange-Id: I13926ceeb7740fa4c05cc5b43170e7ce49598f70\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "100da90ca84a3265d6312f24df16f920929234a6", "tree": "7c1653c9ccc60b4af3c51fd1080def66a7b2a224", "parents": [ "299d38100a69b2730b76c5d3dde2633662ba5aec", "96f586125822289e9beba126910503c2deba59a9" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 15 17:15:47 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 15 17:15:47 2022 +0200" }, "message": "Merge \"build(changelog): add stm32mp13 and stm32mp15 scopes\" into integration" }, { "commit": "389594dfa7e60a720d60f0d55296f91ba1610de5", "tree": "0d1b97cc74a3e75b3acea3bb04a815cc18f922ad", "parents": [ "299d38100a69b2730b76c5d3dde2633662ba5aec" ], "author": { "name": "Michal Simek", "email": "michal.simek@xilinx.com", "time": "Wed Jun 15 14:19:56 2022 +0200" }, "committer": { "name": "Michal Simek", "email": "michal.simek@xilinx.com", "time": "Wed Jun 15 14:19:56 2022 +0200" }, "message": "fix(zynqmp): move bl31 with DEBUG\u003d1 back to OCM\n\nBy default placing bl31 to addrexx 0x1000 is not good. Because this\nlocation is used by U-Boot SPL. That\u0027s why move TF-A back to OCM where it\nshould be placed. BL31_BASE address exactly matches which requested address\nfor U-BOOT SPL boot flow.\n\nSigned-off-by: Michal Simek \u003cmichal.simek@xilinx.com\u003e\nChange-Id: I608c1b88baffec538c6ae528f057820e34971c4c\n" }, { "commit": "50b449776df11cac06347e8ef1af5dae701a0e3a", "tree": "00e0cd247bda630f1b3e403597627dd9b26bd331", "parents": [ "f24237921e3fa61e64fa1ec845e14e2748d04a2b" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 16:53:37 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "feat(arm): retrieve the right ROTPK for cca\n\nThe cca chain of trust involves 3 root-of-trust public keys:\n- The CCA components ROTPK.\n- The platform owner ROTPK (PROTPK).\n- The secure world ROTPK (SWD_ROTPK).\n\nUse the cookie argument as a key ID for plat_get_rotpk_info() to return\nthe appropriate one.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: Ieaae5b0bc4384dd12d0b616596596b031179044a\n" }, { "commit": "f24237921e3fa61e64fa1ec845e14e2748d04a2b", "tree": "558bae92f135691687d0ae2168dc7a89af707540", "parents": [ "98662a73c903b06f53c9f9da6a9404187fc10352" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 16:50:49 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "feat(arm): add support for cca CoT\n\n- Use the development PROTPK and SWD_ROTPK if using cca CoT.\n\n- Define a cca CoT build flag for the platform code to provide\ndifferent implementations where needed.\n\n- When ENABLE_RME\u003d1, CCA CoT is selected by default on Arm\nplatforms if no specific CoT is specified by the user.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I70ae6382334a58d3c726b89c7961663eb8571a64\n" }, { "commit": "98662a73c903b06f53c9f9da6a9404187fc10352", "tree": "0e2a30a7177fd14e49c308e3c9e219b0637e009a", "parents": [ "1b7d656ac6f6dbc00af422a77b9a5b24fbe0a3c6" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 16:31:07 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "feat(arm): provide some swd rotpk files\n\nWhen using the new cca chain of trust, a new root of trust key is needed\nto authenticate the images belonging to the secure world. Provide a\ndevelopment one to deploy this on Arm platforms.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I9ea7bc1c15c0c94c1021d879a839cef40ba397e3\n" }, { "commit": "1b7d656ac6f6dbc00af422a77b9a5b24fbe0a3c6", "tree": "daa8070c1ad0458755a391ca8c290d0ba6e37825", "parents": [ "d5de70ce28693b19ffeedfcadbe8b6b2616afc0d" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 16:25:52 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "build(tbbr): drive cert_create changes for cca CoT\n\nThe build system needs to drive the cert_create tool in a slightly\ndifferent manner when using the cca chain of trust.\n\n- It needs to pass it the plat, core_swd, and swd ROT key files.\n\n- It must now generate the cca, core_swd, and plat key certificates,\nand exclude the non-relevant certificates.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I5759bfaf06913f86b47c7d04c897773bba16a807\n" }, { "commit": "d5de70ce28693b19ffeedfcadbe8b6b2616afc0d", "tree": "8048656150885f6781aa9c16dc01daf54179a70e", "parents": [ "147f52f3e81f7ccf1dae90bc5687ec137feeb46c" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 17:03:30 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "refactor(arm): add cca CoT certificates to fconf\n\nAdding support in fconf for the cca CoT certificates for cca, core_swd,\nand plat key.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I8019cbcb7ccd4de6da624aebf3611b429fb53f96\n" }, { "commit": "147f52f3e81f7ccf1dae90bc5687ec137feeb46c", "tree": "398cd51fa957da1a9219d4dc6433d65291bf0768", "parents": [ "0a6bf811d7f873a180ef4b9f96f5596b26d270c6" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 16:36:26 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "feat(fiptool): add cca, core_swd, plat cert in FIP\n\nAdded support for cca CoT in the fiptool by adding the cca,\ncore_swd, and plat key certificates.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I1ba559e188ad8c33cb0e643d7a2fc6fb96736ab9\n" }, { "commit": "0a6bf811d7f873a180ef4b9f96f5596b26d270c6", "tree": "20d848e5422b0e1b2195adfffc504a6d595135e6", "parents": [ "56b741d3e41cd6b2f6863a372a9489c819e2b0e9" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 16:21:53 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "feat(cert_create): define the cca chain of trust\n\nSelection of the cca chain of trust is done through the COT build\noption:\n\n\u003e make COT\u003dcca\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I123c0a841f67434633a3123cc1fa3e2318585482\n" }, { "commit": "56b741d3e41cd6b2f6863a372a9489c819e2b0e9", "tree": "8aae35da4e3c78a2206349a53802c6a3b9b260f3", "parents": [ "55ae7715ca7270c768b5ec5fbaf96fe17cc465d2" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Thu Apr 21 15:49:00 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "feat(cca): introduce new \"cca\" chain of trust\n\nThis chain of trust is targeted at Arm CCA solutions and defines 3\nindependent signing domains:\n\n1) CCA signing domain. The Arm CCA Security Model (Arm DEN-0096.A.a) [1]\nrefers to the CCA signing domain as the provider of CCA components\nrunning on the CCA platform. The CCA signing domain might be independent\nfrom other signing domains providing other firmware blobs.\n\nThe CCA platform is a collective term used to identify all hardware and\nfirmware components involved in delivering the CCA security guarantee.\nHence, all hardware and firmware components on a CCA enabled system that\na Realm is required to trust.\n\nIn the context of TF-A, this corresponds to BL1, BL2, BL31, RMM and\nassociated configuration files.\n\nThe CCA signing domain is rooted in the Silicon ROTPK, just as in the\nTBBR CoT.\n\n2) Non-CCA Secure World signing domain. This includes SPMC (and\nassociated configuration file) as the expected BL32 image as well as\nSiP-owned secure partitions. It is rooted in a new SiP-owned key called\nSecure World ROTPK, or SWD_ROTPK for short.\n\n3) Platform owner signing domain. This includes BL33 (and associated\nconfiguration file) and the platform owner\u0027s secure partitions. It is\nrooted in the Platform ROTPK, or PROTPK.\n\n[1] https://developer.arm.com/documentation/DEN0096/A_a\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I6ffef3f53d710e6a2072fb4374401249122a2805\n" }, { "commit": "55ae7715ca7270c768b5ec5fbaf96fe17cc465d2", "tree": "5c24a4b3ec18b6a58b809384d288b10acbfa0231", "parents": [ "25514123a6baef2ccb72037bd37d24d58add31cc" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Jun 01 13:45:39 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:37 2022 -0500" }, "message": "build(changelog): add new scope for CCA\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: Iccba57a292e6668e6a6d93f1cb0e1633592a4009\n" }, { "commit": "25514123a6baef2ccb72037bd37d24d58add31cc", "tree": "04e504d2c0fc39f6a9a798cdd063d3e5dca03196", "parents": [ "7460c41d274edbc3f0236bc5181a63517350a066" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed Jun 08 16:50:42 2022 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Jun 14 09:47:32 2022 -0500" }, "message": "refactor(fvp): increase bl2 size when bl31 in DRAM\n\nIncrease the space for BL2 by 0xC000 to accommodate the increase in size\nof BL2 when ARM_BL31_IN_DRAM is set.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: Ifc99da51f2de3c152bbed1c8269dcc8b9100797a\n" }, { "commit": "299d38100a69b2730b76c5d3dde2633662ba5aec", "tree": "9000e9acd62728657c77045bc4d3a665da09525b", "parents": [ "bc779e162986a350822c3226140fff60f1e71fcf", "39eb5ddbbf98bdb6c012a9d852f489f2f8e15c05" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 13 22:55:09 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 13 22:55:09 2022 +0200" }, "message": "Merge \"fix(errata): workaround for Neoverse-V1 erratum 2294912\" into integration" }, { "commit": "39eb5ddbbf98bdb6c012a9d852f489f2f8e15c05", "tree": "9000e9acd62728657c77045bc4d3a665da09525b", "parents": [ "bc779e162986a350822c3226140fff60f1e71fcf" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Jun 08 16:28:46 2022 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Mon Jun 13 21:15:41 2022 +0200" }, "message": "fix(errata): workaround for Neoverse-V1 erratum 2294912\n\nNeoverse-V1 erratum 2294912 is a cat B erratum that applies to revisions\nr0p0 - r1p1 and is still open. The workaround is to set bit[0] of\nCPUACTLR2_EL1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not\ncause invalidations to other PE caches.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1401781/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ia7afb4c42fe66b36fdf38a7d4281a0d168f68354\n" }, { "commit": "bc779e162986a350822c3226140fff60f1e71fcf", "tree": "f5655364954deab9e03291983cf5eccf9ee470e7", "parents": [ "cadd6afcc1306ca142e411875de2baae30da64b9", "86869f99d0c144ed18fb947866554a4a56b67741" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 13 20:12:31 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 13 20:12:31 2022 +0200" }, "message": "Merge \"feat(zynqmp): add support for xck24 silicon\" into integration" }, { "commit": "cadd6afcc1306ca142e411875de2baae30da64b9", "tree": "e0b5e9a33645d638cddad718fa45bd0d236f77e6", "parents": [ "aaf1d8df0d7c3ae16d417b0cb8c2f2a14ff58ec8", "d20052f33a3ee4ed7e72e6b0aab609a4db06570e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 13 14:18:57 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 13 14:18:57 2022 +0200" }, "message": "Merge \"refactor(context mgmt): refactor EL2 context save and restore functions\" into integration" }, { "commit": "aaf1d8df0d7c3ae16d417b0cb8c2f2a14ff58ec8", "tree": "0c69f78dd8c82310986c775d64aa5cacbe135cfa", "parents": [ "7460c41d274edbc3f0236bc5181a63517350a066", "47c681b7d7f03e77f6cdd7b5d116ae64671ab8ca" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jun 10 11:57:12 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 10 11:57:12 2022 +0200" }, "message": "Merge changes from topic \"jc/detect_feat\" into integration\n\n* changes:\n feat(trbe): add trbe under feature detection mechanism\n feat(brbe): add brbe under feature detection mechanism\n" }, { "commit": "7460c41d274edbc3f0236bc5181a63517350a066", "tree": "8fc622860a5071683f6e9a21d764e0d60ead81e4", "parents": [ "65841e6660b64c23caff50f0cacb7694a90bf995", "86b015eb1be57439c2a01cb35d800c7f1b5c8467" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 09 16:23:04 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 09 16:23:04 2022 +0200" }, "message": "Merge \"fix(mmc): remove broken, unsecure, unused eMMC RPMB handling\" into integration" }, { "commit": "d20052f33a3ee4ed7e72e6b0aab609a4db06570e", "tree": "ff8f85a0a3b643fec89ed4cd1b27afbff10dc385", "parents": [ "65a5e1c04df56dbc0feb270fbae13c884020a5b9" ], "author": { "name": "Zelalem Aweke", "email": "zelalem.aweke@arm.com", "time": "Mon Apr 04 17:42:48 2022 -0500" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jun 08 12:48:41 2022 +0100" }, "message": "refactor(context mgmt): refactor EL2 context save and restore functions\n\nThis patch splits the el2_sysregs_context_save/restore functions\ninto multiple functions based on features. This will allow us to\nselectively save and restore EL2 context registers based on\nfeatures enabled for a particular configuration.\n\nFor now feature build flags are used to decide which registers\nto save and restore. The long term plan is to dynamically check\nfor features that are enabled and then save/restore registers\naccordingly. Splitting el2_sysregs_context_save/restore functions\ninto smaller assembly functions makes that task easier. For more\ninformation please take a look at:\nhttps://trustedfirmware-a.readthedocs.io/en/latest/design_documents/context_mgmt_rework.html\n\nSigned-off-by: Zelalem Aweke \u003czelalem.aweke@arm.com\u003e\nChange-Id: I1819a9de8b70fa35c8f45568908025f790c4808c\n" }, { "commit": "65841e6660b64c23caff50f0cacb7694a90bf995", "tree": "fc8544c79c9909596dc86a5154259321b387e532", "parents": [ "925ce7913601e75913809b35a87d3097cecb083a", "fb00dc4a7b208cf416d082bb4367b54286bc8e3b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Jun 08 13:37:33 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 08 13:37:33 2022 +0200" }, "message": "Merge \"fix(rme/fid): refactor RME fid macros\" into integration" }, { "commit": "86b015eb1be57439c2a01cb35d800c7f1b5c8467", "tree": "67da435b12f41e4dc2a55d1dd705329ae1bc1ea2", "parents": [ "925ce7913601e75913809b35a87d3097cecb083a" ], "author": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Wed Jun 08 08:42:24 2022 +0200" }, "committer": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Wed Jun 08 08:57:05 2022 +0200" }, "message": "fix(mmc): remove broken, unsecure, unused eMMC RPMB handling\n\nReplay-protected memory block access is enabled by writing 0x3\nto PARTITION_ACCESS (bit[2:0]). Instead the driver is using the\nfirst boot partition, which does not provide any playback protection.\nAdditionally, it unconditionally activates the first boot partition,\npotentially breaking boot for SoCs that consult boot partitions,\nrequire boot ack or downgrading to an old bootloader if the first\npartition happens to be the inactive one.\n\nAlso, neither enabling or disabling the RPMB observes the\nPARTITION_SWITCH_TIME. As there are no in-tree users for these\nfunctions, drop them for now until a properly functional implementation\nis added. That one will likely share most code with the existing boot\npartition switch, which doesn\u0027t suffer from the described issues.\n\nChange-Id: Ia4a3f738f60a0dbcc33782f868cfbb1e1c5b664a\nSigned-off-by: Ahmad Fatoum \u003ca.fatoum@pengutronix.de\u003e\n" }, { "commit": "925ce7913601e75913809b35a87d3097cecb083a", "tree": "e7499210775fb2c5ba60446374d4e60b17068078", "parents": [ "60942bc9d545989ad10005a321b46c41d6e2910a", "95e4908e17fbb44aed1f8612fefdd6d21fef8f49" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 08 00:14:59 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 08 00:14:59 2022 +0200" }, "message": "Merge changes from topic \"stm32mp-emmc-boot-fip\" into integration\n\n* changes:\n feat(stm32mp1): extend STM32MP_EMMC_BOOT support to FIP format\n refactor(mmc): replace magic value with new PART_CFG_BOOT_PARTITION_NO_ACCESS\n refactor(mmc): export user/boot partition switch functions\n" }, { "commit": "60942bc9d545989ad10005a321b46c41d6e2910a", "tree": "3a04d7b099e7b9c580ca229b545600785d24e040", "parents": [ "65a5e1c04df56dbc0feb270fbae13c884020a5b9", "44fea93bf729f631f6ae47e06ac7b6012a795791" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 07 16:47:12 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 07 16:47:12 2022 +0200" }, "message": "Merge changes from topic \"st-pinctrl\" into integration\n\n* changes:\n feat(stm32mp1-fdts): change pin-controller to pinctrl\n feat(st): search pinctrl node by compatible\n" }, { "commit": "44fea93bf729f631f6ae47e06ac7b6012a795791", "tree": "3a04d7b099e7b9c580ca229b545600785d24e040", "parents": [ "b14d3e22b4964ce589d107e7fd68601bf070f44c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 11 14:23:43 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jun 07 15:36:37 2022 +0200" }, "message": "feat(stm32mp1-fdts): change pin-controller to pinctrl\n\nDue to commit updating kernel yaml file [1], we need to align TF-A DT\nfiles to what is done in kernel.\n\n[1] c09acbc499e8 (\"dt-bindings: pinctrl: use pinctrl.yaml\")\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Id717162e42d3959339d6c01883e87a9d4399f5d9\n" }, { "commit": "b14d3e22b4964ce589d107e7fd68601bf070f44c", "tree": "95c8ce46997f5394ff00b5b9d4d8286caa2385bc", "parents": [ "65a5e1c04df56dbc0feb270fbae13c884020a5b9" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 11 14:18:13 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jun 07 15:36:24 2022 +0200" }, "message": "feat(st): search pinctrl node by compatible\n\nInstead of searching pinctrl node with its name, search with its\ncompatible. This will be necessary before pin-controller name changes\nto pinctrl due to kernel yaml changes.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I00590414fa65e193c6a72941a372bcecac673f60\n" }, { "commit": "65a5e1c04df56dbc0feb270fbae13c884020a5b9", "tree": "5eab170b415538b557bc10f21ef335d6ce6a45bb", "parents": [ "938dfa29687a689c1499859be9d37dc849ada99d", "c1284a7f93309c88fd781d2b4720f742e147284e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 07 14:05:42 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 07 14:05:42 2022 +0200" }, "message": "Merge \"fix(changelog): fix the broken link to commitlintrc.js\" into integration" }, { "commit": "c1284a7f93309c88fd781d2b4720f742e147284e", "tree": "4a8bec45392205dea0bf41feb5a186da8a9fd40d", "parents": [ "5e529e32ee6cf6ac9203ada4fade49a47893fa51" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jun 07 12:01:41 2022 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Jun 07 12:06:18 2022 +0100" }, "message": "fix(changelog): fix the broken link to commitlintrc.js\n\nThe link to commitlintrc.js file in the v2.7 changelog\nis updated.\n\nChange-Id: I24ee736180d8df72b2d831e110a9a3a80a6d9862\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "86869f99d0c144ed18fb947866554a4a56b67741", "tree": "f911deb9193c8a97a6399b8551636882bc29653b", "parents": [ "5e529e32ee6cf6ac9203ada4fade49a47893fa51" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Tue May 17 09:39:30 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Tue Jun 07 10:03:34 2022 +0530" }, "message": "feat(zynqmp): add support for xck24 silicon\n\nAdd support for new xck24 device.\n\nSigned-off-by: Michal Simek \u003cmichal.simek@xilinx.com\u003e\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I913a34d5a48ea665aaa4348f573fc59566dd5a9b\n" }, { "commit": "fb00dc4a7b208cf416d082bb4367b54286bc8e3b", "tree": "9ebe78a3f3b0ab214b475bde666a64dde23a9c07", "parents": [ "5e529e32ee6cf6ac9203ada4fade49a47893fa51" ], "author": { "name": "Subhasish Ghosh", "email": "subhasish.ghosh@arm.com", "time": "Thu May 12 12:22:17 2022 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jun 06 17:15:15 2022 +0200" }, "message": "fix(rme/fid): refactor RME fid macros\n\nRefactored RME FID macros to simplify usage.\n\nSigned-off-by: Subhasish Ghosh \u003csubhasish.ghosh@arm.com\u003e\nChange-Id: I68f51f43d6c100d90069577412c2e495fe7b7e40\n" }, { "commit": "938dfa29687a689c1499859be9d37dc849ada99d", "tree": "8dab1942020a543213d716508b5529d62eed1b91", "parents": [ "8634793e97141909891e01e9bdceb1af7cc0f877", "66345b8b13dc32bcd9f6af3c04f60532e7d82858" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 06 16:18:20 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 06 16:18:20 2022 +0200" }, "message": "Merge \"feat(imx8mq): add 100us delay after USB OTG SRC bit 0 clear\" into integration" }, { "commit": "8634793e97141909891e01e9bdceb1af7cc0f877", "tree": "0c252a440e2cda20eec2baab8d09ff2df2e42e8a", "parents": [ "5e529e32ee6cf6ac9203ada4fade49a47893fa51", "21189b8e21062b71c9056ac1cf60d25bb018007c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Jun 06 16:17:00 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jun 06 16:17:00 2022 +0200" }, "message": "Merge \"fix(imx8mq): correct architected counter frequency\" into integration" }, { "commit": "47c681b7d7f03e77f6cdd7b5d116ae64671ab8ca", "tree": "652c6f189572f4573dceafa6da2b7bf917789d85", "parents": [ "1298f2f13d6d97dfcac120a2ee68d5eea3797068" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu May 19 14:08:28 2022 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Jun 06 11:43:14 2022 +0100" }, "message": "feat(trbe): add trbe under feature detection mechanism\n\nThis change adds \"FEAT_TRBE\" to be part of feature detection mechanism.\n\nPreviously feature enablement flags were of boolean type, containing\neither 0 or 1. With the introduction of feature detection procedure\nwe now support three states for feature enablement build flags(0 to 2).\n\nAccordingly, \"ENABLE_TRBE_FOR_NS\" flag is now modified from boolean\nto numeric type to align with the feature detection.\n\nChange-Id: I53d3bc8dc2f6eac63feef22dfd627f3a48480afc\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "1298f2f13d6d97dfcac120a2ee68d5eea3797068", "tree": "bf1b1da903dd38efcbc1b4524f8536c172528312", "parents": [ "5e529e32ee6cf6ac9203ada4fade49a47893fa51" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon May 09 12:33:03 2022 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Jun 06 11:43:03 2022 +0100" }, "message": "feat(brbe): add brbe under feature detection mechanism\n\nThis change adds \"FEAT_BRBE\" to be part of feature detection mechanism.\n\nPreviously feature enablement flags were of boolean type, possessing\neither 0 or 1. With the introduction of feature detection procedure\nwe now support three states for feature enablement build flags(0 to 2).\n\nAccordingly, \"ENABLE_BRBE_FOR_NS\" flag is now modified from boolean\nto numeric type to align with the feature detection.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I1eb52863b4afb10b808e2f0b6584a8a210d0f38c\n" }, { "commit": "7b1a6a08ccc7522687f66e6e989bbc597d08ab06", "tree": "0b58f8cb90359cba84f48c604ec6ba8930f5a4e9", "parents": [ "ffa910312c371080f4d0d50eb1354ad05b7be7a8" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Thu May 19 17:23:35 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Mon Jun 06 11:19:44 2022 +0530" }, "message": "fix(zynqmp): resolve the misra 8.6 warnings\n\nMISRA Violation: MISRA-C:2012 R.8.6\n- Function is declared but never defined.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I0df53ef4b2c91fa8ec3bf3e5491bf37dd7400685\n" }, { "commit": "ffa910312c371080f4d0d50eb1354ad05b7be7a8", "tree": "b35e689f94ea4d1f83d2b906d3d5226910724a38", "parents": [ "5e529e32ee6cf6ac9203ada4fade49a47893fa51" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Thu May 19 14:49:49 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Mon Jun 06 11:18:03 2022 +0530" }, "message": "fix(zynqmp): resolve the misra 4.6 warnings\n\nMISRA Violation: MISRA-C:2012 R.4.6\n- Using basic numerical type int rather than a typedef\nthat includes size and signedness information.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I9fb686e7aa2b85af6dfcb7bb5f87eddf469fb85c\n" }, { "commit": "5e529e32ee6cf6ac9203ada4fade49a47893fa51", "tree": "ab1fe8ba99ce8200cccb36c8e6988a1099ae923e", "parents": [ "950dc3a191e9bb7ba99617a7ed07c04f9b125deb", "1ac6af1199e2d14492a9d75aaba69bc775e55bd8" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jun 03 19:44:00 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jun 03 19:44:00 2022 +0200" }, "message": "Merge \"fix(plat/zynqmp): fix coverity scan warnings\" into integration" }, { "commit": "950dc3a191e9bb7ba99617a7ed07c04f9b125deb", "tree": "704c45701df8b83f490e606e2146c2dd46e823d1", "parents": [ "67656351782b182f831c315f4b1683a14328ad1b", "314f9f7957fbab12dc8d073cf054b99520372e0e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 02 19:33:24 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 02 19:33:24 2022 +0200" }, "message": "Merge \"feat(plat/xilinx/zynqmp): optimization on pinctrl_functions\" into integration" }, { "commit": "67656351782b182f831c315f4b1683a14328ad1b", "tree": "80fea4773356f3859d07ee805e9b867bebb3b28b", "parents": [ "ed96c5322f9f44037bc30110fd553b9672168a51", "cad90b569db7c547470cca922bd93207adcadfad" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 02 17:39:57 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 02 17:39:57 2022 +0200" }, "message": "Merge changes Idafbe02d,Ib01eb5ce into integration\n\n* changes:\n fix(scmi-msg): base: fix protocol list querying\n fix(scmi-msg): base: fix protocol list response size\n" }, { "commit": "95e4908e17fbb44aed1f8612fefdd6d21fef8f49", "tree": "f8b0e5ae9bd706d7cfa7240e794426ad460c16dc", "parents": [ "01c5dd5e59d421b796f1033e92e6ec88d7e1b29b" ], "author": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Thu May 19 07:42:33 2022 +0200" }, "committer": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Thu Jun 02 17:28:33 2022 +0200" }, "message": "feat(stm32mp1): extend STM32MP_EMMC_BOOT support to FIP format\n\nSTM32MP_EMMC_BOOT allowed placing SSBL into the eMMC boot\npartition along with FSBL. This allows atomic update of both\nFSBL and SSBL at the same time. Previously, this was only\npossible for the FSBL, as the eMMC layout expected by TF-A\nhad a single SSBL GPT partition in the eMMC user area.\nTEE binaries remained in dedicated GPT partitions whether\nSTM32MP_EMMC_BOOT was on or off.\n\nThe new FIP format collects SSBL and TEE partitions into\na single binary placed into a GPT partition.\nExtend STM32MP_EMMC_BOOT, so eMMC-booted TF-A first uses\na FIP image placed at offset 256K into the active eMMC boot\npartition. If no FIP magic is detected at that offset or if\nSTM32MP_EMMC_BOOT is disabled, the GPT on the eMMC user area\nwill be consulted as before.\n\nThis allows power fail-safe update of all firmware using the\nbuilt-in eMMC boot selector mechanism, provided it fits into\nthe boot partition - SZ_256K. SZ_256K was chosen because it\u0027s\nthe same offset used with the legacy format and because it\u0027s\nthe size of the on-chip SRAM, where the STM32MP15x BootROM\nloads TF-A into. As such, TF-A may not exceed this size limit\nfor existing SoCs.\n\nSigned-off-by: Ahmad Fatoum \u003ca.fatoum@pengutronix.de\u003e\nChange-Id: Id7bec45652b3a289ca632d38d4b51316c5efdf8d\n" }, { "commit": "01c5dd5e59d421b796f1033e92e6ec88d7e1b29b", "tree": "8e2d51e2da03291572b7c451ec9880e5d1e19ef0", "parents": [ "f85041a657d9cf92a6ff9c08c936cac4b2036050" ], "author": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Tue May 31 10:03:04 2022 +0200" }, "committer": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Thu Jun 02 17:28:33 2022 +0200" }, "message": "refactor(mmc): replace magic value with new PART_CFG_BOOT_PARTITION_NO_ACCESS\n\nDisabling access to the boot partition reverts the MMC to read from the\nuser area. Add a macro to make this clearer.\n\nSuggested-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nSigned-off-by: Ahmad Fatoum \u003ca.fatoum@pengutronix.de\u003e\nChange-Id: I34a5a987980bb4690d08d255f465b11a4697ed5a\n" }, { "commit": "f85041a657d9cf92a6ff9c08c936cac4b2036050", "tree": "ec0e2c6b76d2674c82a68c9e491f725d23be58ca", "parents": [ "ed96c5322f9f44037bc30110fd553b9672168a51" ], "author": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Mon May 23 17:06:37 2022 +0200" }, "committer": { "name": "Ahmad Fatoum", "email": "a.fatoum@pengutronix.de", "time": "Thu Jun 02 17:28:03 2022 +0200" }, "message": "refactor(mmc): export user/boot partition switch functions\n\nAt the moment, mmc_boot_part_read_blocks() takes care to switch\nto the boot partition before transfer and back afterwards.\nThis can introduce large overhead when reading small chunks.\nGive consumers of the API more control by exporting\nmmc_part_switch_current_boot() and mmc_part_switch_user().\n\nSigned-off-by: Ahmad Fatoum \u003ca.fatoum@pengutronix.de\u003e\nChange-Id: Ib641f188071bb8e0196f4af495ec9ad4a292284f\n" }, { "commit": "ed96c5322f9f44037bc30110fd553b9672168a51", "tree": "50d887696ce221b6571a86e3a5c8f215f7ea07e1", "parents": [ "87f76d31409120eed2924f457e78807223884749", "c32ab75c41adfe28a60f1ff159012a7d78e72fdc" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 02 17:26:53 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 02 17:26:53 2022 +0200" }, "message": "Merge \"fix(lib/psa): fix Null pointer dereference error\" into integration" }, { "commit": "87f76d31409120eed2924f457e78807223884749", "tree": "83b0ef358dd723470d531f3a4886f11b2b68a85d", "parents": [ "35f4c7295bafeb32c8bcbdfb6a3f2e74a57e732b", "9eed71b7221c5fc7ed887f1087e42c9f1a62f581" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 02 17:12:24 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 02 17:12:24 2022 +0200" }, "message": "Merge \"fix(stm32mp1): fdts: stm32mp1: align DDR regulators with new driver\" into integration" } ], "next": "96f586125822289e9beba126910503c2deba59a9" }