1. 8e53b2f fix(intel): fix UART baud rate and clock by Sieu Mun Tang · 1 year, 10 months ago
  2. ad47f14 feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands by Sieu Mun Tang · 2 years ago
  3. f0f631f Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration by Madhukar Pappireddy · 2 years ago
  4. f65bdf3 feat(intel): implement timer init divider via cpu frequency. (#1) by BenjaminLimJL · 2 years ago
  5. 11f4f03 feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge by Sieu Mun Tang · 2 years ago
  6. 447e699 feat(intel): add macro to switch between different UART PORT by Boon Khai Ng · 2 years, 8 months ago
  7. 39f262c build(intel): enable access to on-chip ram in BL31 for N5X by Boon Khai Ng · 2 years, 11 months ago
  8. f571183 fix(intel): make FPGA memory configurations platform specific by Sieu Mun Tang · 2 years, 2 months ago
  9. c703d75 fix(intel): fix ECC Double Bit Error handling by Sieu Mun Tang · 2 years, 1 month ago
  10. 1f1c020 build(intel): define a macro for SIMICS build by Abdul Halim, Muhammad Hadi Asyrafi · 3 years, 10 months ago
  11. 325eb35 build(intel): add N5X as a new Intel platform by Sieu Mun Tang · 2 years, 1 month ago