)]}' { "log": [ { "commit": "71f2239f53cd3137ad6abdaf0334dc53f2f21cb1", "tree": "552dc68e941d81084d65bd795d13d823153c3b80", "parents": [ "14f0a0817297905c03ddf2c4c6040482ef71d744" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:20:24 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3\n\nBecause the Realtime module stop control register n (RMSTPCRn)\nare not supported in R-Car D3. Therefore, remove access to these\nregisters in R-Car D3.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I4647e28d0e176ff97151e9842019ba12cefe5c03\n" }, { "commit": "14f0a0817297905c03ddf2c4c6040482ef71d744", "tree": "11d0fc72beff801e97b61ad802a59eed0bf8c696", "parents": [ "7d58aed3b05fa8c677a7c823c1ca5017a462a3d3" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:19:39 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): add process of SSCG setting for R-Car D3\n\n- Added the condition where output the SSCG (MD12) setting\n to log for R-Car D3.\n- Added the process to switching the bit rate of SCIF by the\n SSCG (MD12) setting value for R-Car D3.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9\n" }, { "commit": "7d58aed3b05fa8c677a7c823c1ca5017a462a3d3", "tree": "ccd0ccdbe8e2b7ecb163ef464391eaf4bf3351e2", "parents": [ "d10f87674ecee54cffe1ab554cc05733fd16c7f0" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:17:12 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): add process to back up X6 and X7 register\u0027s value\n\nBecause the x6 and x7 registers will be overwritten by the callee function,\nadded the processing the register\u0027s value push to/pop from stack memory.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8\n" }, { "commit": "d10f87674ecee54cffe1ab554cc05733fd16c7f0", "tree": "4e7b94aa659ab0a279eb278b5f5d55264cbde221", "parents": [ "63a7a34706eedba4d13ce6fc661a634801cf8909" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:14:11 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR\n\nModified the operation register to clearing the state bit of\nthe SYSCISR register from SYSCISR to SYSCISCR.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I9a0820b6414425fa2f4197f60852137827414a4d\n" }, { "commit": "63a7a34706eedba4d13ce6fc661a634801cf8909", "tree": "098f8edad273ff30e97af128928b1a05af5daf16", "parents": [ "a4d821a5a625d941f95ec39fb51ac4fc07c46c5c" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:13:17 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up\n\nAdded the process of SYSECEXTMASK bit set/clear for following\npower Resume/Shutoff flow.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b\n" }, { "commit": "a4d821a5a625d941f95ec39fb51ac4fc07c46c5c", "tree": "1009e257f4c4bde464029ab66e0ae08c02b01575", "parents": [ "42ffd279dd1a686b19e2f1b69d2e35413d5efeba" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 18:43:26 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): change the memory map for OP-TEE\n\nThe memory area size of OP-TEE was changed from 1MB to 2MB\nbecause the size of OP-TEE has increased.\n\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: Ic8a165c83a3a9ef2829f68d5fabeed9ccb6da95e\n" }, { "commit": "42ffd279dd1a686b19e2f1b69d2e35413d5efeba", "tree": "5b2453c739d55c9129938d4ee8cdb51c81cb3340", "parents": [ "2892fedaf27d8bbc68780a4a2c506c768e81b9f1" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:05:06 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): use PRR cut to determine DRAM size on M3\n\nThe new M3 DRAM size can be determined by the PRR cut version.\nRead the PRR cut version, and if it is older than cut 30, use\nlegacy DRAM size scheme, else report 8GB in 2GBx4 2ch split.\n\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nSigned-off-by: Marek Vasut \u003cmarek.vasut+renesas@gmail.com\u003e # Fix DRAM size judgment by PRR register, reword commit message\nChange-Id: Ib83176d0d09cab5cae0119ba462e42c66c642798\n" }, { "commit": "2892fedaf27d8bbc68780a4a2c506c768e81b9f1", "tree": "2fe29cd71847bc94c72acda2f49ad57ad8e75e0c", "parents": [ "a8c0c3e9d0df2215ed3b9ef66f4596787d957566" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:28:58 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537\n\nApply ERRATA_A53_1530924 and ERRATA_A57_1319537.\n\nSigned-off-by: Koichi Yamaguchi \u003ckoichi.yamaguchi.zb@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nSigned-off-by: Marek Vasut \u003cmarek.vasut+renesas@gmail.com\u003e # Drop Makefile header change, reword commit message\nChange-Id: I7d6e7e40bad6545a1d96470ce1a6e2d04e042670\n" }, { "commit": "a8c0c3e9d0df2215ed3b9ef66f4596787d957566", "tree": "eb077da42bf113d2238ca2a46ba1dfceea6248f0", "parents": [ "77ab3661e55c39694c7ee81de2d1615775711b64" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:39:19 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3\n\nFix disabling MFIS write protection for R-Car D3.\n\nSigned-off-by: Koichi Yamaguchi \u003ckoichi.yamaguchi.zb@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I8bb5787c09c53dff55d6de89adfcb71157533976\n" }, { "commit": "77ab3661e55c39694c7ee81de2d1615775711b64", "tree": "3ddfbc99cf010805b0035311170dc645424da3d7", "parents": [ "c3d192b8e52823dcbc32e21e47c30693d38bb49f" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:25:09 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "fix(plat/rcar3): fix eMMC boot support for R-Car D3\n\nFix to support of booting from eMMC (50MHz x 8) on\nDraak board for R-Car D3.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I0ab2b5c7f8075acbf5f4a69694fb535dddc1a4c8\n" }, { "commit": "c3d192b8e52823dcbc32e21e47c30693d38bb49f", "tree": "e82aeccb327a0a5846a21b598d4da5414471cba6", "parents": [ "fb3406b6b573cb0b35138ca3c89c5641d3d7b790" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:18:57 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "fix(plat/rcar3): fix version judgment for R-Car D3\n\nAdded the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I326aa42374b70b6a4a71893561a7eaa0b6eddef0\n" }, { "commit": "fb3406b6b573cb0b35138ca3c89c5641d3d7b790", "tree": "867a627315b746e56513402bd217e0e1da0999e7", "parents": [ "bb273e3be1c4f1cddeac9ceaac95fb56e41e6b98" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:43:45 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "fix(plat/rcar3): fix source file to make about GICv2\n\nChanged the plat/renesas/common/common.mk to change the source files\nabout GICv2 by include gicv2.mk, because gic_common.c has deprecated.\n\nSigned-off-by: Hideyuki Nitta \u003chideyuki.nitta.jf@hitachi.com\u003e\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: Iaa7eae6b2c1dd79a05339325e6bc422d87bce49e\n" }, { "commit": "bb273e3be1c4f1cddeac9ceaac95fb56e41e6b98", "tree": "6290ddb885964df91ed2e97bee8f80524fedf971", "parents": [ "02950791622f1109aa633baf5977f954f76427c3" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 18:58:23 2021 +0900" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@gmail.com", "time": "Sun Sep 12 01:13:48 2021 +0200" }, "message": "fix(drivers/rcar3): console: fix a return value of console_rcar_init\n\nThis commit fixes a return value of console_rcar_init because it is\nexpected to return 1 on success but the function always returns 0.\n\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nChange-Id: I97a6800578e3c517c0c1e3c00dc75f0ef75e8778\n" }, { "commit": "02950791622f1109aa633baf5977f954f76427c3", "tree": "41baba8601c88e374903c65542341bf3fb52487d", "parents": [ "a4ea205025cdd85e87cad6a1c90b0c98ef4ab5bb", "c69f815b09ab85d3ace8fd2979ffafb1184ec76c" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Fri Sep 10 17:17:46 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 10 17:17:46 2021 +0200" }, "message": "Merge changes from topic \"gic-700-auto\" into integration\n\n* changes:\n feat(arm_fpga): support GICv4 images\n feat(gicv3): detect GICv4 feature at runtime\n feat(gicv3): multichip: detect GIC-700 at runtime\n refactor(gic): move GIC IIDR numbers\n refactor(gicv3): rename GIC Clayton to GIC-700\n" }, { "commit": "a4ea205025cdd85e87cad6a1c90b0c98ef4ab5bb", "tree": "e0bb86260c9bc969fb50890553e0680b622e6744", "parents": [ "0a948cd2aa18a3be76a9f78cf463742319480cd4", "975563dbfc012b6e8a7765dd8e48220e1bc53dec" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Sep 10 01:02:56 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 10 01:02:56 2021 +0200" }, "message": "Merge \"fix(plat/marvell/a3k): enable workaround for erratum 1530924\" into integration" }, { "commit": "0a948cd2aa18a3be76a9f78cf463742319480cd4", "tree": "81e4896469ce4572335e9e82ab612227aa6dccfc", "parents": [ "9ecf943889e66c435a538c71cfb8214ace5af9bb", "d0bbe8150eb35fe2bac1567751bf84a8f073dd39" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 09 20:48:04 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 20:48:04 2021 +0200" }, "message": "Merge \"fix(docs-contributing.rst): fix formatting for code snippet\" into integration" }, { "commit": "9ecf943889e66c435a538c71cfb8214ace5af9bb", "tree": "739c2a639f896877ce23886fd61e169798b7c41c", "parents": [ "2ed0c59bd0a54926d3e0935155a59e6e936df735", "07f81627ab38f488b3780023c5fd9633ce9209c8" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:49:44 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:49:44 2021 +0200" }, "message": "Merge \"docs(stm32mp1): update doc for FIP/FCONF\" into integration" }, { "commit": "2ed0c59bd0a54926d3e0935155a59e6e936df735", "tree": "69676111e1e4ebbc75137024d0c0996721401031", "parents": [ "d3f91e242ae858e459a3cda64cc0abbb69b59ce8", "4584e01dc643665038004f6c8a4f8bd64e14dacb" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:49:27 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:49:27 2021 +0200" }, "message": "Merge \"feat(plat/st): add a new DDR firewall management\" into integration" }, { "commit": "d3f91e242ae858e459a3cda64cc0abbb69b59ce8", "tree": "7986cea0fcdacc5e143e4d00fde0b7dd6d03f676", "parents": [ "20a20538f8e6aa40b91ed596bfe1ff5a123222c4", "ce7ef9d146ce5ca6b9be5ef049377b3817d53d10" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:49:06 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:49:06 2021 +0200" }, "message": "Merge \"feat(tzc400): update filters by region\" into integration" }, { "commit": "20a20538f8e6aa40b91ed596bfe1ff5a123222c4", "tree": "510ca96285c2bee2e654eda9d8bcac159639a1d0", "parents": [ "d114a382c7fd795decb4cb65b481b2d86b58b30c", "86b43c58a4105c8cef13d860dd73fa9bd560526a" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:48:48 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:48:48 2021 +0200" }, "message": "Merge \"feat(fdts): add firewall regions into STM32MP1 DT\" into integration" }, { "commit": "d114a382c7fd795decb4cb65b481b2d86b58b30c", "tree": "881b670d69d41af541a6c95c399e327d3d53c91f", "parents": [ "282da3c323b229ce3ed2f8045ed0d9917d3607b2", "3cc5155c8485fa7d991c145ec2a15eced1447824" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:48:29 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:48:29 2021 +0200" }, "message": "Merge changes from topic \"st_fip_fconf\" into integration\n\n* changes:\n refactor(plat/st): use TZC400 bindings\n feat(dt-bindings): add STM32MP1 TZC400 bindings\n" }, { "commit": "282da3c323b229ce3ed2f8045ed0d9917d3607b2", "tree": "d73782ae701958e2d8e291db0fe43162407d0e39", "parents": [ "ded5979c7958e3146bc0f6e9a7e391b52fffca58", "d5a84eeaac2c8ce14d3f2662dc9523b4abf41516" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:46:38 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:46:38 2021 +0200" }, "message": "Merge changes from topic \"st_fip_fconf\" into integration\n\n* changes:\n feat(plat/st): manage io_policies with FCONF\n feat(fdts): add IO policies for STM32MP1\n" }, { "commit": "ded5979c7958e3146bc0f6e9a7e391b52fffca58", "tree": "7703cbdba2f76646018ede92887d1ad567d73e66", "parents": [ "4b431230e58a9d9c72b0c0ebb0333472178da71b", "29332bcd680ce7e5f864813d9a900360f5e35d41" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:46:22 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:46:22 2021 +0200" }, "message": "Merge changes from topic \"st_fip_fconf\" into integration\n\n* changes:\n feat(plat/st): use FCONF to configure platform\n feat(fdts): add STM32MP1 fw-config DT files\n" }, { "commit": "4b431230e58a9d9c72b0c0ebb0333472178da71b", "tree": "00db072e0ae18d46f55579438b1dbf2997000bfb", "parents": [ "6c7cc938f161275cf37223bd4a34fc87de8d008c", "18b415be9d631b3e0c3a3caacc5f02edb9413f6b" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:46:03 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:46:03 2021 +0200" }, "message": "Merge \"feat(plat/st): improve FIP image loading from MMC\" into integration" }, { "commit": "6c7cc938f161275cf37223bd4a34fc87de8d008c", "tree": "3f6a8b23207d3ce5865deeccbfce25afc3df9228", "parents": [ "5a7b2584dbcb70df13ede91af6305f7a75abcfef", "1d204ee4ab12893fceb12097bd4f0a074be253b2" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu Sep 09 17:45:44 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 17:45:44 2021 +0200" }, "message": "Merge changes from topic \"st_fip_fconf\" into integration\n\n* changes:\n feat(plat/st): use FIP to load images\n refactor(plat/st): updates for OP-TEE\n feat(lib/optee): introduce optee_header_is_valid()\n" }, { "commit": "d0bbe8150eb35fe2bac1567751bf84a8f073dd39", "tree": "bd70fc5502bec511ef8efb405745b41fd483a6a2", "parents": [ "5a7b2584dbcb70df13ede91af6305f7a75abcfef" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Sep 09 14:23:10 2021 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Sep 09 14:25:16 2021 +0100" }, "message": "fix(docs-contributing.rst): fix formatting for code snippet\n\nThis patch will fix the formatting errors concerning code snippet,\nlines 245 and 256 respectively.\nThe code snippet is updated to \u0027shell\u0027 to lex it appropriately.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I53aefd81da350b6511e7a97b5fee7b0d6f9dde2d\n" }, { "commit": "5a7b2584dbcb70df13ede91af6305f7a75abcfef", "tree": "b1e8ff66306d7f8b6baa460a9e2557300e47b2d9", "parents": [ "ab0c8151bce67fed39962faf8bea1bf33b1cb141", "a669983c78828e3f4a4f14b9e5a6ee79dcfde20f" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 09 00:32:08 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 09 00:32:08 2021 +0200" }, "message": "Merge \"fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode\" into integration" }, { "commit": "975563dbfc012b6e8a7765dd8e48220e1bc53dec", "tree": "9d29ead9a0f05a368fd28422a1fb01489f2069c8", "parents": [ "ab0c8151bce67fed39962faf8bea1bf33b1cb141" ], "author": { "name": "Marek Behún", "email": "marek.behun@nic.cz", "time": "Thu Aug 26 17:29:45 2021 +0200" }, "committer": { "name": "Marek Behún", "email": "marek.behun@nic.cz", "time": "Wed Sep 08 14:05:43 2021 +0200" }, "message": "fix(plat/marvell/a3k): enable workaround for erratum 1530924\n\nErratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53\nrevisions from r0p0 to r0p4.\n\nEnable the workaround for this erratum.\n\nSigned-off-by: Marek Behún \u003cmarek.behun@nic.cz\u003e\nChange-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8\n" }, { "commit": "07f81627ab38f488b3780023c5fd9633ce9209c8", "tree": "426ead0c35ef7aa63000e3ff7bc95db52d9d4c30", "parents": [ "4584e01dc643665038004f6c8a4f8bd64e14dacb" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Feb 12 18:04:23 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Sep 08 09:05:16 2021 +0200" }, "message": "docs(stm32mp1): update doc for FIP/FCONF\n\nDescribe the boot using FIP, and how to compile it.\nThe STM32IMAGE boot chain is still available but it is not recommended.\nUpdate the build command lines, for FIP.\nThe memory mapping is also updated.\n\nChange-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "4584e01dc643665038004f6c8a4f8bd64e14dacb", "tree": "77e8df784fe8c733892799fda71760267e91a9b5", "parents": [ "ce7ef9d146ce5ca6b9be5ef049377b3817d53d10" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Sun Sep 27 21:13:53 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Sep 08 09:05:16 2021 +0200" }, "message": "feat(plat/st): add a new DDR firewall management\n\nBased on FCONF framework, define DDR firewall regions\nfrom firmware config file instead of static defines.\n\nChange-Id: I471e15410ca286d9079a86e3dc3474f66d37b5ab\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "ce7ef9d146ce5ca6b9be5ef049377b3817d53d10", "tree": "78db88d03da93108b2885d9e96492f7eab57b178", "parents": [ "86b43c58a4105c8cef13d860dd73fa9bd560526a" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Sun Sep 27 20:48:30 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Sep 08 09:05:16 2021 +0200" }, "message": "feat(tzc400): update filters by region\n\nAdd a new function that allows to enable or disabled filters on\nconfigured regions dynamically. This will avoid the need to\nreconfigure the entire attribute and just manage to\nenable/disable filters.\n\nChange-Id: If0937ca755bec6c45d3649718147108459682fff\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "ab0c8151bce67fed39962faf8bea1bf33b1cb141", "tree": "ba94af79a0c7ea320cdcb17c058a342c9b2df518", "parents": [ "a138717d9e6be47565d94082cb068f6345a140ba", "6c3d92e33fe4e6964576e78df23351085c4c7291" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 08 01:05:41 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 08 01:05:41 2021 +0200" }, "message": "Merge \"docs(contribution-guidelines): add coverity build configuration section\" into integration" }, { "commit": "a138717d9e6be47565d94082cb068f6345a140ba", "tree": "801e32770711b84929f3b81d2626936fc1df969c", "parents": [ "dc8b361c780634ed2cc78ec0067c8986cb242f30", "3017e932768c7357a1a41493c58323419e9a1ec9" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Sep 08 00:04:15 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 08 00:04:15 2021 +0200" }, "message": "Merge changes from topic \"advk-serror\" into integration\n\n* changes:\n fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default\n fix(plat/marvell/a3k): update information about PCIe abort hack\n" }, { "commit": "6c3d92e33fe4e6964576e78df23351085c4c7291", "tree": "dbfaf46b875c5af6be5352bfee15e429314035cf", "parents": [ "3c9962a1c0b4960222bf850034286aef496c3612" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Aug 31 12:27:48 2021 +0100" }, "committer": { "name": "Jayanth Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Sep 08 00:02:46 2021 +0200" }, "message": "docs(contribution-guidelines): add coverity build configuration section\n\nAdded a sub-section in the \"Processes and Policies\" chapter under\nContributor\u0027s guide on how to add new build configurations when new\nsource files are added to the TF-A repository. This will help the patch\ncontributor to update their files to get analysed by Coverity Scan.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I71f410a061028f89bd0e984e48e61e5935616d71\n" }, { "commit": "dc8b361c780634ed2cc78ec0067c8986cb242f30", "tree": "24da8d5d1c5b52da45d8ebc751b940a170338936", "parents": [ "e843fb0a74269e6c46d7689f9e48309090139806", "10198eab3aa7b0eeba10d9667197816b052ba3e4" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue Sep 07 18:00:44 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 07 18:00:44 2021 +0200" }, "message": "Merge changes I0ae8a6ea,I0b4fc83e into integration\n\n* changes:\n feat(tc): Enable SVE for both secure and non-secure world\n feat(tc): populate HW_CONFIG in BL31\n" }, { "commit": "10198eab3aa7b0eeba10d9667197816b052ba3e4", "tree": "8a66db4b6e9b700031ecbcd7708ea8f0f064b5b3", "parents": [ "34a87d74d9fbbe8037431ea5101110a9f1cf30e1" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Fri Aug 20 20:53:34 2021 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Tue Sep 07 14:38:02 2021 +0100" }, "message": "feat(tc): Enable SVE for both secure and non-secure world\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nChange-Id: I0ae8a6ea3245373a17af76c9b7dc3f38f3711091\n" }, { "commit": "34a87d74d9fbbe8037431ea5101110a9f1cf30e1", "tree": "c416e28e0f2a02296a7abee247e087df2d810a1d", "parents": [ "acfe3be2828735fa07868c117315a5ea43cb3853" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Tue Aug 17 17:57:10 2021 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Tue Sep 07 14:37:53 2021 +0100" }, "message": "feat(tc): populate HW_CONFIG in BL31\n\nBL2 passes FW_CONFIG to BL31 which contains information\nabout different DTBs present. BL31 then uses FW_CONFIG\nto get the base address of HW_CONFIG and populate fconf.\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nChange-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616\n" }, { "commit": "e843fb0a74269e6c46d7689f9e48309090139806", "tree": "9e86c4dbaaeae003d71d161f12b1f0864d911cbe", "parents": [ "e5bc3ef3b5f1c9c7803bf5a955ab6633d9e196b5", "7c78e4f7df43f09e54c26637711c6341761f3314" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Sep 07 15:19:33 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 07 15:19:33 2021 +0200" }, "message": "Merge \"docs: nxp soc-lx2160a based platforms\" into integration" }, { "commit": "86b43c58a4105c8cef13d860dd73fa9bd560526a", "tree": "809a22383703bafb1fa255989084c8a684568862", "parents": [ "3cc5155c8485fa7d991c145ec2a15eced1447824" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Jul 02 11:53:18 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(fdts): add firewall regions into STM32MP1 DT\n\nAdd the corresponding firewall memory regions\ninto fw-config device tree.\n\nChange-Id: Ie39b0339f3c42b3dd756354138a872500c64f84c\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "3cc5155c8485fa7d991c145ec2a15eced1447824", "tree": "4ddf65e6a6054216915fad68a4fd6cf6a33693a5", "parents": [ "43de546b909947ab44f104aaee02b98fba70f44c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Jul 05 14:07:29 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "refactor(plat/st): use TZC400 bindings\n\nThis avoids duplicate define of TZC_REGION_NSEC_ALL_ACCESS_RDWR.\nAnd remove the previous TZC400 definitions from stm32mp1_def.h.\n\nChange-Id: I6c72c2a18731f69d855fbce8ce822a21da9364fa\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "d5a84eeaac2c8ce14d3f2662dc9523b4abf41516", "tree": "1665f9a27d7b292d1b5efc89c89788800f64a077", "parents": [ "21e002fb777fad9d02a94dc961f077fb444517fa" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Jul 13 18:07:41 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(plat/st): manage io_policies with FCONF\n\nIntroduced IO policies management through the trusted\nboot firmware config device tree for UUID references.\n\nChange-Id: Ibeeabede51b0514ebba26dbbdae587363b2aa0a7\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "29332bcd680ce7e5f864813d9a900360f5e35d41", "tree": "2c0a1a7fbdca8843f0fe07c3e03e1be09d6320f7", "parents": [ "d9e0586b619b331eb2db75911ca82f927e20bd1c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Jul 06 10:00:44 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(plat/st): use FCONF to configure platform\n\nAdd required code to support FCONF on STM32MP1 platform.\nThe new FW_CONFIG DT file will be inside the FIP, and loaded by BL2.\nIt will be used to configure the addresses where to load other binaries.\nBL2 should be agnostic of which BL32 is in the FIP (OP-TEE or SP_min),\nso optee_utils.c is always compiled, and some OP-TEE flags are removed.\n\nChange-Id: Id957b49b0117864136250bfc416664f815043ada\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "18b415be9d631b3e0c3a3caacc5f02edb9413f6b", "tree": "8dfb32e84a0160a12dd91afe507c288c26117828", "parents": [ "1d204ee4ab12893fceb12097bd4f0a074be253b2" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Jun 18 11:33:26 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(plat/st): improve FIP image loading from MMC\n\nInstead of using a scratch buffer of 512 bytes, we can directly use the\nimage address and max size. The mmc_block_dev_spec struct info is then\noverwritten for each image with this info, except FW_CONFIG and GPT\ntable which will still use the scratch buffer.\nThis allows using multiple blocks read on MMC, and so improves the boot\ntime.\nA cache invalidate is required for the remaining data not used from the\nfirst and last blocks read. It is not required for FW_CONFIG_ID,\nas it is in scratch buffer in SYSRAM, and also because bl_mem_params\nstruct is overwritten in this case. This should also not be done if\nthe image is not found (OP-TEE extra binaries when using SP_min).\n\nChange-Id: If3ecfdfe35bb9db66284036ca49c4bd1be4fd121\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "1d204ee4ab12893fceb12097bd4f0a074be253b2", "tree": "4030170adbd0153305639a474c316c52410200b7", "parents": [ "84090d2ca4aeace94911442ebe4cc7de3ab794e6" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed May 19 18:48:16 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(plat/st): use FIP to load images\n\nBL2 still uses the STM32 header binary format to be loaded from ROM code.\nBL32 and BL33 and their respective device tree files are now put together\nin a FIP file.\nOne DTB is created for each BL. To reduce their sizes, 2 new dtsi file are\nin charge of removing useless nodes for a given BL. This is done because\nBL2 and BL32 share the same device tree files base.\n\nThe previous way of booting is still available, the compilation flag\nSTM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files\nare duplicated and their names modified with _stm32_ to avoid too much\nswitches in the code.\n\nChange-Id: I1ffada0af58486d4cf6044511b51e56b52269817\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "43de546b909947ab44f104aaee02b98fba70f44c", "tree": "0efc213339ddf4c4787196d3d23f911c5d96f0c0", "parents": [ "d5a84eeaac2c8ce14d3f2662dc9523b4abf41516" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Mon Sep 28 12:05:28 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(dt-bindings): add STM32MP1 TZC400 bindings\n\nAdd bindings that will be used to define DDR regions\nand their access rights.\n\nChange-Id: I745a7e580ef2b9e251d53db12c5a0a86dfe34463\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "21e002fb777fad9d02a94dc961f077fb444517fa", "tree": "f45f35f65fb390610949a4032457208722e96610", "parents": [ "29332bcd680ce7e5f864813d9a900360f5e35d41" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Sun Sep 27 20:48:21 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(fdts): add IO policies for STM32MP1\n\nAdd the UUID into the io policies node that are retrieved\nby BL2 using stm32mp_fconf_io.c populate function.\n\nChange-Id: I595d5a41a1e0a27fcc02ea2ab5495d9dbf0e6773\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "d9e0586b619b331eb2db75911ca82f927e20bd1c", "tree": "1486a37a1a0e12fe7d955758ee6e9706ceba8649", "parents": [ "18b415be9d631b3e0c3a3caacc5f02edb9413f6b" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Jul 02 09:35:04 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 07 09:14:05 2021 +0200" }, "message": "feat(fdts): add STM32MP1 fw-config DT files\n\nCreate all boards fw-config DT files. They all include a generic\nstm32mp15-fw-config.dtsi.\n\nChange-Id: Ib9ac8a59e93e01365001b0d11fee41f7c507c08e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "e5bc3ef3b5f1c9c7803bf5a955ab6633d9e196b5", "tree": "86409fb2fc755d6ebc967233b9a3015f194f7c3e", "parents": [ "2b9bfbc2b030c327e323377bb2821df1ff0e4f5c", "2c248ade2e958eed33127b4ea767fbb7499f31a7" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Mon Sep 06 21:00:56 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 06 21:00:56 2021 +0200" }, "message": "Merge \"feat(gic600ae): introduce support for Fault Management Unit\" into integration" }, { "commit": "2b9bfbc2b030c327e323377bb2821df1ff0e4f5c", "tree": "22f811480c374dbd1f177b76c32e5ef7c239b8be", "parents": [ "f465cc1659fdbaf962217aa2f1767a511426b476", "33993a3737737a03ee5a9d386d0a027bdc947c9c" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon Sep 06 18:09:37 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 06 18:09:37 2021 +0200" }, "message": "Merge \"feat(fvp): enable external SP images in BL2 config\" into integration" }, { "commit": "84090d2ca4aeace94911442ebe4cc7de3ab794e6", "tree": "79f213544a4373b90d04a6efee49c17ceea3bb15", "parents": [ "b84a850864c05fef587fcbb301f955428966de64" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Jul 13 14:44:09 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Sep 06 13:21:54 2021 +0200" }, "message": "refactor(plat/st): updates for OP-TEE\n\nProtect BL32 (SP_min) with MMU if OP-TEE is not used.\nValidate OP-TEE header with optee_header_is_valid().\nUse default values in bl2_mem_params_descs[]. They will be overwritten\nin bl2_plat_handle_post_image_load() if OP-TEE is used.\n\nChange-Id: I8614f3a17caa827561614d0f25f30ee90c4ec3fe\nSigned-off-by: Etienne Carriere \u003cetienne.carriere@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "b84a850864c05fef587fcbb301f955428966de64", "tree": "78922c211523f52b81cb39e506e428bfbcbab3f7", "parents": [ "f465cc1659fdbaf962217aa2f1767a511426b476" ], "author": { "name": "Etienne Carriere", "email": "etienne.carriere@st.com", "time": "Mon Apr 15 18:01:29 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Sep 06 13:21:54 2021 +0200" }, "message": "feat(lib/optee): introduce optee_header_is_valid()\n\nThis new function optee_header_is_valid() allows platform to know\nwhether OP-TEE OS is loaded from multi-image (using OP-TEE header\nimage as BL32_IMAGE_ID) or from a single OP-TEE binary image.\nThe function tee_validate_header() is reworked to return a boolean,\nand is now silent.\n\nChange-Id: Idc7dde091f2ada8898f40d02e68c3834ca39d8e8\nSigned-off-by: Etienne Carriere \u003cetienne.carriere@st.com\u003e\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\n" }, { "commit": "f465cc1659fdbaf962217aa2f1767a511426b476", "tree": "21d5909257f309220cfb03f2bd62f167b91dcb24", "parents": [ "ef03e78f42af7f896e3cb582bf1618ba7d7b461b", "3139270693ab0fc6d66fed4fe11e183829b47e2e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sat Sep 04 01:10:55 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Sep 04 01:10:55 2021 +0200" }, "message": "Merge \"feat(board/rdn2): add tzc master source ids for soc dma\" into integration" }, { "commit": "ef03e78f42af7f896e3cb582bf1618ba7d7b461b", "tree": "b00fa72b3cc8d0bd2aa0ed5fccd6db102b03c9a7", "parents": [ "b7942a91b850aba426cfc2084fb6eaef8b864451", "1cafb08debe7cb99968b38a070d25fee0cc9316d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Sep 03 23:58:01 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 03 23:58:01 2021 +0200" }, "message": "Merge changes from topic \"erratas\" into integration\n\n* changes:\n errata: workaround for Neoverse N2 erratum 2138956\n errata: workaround for Neoverse N2 erratum 2189731\n errata: workaround for Cortex-A710 erratum 2017096\n errata: workaround for Cortex-A710 erratum 2055002\n" }, { "commit": "1cafb08debe7cb99968b38a070d25fee0cc9316d", "tree": "068f2e83f25e081158992fd0eee9cb4dbffdb317", "parents": [ "7cfae93227be77f137265e8de4f1331e5d7beb3a" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Sep 01 01:36:43 2021 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Sep 03 15:44:56 2021 -0500" }, "message": "errata: workaround for Neoverse N2 erratum 2138956\n\nNeoverse N2 erratum 2138956 is a Cat B erratum that applies to\nrevision r0p0 and is still open. This erratum can be avoided by\ninserting a sequence of 16 DMB ST instructions prior to WFI or WFE.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I1aac87b3075992f875451e4767b21857f596d0b2\n" }, { "commit": "7cfae93227be77f137265e8de4f1331e5d7beb3a", "tree": "2cd2ec4261027f7bf9e5a64baeeb38a0138b464c", "parents": [ "afc2ed63f9c83a3b7408d804cbe22f02d34d075d" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Mon Aug 30 13:02:51 2021 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Sep 03 15:44:56 2021 -0500" }, "message": "errata: workaround for Neoverse N2 erratum 2189731\n\nNeoverse N2 erratum 2189731 is a Cat B erratum that applies to\nrevision r0p0 and is still open. The workaround is to set\nCPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to\ninvalidate the hardware prefetcher state trained from any EL.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03\n" }, { "commit": "afc2ed63f9c83a3b7408d804cbe22f02d34d075d", "tree": "daf947db21682ae911e9b73636ec51ae96e92e0a", "parents": [ "213afde907a375f4f28ac1843b633ca83887f174" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Mar 31 18:45:55 2021 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Sep 03 15:44:56 2021 -0500" }, "message": "errata: workaround for Cortex-A710 erratum 2017096\n\nCortex-A710 erratum 2017096 is a Cat B erratum that applies to\nrevisions r0p0, r1p0 \u0026 r2p0 and is still open. The workaround is to\nset CPUECLTR_EL1[8] to 1 which disables store issue prefetching.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775101/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3\n" }, { "commit": "213afde907a375f4f28ac1843b633ca83887f174", "tree": "0f0896ae7f9075d6794bb3ea452cca773092c0de", "parents": [ "4618b2bfa7116371a5785a32f69ef2ea928f7cb7" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Mar 31 16:45:40 2021 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Sep 03 15:44:47 2021 -0500" }, "message": "errata: workaround for Cortex-A710 erratum 2055002\n\nCortex-A710 erratum 2055002 is a Cat B erratum that applies to\nrevisions r1p0 \u0026 r2p0 and is still open. The workaround is to\nset CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.\nThis workaround works on revision r1p0 \u0026 r2p0.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775101/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81\n" }, { "commit": "b7942a91b850aba426cfc2084fb6eaef8b864451", "tree": "93bb4f59f562f3a91d29008a7769014f93f02980", "parents": [ "81de40f23b8a9302991d4ebd42c38b88a45511da", "4618b2bfa7116371a5785a32f69ef2ea928f7cb7" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Sep 03 21:31:00 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 03 21:31:00 2021 +0200" }, "message": "Merge changes from topic \"erratas\" into integration\n\n* changes:\n errata: workaround for Neoverse N2 erratum 2025414\n errata: workaround for Neoverse N2 erratum 2067956\n" }, { "commit": "81de40f23b8a9302991d4ebd42c38b88a45511da", "tree": "280a3c4256dc3446c4d914ce194d11996a5223e9", "parents": [ "9dc2534fd742342c9d25e72200107b3481275054", "08695df91dffb2e45c01866b760d73cb531a071b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Sep 03 15:17:08 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 03 15:17:08 2021 +0200" }, "message": "Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration\n\n* changes:\n refactor(plat/nxp): refine api to read SVR register\n refactor(plat/nxp): each errata use a seperate source file\n refactor(plat/nxp): use a unified errata api\n refactor(plat/soc-lx2160): move errata to common directory\n" }, { "commit": "33993a3737737a03ee5a9d386d0a027bdc947c9c", "tree": "af1010250e949c7ae020e5285e8d33d7f2349c01", "parents": [ "9dc2534fd742342c9d25e72200107b3481275054" ], "author": { "name": "Balint Dobszay", "email": "balint.dobszay@arm.com", "time": "Fri Mar 26 15:19:11 2021 +0100" }, "committer": { "name": "Balint Dobszay", "email": "balint.dobszay@arm.com", "time": "Fri Sep 03 11:12:10 2021 +0200" }, "message": "feat(fvp): enable external SP images in BL2 config\n\nCurrently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.\nThis is a problem when building a system with other SPs (e.g. from\nTrusted Services). This commit implements a workaround to enable adding\nSP UUIDs to the list at build time.\n\nSigned-off-by: Balint Dobszay \u003cbalint.dobszay@arm.com\u003e\nChange-Id: Iff85d3778596d23d777dec458f131bd7a8647031\n" }, { "commit": "7c78e4f7df43f09e54c26637711c6341761f3314", "tree": "362636c527c71ceb043aa1311cd20b18687869c6", "parents": [ "9dc2534fd742342c9d25e72200107b3481275054" ], "author": { "name": "Pankaj Gupta", "email": "pankaj.gupta@nxp.com", "time": "Thu Mar 25 14:56:16 2021 +0530" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Sep 03 09:13:22 2021 +0200" }, "message": "docs: nxp soc-lx2160a based platforms\n\nAddition of documents for platforms based on\nNXP SoC LX2160A.\n\nSigned-off-by: Pankaj Gupta \u003cpankaj.gupta@nxp.com\u003e\nChange-Id: I39ac5a9eb0b668d26301a0a24a1e6bf87f245f02\n" }, { "commit": "9dc2534fd742342c9d25e72200107b3481275054", "tree": "2e7d7163b5cb91f53868d483e041b24512e071b6", "parents": [ "3c9962a1c0b4960222bf850034286aef496c3612", "00bee997614f8a98737f4dc0a5ac9d96d2d28cf1" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 02 22:20:54 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 02 22:20:54 2021 +0200" }, "message": "Merge \"errata: workaround for Cortex-A78 errata 1952683\" into integration" }, { "commit": "4618b2bfa7116371a5785a32f69ef2ea928f7cb7", "tree": "163376a7e9edf9fbadbc27c0512e849e51e45332", "parents": [ "65e04f27d42c5eccdb3893e41e25363f396e42ed" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Mar 31 10:10:27 2021 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Sep 02 11:00:13 2021 -0500" }, "message": "errata: workaround for Neoverse N2 erratum 2025414\n\nNeoverse N2 erratum 2025414 is a Cat B erratum that applies to\nrevision r0p0 and is still open. The workaround is to set\nCPUECLTR_EL1[8] to 1 which disables store issue prefetching.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a\n" }, { "commit": "65e04f27d42c5eccdb3893e41e25363f396e42ed", "tree": "da7d35a3dc1398584e6f58b19f6be81c5beb4243", "parents": [ "3c9962a1c0b4960222bf850034286aef496c3612" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Mar 30 16:08:32 2021 -0500" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Sep 02 10:52:50 2021 -0500" }, "message": "errata: workaround for Neoverse N2 erratum 2067956\n\nNeoverse N2 erratum 2067956 is a Cat B erratum that applies to\nrevision r0p0 and is still open. The workaround is to set\nCPUACTLR_EL1[46] to force L2 tag ECC inline correction mode.\nThis workaround works on revision r0p0.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1982442/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21\n" }, { "commit": "2c248ade2e958eed33127b4ea767fbb7499f31a7", "tree": "7b87a052a694c4b08972f7023f7add91714e89b3", "parents": [ "3c9962a1c0b4960222bf850034286aef496c3612" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Tue May 04 16:14:09 2021 -0700" }, "committer": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Wed Sep 01 08:24:33 2021 -0700" }, "message": "feat(gic600ae): introduce support for Fault Management Unit\n\nThe FMU is part of the GIC Distributor (GICD) component. It implements\nthe following functionality in GIC-600AE:\n\n* Provides software the means to enable or disable a Safety Mechanism\n within a GIC block.\n* Receives error signaling from all Safety Mechanisms within other GIC\n blocks.\n* Maintains error records for each GIC block, for software inspection\n and provides information on the source of the error.\n* Retains error records across functional reset.\n* Enables software error recovery testing by providing error injection\n capabilities in a Safety Mechanism.\n\nThis patch introduces support to enable error detection for all safety\nmechanisms provided by the FMU. Platforms are expected to invoke the\ninitialization function during cold boot.\n\nThe support for the FMU is guarded by the GICV3_SUPPORT_GIC600AE_FMU\nmakefile variable. The default value of this variable is \u00270\u0027.\n\nChange-Id: I421c3d059624ddefd174cb1140a2d2a2296be0c6\nSigned-off-by: Varun Wadekar \u003cvwadekar@nvidia.com\u003e\n" }, { "commit": "c69f815b09ab85d3ace8fd2979ffafb1184ec76c", "tree": "e5ec55634617f8ad0aeb3fc5845a86e5032ad226", "parents": [ "858f40e379684fefc8b52c7b9e60576bc3794a69" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue May 18 15:53:05 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 16:14:03 2021 +0100" }, "message": "feat(arm_fpga): support GICv4 images\n\nUp until now we relied on the GICs used in our FPGA images to be GICv3\ncompliant, without the \"direct virtual injection\" feature (aka GICv4)\nenabled.\nTo support newer images which have GICv4 compliant GICs, enable the\nnewly introduced GICv4 detection code, and use that also when we adjust\nthe redistributor region size in the devicetree.\n\nThis allows the same BL31 image to be used with GICv3 or GICv4 FPGA\nimages.\n\nChange-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "858f40e379684fefc8b52c7b9e60576bc3794a69", "tree": "6b0ba23592655241749ed93534cdad8727d85614", "parents": [ "feb7081863f454b9e465efc074ca669f7a4c783d" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue May 18 15:51:06 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 16:14:03 2021 +0100" }, "message": "feat(gicv3): detect GICv4 feature at runtime\n\nAt the moment we have a GIC_ENABLE_V4_EXTN build time variable to\ndetermine whether the GIC interrupt controller is compliant to version\n4.0 of the spec or not. This just changes the number of 64K MMIO pages\nwe expect per redistributor.\n\nTo support firmware builds which run on variable systems (emulators,\nfast model or FPGAs), let\u0027s make this decision at runtime.\nThe GIC specification provides several architected flags to learn the\nsize of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.\n\nProvide a (static inline) function to return the size of each\nredistributor.\nWe keep the GIC_ENABLE_V4_EXTN build time variable around, but change\nits meaning to enable this autodetection code. Systems not defining this\nrely on a \"pure\" GICv3 (as before), but platforms setting it to \"1\" can\nnow deal with both configurations.\n\nChange-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "feb7081863f454b9e465efc074ca669f7a4c783d", "tree": "c15e8b61a2bdc66d1e2faca5897eaf0a11ada528", "parents": [ "1fe27d71353dd35f60555012c5ace246836517cc" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue May 18 15:46:58 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 16:14:03 2021 +0100" }, "message": "feat(gicv3): multichip: detect GIC-700 at runtime\n\nAt the moment we have a GIC_ENABLE_V4_EXTN build time variable to\ndetermine whether the GIC interrupt controller is compliant to version\n4.0 of the GIC spec or not.\nIn case of the GIC-600 multichip support we were somewhat abusing that\nflag to differentiate between a GIC-700 and GIC-600 implementation\nbeing used in the system.\n\nTo avoid a build time dependency on this flag, look at the GICD_IIDR\nregister and check if the hardware is a GIC-600 or not, to make this\ndecision at runtime. We then use the values for either GIC-700 or the\nGIC-600, respectively.\n\nChange-Id: I8c09ec1cd6fd60d28da879ed55ffef5506f9869d\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "1fe27d71353dd35f60555012c5ace246836517cc", "tree": "49569a4985d4e91960045d2dd9f576973e655153", "parents": [ "0c9f91cf699565c858e650d19bbdcab513d5001a" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Aug 24 10:02:52 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Sep 01 12:50:08 2021 +0100" }, "message": "refactor(gic): move GIC IIDR numbers\n\nFor the GIC power management we need to identify certain GIC\nimplementations, so we have the IIDR values for some Arm Ltd. GIC models\ndefined.\nWe will need those number elsewhere very soon, so export them to a\nshared header file, to avoid defining them again.\n\nChange-Id: I1b8e2d93d6cea0d066866143c89eef736231134f\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "3c9962a1c0b4960222bf850034286aef496c3612", "tree": "6b529c15d9d0fa5b43dae509bdadc534cb3e3451", "parents": [ "523569d09d79d6268c715052ab86d8bb30512b4a", "9380f754181a56abe20c3c4e9152b3604ae30c65" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Aug 31 00:14:24 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 31 00:14:24 2021 +0200" }, "message": "Merge \"errata: workaround for Neoverse-N2 errata 2002655\" into integration" }, { "commit": "523569d09d79d6268c715052ab86d8bb30512b4a", "tree": "62894fa482794ec144919e88350ac76a26851bd0", "parents": [ "cb9ddac9fe71a9eca919af4d83dd8868aa6a9c17", "a64bcc2b4528962a3b11ac3798e36e52dca2787f" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Aug 31 00:02:49 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 31 00:02:49 2021 +0200" }, "message": "Merge changes I1e8c2bc3,I9bcff306 into integration\n\n* changes:\n errata: workaround for Cortex-A710 errata 2081180\n errata: workaround for Cortex-A710 errata 1987031\n" }, { "commit": "9380f754181a56abe20c3c4e9152b3604ae30c65", "tree": "6a66d6127cbae36d756c1f684a0dff9113b2c3d5", "parents": [ "cb9ddac9fe71a9eca919af4d83dd8868aa6a9c17" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Fri Aug 06 17:46:10 2021 -0700" }, "committer": { "name": "nayankumar.patel", "email": "nayankumar.patel@arm.com", "time": "Mon Aug 30 22:31:55 2021 +0200" }, "message": "errata: workaround for Neoverse-N2 errata 2002655\n\nNeoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of\nthe Neoverse-N2 processor core, and it is still open.\n\nNeoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token\u003d\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I1380418146807527abd97cdd4918265949ba5c01\n" }, { "commit": "a669983c78828e3f4a4f14b9e5a6ee79dcfde20f", "tree": "fdf68aa8d22cc69d543022583762d0097347311d", "parents": [ "cb9ddac9fe71a9eca919af4d83dd8868aa6a9c17" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Fri Aug 27 11:16:43 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Fri Aug 27 11:16:43 2021 +0200" }, "message": "fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode\n\nThere is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not\nSGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z standard)\nbut upclocked 2.5x. This mode is commonly known under name 2500Base-X.\n\nSo remove incorrect SGMII keyword from names and comments and replace it\nby more adequate 2500Base-X keyword.\n\nThere is no functional change in code, just renaming macros and updating\ncomments.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: If79aec16cc233f4896aafd75bfbbebb3f172a197\n" }, { "commit": "cb9ddac9fe71a9eca919af4d83dd8868aa6a9c17", "tree": "497ebe39a5a38f2d647e3fe72249f3b13a4555cd", "parents": [ "296affb793186125441fb4f9872251b9a8768715", "099c90b81d1d12b0f71efba81ffc840ae3b135d4" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Aug 26 23:07:13 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 26 23:07:13 2021 +0200" }, "message": "Merge \"docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options\" into integration" }, { "commit": "296affb793186125441fb4f9872251b9a8768715", "tree": "eedae7f875980d7f4caea142ee4bc052b84e756d", "parents": [ "d0464435f6ba4e8eca6f38bebd3f0a00b9a1b378", "d01139f3b59a1bc6542e74f52ff3fb26eea23c69" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Aug 26 18:05:06 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 26 18:05:06 2021 +0200" }, "message": "Merge changes I75a4554a,Idce603e4 into integration\n\n* changes:\n feat(plat/marvell): introduce t9130_cex7_eval\n feat(plat/marvell/a8k): allow overriding default paths\n" }, { "commit": "d0464435f6ba4e8eca6f38bebd3f0a00b9a1b378", "tree": "110a79e585276469f3e5c0bbdef2445f9a4e8434", "parents": [ "abd63ed0c575a2517c43fe8dc4321d6e9fc512c3", "47d6f5ff16d1f2ad009d630a381054b10fa0a06f" ], "author": { "name": "Varun Wadekar", "email": "vwadekar@nvidia.com", "time": "Thu Aug 26 12:18:59 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Aug 26 12:18:59 2021 +0200" }, "message": "Merge \"feat(cpus): workaround for Cortex A78 AE erratum 1941500\" into integration" }, { "commit": "08695df91dffb2e45c01866b760d73cb531a071b", "tree": "f17134b90bc1ce22e0829b32857019bc64b12d6b", "parents": [ "1ca72295290a11164657da66e014ba690e05bc1e" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Jul 20 17:14:32 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Aug 26 10:08:57 2021 +0800" }, "message": "refactor(plat/nxp): refine api to read SVR register\n\n1. Refined struct soc_info_t definition.\n2. Refined get_soc_info function.\n3. Fixed some SVR persernality value.\n4. Refined API to get cluster numbers and cores per cluster.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4\n" }, { "commit": "d01139f3b59a1bc6542e74f52ff3fb26eea23c69", "tree": "649074b204bc6fe4ae316e338996f35d7e938e64", "parents": [ "0b702afc3aabc349a513a5b00397b58a62fea634" ], "author": { "name": "Marcin Wojtas", "email": "mw@semihalf.com", "time": "Tue Jun 22 23:44:26 2021 +0200" }, "committer": { "name": "Marcin Wojtas", "email": "mw@semihalf.com", "time": "Thu Aug 26 04:08:50 2021 +0200" }, "message": "feat(plat/marvell): introduce t9130_cex7_eval\n\nThis patch adds the necessary files to support\nthe SolidRun CN913X CEx7 Evaluation Board.\n\nBecause the DRAM connectivity and SerDes settings\nis shared with the CN913X DB - reuse relevant\nboard-specific files.\n\nChange-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80\nSigned-off-by: Marcin Wojtas \u003cmw@semihalf.com\u003e\n" }, { "commit": "0b702afc3aabc349a513a5b00397b58a62fea634", "tree": "129c1b1f9b0420757a0b7673015b65ca7636871f", "parents": [ "abd63ed0c575a2517c43fe8dc4321d6e9fc512c3" ], "author": { "name": "Marcin Wojtas", "email": "mw@semihalf.com", "time": "Tue Aug 24 04:19:07 2021 +0200" }, "committer": { "name": "Marcin Wojtas", "email": "mw@semihalf.com", "time": "Thu Aug 26 04:07:11 2021 +0200" }, "message": "feat(plat/marvell/a8k): allow overriding default paths\n\nThe common makefile used by every a8k/cn913x platform\n(a8k_common.mk) assumed default paths in PLAT_INCLUDES,\nBLE/BL31_PORTING_SOURCES. Allow overriding those\nvariables, in order to avoid code duplication.\n\nIt can be helpful in case using multiple board variants\nor sharing common settings between different platforms.\n\nChange-Id: Idce603e44ed04d99fb1e3e11a2bb395d552e2bf7\nSigned-off-by: Marcin Wojtas \u003cmw@semihalf.com\u003e\n" }, { "commit": "a64bcc2b4528962a3b11ac3798e36e52dca2787f", "tree": "9debc5e1989d9c3d571b1e59cfd408cb37f260b5", "parents": [ "fbcf54aeb970195ea2944cb7bbc704145ec8f07e" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Wed Aug 25 17:35:15 2021 -0700" }, "committer": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Wed Aug 25 17:35:15 2021 -0700" }, "message": "errata: workaround for Cortex-A710 errata 2081180\n\nCortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,\nand r2p0 of the Cortex-A710 processor core, and it is still open.\n\nA710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542\n" }, { "commit": "abd63ed0c575a2517c43fe8dc4321d6e9fc512c3", "tree": "73b921b614b74a57cd1dfbb3eb921f171c29c0bf", "parents": [ "6657c1e3cc87591d330859a7486168bed5e01e31", "13bacd3bc3e6b76009adf9183e5396b6457eb12c" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed Aug 25 10:49:42 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 25 10:49:42 2021 +0200" }, "message": "Merge changes from topic \"allwinner-r329\" into integration\n\n* changes:\n feat(plat/allwinner): add R329 support\n refactor(plat/allwinner): allow custom BL31 offset\n refactor(plat/allwinner): allow new AA64nAA32 position\n fix(plat/allwinner): delay after enabling CPU power\n" }, { "commit": "6657c1e3cc87591d330859a7486168bed5e01e31", "tree": "1deb992fd9985769830bb7379e835ead26f0532b", "parents": [ "19ebec9f667426c62420f759ebe363125703d3f2", "f4616efafbc1004f1330f515b898e7617e338875" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Aug 25 10:30:29 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Aug 25 10:30:29 2021 +0200" }, "message": "Merge \"cpu: add support for Demeter CPU\" into integration" }, { "commit": "1ca72295290a11164657da66e014ba690e05bc1e", "tree": "ee262fda482f8f3a95a76bd34476378718bb5af0", "parents": [ "9616db154b0be0abe27f7d267482772b54c88664" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Aug 24 12:01:27 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Wed Aug 25 09:53:20 2021 +0800" }, "message": "refactor(plat/nxp): each errata use a seperate source file\n\nDon\u0027t mix erratas together in one file.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: Ib1671011b91a41b0653210e4706d62b7e946c642\n" }, { "commit": "9616db154b0be0abe27f7d267482772b54c88664", "tree": "09a9fa9af980a83d9343f34fa456a72786cb6dc8", "parents": [ "64cadc163721ee471ab83bb89e35a7fe54d119c2" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Jul 20 15:21:06 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Wed Aug 25 09:53:20 2021 +0800" }, "message": "refactor(plat/nxp): use a unified errata api\n\nUse a unfied API soc_errata() for each platforms,\nadd print a INFO message for each enabled errata,\nso that it will be easy to check which errata is\nenabled on current platform.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I5eab3f338db6b46c57cbad475819043fc60ca6d3\n" }, { "commit": "64cadc163721ee471ab83bb89e35a7fe54d119c2", "tree": "feab05ea73a34a28cceb12b46d2785ccc76f4767", "parents": [ "19ebec9f667426c62420f759ebe363125703d3f2" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Jul 20 14:54:01 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Wed Aug 25 09:53:20 2021 +0800" }, "message": "refactor(plat/soc-lx2160): move errata to common directory\n\nWill add more Erratas, some errata can be used for multiple\nplatforms, so move errata to be common code which can\nbe share between different platforms.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: Ib149b3eac365bdb593331e9f38f0b89d92c9c0d1\n" }, { "commit": "13bacd3bc3e6b76009adf9183e5396b6457eb12c", "tree": "f71536a59af6611076b702e2d24bbfd4300072d5", "parents": [ "f04dfbb297f03d7f8d7f7c00ce8712e1a10295cf" ], "author": { "name": "Icenowy Zheng", "email": "icenowy@sipeed.com", "time": "Thu Jul 22 09:41:16 2021 +0800" }, "committer": { "name": "Icenowy Zheng", "email": "icenowy@aosc.io", "time": "Wed Aug 25 02:11:59 2021 +0800" }, "message": "feat(plat/allwinner): add R329 support\n\nAllwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A\nsupport for it, to provide a PSCI implementation containing CPU\nboot/shutdown and SoC reset.\n\nChange-Id: I0fa37ee9b4a8e0e1137bf7cf7d614b6ca9624bfe\nSigned-off-by: Icenowy Zheng \u003cicenowy@sipeed.com\u003e\n" }, { "commit": "f04dfbb297f03d7f8d7f7c00ce8712e1a10295cf", "tree": "192788f7a7bda300036e3c6179ac6057e0b9c91a", "parents": [ "080939f9244f1717c7bb4c32ff30fb72032d36fb" ], "author": { "name": "Icenowy Zheng", "email": "icenowy@sipeed.com", "time": "Fri Jul 23 11:35:24 2021 +0800" }, "committer": { "name": "Icenowy Zheng", "email": "icenowy@aosc.io", "time": "Wed Aug 25 00:35:24 2021 +0800" }, "message": "refactor(plat/allwinner): allow custom BL31 offset\n\nNot all Allwinner SoCs have the same arrangement to SRAM A2.\n\nAllow to specify a offset at which BL31 will stay in SRAM A2.\n\nChange-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9\nSigned-off-by: Icenowy Zheng \u003cicenowy@sipeed.com\u003e\n" }, { "commit": "080939f9244f1717c7bb4c32ff30fb72032d36fb", "tree": "0f1fc7589dfee2b37bdc03805b02125d63b1f3f5", "parents": [ "86a7429e477786dad6fab002538aef825f4ca35a" ], "author": { "name": "Icenowy Zheng", "email": "icenowy@sipeed.com", "time": "Thu Jul 22 09:35:19 2021 +0800" }, "committer": { "name": "Icenowy Zheng", "email": "icenowy@aosc.io", "time": "Wed Aug 25 00:33:59 2021 +0800" }, "message": "refactor(plat/allwinner): allow new AA64nAA32 position\n\nIn newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register\ncalled \"General Control Register0\" in the manual rather than the\n\"Cluster 0 Control Register0\" in older SoCs.\n\nNow the position of AA64nAA32 (reg and bit offset) is defined in a few\nmacros instead assumed to be at bit offset 24 of\nSUNXI_CPUCFG_CLS_CTRL_REG0.\n\nChange-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668\nSigned-off-by: Icenowy Zheng \u003cicenowy@sipeed.com\u003e\n" }, { "commit": "86a7429e477786dad6fab002538aef825f4ca35a", "tree": "894dd3226d13487400be81558d070d6d42b22733", "parents": [ "9fcefe38d54bdfd86648248854944d95bb99a92a" ], "author": { "name": "Icenowy Zheng", "email": "icenowy@sipeed.com", "time": "Thu Jul 22 09:32:57 2021 +0800" }, "committer": { "name": "Icenowy Zheng", "email": "icenowy@aosc.io", "time": "Wed Aug 25 00:15:27 2021 +0800" }, "message": "fix(plat/allwinner): delay after enabling CPU power\n\nAdds a 1us delay after enabling power to a CPU core, to prevent\ninrush-caused CPU crash before it\u0027s up.\n\nChange-Id: I8f4c1b0dc0d1d976b31ddc30efe7a77a1619b1b3\nSigned-off-by: Icenowy Zheng \u003cicenowy@sipeed.com\u003e\n" }, { "commit": "19ebec9f667426c62420f759ebe363125703d3f2", "tree": "37283bb967e695b331680baa53c4aa6720731c08", "parents": [ "acfe3be2828735fa07868c117315a5ea43cb3853", "5d2793a61aded9602af86e90a571f64ff07f93b3" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Tue Aug 24 17:52:37 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Aug 24 17:52:37 2021 +0200" }, "message": "Merge \"fix(rpi4): drop /memreserve/ region\" into integration" }, { "commit": "3139270693ab0fc6d66fed4fe11e183829b47e2e", "tree": "ae6bffd894ce9ee2f4475e3845c66aef45670ab0", "parents": [ "acfe3be2828735fa07868c117315a5ea43cb3853" ], "author": { "name": "Vijayenthiran Subramaniam", "email": "vijayenthiran.subramaniam@arm.com", "time": "Tue Jul 06 14:52:04 2021 +0530" }, "committer": { "name": "Vijayenthiran Subramaniam", "email": "vijayenthiran.subramaniam@arm.com", "time": "Tue Aug 24 11:07:43 2021 +0530" }, "message": "feat(board/rdn2): add tzc master source ids for soc dma\n\nAdd TZC master source id for DMA in the SoC space and for the DMAs\nbehind the I/O Virtualization block to allow the non-secure transactions\nfrom these DMAs targeting DRAM.\n\nSigned-off-by: Vijayenthiran Subramaniam \u003cvijayenthiran.subramaniam@arm.com\u003e\nChange-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c\n" }, { "commit": "3017e932768c7357a1a41493c58323419e9a1ec9", "tree": "8a58c24c95366eb298469279d148f4165ae3d241", "parents": [ "068fe919613197bf221c00fb84a1d94c66a7a8ca" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Fri Jul 09 15:10:27 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Aug 24 01:00:52 2021 +0200" }, "message": "fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default\n\nIt was enabled in commit 3c7dcdac5c50 (\"marvell/a3700: Prevent SError\naccessing PCIe link while it is down\") with a workaround for a bug found\nin U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver\nfor Armada 37xx SoC) which results in SError interrupt caused by AXI\nSLVERR on external access (syndrome 0xbf000002) and immediate kernel\npanic.\n\nNow when proper patches are in both U-Boot and Linux kernel projects,\nthis workaround in TF-A should not have to be enabled by default\nanymore as it has unwanted side effects like propagating all external\naborts, including non-fatal/correctable into EL3 and making them as\nfatal which cause immediate abort.\n\nAdd documentation for HANDLE_EA_EL3_FIRST build option into Marvell\nArmada build section.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491\n" }, { "commit": "068fe919613197bf221c00fb84a1d94c66a7a8ca", "tree": "2ad53518c80eb253afb701940b2e8445738f8785", "parents": [ "485d1f8003f7a05049bf770b676d46cc31e799cb" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Sat Jun 26 16:26:56 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Mon Aug 23 23:59:53 2021 +0100" }, "message": "fix(plat/marvell/a3k): update information about PCIe abort hack\n\nA3700 plat_ea_handler was introduced into TF-A codebase just because of\nbugs in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c.\n\nThese bugs were finally fixed in both U-Boot and Linux kernel drivers:\nhttps://source.denx.de/u-boot/u-boot/-/commit/eccbd4ad8e4e182638eafbfb87ac139c04f24a01\nhttps://git.kernel.org/stable/c/f18139966d072dab8e4398c95ce955a9742e04f7\n\nAdd all these information into comments, including printing error\nmessage into a3k plat_ea_handler. Also check that abort is really\nasynchronous and comes from lower level than EL3.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I46318d221b39773d5e25b3a0221d7738736ffdf1\n" }, { "commit": "fbcf54aeb970195ea2944cb7bbc704145ec8f07e", "tree": "e65f8983fe1049f8d6abb95a8da884f7c208318a", "parents": [ "9fcefe38d54bdfd86648248854944d95bb99a92a" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Fri Aug 06 16:39:48 2021 -0700" }, "committer": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Mon Aug 23 15:51:26 2021 -0700" }, "message": "errata: workaround for Cortex-A710 errata 1987031\n\nCortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,\nand r2p0 of the Cortex-A710 processor core, and it is still open.\n\nA710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token\u003d\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179\n" }, { "commit": "00bee997614f8a98737f4dc0a5ac9d96d2d28cf1", "tree": "e873e67f9c0886a00e654e0363f33fe9e96d6daa", "parents": [ "9fcefe38d54bdfd86648248854944d95bb99a92a" ], "author": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Wed Aug 11 13:33:00 2021 -0700" }, "committer": { "name": "nayanpatel-arm", "email": "nayankumar.patel@arm.com", "time": "Mon Aug 23 12:19:29 2021 -0700" }, "message": "errata: workaround for Cortex-A78 errata 1952683\n\nCortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of\nthe Cortex-A78 processor core, and it was fixed in r1p0.\n\nA78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400\n\nSigned-off-by: nayanpatel-arm \u003cnayankumar.patel@arm.com\u003e\nChange-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0\n" }, { "commit": "acfe3be2828735fa07868c117315a5ea43cb3853", "tree": "e23df2bac1da4c7b15bec07e3d1a972d0fe2083b", "parents": [ "3b15e9ad11949fb6f7029bf69e3db9feab052d6f", "578f468ac058bbb60b08f78e2aa2c20cdc601620" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 21:42:19 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 21:42:19 2021 +0200" }, "message": "Merge changes I976aef15,I11ae679f into integration\n\n* changes:\n feat(plat/xilinx/zynqmp): add support for runtime feature config\n feat(plat/xilinx/zynqmp): sync IOCTL IDs\n" }, { "commit": "3b15e9ad11949fb6f7029bf69e3db9feab052d6f", "tree": "bbb2c6db59472bc06b91a1a17380b879a48b09ab", "parents": [ "f8bcfa8b76fb03ad8c6a1242ac8ce7fb05a47f4a", "b4f8d44597faf641177134ee08db7c3fcef5aa14" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 18:22:51 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 18:22:51 2021 +0200" }, "message": "Merge \"fix(el3_runtime): correct CASSERT for pauth\" into integration" }, { "commit": "f8bcfa8b76fb03ad8c6a1242ac8ce7fb05a47f4a", "tree": "5847efc5fe8034d9214e4ac848c00012c284b8ea", "parents": [ "15405fccae1f2a9f2a1cf9a466653144c9373209", "325716c97b7835b8d249f12c1461556bab8c53a0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 18:07:24 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 18:07:24 2021 +0200" }, "message": "Merge \"fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit\" into integration" }, { "commit": "15405fccae1f2a9f2a1cf9a466653144c9373209", "tree": "055136cdb41fc309747d0e277c93046cfb7d42c3", "parents": [ "bd4b4b03c2cc8d05bb670ad80e277c48f2b2750e", "99080bd1273331007f0b2d6f64fed51ac6861bcd" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Aug 20 16:33:57 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Aug 20 16:33:57 2021 +0200" }, "message": "Merge \"fix(plat/st): apply security at the end of BL2\" into integration" }, { "commit": "0c9f91cf699565c858e650d19bbdcab513d5001a", "tree": "ee136e29c4f8561013c2654c8c01140ccdd6779c", "parents": [ "9fcefe38d54bdfd86648248854944d95bb99a92a" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Jul 20 19:20:07 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Aug 20 14:23:35 2021 +0100" }, "message": "refactor(gicv3): rename GIC Clayton to GIC-700\n\nThe GIC IP formerly known as \"GIC Clayton\" has been released under the\nname of \"GIC-700\".\n\nRename occurences of Clayton in comments and macro names to reflect the\nofficial name.\n\nChange-Id: Ie8c55f7da7753127d58c8382b0033c1b486f7909\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" } ], "next": "099c90b81d1d12b0f71efba81ffc840ae3b135d4" }