)]}' { "log": [ { "commit": "764aa951b2ca451694c74791964a712d423d8206", "tree": "dd1efbef95bb6837d1259cde219ba0fe4da7288d", "parents": [ "d5f225d95d3dc7473340ffebfcb9068b54f91a17" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jul 13 09:47:03 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): ensure that passed region lies within Non-Secure region of DRAM\n\nEnsured DLME data region and DRTM parameters are lies within Non-Secure\nregion of DRAM by calling platform function \u0027plat_drtm_validate_ns_region\u0027.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I93ead775f45ca7748193631f8f9eec4326fcf20a\n" }, { "commit": "d5f225d95d3dc7473340ffebfcb9068b54f91a17", "tree": "228c23b7c88dff413f065a58c41e78c250caf8f6", "parents": [ "b1392f429cdd368ea2b8e183a1ac0fb31deaf694" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Jul 04 14:51:07 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(fvp): add plat API to validate that passed region is non-secure\n\nAdded a platform function to check passed region is within\nthe Non-Secure region of DRAM.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: Ie5808fa6a1b6e6bc99f4185fa8acc52af0d5f14d\n" }, { "commit": "b1392f429cdd368ea2b8e183a1ac0fb31deaf694", "tree": "1dc0c7f0ad74382683d0927ec2b0529d09e24ad3", "parents": [ "d1747e1b8e617ad024456791ce0ab8950bb282ca" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jun 23 13:11:48 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): ensure that no SDEI event registered during dynamic launch\n\nEnsured no SDEI event are registered during dynamic launch.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Ied3b2d389aa3d9a96ace9078581d5e691f0b38a7\n" }, { "commit": "d1747e1b8e617ad024456791ce0ab8950bb282ca", "tree": "b9c8c02390c6df1d4a7d5544d416f92eeffdc6ce", "parents": [ "d42119cc294fbca2afc263fe5e44538a0ca5e7b8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jun 23 10:43:31 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): prepare EL state during dynamic launch\n\nPrepared EL state before dynamic launch\n\nChange-Id: I3940cd7fc74da1a1addbeb08ae34f16771395e61\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\n" }, { "commit": "d42119cc294fbca2afc263fe5e44538a0ca5e7b8", "tree": "1b288c384674c52107e646048a338d452b5fa002", "parents": [ "2090e55283c4bf85c7a61735ca0e872745c55896" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jun 22 13:11:14 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): prepare DLME data for DLME launch\n\nPrepared DLME data before DLME launch\n\nChange-Id: I28e2132d9c832ab5bd25cf884925b99cc48258ea\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "2090e55283c4bf85c7a61735ca0e872745c55896", "tree": "2df7f09933bdd607a6a84462cdee5e1b4cada2d4", "parents": [ "2b13a985994213f766ada197427f96e064f1b59b" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jun 21 18:11:53 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): take DRTM components measurements before DLME launch\n\nTaken measurement of various DRTM components in the Event Log\nbuffer to pass it to DLME.\n\nChange-Id: Ic56620161f42596d22bf40d5c83c041cbce0b618\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "2b13a985994213f766ada197427f96e064f1b59b", "tree": "4d12e60b0692cb9af3111cc80c6acbc3dc1de2fc", "parents": [ "1436e37dcb894a539a22da48a34ef01566ae728b" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jun 21 18:08:50 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): add a few DRTM DMA protection APIs\n\nAdded DRTM DMA protections APIs, and called them during\nthe DLME launch and DRTM SMC handling.\n\nChange-Id: I29e7238c04e2ca9f26600276c5c05bff5387789e\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "1436e37dcb894a539a22da48a34ef01566ae728b", "tree": "0f5d07381fd3f252f6c8c8f11a27173bf2c797f9", "parents": [ "586f60cc571f0f3b6d20eb5033717e9b0cc66af4" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jun 21 09:41:32 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): add remediation driver support in DRTM\n\nAdded remediation driver for DRTM to set/get the error\nfrom non-volatile memory\n\nChange-Id: I8f0873dcef4936693e0f39a3c95096cb689c04b7\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\n" }, { "commit": "586f60cc571f0f3b6d20eb5033717e9b0cc66af4", "tree": "e94a95e6b6e2196ed271c2f56c0f21ecca687c73", "parents": [ "40814266d53b7154daf5d212de481b397db43823" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Jul 12 21:48:04 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(fvp): add plat API to set and get the DRTM error\n\nAdded a platform function to set and get DRTM error.\nAlso, added a platform function to reset the system.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I471f2387f8c78b21a06af063a6fa02cda3646557\n" }, { "commit": "40814266d53b7154daf5d212de481b397db43823", "tree": "b69866f895a30a295f5655bd0bb7d9f22965c527", "parents": [ "40e1fad69b9f28ab5e57cea33261bf629b05519c" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Jun 17 11:42:17 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): add Event Log driver support for DRTM\n\nAdded Event Log driver support for DRTM. This driver\nis responsible for the doing the hash measurement of\nvarious DRTM components as per [1], and putting these\nmeasurements in the Event Log buffer.\n\n[1]: https://developer.arm.com/documentation/den0113/a, section 3.16\n\nChange-Id: I9892c313cf6640b82e261738116fe00f7975ee12\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "40e1fad69b9f28ab5e57cea33261bf629b05519c", "tree": "c8832146ca5329a6f9fa953d98eb0a140c7b05c7", "parents": [ "bd6cc0b2388c52f2b232427be61ff52c042d724a" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Jun 21 15:36:45 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): check drtm arguments during dynamic launch\n\nCheck the sanity of arguments before dynamic launch.\n\nChange-Id: Iad68f852b09851b0c55a55df6ba16576e105758a\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\n" }, { "commit": "bd6cc0b2388c52f2b232427be61ff52c042d724a", "tree": "f2b9ac9bef696fdf10cbe324ede39dba9a938dbf", "parents": [ "b9b175086ce6c20480ec6bccdcf5a784f8cc8298" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jun 20 17:42:41 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): introduce drtm dynamic launch function\n\nThis function is placeholder for checking all the necessary conditions\nbefore doing drtm dynamic launch.\nIn this patch following conditions are checked (based on Table 31 of\nDRTM spec beta0), rest of the conditions will be added in later\npatches.\n - Only boot PE is online\n - Caller execution state is AArch64\n - Caller exception level is NS-EL2 or NS-EL1\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I622b946bc191bb39f828831336ceafbc10834c19\n" }, { "commit": "b9b175086ce6c20480ec6bccdcf5a784f8cc8298", "tree": "4b765f0152ddf64d700f81412769394b5f337ee9", "parents": [ "e9467afb2d483ccec8f816902624d848e8f21d86" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Jun 15 15:06:43 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "refactor(measured-boot): split out a few Event Log driver functions\n\nReorganized a few Event Log functions into multiple functions so that\nthey can be used for the upcoming DRTM feature. This change mainly\nimplements below new functions -\n1. event_log_buf_init - called by \u0027event_log_init\u0027 to initialise Event\n Log buffer\n2. event_log_write_specid_event - called by \u0027event_log_fixed_header\u0027 to\n write specification id event to Event Log buffer\n3. event_log_measure and event_log_record - called by\n \u0027event_log_measure_and_record\u0027 to measure and record the measurement\n to the Event Log buffer\n\nChange-Id: I1aabb57f79bead726fcf36d59839702cd6a3521d\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "e9467afb2d483ccec8f816902624d848e8f21d86", "tree": "42676a769a7be7d35bc8d9c16345796fd7945cef", "parents": [ "2a1cdee4f5e6fe0b90399e442075880acad1869e" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Jun 16 13:46:43 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): retrieve DRTM features\n\nRetrieved below DRTM features via DRTM_FEATURES SMC call -\n1. TPM features\n2. Minimum memory requirement\n3. Boot PE ID\n4. DMA protection\n\nChange-Id: Ia6dc497259541ce30a6550afa35d95d9a9a366af\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\n" }, { "commit": "2a1cdee4f5e6fe0b90399e442075880acad1869e", "tree": "fcad28db94567a95dd811092c4df89e812b4cff3", "parents": [ "e6381f9cf8c0c62c32d5a4765aaf166f50786914" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Mar 11 17:50:58 2022 -0600" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): add platform functions for DRTM\n\nAdded platform hooks to retrieve DRTM features and\naddress map.\nAdditionally, implemented these hooks for the FVP platform.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: I5621cc9807ffff8139ae8876250147f7b2c76759\n" }, { "commit": "e6381f9cf8c0c62c32d5a4765aaf166f50786914", "tree": "60e96f3718afc0d1f8fcf4b252f527a818bf4327", "parents": [ "ff1e42e20aa247ba11cf81742abff07ece376ba8" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu May 12 12:49:55 2022 -0500" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(sdei): add a function to return total number of events registered\n\nThis patch adds a public API to return the total number of registered\nevents. The purpose of this is primarily for DRTM to ensure that no\nSDEI event can interfere with a dynamic launch.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I1d1cba2da7d5566cc340620ee1ce7d7844740b86\n" }, { "commit": "ff1e42e20aa247ba11cf81742abff07ece376ba8", "tree": "bd522fffe8a60ba955d7444b63b06476e86bb2f8", "parents": [ "d54792bd93f76b943bf0559c8373b898e0e3b93c" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Mar 03 11:42:27 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): add PCR entries for DRTM\n\nAdded PCR entries for the measurement performed by the\nDCE and D-CRTM in DRTM implementation\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: Ib9bfafe7fa2efa1cc36d7ff138468d648235dcf1\n" }, { "commit": "d54792bd93f76b943bf0559c8373b898e0e3b93c", "tree": "800ac6db6455586c2008695c4292fc7092f1b2ec", "parents": [ "2bf4f27f58ae510d428e3b55f020691a54bcba6f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Feb 24 20:22:39 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): update drtm setup function\n\nUpdated DRTM setup functionality that mainly does below 2 things\n1. Initialise the DRTM DMA protection, this function assumes the\n platform must support complete DMA protection.\n2. Initialise the Crypto module that will be useful to calculate\n the hash of various DRTM element involved.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\nChange-Id: I3d6e4d534686d391fa7626094d2b2535dac74e00\n" }, { "commit": "2bf4f27f58ae510d428e3b55f020691a54bcba6f", "tree": "825c3335c97430e33b175ab9c275edfb3c68c78b", "parents": [ "8b653909b7e2371c6dcddbeac112b9671c886f34" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Jun 20 15:32:38 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "refactor(crypto): change CRYPTO_SUPPORT flag to numeric\n\nUpdated CRYPTO_SUPPORT flag to numeric to provide below\nsupports -\n1. CRYPTO_SUPPORT \u003d 1 -\u003e Authentication verification only\n2. CRYPTO_SUPPORT \u003d 2 -\u003e Hash calculation only\n3. CRYPTO_SUPPORT \u003d 3 -\u003e Authentication verification and\n hash calculation\n\nChange-Id: Ib34f31457a6c87d2356d736ad2d048dc787da56f\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "8b653909b7e2371c6dcddbeac112b9671c886f34", "tree": "a91afcb57b340bc5e4559ccb0cc207765442a80a", "parents": [ "c9bd1bacffd9697ec4ebac77e45588cf6c261a3b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Feb 25 09:11:12 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(mbedtls): update mbedTLS driver for DRTM support\n\nUpdated mbedTLS driver to include mbedTLS functions necessary for a\nDRTM supported build.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: If0120374a971519cf84f93e0c59e1a320a72cd97\n" }, { "commit": "c9bd1bacffd9697ec4ebac77e45588cf6c261a3b", "tree": "876d8e227387c6ba7d3d929d188f934af99f4af7", "parents": [ "e43caf3890817e91b3d35b5ae1149a208f1a4016" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Feb 25 09:06:57 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(fvp): add crypto support in BL31\n\nDRTM implementation needs crypto support in BL31 to calculate\nhash of various DRTM components\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: I659ce8e54550946db253d23f150cca8b2fa7b880\n" }, { "commit": "e43caf3890817e91b3d35b5ae1149a208f1a4016", "tree": "afe2563fadbb0d7a723197dfdae2b05c74567855", "parents": [ "9e0d2bae7edfefa696c6e833fc54f23b6ce33efd" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Feb 25 08:29:35 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(crypto): update crypto module for DRTM support\n\nUpdated crypto module to include crypto calls necessary for a\nDRTM supported build.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: I4f945997824393f46864b7fb7fd380308a025452\n" }, { "commit": "9e0d2bae7edfefa696c6e833fc54f23b6ce33efd", "tree": "e0d8415648bc33e5dfd5990255d1ed0f64b717f7", "parents": [ "e62748e3f1f16934f0ef2d5742f3ca0b125eaea2" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Sep 22 21:41:55 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "build(changelog): add new scope for mbedTLS and Crypto module\n\nAdded new scope for mbedTLS and Crypto module.\n\nChange-Id: I127e7e32f103210e0a1c4c3072afa7249a24a7db\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "e62748e3f1f16934f0ef2d5742f3ca0b125eaea2", "tree": "a52c5c063435479377176037968cfb951f50b249", "parents": [ "7b224f19f467c11860e6a064846b02353b39575f" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Feb 23 11:26:53 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(drtm): add standard DRTM service\n\nAdded a dummy DRTM setup function and also, introduced DRTM SMCs\nhandling as per DRTM spec [1]. Few basic SMCs are handled in this\nchange such as ARM_DRTM_SVC_VERSION and ARM_DRTM_SVC_FEATURES\nthat returns DRTM version and functions ids supported respectively,\nand others are dummy for now.\n\n[1]: https://developer.arm.com/documentation/den0113/latest\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\nChange-Id: I8c7afe920c78e064cbab2298f59e6837c70ba8ff\n" }, { "commit": "7b224f19f467c11860e6a064846b02353b39575f", "tree": "9f7c95b4b3346858772d6fce4b87b768366042d1", "parents": [ "8a8dace5a5cd3a51d67df3cea86628f29cc96013" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Jun 27 09:21:14 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "build(changelog): add new scope for DRTM service\n\nAdded new scope for DRTM service.\n\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\nChange-Id: Idffb178026ef2910102b55e640d5f5bf904e6064\n" }, { "commit": "8a8dace5a5cd3a51d67df3cea86628f29cc96013", "tree": "2d300b304e88a3647b6f71c6fccbb8578a28a4d5", "parents": [ "44df105ff867aeb2aa5d20faa3e8389866099956" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Feb 23 09:47:59 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(fvp): increase MAX_XLAT_TABLES entries for DRTM support\n\nDRTM implementation maps the DLME data region provided by the\nDCE-preamble in BL31, hence increased MAX_XLAT_TABLES entries\ncount.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\nChange-Id: I5f0ac69e009c4f81d3590fdb1f4c0a7f73c5c99d\n" }, { "commit": "44df105ff867aeb2aa5d20faa3e8389866099956", "tree": "f855b8985c98d372f7089976ab61087cc04dab6d", "parents": [ "d72c486b52dc654e4216d41dcc1b0f87bdbdf3e9" ], "author": { "name": "Lucian Paul-Trifu", "email": "lucian.paultrifu@gmail.com", "time": "Wed Feb 23 09:34:45 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(fvp): increase BL31\u0027s stack size for DRTM support\n\nThe stack size of BL31 has been increased to accommodate the\nintroduction of mbedTLS support for DRTM.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\nChange-Id: Id0beacf4df553af4ecbe714af20e71604ccfed59\n" }, { "commit": "d72c486b52dc654e4216d41dcc1b0f87bdbdf3e9", "tree": "f432e56f590ade8ff0ef6d8d7a24b8de20f6adb5", "parents": [ "6f70cce62592ddef2c551a146590f72e95fb9dd1" ], "author": { "name": "Lucian Paul-Trifu", "email": "lucian.paultrifu@gmail.com", "time": "Wed Jun 22 18:45:30 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Oct 05 15:25:28 2022 +0100" }, "message": "feat(fvp): add platform hooks for DRTM DMA protection\n\nAdded necessary platform hooks for DRTM DMA protection.\nThese calls will be used by the subsequent DRTM implementation\npatches.\nDRTM platform API declarations have been listed down in a\nseparate header file.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nSigned-off-by: Lucian Paul-Trifu \u003clucian.paultrifu@gmail.com\u003e\nChange-Id: Ib9726d1d3570800241bde702ee7006a64f1739ec\n" }, { "commit": "6f70cce62592ddef2c551a146590f72e95fb9dd1", "tree": "2e80ea46fe37395073f0b83e7eb2454ccb335235", "parents": [ "2ddb5415ca0e5642f16bd0eee6f8f29a95d15c34", "337ff4f1dd6604738d79fd3fa275ae74d74256b2" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Oct 05 15:08:32 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 05 15:08:32 2022 +0200" }, "message": "Merge \"fix(qemu): enable SVE and SME\" into integration" }, { "commit": "2ddb5415ca0e5642f16bd0eee6f8f29a95d15c34", "tree": "27653e3c4cf6dd4f02db3ff2fd1c2b3f8acfb22c", "parents": [ "af1ee1fad2437772553aefcc682e2e9f53e72419", "ab545efddcdbf5d08ad3b1e8f4ea15a0faf168a7" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Oct 05 14:44:05 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 05 14:44:05 2022 +0200" }, "message": "Merge \"fix(rss): fix build issues with comms protocol\" into integration" }, { "commit": "ab545efddcdbf5d08ad3b1e8f4ea15a0faf168a7", "tree": "b80b56644a7a1c9a8b1e5ccf3b6fb0cba760735f", "parents": [ "b97b2817ac438a0ba6df45cd159df84ae793bd31" ], "author": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Mon Oct 03 15:34:02 2022 +0200" }, "committer": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Wed Oct 05 13:37:35 2022 +0200" }, "message": "fix(rss): fix build issues with comms protocol\n\nSigned-off-by: Tamas Ban \u003ctamas.ban@arm.com\u003e\nChange-Id: I77d2d3c5ac39a840b768f84f859d76b3965749aa\n" }, { "commit": "af1ee1fad2437772553aefcc682e2e9f53e72419", "tree": "4569d0ec6fc07509f5071839066d8018e017907d", "parents": [ "a9120f596f1f34d67132f770d56c31bd34b47b05", "cd7890d79e9d508e82f3078f02e8277f8c8df181" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Oct 05 13:37:10 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 05 13:37:10 2022 +0200" }, "message": "Merge changes from topic \"mt8188 cpu_pm\" into integration\n\n* changes:\n feat(mediatek): move lpm drivers back to common\n feat(mt8188): add cpu_pm driver\n fix(mt8188): refine c-state power domain for extensibility\n" }, { "commit": "a9120f596f1f34d67132f770d56c31bd34b47b05", "tree": "2b25e527d4811799e55be43211cb4c68cf99a684", "parents": [ "4f2c4ecfb087dd32b277000dc1578837dee1fd71", "8a998b5aca3ca895a7722e7496a7fd18cd838f94" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Oct 05 11:31:36 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 05 11:31:36 2022 +0200" }, "message": "Merge \"fix(mt8186-emi-mpu): fix SCP permission\" into integration" }, { "commit": "337ff4f1dd6604738d79fd3fa275ae74d74256b2", "tree": "dc1dfa97f8e30ff7c51bf3719701eab311248b4f", "parents": [ "4f2c4ecfb087dd32b277000dc1578837dee1fd71" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Oct 04 13:41:32 2022 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Oct 05 10:17:55 2022 +0100" }, "message": "fix(qemu): enable SVE and SME\n\nStarting with QEMU v3.1.0 (Dec 2018), QEMU\u0027s TCG emulation engine supports\nthe SVE architecture extension. In QEMU v7.1.0 (Aug 2022) it also gained\nSME support.\n\nAs it stands today, running TF-A under QEMU with \"-cpu max\" makes Linux\nhang, because SME and SVE accesses trap to EL3, but are never handled\nthere. This is because the Linux kernel sees the SVE or SME feature bits,\nand assumes firmware has enabled the feature for lower exception levels.\nThis requirement is described in the Linux kernel booting protocol.\n\nEnable those features in the TF-A build, so that BL31 does the proper\nEL3 setup to make the feature usable in non-secure world.\nWe check the actual feature bits before accessing SVE or SME registers,\nso this is safe even for older QEMU version or when not running with\n-cpu max. As SVE and SME are AArch64 features only, do not enable them\nwhen building for AArch32.\n\nChange-Id: I5b718eb298a0bbcf36244479e8d42e54a2faca61\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "4f2c4ecfb087dd32b277000dc1578837dee1fd71", "tree": "55624b38c8b6c86eb4bebe76fb19c4ef3f78abd9", "parents": [ "afc9b23b13e679a735182a261ffde25982f23889", "0423868373026a667f0c004e4d365fa12fd734ef" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Oct 05 11:15:28 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 05 11:15:28 2022 +0200" }, "message": "Merge changes from topic \"aarch32_debug_aborts\" into integration\n\n* changes:\n feat(stm32mp1): add plat_report_*_abort functions\n feat(debug): add helpers for aborts on AARCH32\n feat(debug): add AARCH32 CP15 fault registers\n" }, { "commit": "afc9b23b13e679a735182a261ffde25982f23889", "tree": "5c78349902f3e4700472686684e43aac874aae56", "parents": [ "c19116dd61068d70808ff71efbe914e50a5346e3", "29e6fc5cc7d0c8bc4ba615fd97df4cb65d3c7ba3" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Oct 05 11:00:26 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Oct 05 11:00:26 2022 +0200" }, "message": "Merge \"feat(fvp): support building RSS comms driver\" into integration" }, { "commit": "c19116dd61068d70808ff71efbe914e50a5346e3", "tree": "a85db3b3bf0391f266f8e8ababb6215fa7c96631", "parents": [ "b97b2817ac438a0ba6df45cd159df84ae793bd31", "e0b6826e44116fb6f261df1fc06b269721d29999" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Oct 04 17:06:43 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 04 17:06:43 2022 +0200" }, "message": "Merge \"refactor(console): move putchar() to console driver\" into integration" }, { "commit": "8a998b5aca3ca895a7722e7496a7fd18cd838f94", "tree": "61c913440165ac9942168ae31e76eec537e8a7d2", "parents": [ "b97b2817ac438a0ba6df45cd159df84ae793bd31" ], "author": { "name": "Yidi Lin", "email": "yidilin@chromium.org", "time": "Mon Oct 03 19:26:33 2022 +0800" }, "committer": { "name": "Yidi Lin", "email": "yidilin@chromium.org", "time": "Tue Oct 04 22:31:16 2022 +0800" }, "message": "fix(mt8186-emi-mpu): fix SCP permission\n\nHardware video decoding is not working after enabling EMI MPU protection\nfor SCP.\n\nAccording to coreboot DEVAPC setting, SCP belongs to domain 4 instead of\ndomain 3. So correct the permission setting.\n\nBUG\u003db:249954378\nTEST\u003dplay video and see codec irq count is incrementing.\n\nSigned-off-by: Yidi Lin \u003cyidilin@chromium.org\u003e\nChange-Id: If71de3eabf8682909f96924c159aa92f25deb96c\n" }, { "commit": "b97b2817ac438a0ba6df45cd159df84ae793bd31", "tree": "6d61d87ab5608c8300b0ee4b48d7803b406ad2cb", "parents": [ "252b2bd8a3ad648a0bb49e79e55d4b7b1dfe06d3", "b0eb6d124b1764264778d17b1519bfe62b7b9337" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Oct 04 11:50:43 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 04 11:50:43 2022 +0200" }, "message": "Merge \"fix(versal-net): use api_id directly without FUNCID_MASK\" into integration" }, { "commit": "252b2bd8a3ad648a0bb49e79e55d4b7b1dfe06d3", "tree": "2653b61fd4052b33a7d20ce738ef1f18ddb374b6", "parents": [ "9bd1aed30ddee8415a198209f5bb6f0b72a70104", "91890b7ab32e3118e778fab4e10dd81ac999eb1a" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Oct 04 10:45:50 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Oct 04 10:45:50 2022 +0200" }, "message": "Merge changes I134f125f,Ia4bf45bf into integration\n\n* changes:\n refactor(sgi): rename RD-Edmunds to RD-V2\n refactor(cpu): use the updated IP name for Demeter CPU\n" }, { "commit": "e0b6826e44116fb6f261df1fc06b269721d29999", "tree": "2081d3e2d813786456b70d7f657554d1963c946f", "parents": [ "9bd1aed30ddee8415a198209f5bb6f0b72a70104" ], "author": { "name": "Claus Pedersen", "email": "claustbp@google.com", "time": "Mon Sep 12 23:47:10 2022 +0000" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Oct 04 09:30:48 2022 +0200" }, "message": "refactor(console): move putchar() to console driver\n\nMoving putchar() out of libc and adding a weak dummy\nimplementation in libc.\n\nThis is to remove libc\u0027s dependencies to the platform\ndriver.\n\nSigned-off-by: Claus Pedersen \u003cclaustbp@google.com\u003e\nChange-Id: Ib7fefaec0babb783def614ea23521f482fa4a28a\n" }, { "commit": "cd7890d79e9d508e82f3078f02e8277f8c8df181", "tree": "bf2b0ca5d882e5b82cc8a38afc16fb0cababe7ef", "parents": [ "4fe7e6a8d9f09c40d087167432cb07621c175b3f" ], "author": { "name": "Bo-Chen Chen", "email": "rex-bc.chen@mediatek.com", "time": "Thu Sep 29 10:41:26 2022 +0800" }, "committer": { "name": "Bo-Chen Chen", "email": "rex-bc.chen@mediatek.com", "time": "Tue Oct 04 09:52:10 2022 +0800" }, "message": "feat(mediatek): move lpm drivers back to common\n\nIn order to sync drivers with MediaTek internal code base, we move lpm\ndrivers back to common folder.\n\nSigned-off-by: Bo-Chen Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I1066e092febe0abb9782a46f668613e137737c88\n" }, { "commit": "4fe7e6a8d9f09c40d087167432cb07621c175b3f", "tree": "9170fcda8d83e23a1c6cdf2914e5dd0869d53714", "parents": [ "e35f4cbf80ba671c42644c1ac7f8f6541042c6e5" ], "author": { "name": "Edward-JW Yang", "email": "edward-jw.yang@mediatek.com", "time": "Mon Sep 05 17:36:36 2022 +0800" }, "committer": { "name": "Bo-Chen Chen", "email": "rex-bc.chen@mediatek.com", "time": "Tue Oct 04 09:52:10 2022 +0800" }, "message": "feat(mt8188): add cpu_pm driver\n\n- Add cpu_pm driver for CPU idle and SMP flow.\n- Add SMP driver for CPU power on/off control.\n- Add CPC driver to handle CPU powered on/off in CPU suspend.\n- Add mbox driver for tinysys support.\n\nSigned-off-by: Edward-JW Yang \u003cedward-jw.yang@mediatek.com\u003e\nChange-Id: I20141474e1c43cdfacb9f2c6a2285721e50a617c\n" }, { "commit": "e35f4cbf80ba671c42644c1ac7f8f6541042c6e5", "tree": "ad8008ae7f13fb46b3acf9e06fbdf4962bc0dcdd", "parents": [ "9bd1aed30ddee8415a198209f5bb6f0b72a70104" ], "author": { "name": "Edward-JW Yang", "email": "edward-jw.yang@mediatek.corp-partner.google.com", "time": "Thu Sep 15 21:09:10 2022 +0800" }, "committer": { "name": "Bo-Chen Chen", "email": "rex-bc.chen@mediatek.com", "time": "Tue Oct 04 09:44:08 2022 +0800" }, "message": "fix(mt8188): refine c-state power domain for extensibility\n\n1. MT8188 uses \"suspend to RAM\" instead of \"suspend to idle\", so\n remove s2idle state.\n2. Definition c-state power domain:\n - bit[7:4] (main state id):\n 1: Cluster.\n 2: Mcusys.\n 3: Memory.\n 4: System pll.\n 5: System bus.\n 6: SoC 26m/DCXO.\n 7: Vcore buck.\n 15: Suspend.\n - bit[3:0] (reserved for state_id extension):\n 4: CPU buck.\n\nSigned-off-by: Edward-JW Yang \u003cedward-jw.yang@mediatek.corp-partner.google.com\u003e\nChange-Id: Ibacd3d642f78726e1f1c08f18892481d2695f9e6\n" }, { "commit": "9bd1aed30ddee8415a198209f5bb6f0b72a70104", "tree": "45fb079e9c88af60d4c4ebebc63b6263ed210c89", "parents": [ "967d8c99f42990aeca1e5fdd332795dbb3787276", "b41b082464a164f32a5f1397894619c6b0680ed3" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Oct 03 16:46:52 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 16:46:52 2022 +0200" }, "message": "Merge \"refactor(psci): unify psci_is_last_on_cpu and psci_is_last_on_cpu_safe\" into integration" }, { "commit": "0423868373026a667f0c004e4d365fa12fd734ef", "tree": "60699886899df2e686fe0687ba22c27cdb010792", "parents": [ "6dc5979a6cb2121e4c16e7bd62e24030e0f42755" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Aug 29 19:04:29 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Oct 03 14:44:05 2022 +0200" }, "message": "feat(stm32mp1): add plat_report_*_abort functions\n\nThe new helpers are created in STM32MP1 platform for prefetch and data\naborts.\nWhile at it, put plat_report_exception() under DEBUG flag. If DEBUG is\nnot set, the weak function which does the same will be used.\nThis plat_report_exception() function can also be simplified, as it will\nno more be used to report aborts.\n\nChange-Id: Ibe989b28e236693f317cffb0545ea0611b7bdde4\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "6dc5979a6cb2121e4c16e7bd62e24030e0f42755", "tree": "7ebdf7c842237a33b42e2451016c1804d1156d55", "parents": [ "bb2289142cbf0f3546c1034e0500b5dc32aef740" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Feb 15 16:42:20 2019 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Oct 03 14:42:40 2022 +0200" }, "message": "feat(debug): add helpers for aborts on AARCH32\n\nNew helper functions are created to handle data \u0026 prefetch aborts\nin AARCH32. They call platform functions, just like what\nreport_exception is doing.\nAs extended MSR/MRS instructions (to access lr_abt in monitor mode)\nare only available if CPU (Armv7) has virtualization extension,\nthe functions branch to original report_exception handlers if this is\nnot the case.\nThose new helpers are created mainly to distinguish data and prefetch\naborts, as they both share the same mode.\nThis adds 40 bytes of code.\n\nChange-Id: I5dd31930344ad4e3a658f8a9d366a87a300aeb67\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "bb2289142cbf0f3546c1034e0500b5dc32aef740", "tree": "0646c660498de452bd11e45e7ea61dfc8153542b", "parents": [ "967d8c99f42990aeca1e5fdd332795dbb3787276" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue May 21 18:59:18 2019 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Oct 03 14:06:25 2022 +0200" }, "message": "feat(debug): add AARCH32 CP15 fault registers\n\nFor an easier debug on Aarch32, in case of abort, it is useful to access\nDFSR, IFSR, DFAR and IFAR CP15 registers.\n\nChange-Id: Ie6b5a2882cd701f76e9d455ec43bd4b0fbe3cc78\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "b0eb6d124b1764264778d17b1519bfe62b7b9337", "tree": "d9ea19eac85350d57169da92baf994fe08ed17da", "parents": [ "aa9d315009fba78cb3135b06d93001b2b18cf748" ], "author": { "name": "Michal Simek", "email": "michal.simek@amd.com", "time": "Mon Oct 03 14:02:57 2022 +0200" }, "committer": { "name": "Michal Simek", "email": "michal.simek@amd.com", "time": "Mon Oct 03 14:03:38 2022 +0200" }, "message": "fix(versal-net): use api_id directly without FUNCID_MASK\n\nThe purpose of this code is to extract api_id from smc_fid but this masking\nis done already in the code with using generic mask from smccc.h\n(FUNCID_NUM_MASK). That\u0027s why remove FUNCID_MASK is which not needed and\nactually also equal to already used FUNCID_NUM_MASK.\n\nSigned-off-by: Michal Simek \u003cmichal.simek@amd.com\u003e\nChange-Id: I1113825baa5d9d58d9d7c5d9d5855fecf62e8d45\n" }, { "commit": "967d8c99f42990aeca1e5fdd332795dbb3787276", "tree": "462a5fabbaf8f1a72b617d832be95c8b5b207c62", "parents": [ "e8f4ec1ab0b52dce2e4f0ab522853642881cde95", "4348497acedef2c932df79af4a4f648658625b72" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 13:37:54 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 13:37:54 2022 +0200" }, "message": "Merge \"build(rss): introduce rss_comms.mk makefile\" into integration" }, { "commit": "29e6fc5cc7d0c8bc4ba615fd97df4cb65d3c7ba3", "tree": "e68651947a4bec7eae4ff29627b2c26cc3a48536", "parents": [ "4348497acedef2c932df79af4a4f648658625b72" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Aug 31 14:05:38 2022 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 12:52:21 2022 +0200" }, "message": "feat(fvp): support building RSS comms driver\n\nOn one hand, there is currently no upstream platform supporting the\nRSS. On the other hand, we are gradually introducing driver code for\nRSS. Even though we cannot test this code in the TF-A CI right now, we\ncan at least build it to make sure no build regressions are introduced\nas we continue development.\n\nThis patch adds support for overriding PLAT_RSS_NOT_SUPPORTED build\nflag (which defaults to 1 on the Base AEM FVP) from the command\nline. This allows introducing an ad-hoc CI build config with\nPLAT_RSS_NOT_SUPPORTED\u003d0, which will correctly pull in the RSS and MHU\nsource files. Of course, the resulting firmware will not be\nfunctional.\n\nChange-Id: I2b0e8dd03bf301e7063dd4734ea5266b73265be1\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "4348497acedef2c932df79af4a4f648658625b72", "tree": "462a5fabbaf8f1a72b617d832be95c8b5b207c62", "parents": [ "e8f4ec1ab0b52dce2e4f0ab522853642881cde95" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed Aug 31 13:53:10 2022 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 12:44:36 2022 +0200" }, "message": "build(rss): introduce rss_comms.mk makefile\n\nProvide a new makefile as a convenience for platform makefiles to pull\nin the list of source files and headers for the RSS communication\ndriver.\n\nChange-Id: I188a1a8f4e77318cdc87c3155b280090c46ce813\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "91890b7ab32e3118e778fab4e10dd81ac999eb1a", "tree": "a74162239191cb495679a58d87656981abda0969", "parents": [ "bd063a73a86b8845d06730fa7afde8f5061fef60" ], "author": { "name": "Joel Goddard", "email": "joel.goddard@arm.com", "time": "Wed Sep 21 21:51:12 2022 +0530" }, "committer": { "name": "Joel Goddard", "email": "joel.goddard@arm.com", "time": "Mon Oct 03 15:31:40 2022 +0530" }, "message": "refactor(sgi): rename RD-Edmunds to RD-V2\n\nNeoverse Reference Design platform RD-Edmunds has been renamed to RD-V2\nand so all corresponding references have been changed.\n\nSigned-off-by: Joel Goddard \u003cjoel.goddard@arm.com\u003e\nChange-Id: I134f125f8ce9ec2f42988ecd742de307da936f2b\n" }, { "commit": "bd063a73a86b8845d06730fa7afde8f5061fef60", "tree": "80d68fbbdfbb98ce42e233ed327fe92307afef8f", "parents": [ "e8f4ec1ab0b52dce2e4f0ab522853642881cde95" ], "author": { "name": "Joel Goddard", "email": "joel.goddard@arm.com", "time": "Wed Sep 21 21:52:28 2022 +0530" }, "committer": { "name": "Joel Goddard", "email": "joel.goddard@arm.com", "time": "Mon Oct 03 15:31:40 2022 +0530" }, "message": "refactor(cpu): use the updated IP name for Demeter CPU\n\nNeoverse Demeter CPU has been renamed to Neoverse V2 CPU.\nCorrespondingly, update the CPU library, file names and other\nreferences to use the updated IP name.\n\nSigned-off-by: Joel Goddard \u003cjoel.goddard@arm.com\u003e\nChange-Id: Ia4bf45bf47807c06f4c966861230faea420d088f\n" }, { "commit": "e8f4ec1ab0b52dce2e4f0ab522853642881cde95", "tree": "ec6e115cf7c95fbaa77e1bd8ef635af9cbdd2eec", "parents": [ "8efbd9dc29c4d1c87a503a5d40d7b5f80985551b", "14a070408d9231dc1c487dfe36058b93faf5915c" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Oct 03 11:58:07 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 11:58:07 2022 +0200" }, "message": "Merge changes from topic \"st_uart_updates\" into integration\n\n* changes:\n feat(stm32mp1): add early console in SP_min\n feat(st): properly manage early console\n feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE\n docs(st): introduce STM32MP_RECONFIGURE_CONSOLE\n feat(st): add trace for early console\n fix(stm32mp1): enable crash console in FIQ handler\n feat(st-uart): add initialization with the device tree\n refactor(stm32mp1): move DT_UART_COMPAT in include file\n feat(stm32mp1): configure the serial boot load address\n fix(stm32mp1): update the FIP load address for serial boot\n refactor(st): configure baudrate for UART programmer\n refactor(st-uart): compute the over sampling dynamically\n" }, { "commit": "8efbd9dc29c4d1c87a503a5d40d7b5f80985551b", "tree": "7c07945c6ef5e1e453c6998d9454ad17bad50490", "parents": [ "4db1bd801c8ccef9c8f643ad1339b49c769be287", "08ae2471b1417f1d8083a79771338aa2a00b6711" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 11:21:28 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 11:21:28 2022 +0200" }, "message": "Merge \"fix(rcar3): fix RPC-IF device node name\" into integration" }, { "commit": "4db1bd801c8ccef9c8f643ad1339b49c769be287", "tree": "8c0ccfc2d403298835da27ae8526a5c5ab64725a", "parents": [ "fe8573ef1c2c935213a40e2822e113cff2b255fd", "0d33d38334cae909a66c74187a36b5833afb8093" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Oct 03 11:14:30 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 11:14:30 2022 +0200" }, "message": "Merge \"fix(st): add missing string.h include\" into integration" }, { "commit": "fe8573ef1c2c935213a40e2822e113cff2b255fd", "tree": "4ecdf4f8a5145072e361f9a64f238bc71acfbf73", "parents": [ "34cf68ad4a2dc558affa8a4d7198f039ed0a5513", "dd7adcf3a89a75973a88118eeb867d1c212c4ad0" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 10:51:09 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 10:51:09 2022 +0200" }, "message": "Merge \"fix(intel): fix asynchronous read response by copying data to input buffer\" into integration" }, { "commit": "34cf68ad4a2dc558affa8a4d7198f039ed0a5513", "tree": "e054f64da45ee36365827a350e50a504602cc43d", "parents": [ "aa9d315009fba78cb3135b06d93001b2b18cf748", "fbf7aef408a9f67fabc712bbfd52438290364879" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 10:50:01 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Oct 03 10:50:01 2022 +0200" }, "message": "Merge \"fix(intel): fix Mac verify update and finalize for return response data\" into integration" }, { "commit": "08ae2471b1417f1d8083a79771338aa2a00b6711", "tree": "e8c683b073d4cda60d3b9853e61e30be3108c1de", "parents": [ "aa9d315009fba78cb3135b06d93001b2b18cf748" ], "author": { "name": "Geert Uytterhoeven", "email": "geert+renesas@glider.be", "time": "Wed Mar 23 14:21:31 2022 +0100" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Oct 03 10:47:23 2022 +0200" }, "message": "fix(rcar3): fix RPC-IF device node name\n\nAccording to the Generic Names Recommendation in the Devicetree\nSpecification Release v0.3, and the DT Bindings for the Renesas Reduced\nPin Count Interface, the node name for a Renesas RPC-IF device should be\n\"spi\". The node name matters, as the node is enabled by passing a DT\nfragment from TF-A to subsequent software.\n\nFix this by renaming the device node in the passed DT fragment from\n\"rpc\" to \"spi\".\n\nFixes: 12c75c8886a0ee69 (\"feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked\")\nSigned-off-by: Geert Uytterhoeven \u003cgeert+renesas@glider.be\u003e\nChange-Id: Idb43353947607611331abc344f8c8ae932a20408\n" }, { "commit": "0d33d38334cae909a66c74187a36b5833afb8093", "tree": "91543cdb02e2c78092912bab5967eede651ce20a", "parents": [ "aa9d315009fba78cb3135b06d93001b2b18cf748" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Oct 03 09:30:34 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Oct 03 10:00:03 2022 +0200" }, "message": "fix(st): add missing string.h include\n\nSince patch on libc refactoring, there is a compilation error with\nSTM32MP_USB_PROGRAMMER\u003d1:\nplat/st/common/stm32cubeprogrammer_usb.c:81:35: error:\n implicit declaration of function \u0027strnlen\u0027\n [-Werror\u003dimplicit-function-declaration]\n length +\u003d strnlen((char *)\u0026dfu-\u003ebuffer[GET_PHASE_LEN],\n\nThe string.h header file should be included.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I1fbb2d9714cbc0d0640cb5e3c5ae8201dbfbe14e\n" }, { "commit": "aa9d315009fba78cb3135b06d93001b2b18cf748", "tree": "a6dadb816f43965388fbd42679c46dd4d03bb683", "parents": [ "8e834443a2c0cee8284419c91b8aa6db4755b92b", "c5862af72d5c2f2b637d9d54c29d2d5e43a3b991" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Sep 30 17:50:15 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 30 17:50:15 2022 +0200" }, "message": "Merge \"chore(libc): clean up includes in lib/libc/printf.c\" into integration" }, { "commit": "8e834443a2c0cee8284419c91b8aa6db4755b92b", "tree": "d6c2022c2db14da6cb8d1c5fe884c29644b46753", "parents": [ "76250d51d65b78e9dfc6bc1929bcdf87e8149ba5", "833b4ffefd42601e9d1d8f929ccbf8d0da7c23e6" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Fri Sep 30 15:35:42 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 30 15:35:42 2022 +0200" }, "message": "Merge \"docs(changelog): fix incorrect documentation title\" into integration" }, { "commit": "76250d51d65b78e9dfc6bc1929bcdf87e8149ba5", "tree": "4f0b1e28bc4a300b4d8d40234c0f974f34aa7a48", "parents": [ "2c16b802cb50c73956e2498e5757063f2d4df9d4", "c889088386432af69e3ca853825c4219884c1cc1" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Sep 30 14:35:25 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 30 14:35:25 2022 +0200" }, "message": "Merge \"fix(zynqmp): resolve MISRA-C:2012 R.10.1 warnings\" into integration" }, { "commit": "2c16b802cb50c73956e2498e5757063f2d4df9d4", "tree": "976073b5ecafff600c6cb26b3c0910ee6417f8f6", "parents": [ "62068b10a31d8a1d61d9b0bf40f4f04a564fe4d2", "00e8f79c15d36f65f6c7f127177105e02177cbc0" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Sep 30 14:14:26 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 30 14:14:26 2022 +0200" }, "message": "Merge \"fix(ras): trap \"RAS error record\" accesses only for NS\" into integration" }, { "commit": "c889088386432af69e3ca853825c4219884c1cc1", "tree": "c29f817653e6f6dad3d602e738cd4173278c67bf", "parents": [ "62068b10a31d8a1d61d9b0bf40f4f04a564fe4d2" ], "author": { "name": "HariBabu Gattem", "email": "haribabu.gattem@amd.com", "time": "Thu Sep 29 23:59:11 2022 -0700" }, "committer": { "name": "HariBabu Gattem", "email": "haribabu.gattem@amd.com", "time": "Fri Sep 30 10:40:34 2022 +0200" }, "message": "fix(zynqmp): resolve MISRA-C:2012 R.10.1 warnings\n\nMISRA Violation: MISRA-C: 2012 R.10.1\n- The operand to the operator does not have an essentially\nunsigned type.\n\nSigned-off-by: HariBabu Gattem \u003charibabu.gattem@amd.com\u003e\nChange-Id: I0f974e9d6f63dddfab55d55c952a57645d931e40\n" }, { "commit": "833b4ffefd42601e9d1d8f929ccbf8d0da7c23e6", "tree": "4bb1aeb42290ad09696dee15dadfbc2000b39074", "parents": [ "58aebb6a53170cca6211e400e6630d2747bac9de" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 29 16:42:23 2022 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Thu Sep 29 16:56:12 2022 +0100" }, "message": "docs(changelog): fix incorrect documentation title\n\nChange-Id: Idb4b174f65891ba406f83c213c80ebb8a6ba0b81\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "b41b082464a164f32a5f1397894619c6b0680ed3", "tree": "03ec4ee0dfe637cbb3d987c6f6875c1e8289b3de", "parents": [ "ea7aee20c1fed0d206020ccb8541c2fa8d4a3795" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Mon Aug 22 23:46:10 2022 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Thu Sep 29 16:37:34 2022 +0100" }, "message": "refactor(psci): unify psci_is_last_on_cpu and psci_is_last_on_cpu_safe\n\n\"psci_is_last_on_cpu\" and \"psci_is_last_on_cpu_safe\" modules perform\nmostly similar functionalities, verifying whether the current CPU\nis the only active core and other cores have been turned off.\n\nHowever, psci_is_last_on_cpu_safe function differs from the other with:\n1. Safe API locks the power domain\n\nThis patch removes the section duplicating the functionality\nand ensures that \"psci_is_last_on_cpu api\",is reused in\n\"psci_is_last_on_cpu_safe\" procedure.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: Ie372519e423898d7afa5427cdd77a7f9d3369587\n" }, { "commit": "62068b10a31d8a1d61d9b0bf40f4f04a564fe4d2", "tree": "33e9dd629f301254a619496da9762749e1986383", "parents": [ "76453e7e7e8d099fc0560a36786e3eee44af0f61", "18af644279b36e841068db0e1c857dedf1456b38" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Sep 29 16:45:48 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 29 16:45:48 2022 +0200" }, "message": "Merge \"feat(ls1043ardb): update ddr configure for ls1043ardb-pd\" into integration" }, { "commit": "76453e7e7e8d099fc0560a36786e3eee44af0f61", "tree": "c81d2d75b6841d5f68b486369e9e69c01619fd0b", "parents": [ "ea7aee20c1fed0d206020ccb8541c2fa8d4a3795", "364b4cddbab859a56e63813aab4e983433187191" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Sep 29 16:39:01 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 29 16:39:01 2022 +0200" }, "message": "Merge \"fix(rme): update FVP platform token\" into integration" }, { "commit": "364b4cddbab859a56e63813aab4e983433187191", "tree": "c81d2d75b6841d5f68b486369e9e69c01619fd0b", "parents": [ "ea7aee20c1fed0d206020ccb8541c2fa8d4a3795" ], "author": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Mon Sep 19 16:46:49 2022 +0200" }, "committer": { "name": "Mate Toth-Pal", "email": "mate.toth-pal@arm.com", "time": "Thu Sep 29 15:35:18 2022 +0200" }, "message": "fix(rme): update FVP platform token\n\nUpdate test CCA Platform token in fvp_plat_attest_token.c to be\nup-to-date with RMM spec Beta0.\n\nChange-Id: I0f5e2ac1149eb6f7a93a997682f41d90e109a049\nSigned-off-by: Mate Toth-Pal \u003cmate.toth-pal@arm.com\u003e\n" }, { "commit": "ea7aee20c1fed0d206020ccb8541c2fa8d4a3795", "tree": "380e74fab135d133fc125780c88ba000b6da0078", "parents": [ "a291687de235da617afe25ad5226f448cac5c567", "8e51cccaefc1e0e79ac2f0667ffec1cc46cf7665" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Sep 29 10:25:57 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 29 10:25:57 2022 +0200" }, "message": "Merge \"fix(rmmd): return X4 output value\" into integration" }, { "commit": "a291687de235da617afe25ad5226f448cac5c567", "tree": "b16a7a6d07af40dc6b73551964bed548b8820524", "parents": [ "711ce52bc694cbcd64e3bed7bfc690269cf0fa7e", "cdb62114cfcdaeb85e64bcde459342a0a95f58e3" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Thu Sep 29 10:15:01 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 29 10:15:01 2022 +0200" }, "message": "Merge \"fix(zynqmp): resolve misra 4.6 warnings\" into integration" }, { "commit": "711ce52bc694cbcd64e3bed7bfc690269cf0fa7e", "tree": "a42fd1863aecff71229608311a94c1b93c240e02", "parents": [ "3a3722c9e15a41bc9811c7f1fb8eade32405f0c1", "31259019235aebf7aa533d5c893940f597fb1a8b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu Sep 29 08:20:59 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Sep 29 08:20:59 2022 +0200" }, "message": "Merge \"feat(rss): add new comms protocols\" into integration" }, { "commit": "00e8f79c15d36f65f6c7f127177105e02177cbc0", "tree": "06569ac7e9de7f15a77bd4826834b259a422c11a", "parents": [ "d8d0ea9a7fcd5ace63a8c863176d9535adfc581d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue Sep 27 14:30:34 2022 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Sep 28 17:10:57 2022 +0100" }, "message": "fix(ras): trap \"RAS error record\" accesses only for NS\n\nRAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error\nrecord registers (RAS ERR* \u0026 RAS ERX*) from lower EL\u0027s in any security\nstate. To give more fine grain control per world basis re-purpose this\nmacro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only\nif Error record registers are accessed from NS.\nThis will also help in future scenarios when RAS handling(in Firmware\nfirst handling paradigm)can be offloaded to a secure partition.\n\nThis is first patch in series to refactor RAS framework in TF-A.\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Ifa7f60bc8c82c9960adf029001bc36c443016d5d\n" }, { "commit": "3a3722c9e15a41bc9811c7f1fb8eade32405f0c1", "tree": "dd7b460bb38f4963d5fe90a7bc23cdcc68a8c7e9", "parents": [ "58aebb6a53170cca6211e400e6630d2747bac9de", "066450abf326f1a68a21cdddf29f62eff95041a9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Sep 28 16:06:45 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 28 16:06:45 2022 +0200" }, "message": "Merge \"fix(tc): resolve the static-checks errors\" into integration" }, { "commit": "8e51cccaefc1e0e79ac2f0667ffec1cc46cf7665", "tree": "4238dd82a225934060809e762f05d7fab3370e6a", "parents": [ "aef9b0da2aa64b2bb6cd12bb43589074d861d3ac" ], "author": { "name": "AlexeiFedorov", "email": "Alexei.Fedorov@arm.com", "time": "Fri Sep 23 16:57:28 2022 +0100" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Sep 28 15:11:03 2022 +0200" }, "message": "fix(rmmd): return X4 output value\n\nReturn values contained in \u0027smc_result\u0027 structure\nare shifted down by one register:\nX1 written by RMM is returned to NS in X0 and\nX5 is returned in X4.\n\nSigned-off-by: AlexeiFedorov \u003cAlexei.Fedorov@arm.com\u003e\nChange-Id: I92907ac3ff3bac8554643ae7c198a4a758c38cb3\n" }, { "commit": "066450abf326f1a68a21cdddf29f62eff95041a9", "tree": "dd7b460bb38f4963d5fe90a7bc23cdcc68a8c7e9", "parents": [ "58aebb6a53170cca6211e400e6630d2747bac9de" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Sep 28 11:41:48 2022 +0100" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Wed Sep 28 13:48:12 2022 +0100" }, "message": "fix(tc): resolve the static-checks errors\n\nConverted the space indentation to tabs to fix the\nerrors listed under tf-static-checks CI job.\n\nChange-Id: Ie911a5befd0eeaa5a2019245cc3c43ad375cd068\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\n" }, { "commit": "31259019235aebf7aa533d5c893940f597fb1a8b", "tree": "eeba2cf148c4092977d7342862ec7536c2051626", "parents": [ "58aebb6a53170cca6211e400e6630d2747bac9de" ], "author": { "name": "Raef Coles", "email": "raef.coles@arm.com", "time": "Wed Jun 15 14:37:22 2022 +0100" }, "committer": { "name": "Raef Coles", "email": "raef.coles@arm.com", "time": "Wed Sep 28 13:38:02 2022 +0100" }, "message": "feat(rss): add new comms protocols\n\nThe current comms protocol (where arguments and return data is embedded\ninto the MHU message) is now protocol v0. Protocol v1 embeds pointers\ninto the message, and has the RSS retrieve the data via DMA.\n\nChange-Id: I08d7f09c4eaea673769fde9eee194447a99f1b78\nSigned-off-by: Raef Coles \u003craef.coles@arm.com\u003e\n" }, { "commit": "18af644279b36e841068db0e1c857dedf1456b38", "tree": "42b85c06a4b4d57491bed4ad6d5176be4ac6aa30", "parents": [ "d8d0ea9a7fcd5ace63a8c863176d9535adfc581d" ], "author": { "name": "Chunlei Xu", "email": "chunlei.xu@nxp.com", "time": "Wed Sep 28 16:58:15 2022 +0800" }, "committer": { "name": "Chunlei Xu", "email": "chunlei.xu@nxp.com", "time": "Wed Sep 28 16:58:15 2022 +0800" }, "message": "feat(ls1043ardb): update ddr configure for ls1043ardb-pd\n\nDDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R.\nNew ddr configure is compatible with both pd and old version of ls1043ardb.\n\nSigned-off-by: Chunlei Xu \u003cchunlei.xu@nxp.com\u003e\nChange-Id: I714c091a2cf15046438d0723fb55a4410c386ef4\n" }, { "commit": "c5862af72d5c2f2b637d9d54c29d2d5e43a3b991", "tree": "8b663a19af458c56cd0966f27c783927d13962ad", "parents": [ "58aebb6a53170cca6211e400e6630d2747bac9de" ], "author": { "name": "Jorge Troncoso", "email": "jatron@google.com", "time": "Tue Sep 27 17:35:54 2022 -0700" }, "committer": { "name": "Jorge Troncoso", "email": "jatron@google.com", "time": "Tue Sep 27 22:50:54 2022 -0700" }, "message": "chore(libc): clean up includes in lib/libc/printf.c\n\nstddef.h is needed for the definition of size_t\nstdio.h is needed for the declaration of putchar\n\nSigned-off-by: Jorge Troncoso \u003cjatron@google.com\u003e\nChange-Id: I72dac843dbbfc440cff0f9e9d13669b78a812abc\n" }, { "commit": "58aebb6a53170cca6211e400e6630d2747bac9de", "tree": "1097fb2919edd562fe2d6dc0fbaf4ed63d6e07d4", "parents": [ "0f2ab75fa3dee9756e52c5dd07fb6d0bd5c48bfc", "d307229d754ae4d833ed50be50420aaf070065bf" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Wed Sep 28 01:19:28 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Sep 28 01:19:28 2022 +0200" }, "message": "Merge \"fix(libc): pri*ptr macros for aarch64\" into integration" }, { "commit": "0f2ab75fa3dee9756e52c5dd07fb6d0bd5c48bfc", "tree": "9482dcf75d891024f5891b85653c9da3f9e0c147", "parents": [ "14ec900a429276f9ad6d60a297f0e1cef993b498", "a816de564f927ebb72ab7692b8b3f46073179310" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue Sep 27 13:03:54 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 27 13:03:54 2022 +0200" }, "message": "Merge \"feat(tc): add RTC PL031 device tree node\" into integration" }, { "commit": "14ec900a429276f9ad6d60a297f0e1cef993b498", "tree": "cc153548d08fbfedfbc2b8bb408d14355685f1b9", "parents": [ "d8d0ea9a7fcd5ace63a8c863176d9535adfc581d", "8fecda3c8a2be9c85e8741a8494ba575e242835d" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Sep 27 11:42:46 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Sep 27 11:42:46 2022 +0200" }, "message": "Merge \"docs(maintainers): add myself as TC code owner\" into integration" }, { "commit": "8fecda3c8a2be9c85e8741a8494ba575e242835d", "tree": "65bdfb9af55023d00555a666c1fef166939dbc8a", "parents": [ "cdbea24097a0c94fcfacc9487c732125a325fde5" ], "author": { "name": "Anders Dellien", "email": "anders.dellien@arm.com", "time": "Wed Sep 21 15:56:02 2022 +0100" }, "committer": { "name": "Anders Dellien", "email": "anders.dellien@arm.com", "time": "Tue Sep 27 09:47:54 2022 +0100" }, "message": "docs(maintainers): add myself as TC code owner\n\nSigned-off-by: Anders Dellien \u003canders.dellien@arm.com\u003e\nChange-Id: Ic67334bf1a979cb7b7355d0dcca7eb94752c4611\n" }, { "commit": "d307229d754ae4d833ed50be50420aaf070065bf", "tree": "c0102e83a0efdffaef2850a2040b9a0efb400a77", "parents": [ "d8d0ea9a7fcd5ace63a8c863176d9535adfc581d" ], "author": { "name": "K", "email": "kayo@illumium.org", "time": "Wed Jul 27 17:30:49 2022 +0500" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Sep 27 09:19:32 2022 +0200" }, "message": "fix(libc): pri*ptr macros for aarch64\n\nThis fix solves problems with using PRI*PTR on aarch64 like so:\nerror: format \u0027%x\u0027 expects argument of type \u0027unsigned int\u0027, but\nargument 3 has type \u0027uintptr_t\u0027 {aka \u0027long unsigned int\u0027}\n\nChange-Id: I135d3e5cea5459f138b20331b5e9472e2e9e566c\nSigned-off-by: K \u003ckayo@illumium.org\u003e\n" }, { "commit": "cdb62114cfcdaeb85e64bcde459342a0a95f58e3", "tree": "e2452c3bc025a372eb4ff4ffebb9022d22bd3f10", "parents": [ "d8d0ea9a7fcd5ace63a8c863176d9535adfc581d" ], "author": { "name": "HariBabu Gattem", "email": "haribabu.gattem@amd.com", "time": "Thu Sep 22 02:45:16 2022 -0700" }, "committer": { "name": "HariBabu Gattem", "email": "haribabu.gattem@amd.com", "time": "Mon Sep 26 12:13:00 2022 +0200" }, "message": "fix(zynqmp): resolve misra 4.6 warnings\n\nMISRA Violation: MISRA-C:2012 R.4.6\n- Using basic numerical type int rather than a typedef\nthat includes size and signedness information.\n\nSigned-off-by: HariBabu Gattem \u003charibabu.gattem@amd.com\u003e\nChange-Id: I3779f7b6e074e33cb66ace3bef2117029badce1e\n" }, { "commit": "d8d0ea9a7fcd5ace63a8c863176d9535adfc581d", "tree": "424b6065f3eb3f3fdeb04a55baeb414f2ec91bf9", "parents": [ "2aaed8608004f7d29be5da49289bb16c1b0df20f", "eb3d4015a3a2db15b4f5d6b9706f80e99b5f9072" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Sep 26 11:02:51 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Sep 26 11:02:51 2022 +0200" }, "message": "Merge \"docs(fwu): update firmware update design\" into integration" }, { "commit": "2aaed8608004f7d29be5da49289bb16c1b0df20f", "tree": "9225cb4fd95261156b1f519a8a67d7e4904dce09", "parents": [ "278bc857d8a6a317f8598ee5ade04a8914e6d110", "885e26830499284a7718f825579d6ebeb8b6cd89" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Sep 23 17:24:01 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Sep 23 17:24:01 2022 +0200" }, "message": "Merge \"refactor(libc): clean up dependencies in libc\" into integration" }, { "commit": "14a070408d9231dc1c487dfe36058b93faf5915c", "tree": "9ef5cffdcf3610b6cb5c3fab0fbdcadeb938c1b2", "parents": [ "5223d88032dcecb880d620e63bfa70799dc6cc1a" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Fri Oct 15 16:49:07 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "feat(stm32mp1): add early console in SP_min\n\nAllow early console to be used at the beginning of SP_min, before\nthe clocks and UART have been reconfigured.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I53d66938d42fcec830d9b81e5ef62b3790d0c3b3\n" }, { "commit": "5223d88032dcecb880d620e63bfa70799dc6cc1a", "tree": "f02ed1cf4b81688b2ddc389442fee3028bfabea9", "parents": [ "ea69dcdc737d8b48fec769042922914e988153ef" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 13 13:59:48 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "feat(st): properly manage early console\n\nThe new flag STM32MP_RECONFIGURE_CONSOLE is managed in platform.mk.\nIt is used in stm32mp_setup_early_console() when calling\nplat_crash_console_init(). This call is also under:\n\"#if defined(IMAGE_BL2)\"\nas this crash console init shouldn\u0027t be done by default in BL32.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Ib6b89db83d80095b662a2016e18ceb3fa8668435\n" }, { "commit": "ea69dcdc737d8b48fec769042922914e988153ef", "tree": "6d17982bb27c42a9948b22a4d189c47a7a334257", "parents": [ "156709dddedd7320aee630c4967dbe8c62a31617" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 13 13:55:43 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE\n\nIf the flag STM32MP_RECONFIGURE_CONSOLE is set in BL32, the UART init\nshould be skipped if the UART clock is set to zero. This will be used\nwhen configuring the default console, after an early console has been\nconfigured.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Icbc640c7bdd6342f9c3ec1586a0d0c64127b18b8\n" }, { "commit": "156709dddedd7320aee630c4967dbe8c62a31617", "tree": "85ee3e5226793a7242a99a04ce0dd1737c706e3c", "parents": [ "00606df01201fcad509ea9ddff89d5f176bee793" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue Sep 13 13:53:41 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "docs(st): introduce STM32MP_RECONFIGURE_CONSOLE\n\nThis flag will be used in BL32, to reconfigure UART parameters for\nthe early or crash console. By default, it is zero, as UART is\nalready configured in BL2.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I7b28ff489479ab04a2fade027933524cdd36e959\n" }, { "commit": "00606df01201fcad509ea9ddff89d5f176bee793", "tree": "76afb0b8f3446246e47858a62a5c4663990f3ac6", "parents": [ "484e846a03a1af5f88e2e28835b6349cc5977935" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Thu Jun 09 17:34:30 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "feat(st): add trace for early console\n\nWhen the early console is configured with STM32MP_EARLY_CONSOLE,\ndisplay a message indicating it is enabled.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Iafdfa5afef27eba823d707841853a8a46de0b42d\n" }, { "commit": "484e846a03a1af5f88e2e28835b6349cc5977935", "tree": "fd39cf0469275e0cc010183c035a2fd57589d88c", "parents": [ "d99998f76ed2e8676be25e31e9479a90c16c7098" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Mar 07 16:09:23 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "fix(stm32mp1): enable crash console in FIQ handler\n\nWhen a FIQ occurs and is trapped by SP_min, it is an unrecoverable\nerror. As kernel may have switched the UART console off, we should\nre-enable it with plat_crash_console_init() for those failing states.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Ib02e1271b6213f8e383a062b74494abf8826188f\n" }, { "commit": "d99998f76ed2e8676be25e31e9479a90c16c7098", "tree": "e6b96cc7cc640387c0ff300e9852fe381e3fa7d0", "parents": [ "7d197d6281717b18906798fc8e0e42ed91df6b9b" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Thu Apr 14 11:19:03 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "feat(st-uart): add initialization with the device tree\n\nAdd the pincontrol configuration and clock enable in UART driver\nwith information found in the device tree.\n\nThis patch avoids an issue on STM32MP13x platform because the UART\nconfiguration is reset by the ROM code for UART serial boot\n(STM32MP_UART_PROGRAMMER\u003d1).\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: I575fd0e1026b857059abcfd4a3166eb3a239e1fd\n" }, { "commit": "7d197d6281717b18906798fc8e0e42ed91df6b9b", "tree": "bfdd37f040aa11b7d35ab63ba181d2cb01b09e21", "parents": [ "4b2f23e55f27b6baccf3e858234e69685d51fcf4" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Thu Apr 14 11:15:43 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "refactor(stm32mp1): move DT_UART_COMPAT in include file\n\nMove the definition of DT_UART_COMPAT in stm32mp1_def.h to be used\nin several files.\n\nChange-Id: I74d0350bcd971df9b15697f2b9ec04061d6a7656\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\n" }, { "commit": "4b2f23e55f27b6baccf3e858234e69685d51fcf4", "tree": "54bb99a2b9cfa19767ed70727934129ce82cc314", "parents": [ "32f2ca04bfd2d93329f2f17d9c9d134f339710f9" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Tue Mar 15 11:20:56 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "feat(stm32mp1): configure the serial boot load address\n\nFor product with 128MB DDR size, the OP-TEE is located at the end\nof the DDR and the FIP can\u0027t be loaded at the default location\nbecause it overlap the OP-TEE final location. So the default value\nfor DWL_BUFFER_BASE is invalid.\n\nTo avoid this conflict the serial boot load address \u003d DWL_BUFFER_BASE\ncan be modified with a configuration flags.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080\n" }, { "commit": "32f2ca04bfd2d93329f2f17d9c9d134f339710f9", "tree": "c7acdade1941c4651db211b7a3172f003ae7c504", "parents": [ "e7705e9afd0de234c89400044d93badd2c135a09" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Mon Feb 28 11:02:35 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "fix(stm32mp1): update the FIP load address for serial boot\n\nUpdate the FIP load address and size for serial boot to support\nproduct with a DDR size \u003d 128MB\n1/ Move the FIP location at the end of the first 128MB\n2/ Reduce the DWL_BUFFER_SIZE to 16MB, to be coherent with the value\n indicated in USB enumeration\n - for STM32MP13x: \"@SSBL /0x03/1*16Me\"\n - for STM32MP15x: \"@Partition3 /0x03/1*16Me\"\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: Id93bf00c64832c17426bfd78e060861275677ecc\n" }, { "commit": "e7705e9afd0de234c89400044d93badd2c135a09", "tree": "0474dab65d8af753f60d102d4ae3d43c66dbfa32", "parents": [ "12581895158f0ff43f277d991c62ea7d0478a836" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@foss.st.com", "time": "Wed Mar 02 15:43:02 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Sep 23 15:17:43 2022 +0200" }, "message": "refactor(st): configure baudrate for UART programmer\n\nAdd the possibility to configure the UART baudrate; reused the\nconsole configuration, defined in STM32MP_UART_BAUDRATE.\n\nThe default value remains 115200.\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@foss.st.com\u003e\nChange-Id: Ifcf2b36e8ac929265405bc88e824ee78be3b5bbb\n" } ], "next": "12581895158f0ff43f277d991c62ea7d0478a836" }