)]}' { "log": [ { "commit": "9576fa93a2effc23a533b80dce41d7104a8d200b", "tree": "6954111ca4a6655815f224ad488f3c17b6e7a640", "parents": [ "0c7707fdf21fc2a8658f5a4bdfd2f8883d02ada5" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Wed Dec 08 14:27:40 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Tue May 10 09:36:20 2022 +0100" }, "message": "feat(spmd): enable SPMD to forward FFA_VERSION to EL3 SPMC\n\nIn order to allow the EL3 SPMC to know the FF-A version of the\nentity running in the normal world, allow the SPMD to\nforward the call rather than replying on its behalf.\n\nThis solution works as the EL3 can ERET directly back to\nthe calling partition however this is not an option\nwhen the SPMC resides in a lower exception level. A new\napproach will be required to support such scenario.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: Ic2d6e49c06340167eadefe893c6e1e20b67ab498\n" }, { "commit": "0c7707fdf21fc2a8658f5a4bdfd2f8883d02ada5", "tree": "d735f8a032969564b3d2af012778b169b4bdc0f3", "parents": [ "f16b6ee3deac93706efe465f399c9542e12d5eeb" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Wed Dec 08 14:24:03 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Tue May 10 09:36:20 2022 +0100" }, "message": "feat(spmc): enable handling FFA_VERSION ABI\n\nReport the SPMC version to the caller, currently v1.1 and\nalso store the requested version to allow the SPMC to\nuse the corresponding FF-A version in future ABI calls.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I79aafd1e6694cbd4b231bbd0cac5834a71063d79\n" }, { "commit": "f16b6ee3deac93706efe465f399c9542e12d5eeb", "tree": "f7d84657ba7d132d7c90f0a8bc62587461d03f4d", "parents": [ "a7c00505f85684326a223535a319c170d14826f6" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Wed Nov 24 10:33:48 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Tue May 10 09:36:20 2022 +0100" }, "message": "feat(spmc): add helper function to obtain endpoint mailbox\n\nAdd a helper function to obtain the relevant mailbox buffers\ndepending on which entity was last run. This will be used in\nsubsequent functionality to populate requested information in\nthe callers RX buffer.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I85959ced4d1454be05a7b3fb6853ed3ab7f0cf3e\n" }, { "commit": "a7c00505f85684326a223535a319c170d14826f6", "tree": "2e41a5f38b284a8ec9a0cf480303a60402551a77", "parents": [ "3de378ff8c9430c964cbe9b0c58fa5afc4d237ce" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Wed Nov 24 10:32:16 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Tue May 10 09:36:20 2022 +0100" }, "message": "feat(spmc): add helper function to obtain hyp structure\n\nWe assume that the first descriptor in the normal world\nendpoints is reserved for the hypervisor and add a helper\nfunction to enable retrieving this directly.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I67c3589994eb820ef420db6ab7e8bd0825d64455\n" }, { "commit": "3de378ff8c9430c964cbe9b0c58fa5afc4d237ce", "tree": "42f0b276ef5cb793feb7b9abdd855b065c0a4218", "parents": [ "c3bdd3d3cf0f9cdf3be117e39386492e645a1bb5" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu Dec 09 18:34:02 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Tue May 10 09:36:15 2022 +0100" }, "message": "feat(spmc): enable parsing of messaging methods from manifest\n\nEnsure that the `messaging-methods` entry is populated in\nan SP\u0027s manifest. Currently only direct messaging is supported\nso alert if this does not match the manifest entry.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I67f1fad71a3507627993a004e0f8579388faf178\n" }, { "commit": "c3bdd3d3cf0f9cdf3be117e39386492e645a1bb5", "tree": "736fbd775386d708bd8c5e7f423c9e56d3547eea", "parents": [ "42f31f5f10ccd86791688aa9d740a458e2f452f5", "aeff14640a91f6d33bfdbc0dc7b0e920f6d14b91" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon May 09 11:30:50 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 09 11:30:50 2022 +0200" }, "message": "Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration\n\n* changes:\n feat(imx8mp): enable BL32 fdt overlay support on imx8mp\n feat(imx8mq): enable optee fdt overlay support\n feat(imx8mn): enable optee fdt overlay support\n feat(imx8mm): enable optee fdt overlay support\n feat(imx8mp): add trusty for imx8mp\n feat(imx8mq): enable trusty for imx8mq\n feat(imx8mn): enable Trusty OS for imx8mn\n feat(imx8mm): enable Trusty OS on imx8mm\n feat(imx8/imx8m): switch to xlat_tables_v2\n feat(imx8m): enable the coram_s tz by default on imx8mn/mp\n feat(imx8m): enable the csu init on imx8m\n feat(imx8m): add a simple csu driver for imx8m family\n refactor(imx8m): replace magic number with enum type\n feat(imx8m): add imx csu/rdc enum type defines for imx8m\n fix(imx8m): check the validation of domain id\n feat(imx8m): enable conditional build for SDEI\n" }, { "commit": "42f31f5f10ccd86791688aa9d740a458e2f452f5", "tree": "3b71bf1a4cda0f807427921a7424c5755e493804", "parents": [ "13ce03aa8ac4cd87646172bc0a681ed8831244e1", "77850c96f23bcdc76ecb0ecd27a982c00fde5d9d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon May 09 10:40:00 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 09 10:40:00 2022 +0200" }, "message": "Merge \"feat(plat/imx8m): do not release JR0 to NS if HAB is using it\" into integration" }, { "commit": "aeff14640a91f6d33bfdbc0dc7b0e920f6d14b91", "tree": "3fa1d4d8a220fd0f6db4d80d509ab383616f9dc2", "parents": [ "023750c6a898e77c185839f5e56f8e23538f718a" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Mar 27 20:28:19 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mp): enable BL32 fdt overlay support on imx8mp\n\nAllow OP-TEE to generate a device-tree overlay binary\nthat will be applied by u-boot on the regular dtb.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: Idfd268cdd8b7ba321f8e1b9b85c2bba7ffdeddf0\n" }, { "commit": "023750c6a898e77c185839f5e56f8e23538f718a", "tree": "be1d0a0d45d0dc8b5e49bf078340da89b9254f93", "parents": [ "26128912884b26fab67bce9d87ba0e1c85a0be1e" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Wed Mar 25 09:29:46 2020 +0100" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mq): enable optee fdt overlay support\n\nEnable optee fdt overlay support\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I362445b93dc293a27c99b0d20a73f6b06ad0cd39\n" }, { "commit": "26128912884b26fab67bce9d87ba0e1c85a0be1e", "tree": "58144657365c77aa7e7e95e2623d8b36af6074ec", "parents": [ "9d0eed111cb1294605b6d82291fef16a51d35e46" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Wed Mar 25 09:28:22 2020 +0100" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mn): enable optee fdt overlay support\n\nEnable optee fdt overlay support.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: Ibea052d35bf746475b8618b3a879eea80875333c\n" }, { "commit": "9d0eed111cb1294605b6d82291fef16a51d35e46", "tree": "afb2118cb9665d2a6ce3c5be01faf78fd954246f", "parents": [ "8b9c21b480dd5c3265be1105a9462b3f5657a6b1" ], "author": { "name": "Silvano di Ninno", "email": "silvano.dininno@nxp.com", "time": "Wed Mar 25 09:24:51 2020 +0100" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mm): enable optee fdt overlay support\n\nEnable optee fdt overlay support.\n\nSigned-off-by: Silvano di Ninno \u003csilvano.dininno@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I28cb8f744236868727ef4a09d7d2946070404d4d\n" }, { "commit": "8b9c21b480dd5c3265be1105a9462b3f5657a6b1", "tree": "670540317c80086249352a37bfd9f48a7474db76", "parents": [ "a18e393339e1d481f4fdf0d621fe4f39ce93a4fe" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Wed Sep 09 16:23:32 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mp): add trusty for imx8mp\n\nAdd trusty support on i.MX8MP.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I501ae76ac35b8c059b3f0a9ce1d51ed13cbdbfe2\n" }, { "commit": "a18e393339e1d481f4fdf0d621fe4f39ce93a4fe", "tree": "678df539df7206eedac77422b7db7d27c41c11f6", "parents": [ "99349c8ecba910dabbaa72b9be91f3ed762036f5" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Fri Feb 21 11:19:49 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mq): enable trusty for imx8mq\n\nAdd trusty support for imx8mq, default load address\nand size for trusty os will be 0xfe000000 and 0x2000000.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I2b35ee525b25b80bf6c9599a0adcc2d9f069aa41\n" }, { "commit": "99349c8ecba910dabbaa72b9be91f3ed762036f5", "tree": "93c827c6345618bcee8b5f3b6ab804be5f3aaa67", "parents": [ "ff3acfe3cc1658917376152913a9d1b5b9b8de34" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Fri Feb 21 16:32:53 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mn): enable Trusty OS for imx8mn\n\nAdd trusty support for imx8mn, default load address and\nsize of trusty are 0xbe000000 and 0x2000000.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I63fd5159027d7400b8c6bfc03193dd1330c43140\n" }, { "commit": "ff3acfe3cc1658917376152913a9d1b5b9b8de34", "tree": "71022b4aae42e373e8d800e369bb5588c765c8c2", "parents": [ "4f8d5b018efc42d1ffa76fca8efb0d16a57f5edd" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Fri Feb 21 10:36:47 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8mm): enable Trusty OS on imx8mm\n\nAdd trusty support for imx8mm, default load address\nand size of trusty are 0xbe000000 anx 0x2000000.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I3f8b1adc08933e38a39f1ab1723947319d19a703\n" }, { "commit": "4f8d5b018efc42d1ffa76fca8efb0d16a57f5edd", "tree": "24222eb8384b20757f5946e4a22b891f553832ef", "parents": [ "d5ede92d78c829d8a3adad0759219b79e0dc0707" ], "author": { "name": "Ji Luo", "email": "ji.luo@nxp.com", "time": "Thu Feb 20 23:47:21 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8/imx8m): switch to xlat_tables_v2\n\nspd trusty requires memory dynamic mapping feature to be\nenabled, so we have to use xlat table library v2 instead\nof v1.\n\nSigned-off-by: Ji Luo \u003cji.luo@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I2813af9c7878b1fc2a59e27619c5b643af6a1e91\n" }, { "commit": "d5ede92d78c829d8a3adad0759219b79e0dc0707", "tree": "142f5bc6907e5c66f861ae793f8934a78de5a8bb", "parents": [ "0a76495bc2cb0c5291027020a3cd2d3adf31c8ed" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Fri Apr 16 14:31:09 2021 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8m): enable the coram_s tz by default on imx8mn/mp\n\nEnable the OCRAM_S TZ for secure protection by default on\ni.MX8MN/i.MX8MP. And lock the ocram secure access configure\non i.MX8MM/i.MX8MP.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I2e24f4b823ee5f804415218d5c2e371f4e4c6fe1\n" }, { "commit": "0a76495bc2cb0c5291027020a3cd2d3adf31c8ed", "tree": "d1cded2a6d85e216c629d824f5e9a01e69ee8d09", "parents": [ "71c40d3bb7c90a6c36d5c49d0830ca95aba65a2f" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Tue Jan 07 14:53:54 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8m): enable the csu init on imx8m\n\nEnable the CSU init on i.MX8M SoC family. The \u0027csu_cfg\u0027 array\nis just a placeholder for now as example with limited config listed.\nIn real use case,user can add the CSU config as needed based on system design.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I1f7999efa346f18f6625ed8c478d088ed75f7833\n" }, { "commit": "71c40d3bb7c90a6c36d5c49d0830ca95aba65a2f", "tree": "a15520ebfe8576c6722bab76f623085f81770e86", "parents": [ "d76f012ea8fc0566dcacc067fcaae59d37267ffa" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Tue Jan 07 14:39:15 2020 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:33:58 2022 +0800" }, "message": "feat(imx8m): add a simple csu driver for imx8m family\n\nAdd a simple CSU driver for i.MX8M family.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I0eda3561e7a38a232acdb8e043c7200c630f7e22\n" }, { "commit": "d76f012ea8fc0566dcacc067fcaae59d37267ffa", "tree": "e299d3fb58fed52a620c42164e6df34a905975e1", "parents": [ "0c6dfc47847608b6ade0c00716e93afc6725362c" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Mon Mar 14 17:14:26 2022 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 17:26:51 2022 +0800" }, "message": "refactor(imx8m): replace magic number with enum type\n\nReplace those RDC config related magic numbers with enum type\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I6245ccfa74d079179dc0f205980c2daf5c7af786\n" }, { "commit": "0c6dfc47847608b6ade0c00716e93afc6725362c", "tree": "eb802a79564398b63a9107662dde9e07c955f9f1", "parents": [ "eb7fb938c3ce34ccfb143ae8ba695df899098436" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Tue Mar 15 10:29:09 2022 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 16:57:18 2022 +0800" }, "message": "feat(imx8m): add imx csu/rdc enum type defines for imx8m\n\nAdd various enum type defines for CSU \u0026 RDC module for i.MX8M\nfamily\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I70c050286919eab51c6c553912bd4be57bc60f81\n" }, { "commit": "eb7fb938c3ce34ccfb143ae8ba695df899098436", "tree": "0c4e6db4119984b34da51132da656ba8cee9c8fa", "parents": [ "d2a339dfa1665edf87a30a4318af954e764c205c" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Thu Mar 31 10:26:33 2022 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 16:32:05 2022 +0800" }, "message": "fix(imx8m): check the validation of domain id\n\ncheck the domain id to make sure it is in the valid range\nto make sure no out of range access to the array.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: Iccd7298eea390b6e68156bb356226839a23417ea\n" }, { "commit": "d2a339dfa1665edf87a30a4318af954e764c205c", "tree": "7f98e38e8d35cf954555873d0b42a3f7a8782c91", "parents": [ "13ce03aa8ac4cd87646172bc0a681ed8831244e1" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Mon Mar 28 16:11:23 2022 +0800" }, "committer": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Sat May 07 16:30:03 2022 +0800" }, "message": "feat(imx8m): enable conditional build for SDEI\n\nSDEI support on imx8m is an optional feature, so\nmake it conditional build, not enabled by default.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I6e7e8d77959ea352bc019f8468793992ec7ecfc4\n" }, { "commit": "13ce03aa8ac4cd87646172bc0a681ed8831244e1", "tree": "9260994631d42e45a9d4189e945282320179dcc0", "parents": [ "026dfed89d225a39414c324867ca04d99ddae0de", "bb0fcc7e011ec4319a79734ba44353015860e39f" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri May 06 19:33:59 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 19:33:59 2022 +0200" }, "message": "Merge \"feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC\" into integration" }, { "commit": "026dfed89d225a39414c324867ca04d99ddae0de", "tree": "0dec2e1bf4ea2cf0dd653ddab4a4a37e45481797", "parents": [ "968ffba2700f5d422431a214a82a9db80896006f", "f65bdf3a54eed8f7651761c25bf6cc7437f4474b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 18:53:25 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 18:53:25 2022 +0200" }, "message": "Merge \"feat(intel): implement timer init divider via cpu frequency. (#1)\" into integration" }, { "commit": "968ffba2700f5d422431a214a82a9db80896006f", "tree": "b7f2ca82980d2a884dcbf48477e238b1651ab3f2", "parents": [ "efceb6beade2b88d52ae8e5a7d33b77e8b311dd1", "3db9a39cb75ba13eb5b4061bf04a16fc5b8f9938" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 18:51:26 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 18:51:26 2022 +0200" }, "message": "Merge \"docs(maintainers): add new owners for Trusty SPD\" into integration" }, { "commit": "77850c96f23bcdc76ecb0ecd27a982c00fde5d9d", "tree": "98c9b4dbb52eb850bdeefaee8bf2824b81c6125b", "parents": [ "efceb6beade2b88d52ae8e5a7d33b77e8b311dd1" ], "author": { "name": "Franck LENORMAND", "email": "franck.lenormand@nxp.com", "time": "Sun Jun 13 14:38:01 2021 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 17:53:15 2022 +0200" }, "message": "feat(plat/imx8m): do not release JR0 to NS if HAB is using it\n\nIn case JR0 is used by the HAB for secure boot, it can be used later\nfor authenticating kernel or other binaries.\n\nWe are checking if the HAB is using the JR by the DID set.\n\nSigned-off-by: Franck LENORMAND \u003cfranck.lenormand@nxp.com\u003e\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I6e9595012262ffabfc3f3d4841f446f34e48e059\n" }, { "commit": "3db9a39cb75ba13eb5b4061bf04a16fc5b8f9938", "tree": "b7f2ca82980d2a884dcbf48477e238b1651ab3f2", "parents": [ "efceb6beade2b88d52ae8e5a7d33b77e8b311dd1" ], "author": { "name": "Marco Nelissen", "email": "marcone@google.com", "time": "Wed Apr 06 11:13:44 2022 -0700" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 17:50:26 2022 +0200" }, "message": "docs(maintainers): add new owners for Trusty SPD\n\nSplit TLK/Trusty SPD into two separate components and add additional\nowners for Trusty SPD.\n\nSigned-off-by: Marco Nelissen \u003cmarcone@google.com\u003e\nChange-Id: Ifabd1bb630fe4976e304fa29eac1c516ec6e2e18\n" }, { "commit": "efceb6beade2b88d52ae8e5a7d33b77e8b311dd1", "tree": "34a31f5c097f9bf6c08b5bad256b6ee142d7ccd6", "parents": [ "2c87fabab581345562af525cb067c407aac8dc87", "a475518337e15935469543b1cce353e5b337ef52" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 17:47:28 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 17:47:28 2022 +0200" }, "message": "Merge changes Iaf21883b,I523c5d57,I57164923 into integration\n\n* changes:\n fix(ufs): read and write attribute based on spec\n fix(ufs): disables controller if enabled\n refactor(ufs): adds a function for fdeviceinit\n" }, { "commit": "f65bdf3a54eed8f7651761c25bf6cc7437f4474b", "tree": "4218d0b1e265a0d76de9c4bad22b13e1bb9e5dab", "parents": [ "2c87fabab581345562af525cb067c407aac8dc87" ], "author": { "name": "BenjaminLimJL", "email": "jit.loon.lim@intel.com", "time": "Wed Apr 06 10:19:16 2022 +0800" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 17:37:45 2022 +0200" }, "message": "feat(intel): implement timer init divider via cpu frequency. (#1)\n\nGet cpu frequency and update the timer init div with it.\nThe timer is vary based on the cpu frequency instead of hardcoded.\nThe implementation shall apply to only Agilex and S10\n\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nChange-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422\n" }, { "commit": "2c87fabab581345562af525cb067c407aac8dc87", "tree": "03f49b6b2f9c622c56b546b912f5506bb23cb78d", "parents": [ "44b9d577c0d9603e3bcfe6ba5bff331a87e3dbcc", "2deff904a953c6a87331ab6830ab80e3889d9e23" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri May 06 16:53:24 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 16:53:24 2022 +0200" }, "message": "Merge \"fix(st): fix NULL pointer dereference issues\" into integration" }, { "commit": "44b9d577c0d9603e3bcfe6ba5bff331a87e3dbcc", "tree": "0555ef33e907f919f6f8ff0e97603145ff577038", "parents": [ "fad4a7175bfa5996e408f50d5d27e1f8d8b9ea04", "5b0219ddd5da42413f4c2be9302224b5b71295ff" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri May 06 15:58:03 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 15:58:03 2022 +0200" }, "message": "Merge changes from topic \"ffa_el3_spmc\" into integration\n\n* changes:\n feat(spmc): enable checking of execution ctx count\n feat(spmc): enable parsing of UUID from SP Manifest\n feat(spmc): add partition mailbox structs\n feat(plat/arm): allow BL32 specific defines to be used by SPMC_AT_EL3\n feat(plat/fvp): add EL3 SPMC #defines\n test(plat/fvp/lsp): add example logical partition\n feat(spmc/lsp): add logical partition framework\n" }, { "commit": "fad4a7175bfa5996e408f50d5d27e1f8d8b9ea04", "tree": "989f5baf257aad3f6a3ddcbb993ef89ae7d11a91", "parents": [ "e8ad39759b62541de3a306a21ffc607c0fb39425", "dd1fe7178b578916b1e133b7c65c183e1f994371" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 15:51:25 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 15:51:25 2022 +0200" }, "message": "Merge changes from topic \"xlnx_zynqmp_misra\" into integration\n\n* changes:\n fix(zynqmp): resolve misra R14.4 warnings\n fix(zynqmp): resolve misra R16.3 warnings\n fix(zynqmp): resolve misra R15.7 warnings\n fix(zynqmp): resolve misra R15.6 warnings\n fix(zynqmp): resolve misra 7.2 warnings\n fix(zynqmp): resolve misra R10.3\n" }, { "commit": "e8ad39759b62541de3a306a21ffc607c0fb39425", "tree": "b2c5561d303eed1b04b46fd2f28f9164a0c14d5c", "parents": [ "78c82cd09913554c25557970802c8514f513ca81", "744ad97445ce7aa65adaef376d0b5bafc12a90d3" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri May 06 12:46:03 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 12:46:03 2022 +0200" }, "message": "Merge \"feat(brbe): add BRBE support for NS world\" into integration" }, { "commit": "78c82cd09913554c25557970802c8514f513ca81", "tree": "b47eca41b77002a67ec861a991f460bf70f42c95", "parents": [ "be96158fbb76d6173f2f6ab4ca1655f2918cbb52", "ca0fdbd8e0d625ece0f87ca16eacabf13db70921" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri May 06 11:52:55 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 11:52:55 2022 +0200" }, "message": "Merge changes from topic \"ja/boot_protocol\" into integration\n\n* changes:\n fix(sptool): update Optee FF-A manifest\n feat(sptool): delete c version of the sptool\n feat(sptool): use python version of sptool\n feat(sptool): python version of the sptool\n refactor(sptool): use SpSetupActions in sp_mk_generator.py\n feat(sptool): add python SpSetupActions framework\n" }, { "commit": "2deff904a953c6a87331ab6830ab80e3889d9e23", "tree": "d98d19ef619ca72932fc312f159c3a5970946273", "parents": [ "be96158fbb76d6173f2f6ab4ca1655f2918cbb52" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 06 09:50:43 2022 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri May 06 11:00:15 2022 +0200" }, "message": "fix(st): fix NULL pointer dereference issues\n\nThe get_bl_mem_params_node() function could return NULL. Add asserts to\ncheck the return value is not NULL.\nThis corrects coverity issues:\n\tpager_mem_params \u003d get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);\n\u003e\u003e\u003e CID 378360: (NULL_RETURNS)\n\u003e\u003e\u003e Dereferencing \"pager_mem_params\", which is known to be \"NULL\".\n\n\tpaged_mem_params \u003d get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);\n\u003e\u003e\u003e CID 378360: (NULL_RETURNS)\n\u003e\u003e\u003e Dereferencing \"paged_mem_params\", which is known to be \"NULL\".\n\n\ttos_fw_mem_params \u003d get_bl_mem_params_node(TOS_FW_CONFIG_ID);\n\u003e\u003e\u003e CID 378360: (NULL_RETURNS)\n\u003e\u003e\u003e Dereferencing \"tos_fw_mem_params\", which is known to be \"NULL\".\n\n\nDo the same for other occurrences of get_bl_mem_params_node() return not\nchecked, in the functions plat_get_bl_image_load_info() and\nbl2_plat_handle_pre_image_load().\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I79165b1628fcee3da330f2db4ee5e1dafcb1b21f\n" }, { "commit": "dd1fe7178b578916b1e133b7c65c183e1f994371", "tree": "89a8814fbeb6581ad3a12478b466abb8ecb56131", "parents": [ "e7e5d30308ccfb931f7b6d0afa6c5c23971e95c0" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed May 04 14:27:56 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri May 06 13:45:27 2022 +0530" }, "message": "fix(zynqmp): resolve misra R14.4 warnings\n\nMISRA Violation: MISRA-C:2012 R.14.4\nThe controlling expression of an if statement and the controlling\nexpression of an iteration-statement shall have essentially Boolean type.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I8f3f6f956d1d58ca201fb5895f12bcaabf2afd3b\n" }, { "commit": "e7e5d30308ccfb931f7b6d0afa6c5c23971e95c0", "tree": "629c7f94fa1353bf50bd8264ec4f23a1b61b17a1", "parents": [ "16de22d037644359ef2a04058134f9c326b36633" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri Apr 29 15:17:13 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri May 06 13:45:22 2022 +0530" }, "message": "fix(zynqmp): resolve misra R16.3 warnings\n\nMISRA Violation: MISRA-C:2012 R.16.3\n- An unconditional break statement shall terminate every switch-clause.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I96a8b627c593ff1293b725d443531e42368923c5\n" }, { "commit": "16de22d037644359ef2a04058134f9c326b36633", "tree": "9e6d83830727a481a2d3c1ad9eef453c12fce75d", "parents": [ "eb0d2b17722c01a22bf3ec1123f7bed2bf891b09" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed May 04 14:23:32 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri May 06 13:45:16 2022 +0530" }, "message": "fix(zynqmp): resolve misra R15.7 warnings\n\nMISRA Violation: MISRA-C:2012 R.15.7\n- All if . . else if constructs shall be terminated\nwith an else statement.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: If921ca7c30b2feea6535791aa15f4de7101c3134\n" }, { "commit": "eb0d2b17722c01a22bf3ec1123f7bed2bf891b09", "tree": "2d4517e6e25385d76f32280ffe62be0782f06daa", "parents": [ "5bcbd2de127292f3ad076217e08468388c6844b0" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri Apr 29 13:52:00 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri May 06 13:45:07 2022 +0530" }, "message": "fix(zynqmp): resolve misra R15.6 warnings\n\nMISRA Violation: MISRA-C:2012 R.15.6\n- The body of an iteration-statement or a selection-statement shall be\n a compound statement.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I0fc8eeac0e592f00297a1ac42a1ba3df1144733b\n" }, { "commit": "5bcbd2de127292f3ad076217e08468388c6844b0", "tree": "b55d3d20fadd08588449b68282a109eeed9147a2", "parents": [ "2b57da6c91ebe14588e63e5a24f31ef32711eca2" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri Apr 29 09:58:30 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri May 06 13:43:34 2022 +0530" }, "message": "fix(zynqmp): resolve misra 7.2 warnings\n\nMISRA Violation: MISRA-C:2012 R.7.2\n- A \"u\" or \"U\" suffix shall be applied to all integer constants that are\nrepresented in an unsigned type.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: Ieeff81ed42155c03aebca75b2f33f311279b9ed4\n" }, { "commit": "2b57da6c91ebe14588e63e5a24f31ef32711eca2", "tree": "c9226c4b4c000dac796580e294f687925828b9fa", "parents": [ "3e0a087f30f5786f01cfc2450185cf9f6d17d686" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Thu Apr 28 16:39:07 2022 +0530" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Fri May 06 13:43:28 2022 +0530" }, "message": "fix(zynqmp): resolve misra R10.3\n\nMISRA Violation: MISRA-C:2012 R.10.3\n- The value of an expression shall not be assigned to an object with a\n narrower essential type or of a different essential type category.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I5a60c66788d59e45f41ceb81758b42ef2df9f5f7\n" }, { "commit": "be96158fbb76d6173f2f6ab4ca1655f2918cbb52", "tree": "ea106b3433d98e3e9bd1f321f7e34ce7817de4e9", "parents": [ "d82fae2680b05d18c2575d9b902ee2dddf40b3fa", "a42b426b8548e3304e995f1a49d2470d71072949" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Fri May 06 10:08:54 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 06 10:08:54 2022 +0200" }, "message": "Merge \"fix(fvp): fix NULL pointer dereference issue\" into integration" }, { "commit": "d82fae2680b05d18c2575d9b902ee2dddf40b3fa", "tree": "b31bb218e273c9b51a4d27f270b428aaaf369590", "parents": [ "8d6502183d1ef67d84ef4a086d6eb1aa309086bc", "7cb76fdf1c3d75eb62269cb317e4dc6f169fe482" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 05 22:27:35 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 05 22:27:35 2022 +0200" }, "message": "Merge \"docs(maintainers): update measured boot code owners\" into integration" }, { "commit": "744ad97445ce7aa65adaef376d0b5bafc12a90d3", "tree": "843a7156144107e776b282ba0db093b44c7ac64a", "parents": [ "8d6502183d1ef67d84ef4a086d6eb1aa309086bc" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Jan 28 17:06:20 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu May 05 19:43:10 2022 +0200" }, "message": "feat(brbe): add BRBE support for NS world\n\nThis patch enables access to the branch record buffer control registers\nin non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.\nIt is disabled for all secure world, and cannot be used with ENABLE_RME.\n\nThis option is disabled by default, however, the FVP platform makefile\nenables it for FVP builds.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I576a49d446a8a73286ea6417c16bd0b8de71fca0\n" }, { "commit": "bb0fcc7e011ec4319a79734ba44353015860e39f", "tree": "98ed67adba942403174930384999e90356a864ec", "parents": [ "b7bd9863dc2f0a055e0c4bc065e071c4b1863647" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu May 05 23:42:55 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu May 05 23:47:20 2022 +0800" }, "message": "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC\n\nSMPLSEL and DRVSEL values need to updated in\nDWMMC for the IP to work correctly. This apply\non Stratix 10 device only.\n\nSigned-off-by: Loh Tien Hock \u003ctien.hock.loh@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc\n" }, { "commit": "8d6502183d1ef67d84ef4a086d6eb1aa309086bc", "tree": "7eb09fe829417e4e639b38e19a2ffbba48ad75af", "parents": [ "d6fbcc57f91cdbf6fa1169373514e7187921c3dd", "52ed157fd66812debb13a792c21f763de01aef70" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 05 16:12:04 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 05 16:12:04 2022 +0200" }, "message": "Merge \"fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)\" into integration" }, { "commit": "a42b426b8548e3304e995f1a49d2470d71072949", "tree": "353d4ffad00dc76075d1022cb433057abd9fa6ee", "parents": [ "b7bd9863dc2f0a055e0c4bc065e071c4b1863647" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed May 04 17:21:22 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu May 05 11:33:40 2022 +0100" }, "message": "fix(fvp): fix NULL pointer dereference issue\n\nFixed below NULL pointer dereference issue reported by coverity scan\nby asserting the hw_config_info is not NULL.\n\n*** CID 378361: Null pointer dereferences (NULL_RETURNS)\n/plat/arm/board/fvp/fvp_bl2_setup.c: 84 in plat_get_next_bl_params()\n78\n79 /* To retrieve actual size of the HW_CONFIG */\n80 param_node \u003d get_bl_mem_params_node(HW_CONFIG_ID);\n81 assert(param_node !\u003d NULL);\n82\n83 /* Copy HW config from Secure address to NS address */\n\u003e\u003e\u003e CID 378361: Null pointer dereferences (NULL_RETURNS)\n\u003e\u003e\u003e Dereferencing \"hw_config_info\", which is known to be \"NULL\".\n84 memcpy((void *)hw_config_info-\u003ens_config_addr,\n85 (void *)hw_config_info-\u003econfig_addr,\n86 (size_t)param_node-\u003eimage_info.image_size);\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: Iaf584044cfc3b2583862bcc1be825966eaffd38e\n" }, { "commit": "5b0219ddd5da42413f4c2be9302224b5b71295ff", "tree": "677d06d6e28d0581b3ff05a0fea828753944614e", "parents": [ "857f5790da3770a9ca52416274eec4e545c9be53" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu Dec 09 10:51:05 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu May 05 09:47:31 2022 +0100" }, "message": "feat(spmc): enable checking of execution ctx count\n\nThis is a mandatory entry in an SP\u0027s manifest however\ncurrently an S-EL1 partition running under the EL3 SPMC\nmust have the same amount of execution contexts as\nphysical cores therefore just check the entry matches\nthis value.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I4c2a85ccde7a7bb9b1232cf6389a8c532cbf3d41\n" }, { "commit": "857f5790da3770a9ca52416274eec4e545c9be53", "tree": "705dbb82c1c317fe21f3fa5ca08c86d48b75f6bc", "parents": [ "e1df6008d9b4a00da25ec08fbdcbd3a5967fdb54" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Tue Aug 24 11:31:52 2021 +0100" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu May 05 09:47:31 2022 +0100" }, "message": "feat(spmc): enable parsing of UUID from SP Manifest\n\nTo align with other SPMC implementations parse the UUID\nfrom the SP manifest as 4 uint32 values and store\nthis internally.\n\nChange-Id: I7de5d5ef8d98dc14bc7c76892133c2333358a379\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\n" }, { "commit": "e1df6008d9b4a00da25ec08fbdcbd3a5967fdb54", "tree": "d9d668c703ead3068ad484664b5b7e257a81250a", "parents": [ "2d65ea1930d4ce26cc176a8c60e9401d0b4f862a" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu Sep 02 13:18:41 2021 +0100" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu May 05 09:47:30 2022 +0100" }, "message": "feat(spmc): add partition mailbox structs\n\nAdd mailbox structs to the partition descriptors\nand ensure these are initialised correctly.\n\nChange-Id: Ie80166d19763c266b6a1d23e351d312dc31fb221\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\n" }, { "commit": "2d65ea1930d4ce26cc176a8c60e9401d0b4f862a", "tree": "a5c3e36ae22c53a5bd66bb3ba965baa022692e93", "parents": [ "44639ab73e43e0b79da834dff8c85266d68e5066" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Mon Dec 20 10:53:52 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu May 05 09:47:30 2022 +0100" }, "message": "feat(plat/arm): allow BL32 specific defines to be used by SPMC_AT_EL3\n\nFor EL3 SPMC configuration enabled platforms, allow the reuse of\nBL32 specific definitions.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I37ffbbf680326c101fbb2f146085a96c138f07a1\n" }, { "commit": "44639ab73e43e0b79da834dff8c85266d68e5066", "tree": "9ccd00184ad8f3f3d6412f49c2e1cf5f2f521db4", "parents": [ "a34ccd4c20e23f882e36b3d2b53ab5032aabc6d1" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Mon Nov 29 16:59:02 2021 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu May 05 09:47:30 2022 +0100" }, "message": "feat(plat/fvp): add EL3 SPMC #defines\n\nIntroduce additional #defines for running with the EL3\nSPMC on the FVP.\n\nThe increase in xlat tables has been chosen to allow\nthe test cases to complete successfully and may need\nadjusting depending on the desired usecase.\n\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\nChange-Id: I7f44344ff8b74ae8907d53ebb652ff8def2d2562\n" }, { "commit": "a34ccd4c20e23f882e36b3d2b53ab5032aabc6d1", "tree": "9c55ba5784fedcbd3d6377a7e3623441dfbb46ac", "parents": [ "7affa25cad400101c016082be2d102be0f4fce80" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu Aug 19 14:42:19 2021 +0100" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Thu May 05 09:46:39 2022 +0100" }, "message": "test(plat/fvp/lsp): add example logical partition\n\nAdd an example logical partition to the FVP platform that\nsimply prints and echos the contents of a direct request\nwith the appropriate direct response.\n\nChange-Id: Ib2052c9a63a74830e5e83bd8c128c5f9b0d94658\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\n" }, { "commit": "d6fbcc57f91cdbf6fa1169373514e7187921c3dd", "tree": "ba1d6e5400e1cb94d430baa56ceb128385078d8f", "parents": [ "97a24f82a450838cc12de8bbc7d4157045452bde", "a150486c975a2c6c3840f4780a86414b45d31335" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu May 05 10:30:26 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 05 10:30:26 2022 +0200" }, "message": "Merge changes from topic \"mp/delete_platforms\" into integration\n\n* changes:\n refactor(mt6795): remove mediatek\u0027s mt6795 platform\n refactor(sgm775): remove Arm sgm775 platform\n" }, { "commit": "97a24f82a450838cc12de8bbc7d4157045452bde", "tree": "2e536e0df255ce1073f44728269416cb3b08eaaa", "parents": [ "b7bd9863dc2f0a055e0c4bc065e071c4b1863647", "598d1fa85f8d9c5c62317bfc9d2d561711c980b5" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Thu May 05 09:34:04 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 05 09:34:04 2022 +0200" }, "message": "Merge \"docs(maintainers): add code owners for Firmware Update driver\" into integration" }, { "commit": "598d1fa85f8d9c5c62317bfc9d2d561711c980b5", "tree": "2e536e0df255ce1073f44728269416cb3b08eaaa", "parents": [ "b7bd9863dc2f0a055e0c4bc065e071c4b1863647" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed May 04 16:19:17 2022 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed May 04 16:43:40 2022 +0100" }, "message": "docs(maintainers): add code owners for Firmware Update driver\n\nAdded myself and Sandrine Bailleux as code owners for Firmware\nUpdate driver.\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: I34fad895c6236fedc814fb6da4b04fd7fbed9227\n" }, { "commit": "ca0fdbd8e0d625ece0f87ca16eacabf13db70921", "tree": "7be7b4027792fd014fda15bd328b039582bde1eb", "parents": [ "f4ec47613fef8db8037195147dc2ac6fb6f154ff" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Fri Apr 08 09:52:26 2022 +0100" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 04 15:38:48 2022 +0100" }, "message": "fix(sptool): update Optee FF-A manifest\n\nChange the OPTEE FF-A manifest to comply with changes to the sp pkg [1].\nThe sptool packs the image at the default offset of 0x4000, if it is not\nprovided in the arguments.\n\n[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14507\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I647950410114f7fc24926696212bb7f8101390ac\n" }, { "commit": "f4ec47613fef8db8037195147dc2ac6fb6f154ff", "tree": "57f062e027e18fd7cf2965cbfa2eebaf053f5b1e", "parents": [ "822c72791f791d26e233df0c15a655c3dbd8b117" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Mar 22 19:17:44 2022 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 04 15:37:47 2022 +0100" }, "message": "feat(sptool): delete c version of the sptool\n\nChange-Id: I224762ef66624c78dd87729dac80b2c956ee50ba\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "822c72791f791d26e233df0c15a655c3dbd8b117", "tree": "c95192fc17fc77df4fd845b2431471f1ed68fd5f", "parents": [ "2e82874cc9b7922e000dd4d7718e3153e347b1d7" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Tue Mar 22 16:28:51 2022 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 04 15:37:47 2022 +0100" }, "message": "feat(sptool): use python version of sptool\n\nChange-Id: I567ef0b977c69c38323740a592dd9451e261a407\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\n" }, { "commit": "2e82874cc9b7922e000dd4d7718e3153e347b1d7", "tree": "e60d1995efa18eb03795bc6e34435eaec4500e1d", "parents": [ "a96a07bfb66b7d38fe3da824e8ba183967659008" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 21 16:27:56 2022 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 04 15:36:56 2022 +0100" }, "message": "feat(sptool): python version of the sptool\n\nTo cope with the changes/design decisions in the implementation of\nboot protocol, from FF-A v1.1 specification in the S-EL2 SPM, we have\nchanged the format of the sp pkg header.\nThese changes need to be reflected in the sptool, used for packaging\nthe SP binary, and the SP\u0027s FF-A manifest. Now the SP pkg can\ncontain the boot information blob as defined by the FF-A specification.\nTo cater for these changes, bring to the TF-A project an equivalent to\nthe tool used in the Hafnium project.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I046f5d6e3c2ef0ba6c87f65302e127dedef34c28\n" }, { "commit": "b7bd9863dc2f0a055e0c4bc065e071c4b1863647", "tree": "da9f78c0b810bfacf10da02b69225e22c52da13c", "parents": [ "8ac22f79c47205d017ee2a83bb56ad9a5569f032", "a5d36574fc787e96e56671eb1b0eaef58e980ca8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 04 14:17:38 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 04 14:17:38 2022 +0200" }, "message": "Merge changes from topic \"hm/make-refactor\" into integration\n\n* changes:\n docs(prerequisites): use LLVM utilities to build with clang\n build(make): use clang binutils to compile\n" }, { "commit": "8ac22f79c47205d017ee2a83bb56ad9a5569f032", "tree": "3d2322550c45055cc3be2ef3cb70fe191d19fa4a", "parents": [ "6dc0f1f3296c76357bbda2d5232eab5486b6ccf7", "436cd754f2b0f9c0ce3094961bd1e179eeff2fc1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 04 14:16:36 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 04 14:16:36 2022 +0200" }, "message": "Merge \"feat(allwinner): add SMCCC SOCID support\" into integration" }, { "commit": "7affa25cad400101c016082be2d102be0f4fce80", "tree": "e1728c0729e74138a9a9b038152e4e4fb9790705", "parents": [ "6dc0f1f3296c76357bbda2d5232eab5486b6ccf7" ], "author": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Mon Feb 14 17:06:09 2022 +0000" }, "committer": { "name": "Marc Bonnici", "email": "marc.bonnici@arm.com", "time": "Wed May 04 12:07:33 2022 +0100" }, "message": "feat(spmc/lsp): add logical partition framework\n\nIntroduce a framework to support running logical\npartitions alongside the SPMC in EL3 as per the\nv1.1 FF-A spec.\n\nThe DECLARE_LOGICAL_PARTITION macro has been added to\nsimplify the process to define a Logical Partition.\nThe partitions themselves are statically allocated\nwith the descriptors placed in RO memory.\n\nIt is assumed that the MAX_EL3_LP_DESCS_COUNT will\nbe defined by the platform.\n\nChange-Id: I1c2523e0ad2d9c5d36aeeef6b8bcb1e80db7c443\nSigned-off-by: Marc Bonnici \u003cmarc.bonnici@arm.com\u003e\n" }, { "commit": "a150486c975a2c6c3840f4780a86414b45d31335", "tree": "22fa7f2a96894d75adeef1554f7478b233e0c7bc", "parents": [ "15e54148618012a4798467f4b98ef4ca23e55c6b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 04 11:14:17 2022 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 04 12:23:29 2022 +0200" }, "message": "refactor(mt6795): remove mediatek\u0027s mt6795 platform\n\nMediatek\u0027s mt6795 platform was deprecated in 2.5 release and as per [1]\na platform which has been marked deprecated should be removed from repo\nafter 2 release cycle.\n\n[1] https://trustedfirmware-a.readthedocs.io/en/latest/plat/deprecated.html?highlight\u003ddeprecated\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: Ic427a3071316a13f34a726a1eb086b679e1671a1\n" }, { "commit": "15e54148618012a4798467f4b98ef4ca23e55c6b", "tree": "b273b68c7f07a7941fbd4a7bc4f35dd86d96848c", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 04 10:59:52 2022 +0100" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed May 04 11:15:29 2022 +0100" }, "message": "refactor(sgm775): remove Arm sgm775 platform\n\nArm\u0027s sgm775 platform was deprecated in 2.5 release and as per [1] a\nplatform which has been marked deprecated should be removed from repo\nafter 2 release cycle.\n\n[1] https://trustedfirmware-a.readthedocs.io/en/latest/plat/deprecated.html?highlight\u003ddeprecated\n\nSigned-off-by: Manish Pandey \u003cmanish.pandey2@arm.com\u003e\nChange-Id: I3cce6f330a1def725188eefd558bd0e4ec559725\n" }, { "commit": "a96a07bfb66b7d38fe3da824e8ba183967659008", "tree": "de8b86eb19afa8d4cef29aa7434ba9d8b9504957", "parents": [ "b1e6a41572240839e62099aa00298174b18c696a" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 21 14:11:43 2022 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 04 10:11:24 2022 +0100" }, "message": "refactor(sptool): use SpSetupActions in sp_mk_generator.py\n\nThe \"sp_mk_generator.py\" is responsible for processing the SP layout\nfile, which contains information about the SPs to be deployed on top of\nthe SPM, to generate the \"sp_gen.mk\" file which appends information\nspecific to each SP that shall help with packing all SPs into a fip\nbinary.\nBefore this patch the \"sp_mk_generator.py\" was a monolithic script,\nwhich has now been broken down into functions for each identified\nconfiguration action.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I8ee7487f2e07d53e508d17d0fe4510e22957f5ca\n" }, { "commit": "b1e6a41572240839e62099aa00298174b18c696a", "tree": "6c258d554bdddaa217b90c9816dc3a1b9f8e1b02", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1" ], "author": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Mon Mar 21 14:08:27 2022 +0000" }, "committer": { "name": "J-Alves", "email": "joao.alves@arm.com", "time": "Wed May 04 10:11:24 2022 +0100" }, "message": "feat(sptool): add python SpSetupActions framework\n\nDeveloped python framework to help with SPs configuration. The framework\nallows for functions (dubbed \"actions\" in the framework) to be defined\nthat should process the \"sp_layout.json\" file.\n\nSigned-off-by: J-Alves \u003cjoao.alves@arm.com\u003e\nChange-Id: I278cd5a7aa0574168473e28f3b0fe231d7b548ee\n" }, { "commit": "6dc0f1f3296c76357bbda2d5232eab5486b6ccf7", "tree": "c1a352391919d3e5dd81be4e85bde766300ced3a", "parents": [ "3e0a087f30f5786f01cfc2450185cf9f6d17d686", "9a13b07f6ae94dd62b4b2224eb3cd3ea2830844b" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Wed May 04 08:29:23 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 04 08:29:23 2022 +0200" }, "message": "Merge \"build(commitlint): make the scope optional\" into integration" }, { "commit": "436cd754f2b0f9c0ce3094961bd1e179eeff2fc1", "tree": "f2359bebffafa26eee3fc32ca948c98211a917e8", "parents": [ "3e0a087f30f5786f01cfc2450185cf9f6d17d686" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Fri Sep 25 16:42:06 2020 +0100" }, "committer": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 04 02:30:08 2022 +0200" }, "message": "feat(allwinner): add SMCCC SOCID support\n\nThe Allwinner SID device holds a 16-bit SoC identifier, which we already\nuse in our code.\n\nExport this number through the generic SMCCC SOCID interface, to allow\nan architectural identification of an Allwinner SoC. This enables access\nto this information from non-secure world, simplifies generic drivers\n(ACPI comes to mind), and gives easy and precise access to the SoC ID\nfrom userland in OSes like Linux.\n\nChange-Id: I91753046b2ae5408ca7bc0b864fcd97d24c8267c\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "3e0a087f30f5786f01cfc2450185cf9f6d17d686", "tree": "2bd488870f08ae4f8c469505863b94fd7f2ddec4", "parents": [ "1ced6cad52f3fcfb1efaeab4f6d69984ebdc6b12", "e2b18771fc2a0528dda18dbdaac08dd8530df25a" ], "author": { "name": "André Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 04 02:10:02 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 04 02:10:02 2022 +0200" }, "message": "Merge changes from topic \"allwinner-idle\" into integration\n\n* changes:\n feat(allwinner): provide CPU idle states to the rich OS\n feat(allwinner): simplify CPU_SUSPEND power state encoding\n feat(allwinner): choose PSCI states to avoid translation\n feat(fdt): add the ability to supply idle state information\n fix(allwinner): improve DTB patching error handling\n refactor(allwinner): patch the DTB after setting up PSCI\n refactor(allwinner): move DTB change code into allwinner/common\n" }, { "commit": "1ced6cad52f3fcfb1efaeab4f6d69984ebdc6b12", "tree": "2536449cc0a8834b93c2e49a373ef824572e331e", "parents": [ "0d9133d4f2f6f60a68d91140edb0c6aefe6b9c3a", "b4a878367f8008f9b6b0e3dca3728565ebc8811f" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Tue May 03 17:06:49 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 03 17:06:49 2022 +0200" }, "message": "Merge changes from topic \"refactor-hw-config-load\" into integration\n\n* changes:\n docs(fvp): update loading addresses of HW_CONFIG\n docs(fconf): update device tree binding for FCONF\n feat(fvp): update HW_CONFIG DT loading mechanism\n refactor(st): update set_config_info function call\n refactor(fvp_r): update set_config_info function call\n refactor(arm): update set_config_info function call\n feat(fconf): add NS load address in configuration DTB nodes\n" }, { "commit": "7cb76fdf1c3d75eb62269cb317e4dc6f169fe482", "tree": "f24f4859e96af2149f3cfb4f710ffe5a17545479", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 03 14:59:48 2022 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 03 14:59:48 2022 +0200" }, "message": "docs(maintainers): update measured boot code owners\n\nPropose myself as a code owner of the measured boot module.\n\nAlso do a couple of updates along the way:\n\n - Add the measured boot bindings document to the list of measured\n boot files.\n\n - Fix the list of FVP files. plat/arm/board/fvp/fvp_measured_boot.c\n does not exist anymore. It has been replaced by\n plat/arm/board/fvp/fvp_measured_{bl1,bl2,common}_boot.c files.\n\nChange-Id: Ifb34f4f7c704b1db966b44428bbffd48c5e3c42b\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "9a13b07f6ae94dd62b4b2224eb3cd3ea2830844b", "tree": "b676320e4d5c065acfc233baa61b36391376be1b", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 03 08:14:23 2022 +0200" }, "committer": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Tue May 03 11:06:50 2022 +0200" }, "message": "build(commitlint): make the scope optional\n\nIn all TF-A commit messages, the first line must comply to the\nfollowing format:\n\n type(scope): description\n\nAlthough the conventional commits specification says that the scope\nabove is optional, we have made it mandatory in TF-A and the following\nerror message is printed if no scope is provided:\n\n scope may not be empty [scope-empty]\n\nHowever, this can be too restrictive for some types of commits. For\nexample, it is typically hard to choose a scope for documentation\npatches which modify several documents of different natures.\n\nLift this restriction in the tools and leave it up to the developer to\ndecide whether a scope is needed or not.\n\nChange-Id: I9d35e7790fc3fa74651794216fe8db265ad09982\nSigned-off-by: Sandrine Bailleux \u003csandrine.bailleux@arm.com\u003e\n" }, { "commit": "0d9133d4f2f6f60a68d91140edb0c6aefe6b9c3a", "tree": "57f446476d126b148c9d7df3506b34c05aa3ad9f", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1", "be73459a945d8fa781fcc864943ccd0a8d92421c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon May 02 23:42:48 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 02 23:42:48 2022 +0200" }, "message": "Merge \"feat(xilinx): add SPP/EMU platform support for versal\" into integration" }, { "commit": "be73459a945d8fa781fcc864943ccd0a8d92421c", "tree": "57f446476d126b148c9d7df3506b34c05aa3ad9f", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed Apr 13 09:04:53 2022 +0530" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon May 02 22:49:24 2022 +0200" }, "message": "feat(xilinx): add SPP/EMU platform support for versal\n\nThis patch adds SPP/EMU platform support for Xilinx Versal and\nalso updating the documentation.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: Ibdadec4d00cd33ea32332299e7a00de31dc9d60b\n" }, { "commit": "52ed157fd66812debb13a792c21f763de01aef70", "tree": "016c0e461c9d8cc88e18d7ccb40fafbb0a3666e0", "parents": [ "894c635b8316f579dc3cceab310ed878092f6bb1" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Sun Mar 20 00:49:57 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Sat Apr 30 09:24:03 2022 +0800" }, "message": "fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)\n\nThis patch is to add size checking to make sure that\neach certificate and encryption/decryption request\nare 4-byte align as this driver is expecting. Unaligned\nsize may indicate invalid/corrupted request hence will\nbe rejected.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Ib6f97849ec470e45679c5adc4fbfa3afd10eda90\n" }, { "commit": "894c635b8316f579dc3cceab310ed878092f6bb1", "tree": "37c6519c6c3f928fa1ac5b04f71cd10d60d3950d", "parents": [ "a0cad7ce4f3bea1d3e9aacab5066ef8e3c915c65", "ac4ac38c5443afdef38e38e9247c96359de3a2ea" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Apr 29 23:12:21 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 29 23:12:21 2022 +0200" }, "message": "Merge changes I47014d72,Ibf00c386 into integration\n\n* changes:\n docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS\n feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS\n" }, { "commit": "ac4ac38c5443afdef38e38e9247c96359de3a2ea", "tree": "679c2b5a1a58b6b737aba074b4af2547edefc0d2", "parents": [ "25844ff728e4a0e5430ba2032457aba7b780a701" ], "author": { "name": "Jorge Ramirez-Ortiz", "email": "jorge@foundries.io", "time": "Fri Apr 15 11:51:03 2022 +0200" }, "committer": { "name": "Jorge Ramirez-Ortiz", "email": "jorge@foundries.io", "time": "Fri Apr 29 22:54:34 2022 +0200" }, "message": "docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS\n\nDocument the RESET_TO_BL31 with parameters feature.\n\nSigned-off-by: Jorge Ramirez-Ortiz \u003cjorge@foundries.io\u003e\nChange-Id: I47014d724f2eb822b69a112c3acee546fbfe82d5\n" }, { "commit": "25844ff728e4a0e5430ba2032457aba7b780a701", "tree": "0f99fba1c1cd94b731fc42badae85b37ab41c6eb", "parents": [ "e96ffdc8b44ff4a9d33fe8b95c66a801d94c47db" ], "author": { "name": "Jorge Ramirez-Ortiz", "email": "jorge@foundries.io", "time": "Fri Apr 15 11:46:47 2022 +0200" }, "committer": { "name": "Jorge Ramirez-Ortiz", "email": "jorge@foundries.io", "time": "Fri Apr 29 22:54:23 2022 +0200" }, "message": "feat(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS\n\nIt is not always the case that RESET_TO_BL31 enabled platforms don\u0027t\nexecute a bootloader before BL31.\n\nFor those use cases, being able to receive arguments from that first\nloader (i.e: a DTB with TPM logs) might be necessary feature.\n\nThis code has been validated on iMX8mm.\n\nSigned-off-by: Jorge Ramirez-Ortiz \u003cjorge@foundries.io\u003e\nChange-Id: Ibf00c3867cb1d1012b8b376e64ccaeca1c9d2bff\n" }, { "commit": "a0cad7ce4f3bea1d3e9aacab5066ef8e3c915c65", "tree": "42d45aa240105c5bdd9cf0f638dafdc6e4861ca6", "parents": [ "10f7bd502edf4e9a69772c1563ce7a0f656f31b1", "1277af9bacca36b46d7aa341187bb3abef84332f" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Apr 29 19:10:33 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 29 19:10:33 2022 +0200" }, "message": "Merge \"fix(zynqmp): update the log message to verbose\" into integration" }, { "commit": "10f7bd502edf4e9a69772c1563ce7a0f656f31b1", "tree": "ed036cbb941140846961f8878418df0de03f3bf4", "parents": [ "145f665e07888112fb0d5438af7072e9222f19d9", "187a61761ef5d59bed0c94cca725bd6f116f64d0" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Apr 29 15:29:41 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 29 15:29:41 2022 +0200" }, "message": "Merge \"fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960\" into integration" }, { "commit": "145f665e07888112fb0d5438af7072e9222f19d9", "tree": "637ab48c52326dea64320a6d5fd5e1196af5224e", "parents": [ "06796a08d33363219b3deef357d962170d889e5b", "a0d3df66f31b19b823d0fe171beef121a02386f8" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Apr 29 13:52:59 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 29 13:52:59 2022 +0200" }, "message": "Merge \"docs(fvp): specify correct reference of the hw_config address\" into integration" }, { "commit": "a5d36574fc787e96e56671eb1b0eaef58e980ca8", "tree": "98fdb0bf190e2652d4e39b73f4f990f3d7e9105e", "parents": [ "c8a992fda867f259b04bb4147b91b9dd6482de37" ], "author": { "name": "Harrison Mutai", "email": "harrison.mutai@arm.com", "time": "Wed Feb 23 11:37:12 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Fri Apr 29 13:35:21 2022 +0200" }, "message": "docs(prerequisites): use LLVM utilities to build with clang\n\nMakefile updated to use LLVM utilities instead of GNU utilities when\ncompiling with clang. `CROSS_COMPILE` is not required since this\ndependency has been removed.\n\nChange-Id: I19706b84b9310e07935516681b86596c04ef8ad6\nSigned-off-by: Harrison Mutai \u003charrison.mutai@arm.com\u003e\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "1277af9bacca36b46d7aa341187bb3abef84332f", "tree": "522bffaa7bcb4751718871812c08f1e62c69c9bb", "parents": [ "06796a08d33363219b3deef357d962170d889e5b" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Tue Apr 12 09:21:32 2022 +0530" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 28 23:23:50 2022 +0200" }, "message": "fix(zynqmp): update the log message to verbose\n\nChanging the log message from notice to verbose, to save some space\nand that leads to successfull compilation.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: Iee5a808febf211464eb8ba6f0377f79378333f5d\n" }, { "commit": "06796a08d33363219b3deef357d962170d889e5b", "tree": "896c2c80147638ffd296b72c8549fda97d9aaac9", "parents": [ "942b0392218a93141ed90afafd005c6f28d7014f", "52a314af254966a604e192fcc3326737354f217a" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 28 23:20:16 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 28 23:20:16 2022 +0200" }, "message": "Merge \"feat(smmu): configure SMMU Root interface\" into integration" }, { "commit": "187a61761ef5d59bed0c94cca725bd6f116f64d0", "tree": "aea9a81f0f996986e143ecb76fb4ff17cb415472", "parents": [ "942b0392218a93141ed90afafd005c6f28d7014f" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Apr 14 19:10:17 2022 -0500" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Apr 28 20:33:09 2022 +0200" }, "message": "fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960\n\nCortex-A15 does not support FEAT_CSV2 so the existing workaround for\nSpectre V2 is sufficient to mitigate against Spectre BHB attacks,\nhowever the code needed to be updated to work with the new build flag.\n\nAlso, some code was refactored several years ago and not updated in\nthe Cortex-A15 library file so this patch fixes that as well.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I768c88a38c561c91019b038ac6c22b291955f18e\n" }, { "commit": "942b0392218a93141ed90afafd005c6f28d7014f", "tree": "1e0adbdc38421bec6810c99c398b990b4edf86da", "parents": [ "9b9a21f297811bd7c50318f61fb93f42a5bed9b0", "52cf9c2cd4882534d02e8996e4ff1143ee59290e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 28 18:51:50 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 28 18:51:50 2022 +0200" }, "message": "Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration\n\n* changes:\n feat(intel): add SMC support for HWMON voltage and temp sensor\n feat(intel): add SMC support for Get USERCODE\n fix(intel): extend SDM command to return the SDM firmware version\n feat(intel): add SMC for enquiring firmware version\n fix(intel): configuration status based on start request\n fix(intel): bit-wise configuration flag handling\n fix(intel): get config status OK status\n fix(intel): use macro as return value\n fix(intel): fix fpga config write return mechanism\n feat(intel): add SiP service for DCMF status\n feat(intel): add RSU \u0027Max Retry\u0027 SiP SMC services\n feat(intel): enable SMC SoC FPGA bridges enable/disable\n feat(intel): add SMC/PSCI services for DCMF version support\n feat(intel): allow to access all register addresses if DEBUG\u003d1\n fix(intel): modify how configuration type is handled\n feat(intel): support SiP SVC version\n feat(intel): enable firewall for OCRAM in BL31\n feat(intel): create source file for firewall configuration\n fix(intel): refactor NOC header\n" }, { "commit": "52a314af254966a604e192fcc3326737354f217a", "tree": "0a0bb2ff6156529526fa36aa59dcbc98a4e2e548", "parents": [ "19a9cc3a1b5d5a926e4beb5b61960f22d017528c" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Feb 04 12:30:11 2022 +0100" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Apr 28 18:50:24 2022 +0200" }, "message": "feat(smmu): configure SMMU Root interface\n\nThis change performs a basic configuration of the SMMU root registers\ninterface on an RME enabled system. This permits enabling GPC checks\nfor transactions originated from a non-secure or secure device upstream\nto an SMMU. It re-uses the boot time GPT base address and configuration\nprogrammed on the PE.\nThe root register file offset is platform dependent and has to be\nsupplied on a model command line.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07\n" }, { "commit": "9b9a21f297811bd7c50318f61fb93f42a5bed9b0", "tree": "3d2431211649b220bd84eb77ce3a49adf3bdf29a", "parents": [ "357dd7f69e8b01930c630ef01369b5416ef0b081", "5e690269d579d9461be3c5f5e3f59d4c666863a0" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 28 17:18:47 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 28 17:18:47 2022 +0200" }, "message": "Merge \"feat(qemu): add support for measured boot\" into integration" }, { "commit": "52cf9c2cd4882534d02e8996e4ff1143ee59290e", "tree": "c737b0bb176c427efb5264366d65f51b330a40b8", "parents": [ "93a5b97ec9e97207769db18ae34886e6b8bf2ea4" ], "author": { "name": "Kris Chaplin", "email": "kris.chaplin@linux.intel.com", "time": "Fri Jun 25 11:31:52 2021 +0100" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:46:56 2022 +0800" }, "message": "feat(intel): add SMC support for HWMON voltage and temp sensor\n\nAdd support to read temperature and voltage using SMC command\n\nSigned-off-by: Kris Chaplin \u003ckris.chaplin@linux.intel.com\u003e\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nChange-Id: I806611610043906b720b5096728a5deb5d652b1d\n" }, { "commit": "93a5b97ec9e97207769db18ae34886e6b8bf2ea4", "tree": "19e44a5c84b1a87a9b804524162dd0d33323abc7", "parents": [ "c026dfe38cfae379457a6ef53130bd5ebc9d7808" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Apr 27 18:57:29 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:45:26 2022 +0800" }, "message": "feat(intel): add SMC support for Get USERCODE\n\nThis patch adds SMC support for enquiring FPGA\u0027s User Code.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: I82c1fa9390b6f7509b2284d51e199fb8b6a9b1ad\n" }, { "commit": "c026dfe38cfae379457a6ef53130bd5ebc9d7808", "tree": "b153894ce5ecc3d4f332b7610cd4de6a27c71198", "parents": [ "c34b2a7a1a38dba88b6b668a81bd07c757525830" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Apr 27 18:54:10 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:44:27 2022 +0800" }, "message": "fix(intel): extend SDM command to return the SDM firmware version\n\nUpdates intel_smc_fw_version function to read SDM\nfirmware version in major/minor ACDS release number.\nUpdate CONFIG_STATUS Response Data [1] bit0-23.\n\nReturn INTEL_SIP_SMC_STATUS_ERROR if unexpected\nfirmware version is being retrieved.\n\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nChange-Id: I018ccbb961786a75dc6eb873b0f232e71341e1d2\n" }, { "commit": "c34b2a7a1a38dba88b6b668a81bd07c757525830", "tree": "ef5b911d10b9f1d1084c1e0a869e10c0536b1e18", "parents": [ "e40910e2dc3fa59bcce83ec1cf9a33b3e85012c4" ], "author": { "name": "Abdul Halim, Muhammad Hadi Asyrafi", "email": "muhammad.hadi.asyrafi.abdul.halim@intel.com", "time": "Fri Feb 05 11:50:58 2021 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:44:21 2022 +0800" }, "message": "feat(intel): add SMC for enquiring firmware version\n\nThis command allows non-secure world software to enquire the\nversion of currently running Secure Device Manager (SDM) firmware.\n\nThis will be useful in maintaining backward-compatibility as well\nas ensuring software cross-compabitility.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Ibc23734d1135db74423da5e29655f9d32472a3b0\n" }, { "commit": "e40910e2dc3fa59bcce83ec1cf9a33b3e85012c4", "tree": "209abf2bb8beb21622ba4a42e5ccab7e075df55e", "parents": [ "276a43663e8e315fa1bf0aa4824051d88705858b" ], "author": { "name": "Abdul Halim, Muhammad Hadi Asyrafi", "email": "muhammad.hadi.asyrafi.abdul.halim@intel.com", "time": "Tue Dec 29 16:49:23 2020 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:44:14 2022 +0800" }, "message": "fix(intel): configuration status based on start request\n\nConfiguration status command now returns the result based on the last\nconfig start command made to the runtime software. The status type can\nbe either:\n- NO_REQUEST (default)\n- RECONFIGURATION\n- BITSTREAM_AUTH\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nChange-Id: I97406abe09b49b9d9a5b43e62fe09eb23c729bff\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\n" }, { "commit": "276a43663e8e315fa1bf0aa4824051d88705858b", "tree": "bc45c9aef5477fb26a6b6265557d5564cdd57ae9", "parents": [ "07915a4fd5848fbac69dcbf28f00353eed10a942" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:40:58 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:40:58 2022 +0800" }, "message": "fix(intel): bit-wise configuration flag handling\n\nChange configuration type handling to bit-wise flag. This is to align\nwith Linux\u0027s FPGA Manager definitions and promotes better compatibility.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: I5aaf91d3fec538fe3f4fe8395d9adb47ec969434\n" }, { "commit": "07915a4fd5848fbac69dcbf28f00353eed10a942", "tree": "2ef01bbce49e09e0e8d0e796bd72e7cc31bba51e", "parents": [ "e0fc2d1907b1c8a062c44a435be77a12ffeed84b" ], "author": { "name": "Abdul Halim, Muhammad Hadi Asyrafi", "email": "muhammad.hadi.asyrafi.abdul.halim@intel.com", "time": "Fri Nov 20 11:41:59 2020 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:30:59 2022 +0800" }, "message": "fix(intel): get config status OK status\n\nConfig status have different OK requirement between MBOX_CONFIG_STATUS\nand MBOX_RECONFIG_STATUS request. This patch adds the checking to\ndifferentiate between both command.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nChange-Id: I45a4c3de460b031757dbcbd0b3a8055cb0a55aff\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\n" }, { "commit": "e0fc2d1907b1c8a062c44a435be77a12ffeed84b", "tree": "8bb8faa676d67a057c3b273dbd9faa0e86ba1a80", "parents": [ "ef51b097bfa906bf1cee8ee641a1b7bcc8c5f3c0" ], "author": { "name": "Abdul Halim, Muhammad Hadi Asyrafi", "email": "muhammad.hadi.asyrafi.abdul.halim@intel.com", "time": "Fri Nov 20 11:06:00 2020 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:29:23 2022 +0800" }, "message": "fix(intel): use macro as return value\n\nSMC function should strictly return INTEL_SIP_SMC_STATUS macro. Directly\nreturning value of variable status might cause confusion in calling\nsoftware.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nChange-Id: Iea17f4feaa5c917e8b995471f3019dba6ea8dcd3\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\n" }, { "commit": "357dd7f69e8b01930c630ef01369b5416ef0b081", "tree": "6145b09d0dcdd4b771e727753fb4d26ff01cdc45", "parents": [ "e34ea9b9007d5d399c67ed85b81f71926d0c3ad8", "500d40d877617653d347fb6308144973d4297ab9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 28 16:25:34 2022 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 28 16:25:34 2022 +0200" }, "message": "Merge changes from topic \"vendor_makefile_extension\" into integration\n\n* changes:\n feat(plat/mediatek/build_helpers): introduce mtk makefile\n build(makefile): add extra makefile variable for extension\n" }, { "commit": "ef51b097bfa906bf1cee8ee641a1b7bcc8c5f3c0", "tree": "e0df9abc6fff9c348b4ce6f9501e8c5619027956", "parents": [ "984e236e0dee46708534a23c637271a931ceb67e" ], "author": { "name": "Abdul Halim, Muhammad Hadi Asyrafi", "email": "muhammad.hadi.asyrafi.abdul.halim@intel.com", "time": "Thu Nov 05 18:00:03 2020 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Thu Apr 28 22:25:05 2022 +0800" }, "message": "fix(intel): fix fpga config write return mechanism\n\nThis revert commit 279c8015fefcb544eb311b9052f417fc02ab84aa.\nThe previous change breaks this feature compatibility with Linux driver.\nHence, the fix for the earlier issue is going to be fixed in uboot instead.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Jit Loon Lim \u003cjit.loon.lim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: I93220243bad65ed53322050d990544c7df4ce66b\n" } ], "next": "984e236e0dee46708534a23c637271a931ceb67e" }