)]}' { "log": [ { "commit": "9fa9a0c55cc830e609415d2cedd2d34fcbec1008", "tree": "e089244a3604bcc9903ce935c1eeb2517ecb54a6", "parents": [ "92537e170d18a72252ff7574a655681bcbe21785" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 28 11:34:05 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 28 11:36:00 2022 +0100" }, "message": "fix(st-clock): print enums as unsigned\n\nWith gcc-11, the -Wformat-signedness warning complains about enum values\nthat should be printed as unsigned values. Change %d to %u for several\nlines in the clock driver.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Ia2d24e6feef5e852e0a6bfaa1286fe605f9a16b7\n" }, { "commit": "92537e170d18a72252ff7574a655681bcbe21785", "tree": "e65018e74830f0bbdc4c009abadb7631100cad96", "parents": [ "0446bda15c6ad4f3af0cfb26f06e7c87e4a5142d", "f4e3e1e85f64d8930e89c1396bc9785512f656bd" ], "author": { "name": "Sandrine Bailleux", "email": "sandrine.bailleux@arm.com", "time": "Mon Feb 28 10:39:59 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 28 10:39:59 2022 +0100" }, "message": "Merge \"fix(measured-boot): add RMM entry to event_log_metadata\" into integration" }, { "commit": "0446bda15c6ad4f3af0cfb26f06e7c87e4a5142d", "tree": "ee8a693acfc02f9bf76a9db27fe0284a07c694e3", "parents": [ "8a3429928990924c1b509c0d50401dd9e7d4bf46", "e15591aaf47ab45941f0d7a03abf3e4a830ac1d9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Feb 25 14:52:23 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 25 14:52:23 2022 +0100" }, "message": "Merge \"fix(cert_create): let distclean Makefile target remove the cert_create tool\" into integration" }, { "commit": "e15591aaf47ab45941f0d7a03abf3e4a830ac1d9", "tree": "6404d6cea717dc3cb8793002225f00bbccdf305c", "parents": [ "510155aa7454674e03169fcc8ee4413ebeebfa4a" ], "author": { "name": "Nicolas Boulenguez", "email": "nicolas@debian.org", "time": "Wed Mar 31 12:22:45 2021 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Feb 25 12:55:12 2022 +0000" }, "message": "fix(cert_create): let distclean Makefile target remove the cert_create tool\n\nFor some targets, Make recursively invokes itself in subdirectories.\nWhen delegating the distclean target to tools/cert_create/Makefile,\nthe submake is called with the clean target instead of realclean.\nBecause of this, the submake never removes the cert_create executable.\n\nA proper but more intrusive fix would\n* avoid confusion about the semantics by following traditions or using\n new names\n https://www.gnu.org/prep/standards/standards.html#Standard-Targets\n* avoid typing errors with the special $@ variable.\nSomething like:\n\nIn tools/cert_create/Makefile:\nmostlyclean:\n # Remove most objects but keep some results.\n $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})\nclean: mostlyclean\n # mostlyclean, then remove things built by Make.\n $(call SHELL_DELETE,${BINARY})\ndistclean: clean\n # clean, then remove things built by ./configure (none here).\nrealclean maintainer-clean: distclean\n # distclean, then remove things built by autootols (none here).\n\nIn Makefile:\nmostlyclean clean distclean realclean maintainer-clean:\n\t$(MAKE) -C subdir1 $@\n\t$(MAKE) -C subdir2 $@\n\nSigned-off-by: Nicolas Boulenguez \u003cnicolas@debian.org\u003e\nChange-Id: Iabfeca3da5724ab90a56ad6dcd6870d0a1d6b07f\n" }, { "commit": "8a3429928990924c1b509c0d50401dd9e7d4bf46", "tree": "bbed795df732a758be3cd30fed7f19af7f034c7e", "parents": [ "510155aa7454674e03169fcc8ee4413ebeebfa4a", "c0959d2c460cbf7c14e7ba2a57d69ecddae80fd8" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Feb 25 04:50:31 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 25 04:50:31 2022 +0100" }, "message": "Merge changes I1784d643,Icb6e3699,I7805756e into integration\n\n* changes:\n fix(errata): workaround for Cortex-A510 erratum 2172148\n fix(errata): workaround for Cortex-A510 erratum 2218950\n fix(errata): workaround for Cortex-A510 erratum 2250311\n" }, { "commit": "c0959d2c460cbf7c14e7ba2a57d69ecddae80fd8", "tree": "9a6e6655a79c4988afc50772cb907cfe02b18a6d", "parents": [ "cc79018b71e45acb524fc5d429d394497ad53646" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Feb 15 22:55:22 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 24 22:31:52 2022 +0100" }, "message": "fix(errata): workaround for Cortex-A510 erratum 2172148\n\nCortex-A510 erratum 2172148 is a Cat B erratum that applies to revisions\nr0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I1784d643ca3d1d448340cd421facb5f229df1d22\n" }, { "commit": "cc79018b71e45acb524fc5d429d394497ad53646", "tree": "2d3c6e8268d4eef9478c42d21a0f66fe10f36f99", "parents": [ "7f304b02a802b7293d7a8b4f4030c5ff00158404" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Mon Feb 14 20:19:08 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 24 22:31:47 2022 +0100" }, "message": "fix(errata): workaround for Cortex-A510 erratum 2218950\n\nCortex-A510 erratum 2218950 is a Cat B erratum that applies to revisions\nr0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Icb6e369946f8978a08cf8ed5e4452782efb0a77a\n" }, { "commit": "7f304b02a802b7293d7a8b4f4030c5ff00158404", "tree": "fb56e293993141b23067513982e916ab8cc830cd", "parents": [ "e72bbe47ba7f2a0087654fd99ae24b5b7b444943" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Sun Feb 13 21:00:10 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Thu Feb 24 23:30:41 2022 +0200" }, "message": "fix(errata): workaround for Cortex-A510 erratum 2250311\n\nCortex-A510 erratum 2250311 is a Cat B erratum that applies to revisions\nr0p0, r0p1, r0p2, r0p3 and r1p0 and is fixed in r1p1.\n\nThis erratum workaround is a bit different because it interacts with a\nfeature supported in TFA. The typical method of implementing an errata\nworkaround will not work in this case as the MPMM feature would just be\nre-enabled by context management at every core power on after being\ndisabled by the errata framework. So in addition to disabling MPMM, this\nworkaround also sets a flag in the MPMM runtime framework indicating\nthat the feature should not be enabled even if ENABLE_MPMM\u003d1.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I7805756e65ec90b6ef8af47e200617c9e07a3a7e\n" }, { "commit": "510155aa7454674e03169fcc8ee4413ebeebfa4a", "tree": "dce6334b1455efb866a8e08d4b9ce95d31924f7c", "parents": [ "913e0334f9fc3a69d313ae530e831a0bd642fe25", "e72bbe47ba7f2a0087654fd99ae24b5b7b444943" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Feb 24 20:47:47 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 24 20:47:47 2022 +0100" }, "message": "Merge changes I7b1498fa,I1d2ebee3,I875519ff,I8c427ef2 into integration\n\n* changes:\n fix(errata): workaround for Cortex-A510 erratum 2041909\n fix(errata): workaround for Cortex-A510 erratum 2042739\n fix(errata): workaround for Cortex-A510 erratum 2288014\n fix(errata): workaround for Cortex-A510 erratum 1922240\n" }, { "commit": "913e0334f9fc3a69d313ae530e831a0bd642fe25", "tree": "9aeb2f4d1ba537b4930df034e267f3c1b4f6deec", "parents": [ "e76b018f0554103b8af9ef4dca67c821a5ad2291", "327422633bef112a10579d4daeca0f596cd02911" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 24 15:23:44 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 24 15:23:44 2022 +0100" }, "message": "Merge \"docs(el3-runtimes): context management refactor proposal\" into integration" }, { "commit": "327422633bef112a10579d4daeca0f596cd02911", "tree": "9aeb2f4d1ba537b4930df034e267f3c1b4f6deec", "parents": [ "e76b018f0554103b8af9ef4dca67c821a5ad2291" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Mon Jan 24 11:45:38 2022 +0000" }, "committer": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Thu Feb 24 08:04:48 2022 +0200" }, "message": "docs(el3-runtimes): context management refactor proposal\n\nThis patch submits an RFC to refactor the context management\nmechanism in TF-A.\n\nSigned-off-by: Soby Mathew \u003csoby.mathew@arm.com\u003e\nChange-Id: Ia1ad5a85cb86c129e2feaf36bed123f0067c3965\n" }, { "commit": "e76b018f0554103b8af9ef4dca67c821a5ad2291", "tree": "5226bac5227442b39c22a61d132a03230aa8e280", "parents": [ "2c23b9c1b3a92f85138867816aca39a24e86d34a", "27bc29367cf379773083399e88d34f16173c40d1" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 23 16:31:38 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 23 16:31:38 2022 +0100" }, "message": "Merge \"docs(a3k): add information about system-wide Crypto++ library\" into integration" }, { "commit": "2c23b9c1b3a92f85138867816aca39a24e86d34a", "tree": "9815ad47c84e02d8f314ab1f2aa462d42f02a6b9", "parents": [ "80b895ca71bf7f4a330266df75b073b650cd9f8a", "5a60efa12a57cde98240f861e45609cb9b94d58d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 23 16:27:00 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 23 16:27:00 2022 +0100" }, "message": "Merge \"fix(a3k): fix comment about BootROM address range\" into integration" }, { "commit": "80b895ca71bf7f4a330266df75b073b650cd9f8a", "tree": "d24986a07b230803d45aeb8462c985bdd16269c7", "parents": [ "176717989fba5935e43da99f9297876896164bc6", "ef515f0d3466a8beded4fd662718abbd97391b13" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 23 16:25:44 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 23 16:25:44 2022 +0100" }, "message": "Merge \"feat(board/rdedmunds): add support for rdedmunds variant\" into integration" }, { "commit": "176717989fba5935e43da99f9297876896164bc6", "tree": "96b675db7df71969b0a69f5d235087ef3dd3cbda", "parents": [ "9148f44067f6a870bfe80de2cbcaf0d98e7643e0", "fa7fdfabf07d91439b0869ffd8e805f0166294bf" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Feb 23 15:34:57 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 23 15:34:57 2022 +0100" }, "message": "Merge changes from topic \"bug-fix\" into integration\n\n* changes:\n fix(nxp-crypto): refine code to avoid hang issue for some of toolchain\n build(changelog): add new scope for nxp crypto\n fix(lx2): drop erratum A-009810\n" }, { "commit": "f4e3e1e85f64d8930e89c1396bc9785512f656bd", "tree": "74b3506d5cad65ec00c61434b7c5d976e037da50", "parents": [ "9148f44067f6a870bfe80de2cbcaf0d98e7643e0" ], "author": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Mon Jan 10 15:13:00 2022 +0100" }, "committer": { "name": "Tamas Ban", "email": "tamas.ban@arm.com", "time": "Wed Feb 23 12:41:19 2022 +0100" }, "message": "fix(measured-boot): add RMM entry to event_log_metadata\n\nPlatforms which support Realm world cannot boot up\nproperly if measured boot is enabled at build time.\nAn assertions occurs due to the missing RMM entry\nin the event_log_metadata array.\n\nSigned-off-by: Tamas Ban \u003ctamas.ban@arm.com\u003e\nChange-Id: I172f10a440797f7c9e1bc79dc72242b40c2521ea\n" }, { "commit": "9148f44067f6a870bfe80de2cbcaf0d98e7643e0", "tree": "f634c3abc9f1f161c58cc579b211e9f9bf93cacb", "parents": [ "47909f9d11380bc84f6b8995470a8258facb2809", "dcb1959161935aa58d2bb852f3cef0b96458a4e1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 23 11:56:13 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 23 11:56:13 2022 +0100" }, "message": "Merge \"fix(arm): increase ARM_BL_REGIONS count\" into integration" }, { "commit": "dcb1959161935aa58d2bb852f3cef0b96458a4e1", "tree": "b2ac76940b7d73059795ae3deeff7d41ed72c972", "parents": [ "2ca915ba9c48c2f8ee0480a7240609f56de23434" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Tue Feb 22 14:45:43 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Feb 23 12:34:42 2022 +0200" }, "message": "fix(arm): increase ARM_BL_REGIONS count\n\nOn RME-enabled platforms, it is currently not possible to incorporate\nmapping of all bl_regions specified in bl31 setup[1] with the\nARM_BL_REGIONS macro defined to 6. Hence increased its count to 7.\n\n[1]: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/\nplat/arm/common/arm_bl31_setup.c#n380\n\nChange-Id: Ieaa97f026ab2ae6eae22442595aa4122ba0a13c4\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "e72bbe47ba7f2a0087654fd99ae24b5b7b444943", "tree": "25f3cbc381ef2831c64e97517142af5a429d8e89", "parents": [ "d48088acbe400133037ae74acf1b722b059119bb" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Jan 11 17:54:41 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Feb 23 00:57:05 2022 +0100" }, "message": "fix(errata): workaround for Cortex-A510 erratum 2041909\n\nCortex-A510 erratum 2041909 is a Cat B erratum that applies to revision\nr0p2 and is fixed in r0p3. It is also present in r0p0 and r0p1 but there\nis no workaround in these revisions.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I7b1498faa0c79488dee0d11d07f6e9f58144e298\n" }, { "commit": "d48088acbe400133037ae74acf1b722b059119bb", "tree": "0a0f4da9116079a457079a361f9775e603ba1853", "parents": [ "d5e2512c6b86409686f5d1282922ebdf72459fc2" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri Jan 07 17:12:31 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Feb 23 00:57:00 2022 +0100" }, "message": "fix(errata): workaround for Cortex-A510 erratum 2042739\n\nCortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions\nr0p0, r0p1 and r0p2 and is fixed in r0p3.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I1d2ebee3914396e1e298eb45bdab35ce9e194ad9\n" }, { "commit": "d5e2512c6b86409686f5d1282922ebdf72459fc2", "tree": "0d95eda77d3b6ef439667e27451fef5e1be0e56b", "parents": [ "83435637bfafbf1ce642a5fabb52e8d7b2819e36" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Thu Jan 06 14:54:49 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Feb 23 00:56:55 2022 +0100" }, "message": "fix(errata): workaround for Cortex-A510 erratum 2288014\n\nCortex-A510 erratum 2288014 is a Cat B erratum that applies to revisions\nr0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I875519ff55be90244cc3d3a7e9f7abad0fc3c2b8\n" }, { "commit": "83435637bfafbf1ce642a5fabb52e8d7b2819e36", "tree": "617b54ac87ca4137b5305bfed811f9a85fc3db58", "parents": [ "8a855bd24329e081cf13a257c7d2dc3ab4e5dcca" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue Jan 04 16:15:18 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Feb 23 01:56:43 2022 +0200" }, "message": "fix(errata): workaround for Cortex-A510 erratum 1922240\n\nCortex-A510 erratum 1922240 is a Cat B erratum that applies to revision\nr0p0 and is fixed in r0p1.\n\nSince no errata framework code existed for A510 prior to this patch, it\nhas been added as well. Also some general cleanup changes in the CPU lib\nmakefile.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN2397239\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I8c427ef255cb4b38ed3e5c2c7444fcef957277e4\n" }, { "commit": "47909f9d11380bc84f6b8995470a8258facb2809", "tree": "4aa21ae83e7f2b0a407daa92fed78e78f463941f", "parents": [ "2ca915ba9c48c2f8ee0480a7240609f56de23434", "8a855bd24329e081cf13a257c7d2dc3ab4e5dcca" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Feb 22 18:48:17 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 22 18:48:17 2022 +0100" }, "message": "Merge changes from topic \"x2_errata\" into integration\n\n* changes:\n fix(errata): workaround for Cortex-A710 erratum 2136059\n fix(errata): workaround for Cortex-A710 erratum 2267065\n fix(errata): workaround for Cortex-X2 erratum 2216384\n fix(errata): workaround for Cortex-X2 errata 2081180\n fix(errata): workaround for Cortex-X2 errata 2017096\n" }, { "commit": "2ca915ba9c48c2f8ee0480a7240609f56de23434", "tree": "3fcfeefb69f3c48740642f8e47e647e4c64c76a6", "parents": [ "1776d4091b55c7fff310de9f12db7bd2d38494ad", "a29f6e76cbf76d509c00f84f068b59864d210dfd" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Tue Feb 22 09:44:46 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 22 09:44:46 2022 +0100" }, "message": "Merge \"feat(allwinner): apx803: add aldo1 regulator\" into integration" }, { "commit": "1776d4091b55c7fff310de9f12db7bd2d38494ad", "tree": "f9da4495adecee3be858a2ce1fc8d3695dd2a1d6", "parents": [ "a809a6029c1c0be019a8fdfa65fd8435f99caff9", "10bf3d7ca3994f0abc119a0773f8023e19acafd1" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 21 16:41:38 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 21 16:41:38 2022 +0100" }, "message": "Merge changes from topic \"paulliu-imx8m-eventlog\" into integration\n\n* changes:\n docs(imx8m): update for measured boot for imx8mm\n feat(plat/imx/imx8m/imx8mm): add support for measured boot\n" }, { "commit": "a29f6e76cbf76d509c00f84f068b59864d210dfd", "tree": "ea2ebc80165c8ae7d20445f11dd71f50a1a00ccb", "parents": [ "a809a6029c1c0be019a8fdfa65fd8435f99caff9" ], "author": { "name": "Thierry Bultel", "email": "thierry.bultel@linatsea.fr", "time": "Wed Dec 01 11:56:53 2021 +0100" }, "committer": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Mon Feb 21 16:26:54 2022 +0100" }, "message": "feat(allwinner): apx803: add aldo1 regulator\n\nNotice that aldo1 is typically useful for the Olimex A64 board, where\nit powers the PE bank through the vcc-pe line.\nWithout it, it is not possible to light the user led on PE17, for\ninstance.\n\nChange-Id: I70588bc977b884b22df87f1b075549cb8925925a\nSigned-off-by: Thierry Bultel \u003cthierry.bultel@linatsea.fr\u003e\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a809a6029c1c0be019a8fdfa65fd8435f99caff9", "tree": "62cc45fd062f299be2099422303a48953c1abd5a", "parents": [ "1b33b58b665e5ab5e179b8ee1b71f5412b721e42", "2f452974335d3d000b1e638bd21a6d02a8f5ec22" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Feb 18 19:07:41 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 18 19:07:41 2022 +0100" }, "message": "Merge \"docs(a3k): fix information about SATA GPT booting\" into integration" }, { "commit": "fa7fdfabf07d91439b0869ffd8e805f0166294bf", "tree": "b687b011a692dce43654e2915d6b8df943a1eb9b", "parents": [ "9dcbeb9df3304c2237e093715253ea3938e68187" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Nov 18 15:49:19 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Feb 18 12:03:16 2022 +0800" }, "message": "fix(nxp-crypto): refine code to avoid hang issue for some of toolchain\n\nbitfield structure maybe has strict-aliasing issue for some compiler,\nfor example the old code has hang issue for yocto 3.4 toolchain, so\nrefine the code to avoid to use bitfield structure.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I6b6d7597311240dd6d6b8ca4ce508c69332f9c68\n" }, { "commit": "9dcbeb9df3304c2237e093715253ea3938e68187", "tree": "bd0bba5e201da38eaed3323c0f253af975235ebb", "parents": [ "e36b0e4910aea56f90a6ab9b8cf3dc4008220031" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Feb 18 12:02:04 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Feb 18 12:03:07 2022 +0800" }, "message": "build(changelog): add new scope for nxp crypto\n\nAdd new scope for NXP Crypto CAAM drivers.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I4beb96d1dc655281cb2fc99b8b0b998f35499dba\n" }, { "commit": "e36b0e4910aea56f90a6ab9b8cf3dc4008220031", "tree": "d26661b3dcb590e19ced6d61ba556179b6c83114", "parents": [ "1b33b58b665e5ab5e179b8ee1b71f5412b721e42" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Oct 22 16:29:15 2021 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Feb 18 11:55:27 2022 +0800" }, "message": "fix(lx2): drop erratum A-009810\n\nThe erratum A-009810 should not be applied to LX2, the impaction is\nthat it can cause system reboot when linux tried to power down, so remove\nit.\n\nSigned-off-by: Yangbo Lu \u003cyangbo.lu@nxp.com\u003e\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I5e24229cf8512eff28b315ebcdf18de555c40c74\n" }, { "commit": "1b33b58b665e5ab5e179b8ee1b71f5412b721e42", "tree": "f1ae3e18e8a28d96af212031716e28639365ed14", "parents": [ "23ac80cc8b19d5c07693aeef8402c33ef9504d4e", "a3aeb4c86517f9cee20d1078486917a315f7f6c9" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Feb 17 19:15:55 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 17 19:15:55 2022 +0100" }, "message": "Merge changes from topic \"ls1046a\" into integration\n\n* changes:\n docs(layerscape): add ls1046a soc and board support\n feat(ls1046aqds): add board ls1046aqds support\n feat(ls1046afrwy): add ls1046afrwy board support\n feat(ls1046ardb): add ls1046ardb board support\n feat(ls1046a): add new SoC platform ls1046a\n fix(nxp-tools): fix tool location path for byte_swape\n fix(nxp-qspi): fix include path for QSPI driver\n build(changelog): add new scopes for NXP layerscape platforms\n" }, { "commit": "23ac80cc8b19d5c07693aeef8402c33ef9504d4e", "tree": "8becac2206780cc9a8f639b98c3a7d3fa17fc290", "parents": [ "8d9c1b3ca5f11c50150ff368981883c2ea444b66", "e80354212f591c8813dec27353e8241e03155b4c" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Feb 17 11:10:40 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 17 11:10:40 2022 +0100" }, "message": "Merge \"fix(fvp): extend memory map to include all DRAM memory regions\" into integration" }, { "commit": "8d9c1b3ca5f11c50150ff368981883c2ea444b66", "tree": "40b3235f8c35947279b17f1e2ca4690a1bfa823c", "parents": [ "b9be997d7d27b33f5e47234ba1bd9220a57db2a3", "cff26c19169dd94857e8180cc46b7aa4ccac574a" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Feb 17 00:35:52 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 17 00:35:52 2022 +0100" }, "message": "Merge changes from topic \"st-format-signedness\" into integration\n\n* changes:\n feat(stm32mp1): enable format-signedness warning\n fix(stm32mp1): correct types in messages\n fix(st-pmic): correct verbose message\n fix(st-sdmmc2): correct cmd_idx type in messages\n fix(st-fmc): fix type in message\n fix(mtd): correct types in messages\n fix(usb): correct type in message\n fix(tzc400): correct message with filter\n fix(psci): correct parent_node type in messages\n fix(libc): correct some messages\n fix(fconf): correct image_id type in messages\n fix(bl2): correct messages with image_id\n" }, { "commit": "e80354212f591c8813dec27353e8241e03155b4c", "tree": "17268c117ba5fc53452ed63460b0c1aa149f40c8", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Thu Dec 23 11:01:11 2021 +0100" }, "committer": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Wed Feb 16 20:22:16 2022 +0100" }, "message": "fix(fvp): extend memory map to include all DRAM memory regions\n\nCurrently only the lowest 2 DRAM region were configured in the\nTrustZone Controller, but the platform supports 6 regions spanning the\nwhole address space.\nConfiguring all of them to allow tests to access memory also in those\nhigher memory regions.\n\nFVP memory map:\nhttps://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map\nNote that last row is wrong, describing a non-existing 56bit address,\nall region labels should be shifted upward.\nIssue has been reported and next release will be correct.\n\nChange-Id: I695fe8e24aff67d75e74635ba32a133342289eb4\nSigned-off-by: Federico Recanati \u003cfederico.recanati@arm.com\u003e\n" }, { "commit": "27bc29367cf379773083399e88d34f16173c40d1", "tree": "fa9becac844e4c52d2857a1a2321f78ab1af8439", "parents": [ "2f452974335d3d000b1e638bd21a6d02a8f5ec22" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Wed Feb 16 15:15:42 2022 +0100" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Wed Feb 16 15:15:42 2022 +0100" }, "message": "docs(a3k): add information about system-wide Crypto++ library\n\nOn Debian systems it is possible to use system-wide Crypto++ library.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: Ib01d9376776b8afcb1ca46c16076e28c3d2e581d\n" }, { "commit": "ef515f0d3466a8beded4fd662718abbd97391b13", "tree": "0c19201f546045e6ae98cd9138f5646c241d017b", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Tony K Nadackal", "email": "tony.nadackal@arm.com", "time": "Thu Aug 19 14:44:11 2021 +0100" }, "committer": { "name": "Tony K Nadackal", "email": "tony.nadackal@arm.com", "time": "Wed Feb 16 13:42:24 2022 +0000" }, "message": "feat(board/rdedmunds): add support for rdedmunds variant\n\nAdd initial support for RD-Edmunds platform. This platform is considered\nas a variant of RD-N2 platform with only major change being the CPU\nwhich is Demeter instead of Neoverse-N2.\n\nSigned-off-by: Tony K Nadackal \u003ctony.nadackal@arm.com\u003e\nChange-Id: I939d9eac652fa9e76ad002ee5e6107aa79baa013\n" }, { "commit": "b9be997d7d27b33f5e47234ba1bd9220a57db2a3", "tree": "315c2bbd6605a3de75c1ec940a00d5670a695312", "parents": [ "22bbb34afa7fd7032c2f47d411473abc6b38875b", "c2eba07c47f8d831629104eeffcec11ed7d3b0a5" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Feb 16 11:00:41 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 16 11:00:41 2022 +0100" }, "message": "Merge \"feat(spm): add FFA_MSG_SEND2 forwarding in SPMD\" into integration" }, { "commit": "22bbb34afa7fd7032c2f47d411473abc6b38875b", "tree": "fdaada9757756a7464a3e05ef208357bf802a3ec", "parents": [ "24872370fa466e77ee7cbcac1ce780a93882fad7", "56e8952fc073761be4530be3b5f235ff24caba80" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Feb 15 23:41:24 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 15 23:41:24 2022 +0100" }, "message": "Merge \"refactor(stm32mp1): move PIE flag to SP_min\" into integration" }, { "commit": "24872370fa466e77ee7cbcac1ce780a93882fad7", "tree": "0ed1f7c9eba2f1f28362873d90296a9ffc20a3cf", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49", "cf89fd57ed3286d7842eef41cd72a3977eb6d317" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Feb 15 19:02:01 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Feb 15 19:02:01 2022 +0100" }, "message": "Merge changes from topic \"ea/corstone1000\" into integration\n\n* changes:\n feat(corstone1000): identify bank to load fip\n fix(corstone1000): change base address of FIP in the flash\n feat(corstone1000): implement platform specific psci reset\n feat(corstone1000): made changes to accommodate 3MB for optee\n build(corstone1000): rename diphda to corstone1000\n" }, { "commit": "cff26c19169dd94857e8180cc46b7aa4ccac574a", "tree": "faf99df2aa2ac469fdab175f3909e236a993b315", "parents": [ "43bbdca04f5a20bb4e648e18fc63061b6a6e4ecf" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 10:30:33 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "feat(stm32mp1): enable format-signedness warning\n\nAdd the flag -Wformat-signedness to TF_CFLAGS for STM32MP1.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I6af18778902b0a4dae1c08735d2d070ef3d137ce\n" }, { "commit": "43bbdca04f5a20bb4e648e18fc63061b6a6e4ecf", "tree": "49588aa925e7187680f886130a64f09f6660bb89", "parents": [ "47065ffe44c701b231322ec7160c8624d50a9deb" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 11:10:59 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(stm32mp1): correct types in messages\n\nAvoid warnings when -Wformat-signedness is enabled.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I0ca41cb96826b4f7f9bcf77909fad110325c1e91\n" }, { "commit": "47065ffe44c701b231322ec7160c8624d50a9deb", "tree": "3cdbf0ecee885f5f984a4c081ebf49a51cefbe86", "parents": [ "bc1c98a8c79b6f72395123ea8ed857a488746d4b" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Jan 06 09:35:35 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(st-pmic): correct verbose message\n\nReplace %d with %u in log, to avoid warning when\n-Wformat-signedness is enabled.\n\nChange-Id: Ied5823520181f225ae09bd164e2e52e9a7692c60\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "bc1c98a8c79b6f72395123ea8ed857a488746d4b", "tree": "c4207a7a531c3e3096147ef4bb1696f624ad66eb", "parents": [ "afcdc9d8d71e2b60071d3d34704f0e598e67a514" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 09:58:11 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(st-sdmmc2): correct cmd_idx type in messages\n\nAs cmd_idx is unsigned, we have to use %u and not %d.\nThis avoids warning when -Wformat-signedness is enabled.\n\nChange-Id: I6954a8c939f3fb47dbb2c6db56a1909565af078b\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "afcdc9d8d71e2b60071d3d34704f0e598e67a514", "tree": "688e4374da3dcd5c9ea2b2fd876994770cf3c995", "parents": [ "6e86b462490429fee6db877338a649b0e199b0ec" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 15:21:21 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(st-fmc): fix type in message\n\nAs page is unsigned, we should use %u and not %d.\nFind with -Wformat-signedness.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I7205971ee5e83163e4fe47d33bb9e90832b59ae0\n" }, { "commit": "6e86b462490429fee6db877338a649b0e199b0ec", "tree": "9186dfd0e8cfcefaa76db9efed4e75bb6813cab0", "parents": [ "bd9cd63ba096cb16161efa4df40f957421660df1" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 09:56:54 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(mtd): correct types in messages\n\nSome messages don\u0027t use the correct types, update them.\nThis avoids warning when -Wformat-signedness is enabled.\n\nChange-Id: Ie5384a7d139c48a623e1617c93d15fecc8a36061\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "bd9cd63ba096cb16161efa4df40f957421660df1", "tree": "daf95fe0f21db69bd77147386c2f30c5c42e8c6c", "parents": [ "bdc88d2154448957f452cb472ff95ccec5808ca1" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 15:22:14 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(usb): correct type in message\n\npdev-\u003erequest.bm_request is unsigned, use %u.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Idaadb8440d0b56bcfa02abd7c94a4ab59f5e15ee\n" }, { "commit": "bdc88d2154448957f452cb472ff95ccec5808ca1", "tree": "2e28db357e7dd2376a12da3ef02be114a7a342f2", "parents": [ "b9338eee7fbcac7f4b55f27b064572e847810422" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 09:55:21 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(tzc400): correct message with filter\n\nAs filter is unsigned, we have to use %u and not %d.\nThis avoids warning when -Wformat-signedness is enabled.\n\nChange-Id: I9fc9f15774dc974edfa3db65f5aecd1e70bc146b\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "b9338eee7fbcac7f4b55f27b064572e847810422", "tree": "1cb38b8bea9834f51d662bd05fc7e2a6813da56e", "parents": [ "a211fde940d4dbd8e95e4f352af2a066a4f89f30" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 11:09:23 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(psci): correct parent_node type in messages\n\nAs parent_node is unsigned, we have to use %u and not %d.\nThis avoids warning when -Wformat-signedness is enabled.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I5ab7acb33227d720b2c8a4ec013435442b219a44\n" }, { "commit": "a211fde940d4dbd8e95e4f352af2a066a4f89f30", "tree": "66bb5ccd0c4f73a6f8b4427ddb1eafc27f3b2c13", "parents": [ "cec2fb2b1a8359bf1f349a5b8c8a91a1845f4ca1" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 10:29:32 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(libc): correct some messages\n\nReplace %d with %u in logs, to avoid warning when\n-Wformat-signedness is enabled.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Id058f6fb0fd25ce5f83b1be41082403fcb205841\n" }, { "commit": "cec2fb2b1a8359bf1f349a5b8c8a91a1845f4ca1", "tree": "82cd145ce7dee3b313dc5ddf520a1c09d26feb7b", "parents": [ "e4c77db9c80d87009611a3079454877e6ce45a04" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 10:05:09 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(fconf): correct image_id type in messages\n\nAs image_id is unsigned, we have to use %u and not %d.\nThis avoids warning when -Wformat-signedness is enabled.\n\nChange-Id: I292e1639847e69ba79265fc32871c0ad7eebc94e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "e4c77db9c80d87009611a3079454877e6ce45a04", "tree": "fb4849c48631c21416d526663322010ccd01c3e2", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 14 09:54:36 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 15 18:09:51 2022 +0100" }, "message": "fix(bl2): correct messages with image_id\n\nAs image_id is unsigned, we have to use %u and not %d.\nThis avoids warning when -Wformat-signedness is enabled.\n\nChange-Id: I3f868f3d14c9f19349f0daa8a754179f887339c0\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "cf89fd57ed3286d7842eef41cd72a3977eb6d317", "tree": "0ed1f7c9eba2f1f28362873d90296a9ffc20a3cf", "parents": [ "1559450132c5e712f4d6896e53e4f1cb521fa465" ], "author": { "name": "Satish Kumar", "email": "satish.kumar01@arm.com", "time": "Wed Oct 27 16:31:04 2021 +0100" }, "committer": { "name": "Emekcan Aras", "email": "Emekcan.Aras@arm.com", "time": "Tue Feb 15 13:26:35 2022 +0000" }, "message": "feat(corstone1000): identify bank to load fip\n\nSecure enclave decides the boot bank based on the firmware update\nstate of the system and updates the boot bank information at a given\nlocation in the flash. In this commit, bl2 reads the given flash\nlocation to indentify the bank from which it should load fip from.\n\nSigned-off-by: Satish Kumar \u003csatish.kumar01@arm.com\u003e\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\nChange-Id: I7f0f4ffc97189c9deb99db44afcd966082ffbf21\n" }, { "commit": "5a60efa12a57cde98240f861e45609cb9b94d58d", "tree": "10634aafc4f3b0b09d6a78ed689ee5ed863a93c8", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Mon Feb 14 18:33:24 2022 +0100" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Feb 15 13:21:42 2022 +0100" }, "message": "fix(a3k): fix comment about BootROM address range\n\nA53 AP BootROM is just 16 kB long and is mapped to address range\n0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000.\nA53 AP BootROM itself is in the BootROM window which is 1 MB long and\nmapped to address range 0xFFF00000-0xFFFFFFFF.\n\nCM3 BootROM is not accessible from A53 core.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I5d4a4c7b1e7550c4738c67a872d341f945d48bbc\n" }, { "commit": "1559450132c5e712f4d6896e53e4f1cb521fa465", "tree": "5cd48e1c24676c06bed9e9bf48eb0026e1122ef2", "parents": [ "a599c80d063975cbeedbc86cfb619fca8545c487" ], "author": { "name": "Satish Kumar", "email": "satish.kumar01@arm.com", "time": "Mon Sep 20 06:01:54 2021 +0100" }, "committer": { "name": "Emekcan Aras", "email": "Emekcan.Aras@arm.com", "time": "Tue Feb 15 09:12:32 2022 +0000" }, "message": "fix(corstone1000): change base address of FIP in the flash\n\nMore space in the flash is reserved up front for metadata\nparser and UEFI variables. That requires change in the flash\nbase address of where images are present.\n\nSigned-off-by: Satish Kumar \u003csatish.kumar01@arm.com\u003e\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\nChange-Id: Ieaabe09374d707de18d36505c69b6c9a8c2ec2e9\n" }, { "commit": "a599c80d063975cbeedbc86cfb619fca8545c487", "tree": "aa30cb2b2654adbee8902856f653c3c371d4cc3d", "parents": [ "854d1c103a9b73bbde7ef1b89b06b29e3cc053bb" ], "author": { "name": "Emekcan Aras", "email": "Emekcan.Aras@arm.com", "time": "Wed Nov 17 18:45:32 2021 +0000" }, "committer": { "name": "Emekcan Aras", "email": "Emekcan.Aras@arm.com", "time": "Tue Feb 15 09:11:59 2022 +0000" }, "message": "feat(corstone1000): implement platform specific psci reset\n\nThis change implements platform specific psci reset\nfor the corstone1000.\n\nSigned-off-by: Emekcan Aras \u003cEmekcan.Aras@arm.com\u003e\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\nChange-Id: I25f77234506416c3376ff4a028f6ea40ebe68437\n" }, { "commit": "a3aeb4c86517f9cee20d1078486917a315f7f6c9", "tree": "fab81294e1d4828161062fa0fce1691ad6bf9233", "parents": [ "16662dc40dd2578d3000528ece090ed39ed18b9c" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Fri Jan 28 23:19:20 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "docs(layerscape): add ls1046a soc and board support\n\nUpdate document for nxp-layerscape to add ls1046a SoC and ls1046ardb,\nls1046afrwy board support.\n\nAlso update maintainer of ls1046a platforms.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I522f978bc93aa8d1f1d60fa8efef392b7d854df7\n" }, { "commit": "16662dc40dd2578d3000528ece090ed39ed18b9c", "tree": "8c63d981c3ec262ce31059c7c3950a88adb4b095", "parents": [ "b51dc56ab9ea79e4709f0d0ce965525d0d3da918" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 20 17:43:11 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "feat(ls1046aqds): add board ls1046aqds support\n\nls1046aqds board is full function board to evaluate ls1046a platform.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nSigned-off-by: York Sun \u003cyork.sun@nxp.com\u003e\nSigned-off-by: Pankaj Gupta \u003cpankaj.gupta@nxp.com\u003e\nChange-Id: Id1befe37a25f7c379e76791538348fd03bba78f7\n" }, { "commit": "b51dc56ab9ea79e4709f0d0ce965525d0d3da918", "tree": "6c8cd825ba2db557944b595f7164ae28d1c2bbf2", "parents": [ "bb52f7560b62043ed08a753f399dc80e8c1582d3" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 20 17:42:39 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "feat(ls1046afrwy): add ls1046afrwy board support\n\nThe LS1046A Freeway board (FRWY) is a high-performance computing,\nevaluation, and development platform that supports the LS1046A\narchitecture processor capable of support more than 32,000 CoreMark\nperformance. The FRWY-LS1046A board supports the LS1046A processor,\nonboard DDR4 memory, multiple Gigabit Ethernet, USB3.0 and M2_Type_E\ninterfaces for Wi-Fi, FRWY-LS1046A-AC includes the Wi-Fi card.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nSigned-off-by: York Sun \u003cyork.sun@nxp.com\u003e\nSigned-off-by: Pankaj Gupta \u003cpankaj.gupta@nxp.com\u003e\nChange-Id: I9a9680689e6f17bf4cc76fd5d1883eed6ace5149\n" }, { "commit": "bb52f7560b62043ed08a753f399dc80e8c1582d3", "tree": "d1faedd683c7dd5a36c98191ce5f0437955497e3", "parents": [ "cc708597fa72094c5a01df60e6538e4a7429c2a0" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 20 17:41:49 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "feat(ls1046ardb): add ls1046ardb board support\n\nThe LS1046A reference design board (RDB) is a high-performance\ncomputing, evaluation, and development platform that supports\nthe Layerscape LS1046A architecture processor.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nSigned-off-by: York Sun \u003cyork.sun@nxp.com\u003e\nSigned-off-by: Pankaj Gupta \u003cpankaj.gupta@nxp.com\u003e\nChange-Id: Ib7a01b309e0b0acc7f38e22b138e9e181dff244a\n" }, { "commit": "cc708597fa72094c5a01df60e6538e4a7429c2a0", "tree": "a394f3262969153df577008fad9c69d545d2cd00", "parents": [ "a89412a649020367a3ed0f87658ee131cd3dcd18" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 20 17:40:16 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "feat(ls1046a): add new SoC platform ls1046a\n\nThe LS1046A is a cost-effective, power-efficient, and highly\nintegrated system-on-chip (SoC) design that extends the reach\nof the NXP value-performance line of QorIQ communications\nprocessors. Featuring power-efficient 64-bit Arm Cortex A72\ncores with ECC-protected L1 and L2 cache memories for high\nreliability, running up to 1.8 GHz.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nSigned-off-by: Pankaj Gupta \u003cpankaj.gupta@nxp.com\u003e\nSigned-off-by: rocket \u003crod.dorris@nxp.com\u003e\nSigned-off-by: Biwen Li \u003cbiwen.li@nxp.com\u003e\nChange-Id: I208d9bf1702410463c2b2630d31d0cd4eb7e8837\n" }, { "commit": "a89412a649020367a3ed0f87658ee131cd3dcd18", "tree": "281ff6eb92a1408f5a39ef38a5dea5df20f8bed4", "parents": [ "ae95b1782b7a3ab9bbe46ae9ab31f48fb6ebe137" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 20 17:37:11 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "fix(nxp-tools): fix tool location path for byte_swape\n\nFix byte_swape tool\u0027s location.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I63856a8d62aeb5eb0b41b2b0dc671de96302aa1d\n" }, { "commit": "ae95b1782b7a3ab9bbe46ae9ab31f48fb6ebe137", "tree": "6ba6b36c37f1d08bc7fec129d556916f26f1e826", "parents": [ "1acfb983765e5db303a7caba7da8dcff22703528" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Jan 20 17:35:48 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "fix(nxp-qspi): fix include path for QSPI driver\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: If9322cf2646d3be3391445cb72d338c2d20117a6\n" }, { "commit": "1acfb983765e5db303a7caba7da8dcff22703528", "tree": "fe388b6f05fba99e60deae044f8eca3451c52b4c", "parents": [ "24ce8d134a1fe4c4667c36f7914433ffdcb2c0c9" ], "author": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Thu Feb 10 10:39:56 2022 +0800" }, "committer": { "name": "Jiafei Pan", "email": "Jiafei.Pan@nxp.com", "time": "Tue Feb 15 08:59:58 2022 +0800" }, "message": "build(changelog): add new scopes for NXP layerscape platforms\n\n1. Add scopes for ls1046a and related boards: ls1046ardb,\nls1046aqds, ls1046afwry.\n2. Add new scope for NXP QSPI driver.\n3. Add new scope for NXP tools.\n\nSigned-off-by: Jiafei Pan \u003cJiafei.Pan@nxp.com\u003e\nChange-Id: I68ef7dd25628b393dbfbb8dbf59d5185945ea61c\n" }, { "commit": "2f452974335d3d000b1e638bd21a6d02a8f5ec22", "tree": "4adb71340df275435be4a22c47bde973acf4d064", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Mon Feb 14 18:27:32 2022 +0100" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Feb 15 01:16:48 2022 +0200" }, "message": "docs(a3k): fix information about SATA GPT booting\n\nArmada 3720 BootROM searches for GPT partition with partition type GUID\n6828311A-BA55-42A4-BCDE-A89BB5EDECAE and completely ignores GPT\npartition name. It does not check for \"MARVELL BOOT PARTITION\".\n\nThis fact is incorrectly documented even in official Marvell Armada 3700\nFunctional Specification.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I35279f39de2d12148fc16f2730a9a074dc0b58eb\n" }, { "commit": "c2eba07c47f8d831629104eeffcec11ed7d3b0a5", "tree": "cf4ba5f7fda600a32dd820d73e8d1f59c77e2092", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Thu Feb 03 17:22:37 2022 +0100" }, "committer": { "name": "Federico Recanati", "email": "federico.recanati@arm.com", "time": "Mon Feb 14 13:34:49 2022 +0100" }, "message": "feat(spm): add FFA_MSG_SEND2 forwarding in SPMD\n\nAdd FF-A v1.1 indirect messaging ABI FFA_MSG_SEND2 to SPMD to allow\nmessage forwarding across normal/secure worlds.\n\nChange-Id: I074fbd2e4d13893925f987cee271d49da3aaf64b\nSigned-off-by: Federico Recanati \u003cfederico.recanati@arm.com\u003e\n" }, { "commit": "854d1c103a9b73bbde7ef1b89b06b29e3cc053bb", "tree": "dba8fc8aa75c2d2edbb5738c5b27c885192a9676", "parents": [ "0260eb0d15adab03c63dcda908fe6ac015da129c" ], "author": { "name": "Arpita S.K", "email": "Arpita.S.K@arm.com", "time": "Wed Oct 13 14:49:26 2021 +0530" }, "committer": { "name": "Emekcan Aras", "email": "Emekcan.Aras@arm.com", "time": "Mon Feb 14 10:34:46 2022 +0000" }, "message": "feat(corstone1000): made changes to accommodate 3MB for optee\n\nThese changes are required to accommodate 3MB for OP-TEE and this\nis required for SP\u0027s part of optee\nAdded size macro\u0027s for better readability of the code\nMoved uboot execution memory from CVM to DDR\n\nChange-Id: I16657c6e336fe7c0fffdee1617d10af8a2c76732\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\nSigned-off-by: Arpita S.K \u003cArpita.S.K@arm.com\u003e\n" }, { "commit": "0260eb0d15adab03c63dcda908fe6ac015da129c", "tree": "c1eace113aa53d9dfaf0817b4e37a0bd688590a4", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Vishnu Banavath", "email": "vishnu.banavath@arm.com", "time": "Wed Jan 19 18:43:12 2022 +0000" }, "committer": { "name": "Emekcan Aras", "email": "Emekcan.Aras@arm.com", "time": "Mon Feb 14 10:32:16 2022 +0000" }, "message": "build(corstone1000): rename diphda to corstone1000\n\ndiphda platform is now being renamed to corstone1000.\nThese changes are to replace all the instances and traces\nof diphda corstone1000.\n\nChange-Id: I330f3a112d232b99b4721b6bf0236253b068dbba\nSigned-off-by: Arpita S.K \u003cArpita.S.K@arm.com\u003e\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\n" }, { "commit": "10bf3d7ca3994f0abc119a0773f8023e19acafd1", "tree": "ed9342252fcd32df4ff40dd67faa01b7675bb206", "parents": [ "cb2c4f93c18b948fbfde9d50ab7d30362be0e00a" ], "author": { "name": "Ying-Chun Liu (PaulLiu)", "email": "paulliu@debian.org", "time": "Mon Nov 15 16:13:10 2021 +0800" }, "committer": { "name": "Ying-Chun Liu (PaulLiu)", "email": "paulliu@debian.org", "time": "Mon Feb 14 02:36:35 2022 +0800" }, "message": "docs(imx8m): update for measured boot for imx8mm\n\nSigned-off-by: Ying-Chun Liu (PaulLiu) \u003cpaulliu@debian.org\u003e\nChange-Id: Ib313dc1ffac2fc5d04e0779c9f059236a71e65e7\n" }, { "commit": "cb2c4f93c18b948fbfde9d50ab7d30362be0e00a", "tree": "dafba450529a0528b0350cce6638b1330cd4f543", "parents": [ "b22f18e36530e9b67d0b33a61f2c89fe85345e49" ], "author": { "name": "Ying-Chun Liu (PaulLiu)", "email": "paulliu@debian.org", "time": "Wed Oct 06 09:27:00 2021 +0800" }, "committer": { "name": "Ying-Chun Liu (PaulLiu)", "email": "paulliu@debian.org", "time": "Mon Feb 14 02:36:35 2022 +0800" }, "message": "feat(plat/imx/imx8m/imx8mm): add support for measured boot\n\nAdd helper functions to generate event log for imx8mm\nwhen MEASURED_BOOT\u003d1.\n\nSigned-off-by: Ying-Chun Liu (PaulLiu) \u003cpaulliu@debian.org\u003e\nChange-Id: Ifc947d749055787fbda0b39170aa2eb8865b7802\n" }, { "commit": "b22f18e36530e9b67d0b33a61f2c89fe85345e49", "tree": "4f61145c92159e28955d62315238fbaef2cd4a0b", "parents": [ "2ba3085b8c6b4fae6e0a25466790cca1d317233b", "410c925ab31693dc74d654ff9167c8eed3ec5a62" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Feb 11 18:51:25 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 11 18:51:25 2022 +0100" }, "message": "Merge changes from topic \"snprintf-fix\" into integration\n\n* changes:\n fix(libc): snprintf: include stdint.h\n fix(libc): limit snprintf radix value\n fix(libc): fix snprintf corner cases\n" }, { "commit": "2ba3085b8c6b4fae6e0a25466790cca1d317233b", "tree": "a52c25c859dc3fcc99801e93e7ade4f85ce36d42", "parents": [ "2165f97e886fbc4eefe81961dfd7e5c44f82c6e1", "992d97c45faeaee7b6a82089374addcc0dc74344" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Feb 11 17:57:26 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 11 17:57:26 2022 +0100" }, "message": "Merge \"refactor(measured-boot): cleanup Event Log makefile\" into integration" }, { "commit": "56e8952fc073761be4530be3b5f235ff24caba80", "tree": "7f9fe9a9909d4ba6b2fc52049e2ebf399a427a1b", "parents": [ "2165f97e886fbc4eefe81961dfd7e5c44f82c6e1" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Feb 09 14:03:35 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Feb 11 17:43:31 2022 +0100" }, "message": "refactor(stm32mp1): move PIE flag to SP_min\n\nThe PIE compilation is used only for BL32, move the ENABLE_PIE to\nsp_min-stm32mp1.mk file. Override PIE flags, as sp_min.mk file is\nincluded after the flags are set in Makefile.\nThe BL2_IN_XIP_MEM was added for a feature not yet upstreamed.\nIt is then removed from platform.mk file.\n\nChange-Id: If055e51e0f160f99cd4e4cf68ca718d4d693119c\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nSigned-off-by: Nicolas Toromanoff \u003cnicolas.toromanoff@foss.st.com\u003e\n" }, { "commit": "2165f97e886fbc4eefe81961dfd7e5c44f82c6e1", "tree": "9641c3bf08140966102b0483f3c87b6aa3ad5f10", "parents": [ "92bebd836ab82c79afcf462fc5dc19bc81134bdb", "1af59c457010e6e3e6536752736eb02115bca543" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Feb 11 17:19:55 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 11 17:19:55 2022 +0100" }, "message": "Merge \"feat(common): add SZ_* macros\" into integration" }, { "commit": "92bebd836ab82c79afcf462fc5dc19bc81134bdb", "tree": "4e3c7ba88fa260fcad4a02e6c76f17ce14082b90", "parents": [ "f22182f8e4f1d92dc67fffc0b1f9e786021e1f60", "c870188d2791b2c83118a16f3e537e8104017cc0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Feb 11 17:05:23 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 11 17:05:23 2022 +0100" }, "message": "Merge \"refactor(stm32mp1): update tamp_bkpr return type\" into integration" }, { "commit": "f22182f8e4f1d92dc67fffc0b1f9e786021e1f60", "tree": "c9f0cb3b4c70e3a075e3c24fab5aaaf2db0809e6", "parents": [ "cbadfe694207c9bf0c8f0e639b56666f47a4c712", "a092825d1f3e6ddc10e297219ceb65ab08457468" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Feb 11 15:37:04 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 11 15:37:04 2022 +0100" }, "message": "Merge \"docs(contribution-guidelines): updated the build configuration section\" into integration" }, { "commit": "a092825d1f3e6ddc10e297219ceb65ab08457468", "tree": "078dce69f0502b0970904df32bbffb264fe3c7a3", "parents": [ "e0a6a512b51558b64eb500e6b731e4c743050af2" ], "author": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Tue Feb 08 14:18:24 2022 +0000" }, "committer": { "name": "Jayanth Dodderi Chidanand", "email": "jayanthdodderi.chidanand@arm.com", "time": "Fri Feb 11 12:16:20 2022 +0000" }, "message": "docs(contribution-guidelines): updated the build configuration section\n\nAdded a couple of sub-sections (Coverity Scan and Test Configuration)\nunder \"Add build configuration\" to update the patch owners on the\nsections they need to be aware of while introducing new source files.\n\nSigned-off-by: Jayanth Dodderi Chidanand \u003cjayanthdodderi.chidanand@arm.com\u003e\nChange-Id: I84adb182f9633863aac864df43578249c2269c1e\n" }, { "commit": "c870188d2791b2c83118a16f3e537e8104017cc0", "tree": "817045a1e8a1e7aeab4a98a60e2bcda0466c8bb7", "parents": [ "cbadfe694207c9bf0c8f0e639b56666f47a4c712" ], "author": { "name": "Nicolas Toromanoff", "email": "nicolas.toromanoff@foss.st.com", "time": "Wed Feb 09 12:26:31 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Feb 11 11:05:30 2022 +0100" }, "message": "refactor(stm32mp1): update tamp_bkpr return type\n\ntamp_bkpr() returns a register address. So use uintptr_t instead of\nuin32_t.\n\nSigned-off-by: Nicolas Toromanoff \u003cnicolas.toromanoff@foss.st.com\u003e\nChange-Id: I5eddfa525465313dadfec18d128248a968ba74e2\n" }, { "commit": "410c925ab31693dc74d654ff9167c8eed3ec5a62", "tree": "0040ef88be95f17f0b650cf2f01d61f16147a615", "parents": [ "b30dd4030dcef950eac05393013ee019c3cb3205" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Jan 27 17:47:55 2022 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Feb 10 16:33:32 2022 +0000" }, "message": "fix(libc): snprintf: include stdint.h\n\nThe snprintf code uses the uintptr_t type, which is defined in stdint.h.\nWe do not include this header explicitly, but get the definition\nindirectly through some other header doing so.\n\nHowever this breaks when snprintf is compiled in isolation (for instance\nfor unit-testing), so let\u0027s add this #include to make things right.\n\nChange-Id: I1299767ee482f5cf1af30c4df2e8f7e596969b41\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "b30dd4030dcef950eac05393013ee019c3cb3205", "tree": "aabaeecd55240d1c74177f1eefa7e702f1f1e3ce", "parents": [ "c1f5a0925ddf84981d9e176d146bfddb48eb45d1" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Jan 24 18:16:10 2022 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Thu Feb 10 16:33:32 2022 +0000" }, "message": "fix(libc): limit snprintf radix value\n\nIn our unsigned_num_print() function we first print the integer into a\nlocal buffer, then put this through alignment and padding and output the\nresult. For this we use a local buffer, sized by the maximum possible\nlength of the largest possible number.\n\nHowever this assumes that the radix is not smaller than 10, which is\nindeed the smallest value we pass into this static function at the\nmoment. To prevent accidents in the future, should we add support for\nother radices, add an assert to enforce our assumption.\n\nUnfortunately this cannot be a static assert (CASSERT), since the\ncompiler is not smart enough to see that the argument is always coming\nfrom a literal.\n\nChange-Id: Ic204462600d9f4c281d899cf9f2c698a0a33a874\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "cbadfe694207c9bf0c8f0e639b56666f47a4c712", "tree": "2be4ef34753d84659ea6ce6c0cb371e32a61a792", "parents": [ "94ac06ed5c14842a252500e4d558f070babffdff", "f20eb893a072bb9b404eedb886e8c65fe76ffb45" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Feb 10 16:11:10 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 10 16:11:10 2022 +0100" }, "message": "Merge \"feat(spe): add support for FEAT_SPEv1p2\" into integration" }, { "commit": "f20eb893a072bb9b404eedb886e8c65fe76ffb45", "tree": "2be4ef34753d84659ea6ce6c0cb371e32a61a792", "parents": [ "94ac06ed5c14842a252500e4d558f070babffdff" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Fri Dec 31 16:08:51 2021 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Feb 10 09:30:13 2022 +0000" }, "message": "feat(spe): add support for FEAT_SPEv1p2\n\nAllow access to PMSNEVFR_EL1 register at NS-EL1 or NS-EL2 when\nFEAT_SPEv1p2 is implemented.\n\nChange-Id: I44b1de93526dbe9c11fd061d876371a6c0e6fa9c\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "94ac06ed5c14842a252500e4d558f070babffdff", "tree": "6285d017022cdcdc2e73de7025394d8b35544f48", "parents": [ "acd0e9bf64c4d270bc632eca99aa54a54d0e071a", "4d4821569d15c3411a6fe5dcfc791d6b28c6d6a9" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Feb 09 15:05:47 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Feb 09 15:05:47 2022 +0100" }, "message": "Merge changes from topic \"db/exception_pstate\" into integration\n\n* changes:\n test(el3-runtime): dit is retained on world switch\n fix(el3-runtime): set unset pstate bits to default\n refactor(el3-runtime): add prepare_el3_entry func\n" }, { "commit": "1af59c457010e6e3e6536752736eb02115bca543", "tree": "f5cf7c2d83787d494f12dddc3c302a52b0417673", "parents": [ "acd0e9bf64c4d270bc632eca99aa54a54d0e071a" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 08 10:21:58 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 08 10:49:36 2022 +0100" }, "message": "feat(common): add SZ_* macros\n\nAdd the SZ_* macros from 32 to 2G.\nThis allows removing some defines in raw NAND driver\nand STM32MP1 boot device selection code.\n\nChange-Id: I3c4d4959b0f43e785eeb37a43d03b2906b7fcfbc\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nSigned-off-by: Vishnu Banavath \u003cvishnu.banavath@arm.com\u003e\nSigned-off-by: Arpita S.K \u003cArpita.S.K@arm.com\u003e\n" }, { "commit": "c1f5a0925ddf84981d9e176d146bfddb48eb45d1", "tree": "01cf7f05a86412a54c19024bd69aafb3f22766fd", "parents": [ "e0a6a512b51558b64eb500e6b731e4c743050af2" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue Dec 21 12:35:54 2021 +0000" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Mon Feb 07 16:14:21 2022 +0000" }, "message": "fix(libc): fix snprintf corner cases\n\nThe number formatting routine in snprintf was trying to be clever with\nthe buffer handling, but tripped over its own feet: snprintf() users\nexpect output to be emitted, even if not everything fits into the\nbuffer. The current code gives up completely when the buffer is too\nsmall.\n\nFix those issues and simplify the code on the way, by consequently using\nthe CHECK_AND_PUT_CHAR() macro, which both checks for the buffer size\ncorrectly, but also keeps track of the number of should-be-printed\ncharacters for the return value.\n\nChange-Id: Ifd2b03b9a73f9279abed53081a2d88720ecbdbc1\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "acd0e9bf64c4d270bc632eca99aa54a54d0e071a", "tree": "c2989922f9ca9ea0f1f8397600eb37407097ae5c", "parents": [ "0e1c3f8cb7c46ee5507e317044680d60b5c42dec", "cd3ea90b200534b8c9d81619731c9ce198478a3c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 07 16:41:38 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 07 16:41:38 2022 +0100" }, "message": "Merge \"fix(ufs): don\u0027t zero out the write buffer\" into integration" }, { "commit": "0e1c3f8cb7c46ee5507e317044680d60b5c42dec", "tree": "92d30c3fb297c5fdc7100bec6078b328f4c437ee", "parents": [ "0e38ff2ac6b62b7307ceef7b049d86406c0d3322", "efeb43808d2e3ed23e1d51d5e86460db92971e96" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Feb 07 16:24:39 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Feb 07 16:24:39 2022 +0100" }, "message": "Merge \"feat(rdn2): add board support for rdn2cfg2 variant\" into integration" }, { "commit": "8a855bd24329e081cf13a257c7d2dc3ab4e5dcca", "tree": "e1f8f4128712d7f69980b2b5b05473e669aaaedb", "parents": [ "cfe1a8f7123f0dc8376b2075cc6e8e32b13739b2" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 03:11:44 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 23:36:44 2022 -0600" }, "message": "fix(errata): workaround for Cortex-A710 erratum 2136059\n\nCortex-A710 erratum 2136059 is a Cat B erratum that applies to\nrevisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.\nThe workaround is to set CPUACTLR5_EL1[44] to 1 which will cause\nthe CPP instruction to invalidate the hardware prefetcher state\ntrained from any EL.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775101/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc\n" }, { "commit": "cfe1a8f7123f0dc8376b2075cc6e8e32b13739b2", "tree": "ee7cb7d9d84ed9c3d0fc75313a526ad13c2a217d", "parents": [ "4dff7594f94f1e788aef709cc5b3d079693b6242" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 02:32:54 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 02:32:54 2022 -0600" }, "message": "fix(errata): workaround for Cortex-A710 erratum 2267065\n\nCortex-A710 erratum 2267065 is a Cat B erratum that applies to\nrevisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.\nThe workaround is to set CPUACTLR_EL1[22] to 1\u0027b1. Setting\nCPUACTLR_EL1[22] will cause the CFP instruction to invalidate\nall branch predictor resources regardless of context.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775101/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ia9085aaf9b2b6a2b25d03ab36bd3774839fac9aa\n" }, { "commit": "4dff7594f94f1e788aef709cc5b3d079693b6242", "tree": "756b007c5714517aa97cb518ef118a7b43d2eb98", "parents": [ "c060b5337a43cd42f55b99d83096bb44b51b5335" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 01:29:31 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 01:44:47 2022 -0600" }, "message": "fix(errata): workaround for Cortex-X2 erratum 2216384\n\nCortex-X2 erratum 2216384 is a Cat B erratum that applies to\nrevisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.\nThe workaround is to set CPUACTLR5_EL1[17] to 1\u0027b1 followed by\napplying an instruction patching sequence.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775100/latest\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I3c216161678887c06a28c59644e784e0c7d37bab\n" }, { "commit": "c060b5337a43cd42f55b99d83096bb44b51b5335", "tree": "347f213f60bbf932d13827bc5eefb35a34d4a617", "parents": [ "e7ca4433fa591233e7e2912b689ab56e531f9775" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jan 20 00:42:05 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 01:44:15 2022 -0600" }, "message": "fix(errata): workaround for Cortex-X2 errata 2081180\n\nCortex-X2 erratum 2081180 is a Cat B erratum present in r0p0, r1p0\nand r2p0 of the Cortex-X2 processor core.\n\nCortex-X2 SDEN: https://developer.arm.com/documentation/SDEN1775100\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I64bed2fd5b7e12932d6de2ae668786e689885188\n" }, { "commit": "e7ca4433fa591233e7e2912b689ab56e531f9775", "tree": "f11db3abadf772e599448ad140589fb2fc6c5e2a", "parents": [ "0586c41b3f2d52aae847b7212e7b0c7e19197ea2" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Jan 20 00:01:04 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sun Feb 06 01:43:39 2022 -0600" }, "message": "fix(errata): workaround for Cortex-X2 errata 2017096\n\nCortex-X2 erratum 2017096 is a Cat B erratum that applies to\nrevisions r0p0, r1p0 \u0026 r2p0. The workaround is to set CPUECLTR_EL1[8]\nto 1 which disables store issue prefetching.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775100\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05\n" }, { "commit": "0e38ff2ac6b62b7307ceef7b049d86406c0d3322", "tree": "3740fbe352a6f9b074dce54e9bfbaefa495281cf", "parents": [ "bfc231c1643bb0903eef5fc8f6af7bfbd08e9242", "812daf916c9c977a4f6d7d745d22b90c8492fc71" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Feb 04 16:57:15 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 04 16:57:15 2022 +0100" }, "message": "Merge \"feat(st): update the security based on new compatible\" into integration" }, { "commit": "bfc231c1643bb0903eef5fc8f6af7bfbd08e9242", "tree": "6ac24f75790196459b3fcea541bb085a90a2bce4", "parents": [ "e0a6a512b51558b64eb500e6b731e4c743050af2", "c768b2b22f4fb16cf8be8b4815a1984b29918c20" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Feb 04 16:56:32 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Feb 04 16:56:32 2022 +0100" }, "message": "Merge \"feat(st): add early console in BL2\" into integration" }, { "commit": "efeb43808d2e3ed23e1d51d5e86460db92971e96", "tree": "d24ef7dbbbaad65f48c29e87e2073d4c3a0821b0", "parents": [ "e0a6a512b51558b64eb500e6b731e4c743050af2" ], "author": { "name": "Aditya Angadi", "email": "aditya.angadi@arm.com", "time": "Mon Aug 09 09:38:58 2021 +0530" }, "committer": { "name": "Aditya Angadi", "email": "aditya.angadi@arm.com", "time": "Fri Feb 04 16:31:52 2022 +0530" }, "message": "feat(rdn2): add board support for rdn2cfg2 variant\n\nAdd board support for variant 2 of RD-N2 platform which is a four chip\nvariant with 4 cores on each chip. The \"CSS_SGI_PLATFORM_VARIANT\" value\nis 2 for multi-chip variant. The \"CSS_SGI_CHIP_COUNT_MACRO\" can be in\nthe range [1, 4] for multi-chip variant.\n\nSigned-off-by: Aditya Angadi \u003caditya.angadi@arm.com\u003e\nChange-Id: I6412106e80e2f17704c796226c2ee9fe808705ba\n" }, { "commit": "cd3ea90b200534b8c9d81619731c9ce198478a3c", "tree": "dc7dfd796d2ac3d1369e618ebe12f26e12639d11", "parents": [ "99026cff47e35b3f5abd68a19cba1a4fb683fdc4" ], "author": { "name": "Jorge Troncoso", "email": "jatron@google.com", "time": "Thu Feb 03 15:52:59 2022 -0800" }, "committer": { "name": "Jorge Troncoso", "email": "jatron@google.com", "time": "Thu Feb 03 15:52:59 2022 -0800" }, "message": "fix(ufs): don\u0027t zero out the write buffer\n\nPreviously ufs_write_blocks was memsetting the write buffer before\ncalling ufs_prepare_cmd, causing zeros to be written to UFS. This change\ndeletes the memset call so the original buffer contents get written to\nUFS.\n\nSigned-off-by: Jorge Troncoso \u003cjatron@google.com\u003e\nChange-Id: I3299f11b30e6d7d409408ce11a6759c88607ee18\n" }, { "commit": "e0a6a512b51558b64eb500e6b731e4c743050af2", "tree": "8eca4346a6601e4a51f3757eea6cc1489576d81e", "parents": [ "99026cff47e35b3f5abd68a19cba1a4fb683fdc4", "a758c0b65c6730fb07846899d6436ba257484d34" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Feb 03 22:59:34 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Feb 03 22:59:34 2022 +0100" }, "message": "Merge changes from topic \"msm8916\" into integration\n\n* changes:\n feat(msm8916): allow booting secondary CPU cores\n feat(msm8916): setup hardware for non-secure world\n feat(gic): allow overriding GICD_PIDR2_GICV2 address\n feat(msm8916): initial platform port\n docs(msm8916): new port for Qualcomm Snapdragon 410\n" }, { "commit": "a758c0b65c6730fb07846899d6436ba257484d34", "tree": "8eca4346a6601e4a51f3757eea6cc1489576d81e", "parents": [ "af6447315c8534331513ca6b6556af661e0ba88b" ], "author": { "name": "Stephan Gerhold", "email": "stephan@gerhold.net", "time": "Wed Dec 01 20:04:44 2021 +0100" }, "committer": { "name": "Stephan Gerhold", "email": "stephan@gerhold.net", "time": "Thu Feb 03 15:19:26 2022 +0100" }, "message": "feat(msm8916): allow booting secondary CPU cores\n\nAdd support for the PSCI CPU_ON call to allow booting secondary CPU\ncores. On cold boot they need to be booted with a special register\nsequence. Also, the \"boot remapper\" needs to be configured to point to\nthe BL31_BASE, so the CPUs actually start executing BL31 after reset.\n\nChange-Id: I406c508070ccb046bfdefd51554f12e1db671fd4\nSigned-off-by: Stephan Gerhold \u003cstephan@gerhold.net\u003e\n" }, { "commit": "af6447315c8534331513ca6b6556af661e0ba88b", "tree": "0f5b659bd92d8821951cbd98b132c454f6cee881", "parents": [ "a7521bd5d887bfd69d99a55a81416e38ba9ebc97" ], "author": { "name": "Stephan Gerhold", "email": "stephan@gerhold.net", "time": "Wed Dec 01 20:03:33 2021 +0100" }, "committer": { "name": "Stephan Gerhold", "email": "stephan@gerhold.net", "time": "Thu Feb 03 15:19:26 2022 +0100" }, "message": "feat(msm8916): setup hardware for non-secure world\n\nBooting e.g. Linux in the non-secure world does not work with the\nmsm8916 port yet because essential hardware is not made available to\nthe non-secure world. Add more platform initialization to:\n\n - Initialize the GICv2 and mark secure interrupts.\n Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2\n register address in platform_def.h to avoid a failing assert()\n because of a (hardware) mistake in Qualcomm\u0027s GICv2 implementation.\n\n - Make a timer frame available to the non-secure world.\n The \"Qualcomm Timer\" (QTMR) implements the ARM generic timer\n specification, so the standard defines (CNTACR_BASE etc)\n can be used.\n\n - Make parts of the \"APCS\" register region available to the\n non-secure world, e.g. for CPU frequency control implemented\n in Linux.\n\n - Initialize a platform-specific register to route all SMMU context\n bank interrupts to the non-secure interrupt pin, since all control\n of the SMMUs is left up to the non-secure world for now.\n\nChange-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d\nSigned-off-by: Stephan Gerhold \u003cstephan@gerhold.net\u003e\n" }, { "commit": "a7521bd5d887bfd69d99a55a81416e38ba9ebc97", "tree": "3920525caad56ed5538244071a1caa4bd292a271", "parents": [ "dddba19a6a3cb7a1039beaffc3169c4eb3291afd" ], "author": { "name": "Stephan Gerhold", "email": "stephan@gerhold.net", "time": "Wed Dec 01 20:02:22 2021 +0100" }, "committer": { "name": "Stephan Gerhold", "email": "stephan@gerhold.net", "time": "Thu Feb 03 15:19:22 2022 +0100" }, "message": "feat(gic): allow overriding GICD_PIDR2_GICV2 address\n\nOlder Qualcomm SoCs seem to have a custom Qualcomm implementation of\nthe GICv2 specification. It\u0027s mostly compliant but unfortunately it\nlooks like a mistake was made with the GICD_PIDR registers. PIDR2 is\ndefined to be at offset 0xFE8, but the Qualcomm implementation has it\nat 0xFD8.\n\nIt looks like the entire PIDR0-3/4-7 block is swapped compared to the\nARM implementation: PIDR0 starts at 0xFD0 (instead of 0xFE0)\nand PIDR4 starts at 0xFE0 (instead of 0xFD0).\n\nActually this only breaks a single assert in gicv2_main.c that checks\nthe GIC version: assert((gic_version \u003d\u003d ARCH_REV_GICV2) ...\nIn release mode everything seems to work correctly.\n\nTo keep the code generic, allow affected platforms to override the\nGICD_PIDR2_GICV2 register address in platform_def.h. Since this header\nis typically included very early (e.g. from assert.h), add an #ifndef\nso the definitions from platform_def.h takes priority.\n\nChange-Id: I2929a8c1726f8d751bc28796567eb30b81eca2fe\nSigned-off-by: Stephan Gerhold \u003cstephan@gerhold.net\u003e\n" }, { "commit": "4d4821569d15c3411a6fe5dcfc791d6b28c6d6a9", "tree": "31680f82bf1cff9f355ac12c86d0e60fd1293147", "parents": [ "7d33ffe4c116506ed63e820d5b6edad81680cd11" ], "author": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Fri Oct 22 11:37:34 2021 +0100" }, "committer": { "name": "Daniel Boulby", "email": "daniel.boulby@arm.com", "time": "Thu Feb 03 11:33:55 2022 +0000" }, "message": "test(el3-runtime): dit is retained on world switch\n\nAdd tsp service to check the value of the PSTATE DIT bit is as\nexpected and toggle it\u0027s value. This is used to ensure that\nthe DIT bit is maintained during a switch from the Normal to\nSecure worlds and back.\n\nChange-Id: I4e8bdfa6530e5e75925c0079d4fa2795133c5105\nSigned-off-by: Daniel Boulby \u003cdaniel.boulby@arm.com\u003e\n" } ], "next": "7d33ffe4c116506ed63e820d5b6edad81680cd11" }