)]}' { "log": [ { "commit": "d38eaf99d327bc1400f51c87b6d8a2f92cd828c6", "tree": "2b321cc1b448890df3ccbbb037da4b7ab2faf865", "parents": [ "3b99ab6e370a01caec14bc5422a86001eaf291b8" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 25 17:08:10 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): updates for STM32MP13 device tree compilation\n\nAdd stm32mp13_bl2.dtsi files.\nUpdate compilation variables for STM32MP13.\n\nChange-Id: Ia3aa3abfe09c04c1a57541e565c212aa094e285c\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "3b99ab6e370a01caec14bc5422a86001eaf291b8", "tree": "8022e5d43ce22d46e7f807675983f4edad678c4d", "parents": [ "24d3da76d221390bb47d501c2ed77a1a7d2b42e7" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Feb 25 15:14:52 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1-fdts): add DT files for STM32MP13\n\nSTM32MP13 is a single Cortex-A7 CPU, without co-processor.\nAs for STM32MP15x SoC family, STM32MP15x SoCs come with different\nfeatures, depending on SoC version. Each peripheral node is created.\nSome are left empty for the moment , and will be filled later on.\n\nChange-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "24d3da76d221390bb47d501c2ed77a1a7d2b42e7", "tree": "1f70e0f0276dfa0868ee0125478d8b8fa2fa2d9a", "parents": [ "296ac8012b77ea84079b38cc60ee786a5f91857f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Oct 16 18:59:33 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(dt-bindings): add TZC400 bindings for STM32MP13\n\nAnd new file stm32mp13-tzc400.h is created for STM32MP13.\n\nChange-Id: I18d6aa443d07dc42c0fff56fefb2a47632a2c0e6\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "296ac8012b77ea84079b38cc60ee786a5f91857f", "tree": "7dde9a1b48ea5eaa52585e74188ed2486435220c", "parents": [ "fca10a8f1b47231ef92634a0adf1a26cbfc97c2a" ], "author": { "name": "Nicolas Toromanoff", "email": "nicolas.toromanoff@st.com", "time": "Wed Feb 03 16:52:03 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): add \"Boot mode\" management for STM32MP13\n\nAdd new APIs to enter and exit \"boot mode\".\n\nIn this mode a potential tamper won\u0027t block access or reset\nthe secure IPs needed while boot, without this mode a dead\nlock may occurs.\n\nChange-Id: Iad60d4a0420ec125b842a285f73a20eb54cd1828\nSigned-off-by: Nicolas Toromanoff \u003cnicolas.toromanoff@st.com\u003e\n" }, { "commit": "fca10a8f1b47231ef92634a0adf1a26cbfc97c2a", "tree": "8f6bbe785f800e31dd6190642fd5d1d534b01745", "parents": [ "3331d3637c295993a78f22afe7463cf1c334d329" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 12 15:52:19 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): manage HSLV on STM32MP13\n\nOn STM32MP13, the high speed mode for pads in low voltage is different\nfrom STM32MP15. Each peripheral supporting the feature has its own\nregister.\nSpecial care is taken for SDMMC peripherals. The HSLV mode is enabled\nonly if the max voltage for the pads is lower or equal to 1.8V.\n\nChange-Id: Id94d2cca17dd4aca4d764230a643b2bb9a5f3342\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "3331d3637c295993a78f22afe7463cf1c334d329", "tree": "e3eda27ace49c5283a100d57814824f94b777f90", "parents": [ "6481a8f1e045ac80f0325b8bfe7089ba23deaf7b" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 20 14:10:57 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): add sdmmc compatible in platform define\n\nAdd DT_SDMMC2_COMPAT define in stm32mp1_def.h file in platform.\nIt allows the use of the compatible in platform code.\n\nChange-Id: I535ad67dd133bab59cf81881adaef42d8e88632c\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "6481a8f1e045ac80f0325b8bfe7089ba23deaf7b", "tree": "91d79a01208797207ffdff2b78a92cb438749f7d", "parents": [ "8e07ab5f705b213af28831f7c3e9878154e07df0" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 20 14:08:32 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(st-sdmmc2): allow compatible to be defined in platform code\n\nPut DT_SDMMC2_COMPAT under #ifndef. Keep the default value if it is not\ndefined in platform code.\n\nChange-Id: I611baaf1fc622d33e655ee2c78d9c287baaa6a67\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "8e07ab5f705b213af28831f7c3e9878154e07df0", "tree": "d56e7eafd30ceb6eb57b8f9ccdcd9b5f2f84875f", "parents": [ "ffd1b889225a8aec124df9e330f41dc638fd7180" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Nov 17 15:27:58 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): update IO compensation on STM32MP13\n\nOn STM32MP13, two new SD1 and SD2 IO compensations cells are added,\nfor SDMMC1 and SDMMC2. They have to be managed the same way as the\nmain compensation cell.\n\nChange-Id: Ib7aa648d65fc98e1613bfb46b0e7dd568fd21002\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "ffd1b889225a8aec124df9e330f41dc638fd7180", "tree": "fd2d930aed9ab99dac68206ae53e74f8360181df", "parents": [ "5278ec3faf2010fd6aea1d8cd4294dd229c5c21d" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 18 10:39:52 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): call pmic_voltages_init() in platform init\n\nThe nominal voltage for VDDCPU when Cortex-A7 runs at 650MHz is 1.25V\non STM32MP13. VDDCORE should be set at 1.25V as well.\nThis is necessary, as the PMIC values in its NVMEM are 1.2V.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I3c24fe4cd68c7bf143cf9318ab38a15d6d41b5d2\n" }, { "commit": "5278ec3faf2010fd6aea1d8cd4294dd229c5c21d", "tree": "9e1ba03e1e480a86b19acba9b1455eb9ab0a76be", "parents": [ "1c37d0c1d378769249c797de5b13d73cf6f17a53" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Jan 18 15:49:42 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(st-pmic): add pmic_voltages_init() function\n\nThis new function pmic_voltages_init() is used to set the minimum value\nfor STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved\nfrom device tree.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Ibbe237cb5dccc1fddf92e07ffd3955048ff82075\n" }, { "commit": "1c37d0c1d378769249c797de5b13d73cf6f17a53", "tree": "536bf20f030eeda4fefbad053489cda07c5d4cbf", "parents": [ "d59b9d53b9cfb2443575c62c6716eb5508374a7b" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Thu Nov 26 09:57:09 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): update CFG0 OTP for STM32MP13\n\nThis field is now declared on the 10 LSB bits on STM32MP13.\nSeveral possible values are specified in the Reference Manual, and\nindicate an open or closed device. Other values lead to a system panic.\n\nChange-Id: I697124a21db66a56e7e223d601aa7cf44bb183c4\nSigned-off-by: Nicolas Le Bayon \u003cnicolas.le.bayon@st.com\u003e\n" }, { "commit": "d59b9d53b9cfb2443575c62c6716eb5508374a7b", "tree": "0c3daa91885cfefcfb9c0b2e93021d37d2278cfd", "parents": [ "9be88e75c198b08c508d8e470964720a781294b3" ], "author": { "name": "Patrick Delaunay", "email": "patrick.delaunay@st.com", "time": "Mon Sep 14 14:50:40 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): usb descriptor update for STM32MP13\n\nUpdate USB and DFU descriptor used for STM32MP13x\n\nSigned-off-by: Patrick Delaunay \u003cpatrick.delaunay@st.com\u003e\nChange-Id: I6e8111d279f49400a72baa12ff39f140d97e1c70\n" }, { "commit": "9be88e75c198b08c508d8e470964720a781294b3", "tree": "30fc1178e11fe85d89e3e16813cc3bf4ce1726e6", "parents": [ "1b8898eb32c3872a34fc59f4216736f23af0c6ea" ], "author": { "name": "Gabriel Fernandez", "email": "gabriel.fernandez@st.com", "time": "Wed Mar 11 11:30:34 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(st-clock): add clock driver for STM32MP13\n\nAdd new clock driver for STM32MP13. Split the include file to manage\neither STM32MP13 or STM32MP15.\n\nChange-Id: Ia568cd12b1d5538809204f0fd2224d51e5d1e985\nSigned-off-by: Gabriel Fernandez \u003cgabriel.fernandez@st.com\u003e\n" }, { "commit": "1b8898eb32c3872a34fc59f4216736f23af0c6ea", "tree": "5a7f07ac43a3dabfbd306da1090f5611f7203e6e", "parents": [ "6512c3a62a4a7baaf32597284b242bc7172b7e26" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Mar 10 11:33:13 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(dt-bindings): add bindings for STM32MP13\n\nAdd dedicated clock and reset dt-bindings include files. The former\nfiles are renamed with stm32mp15, and the stm32mp1 file just\ndetermine through STM32MP13 or STM32MP15 flag which file to include.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I0db23996a3ba25f7c3ea920f16230b11cf051208\n" }, { "commit": "6512c3a62a4a7baaf32597284b242bc7172b7e26", "tree": "2c93f815dc5da8a2c692bb5bcdfe97ccdf29b311", "parents": [ "b7d0058a3a9153a3863cf76a6763ea751b3ab48d" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Apr 21 15:03:59 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 22 09:09:23 2022 +0100" }, "message": "feat(stm32mp1): get CPU info from SYSCFG on STM32MP13\n\nThe IDC register from DBGMCU is duplicated in SYSCFG. As SYSCFG is\nalways accessible, get chip ID and revision ID from there on STM32MP13.\n\nChange-Id: Ib0b6e8f68a2934a45ec0012f69db6c12a60adb17\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "b7d0058a3a9153a3863cf76a6763ea751b3ab48d", "tree": "1df66a23c5bb4c2bc40c0c8c595ec70809eeea4b", "parents": [ "225ce4822ccf2e7c7c1fca6cf3918d4399158613" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Oct 21 18:15:12 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): use only one filter for TZC400 on STM32MP13\n\nOn STM32MP13, there is only 1 DDR port, hence only 1 TZC400 filter.\n\nChange-Id: I4f6750022cdaf658cd209a4bf48a6cdb0717020e\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "225ce4822ccf2e7c7c1fca6cf3918d4399158613", "tree": "c73fdf2f3ef367c8b4e5aea67df30f47f1476d0e", "parents": [ "a5308745ee3ab3b77ca942052e60968bcc01340d" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@foss.st.com", "time": "Thu Apr 15 08:27:28 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): add a second fixed regulator\n\nIncrease the fixed regulator number that needs to be\n2 for STM32MP13.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@foss.st.com\u003e\nChange-Id: Ica990fe9a6494b76aed763d2d353f5234fed7cea\n" }, { "commit": "a5308745ee3ab3b77ca942052e60968bcc01340d", "tree": "66f393bb94bad710ebf09d5bcba4383a0ff7d8fd", "parents": [ "5f52eb15970e57d2777d114948fc1110e3dd3f6c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Apr 14 18:08:50 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): adaptations for STM32MP13 image header\n\nThe header must now include by default at least an extra padding\nheader, increasing the size of the header to 512 bytes (0x200).\nThis header will be placed at the end of SRAM3 by BootROM, letting\nthe whole SYSRAM to TF-A.\nThe boot context is now placed in SRAM2, hence this memory has to be\nmapped in BL2 MMU. This mapping is done for all SRAMs in a 2MB area.\n\nChange-Id: I50fcd43ecd0ba2076292b057566efe6809b9971a\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "5f52eb15970e57d2777d114948fc1110e3dd3f6c", "tree": "afc1c2b0fbb43d820cff9350461caf8c65b311c8", "parents": [ "52ac9983d67522b6b821391941c8b0d01fd68941" ], "author": { "name": "Lionel Debieve", "email": "lionel.debieve@st.com", "time": "Wed Apr 08 12:08:55 2020 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): update boot API for header v2.0\n\nAdd the new field for the new header v2.0.\nForce MP13 platform to use v2.0.\nRemoving unused fields in boot_api_context_t for STM32MP13.\n\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\nChange-Id: Iac81aad9a939c1f305184e335e0a907ac69071df\n" }, { "commit": "52ac9983d67522b6b821391941c8b0d01fd68941", "tree": "8646e2eb8e188bdd2d940ade7822a4f8eadcbba1", "parents": [ "30eea116cdd66b3fa1e1208e185eb7285a83d898" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 23 15:25:04 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): update IP addresses for STM32MP13\n\nAdd the IP addresses that are STM32MP13 and update the ones for\nwhich the base address has changed.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Iea71a491da36f721bfd3fbfb010177e2a6a57281\n" }, { "commit": "30eea116cdd66b3fa1e1208e185eb7285a83d898", "tree": "df53ef3d65d51f0cc619cbb272593f8f4ae03fb2", "parents": [ "ef0b8a6c1b1a0eab3626041f3168f82bdb410836" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Feb 12 15:38:34 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): add part numbers for STM32MP13\n\nAdd the new part numbers and adapt the functions that use them.\nThere is no package number in OTP as they all share the same GPIO\nbanks.\nThis part is then stubbed for STM32MP13.\n\nChange-Id: I13414326b140119aece662bf8d82b387dece0dcc\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "ef0b8a6c1b1a0eab3626041f3168f82bdb410836", "tree": "8636be7aff28f7506509f66de1ead1b138943fec", "parents": [ "4b031ab4c50d0b9f7127daa7f4eec634f39de970" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Aug 25 14:40:12 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13\n\nOn STM32MP13, the chip revision Z is 0x1001, contrary to STM32MP15,\nfor which it was 0x2001.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: If65482e824b169282abb5e26ca91e16ef7640b52\n" }, { "commit": "4b031ab4c50d0b9f7127daa7f4eec634f39de970", "tree": "46ca96506adbd3a1da0f90ffecb63ff790edf7ac", "parents": [ "7b48a9f3286b8f174acf8821fec48fd2e4771514" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Feb 05 16:24:21 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13\n\nThe backup register used on STM32MP15 to save the boot interface for\nthe next boot stage was 20. It is now saved in backup register 30\non STM32MP13.\n\nChange-Id: Ibd051ff2eca7202184fa428ed57ecd4ae7388bd8\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "7b48a9f3286b8f174acf8821fec48fd2e4771514", "tree": "a29a9b6aa093d81ea3ac7f3f401725eb14ef9b24", "parents": [ "111a384c90afc629e644e7a8284abbd4311cc6b3" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Feb 06 15:34:16 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): stm32mp_is_single_core() for STM32MP13\n\nSTM32MP13 is a single Cortex-A7 CPU, always return true in\nstm32mp_is_single_core() function.\n\nChange-Id: Icf36eaa887bdf314137eda07c5751cea8c950143\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "111a384c90afc629e644e7a8284abbd4311cc6b3", "tree": "2901bfb7eb0e2e5e3bd1254240542573c4fbd7af", "parents": [ "48ede6615168118c674288f2e4f8ee1b11d2fa02" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Feb 12 09:36:23 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): remove unsupported features on STM32MP13\n\n* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ.\n* STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1\n and reset from MCU traces\n* There is no MCU on STM32MP13. Put MCU security management\n under STM32MP15 flag.\n* The authentication feature is not supported yet on STM32MP13,\n put the code under SPM32MP15 flag.\n* On STM32MP13, the monotonic counter is managed in ROM code, keep\n the monotonic counter update just for STM32MP15.\n* SYSCFG: put registers not present on STM32MP13 under STM32MP15\n flag, as the code that manages them.\n* PMIC: use ldo3 during DDR configuration only for STM32MP15\n* Reset UART pins on USB boot is no more required.\n\nChange-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nSigned-off-by: Gabriel Fernandez \u003cgabriel.fernandez@st.com\u003e\n" }, { "commit": "48ede6615168118c674288f2e4f8ee1b11d2fa02", "tree": "bf93a0dd2e5f04364396670d4d7429703ad6d2e9", "parents": [ "bdec516ee862bfadc25a4d0c02a3b8d859c1fa25" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Feb 03 17:48:07 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): update memory mapping for STM32MP13\n\nSYSRAM is only 128KB and starts at 0x2FFE0000.\nSRAMs are added.\nBL2 code and DTB sizes are also reduced to fit in 128KB.\n\nChange-Id: I25da99ef5c08f8008ff00d38248d61b6045adad4\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "bdec516ee862bfadc25a4d0c02a3b8d859c1fa25", "tree": "8377b92a13903b3036066814d59871cac25da10b", "parents": [ "2d8886aceed613b9be25f20900914cacc8bb0fb9" ], "author": { "name": "Sebastien Pasdeloup", "email": "sebastien.pasdeloup-ext@st.com", "time": "Fri Dec 18 11:50:40 2020 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(stm32mp1): introduce new flag for STM32MP13\n\nSTM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no\nCortex-M4.\nThere is only one DDR port.\nSP_min is not supported, only OP-TEE can be used as monitor.\nSTM32MP13 uses the header v2.0 format for stm32image generation\nfor BL2.\n\nChange-Id: Ie5b0e3230c5e064fe96f3561fc5b3208914dea53\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\n" }, { "commit": "2d8886aceed613b9be25f20900914cacc8bb0fb9", "tree": "6c321a1f50280e83223068c295cb437689b3ff14", "parents": [ "815abebcc1658eccef55d8435c17e98eb64e7bda" ], "author": { "name": "Nicolas Le Bayon", "email": "nicolas.le.bayon@st.com", "time": "Mon Nov 18 17:13:42 2019 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Mon Mar 21 10:53:55 2022 +0100" }, "message": "feat(st): update stm32image tool for header v2\n\nThe stm32image tool is updated to manage new header v2.0 for BL2\nimages.\nAdd new structure for the header v2.0 management.\nAdapt to keep compatibility with v1.0.\nAdd the header version major and minor in the command line\nwhen executing the tool, as well as binary type (0x10 for BL2).\n\nChange-Id: I70c187e8e7e95b57ab7cfad63df314307a78f1d6\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nSigned-off-by: Lionel Debieve \u003clionel.debieve@st.com\u003e\n" }, { "commit": "815abebcc1658eccef55d8435c17e98eb64e7bda", "tree": "002294e1450be3a1acc132147c2d40cfeb8fa2fa", "parents": [ "38dd6b61ae2ae6ba49f425771c0b529f7dbc9b4a", "9b2510b69de26cc7f571731b415f6dec82669b6c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 18 15:55:39 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 18 15:55:39 2022 +0100" }, "message": "Merge changes from topic \"spectre_bhb\" into integration\n\n* changes:\n fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57\n fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72\n fix(fvp): disable reclaiming init code by default\n" }, { "commit": "9b2510b69de26cc7f571731b415f6dec82669b6c", "tree": "7e390dfaf479fdefd0432eb654d6fd2098acefe8", "parents": [ "be9121fd311ff48c94f3d90fe7efcf84586119e4" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Feb 23 23:45:50 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Fri Mar 18 01:01:34 2022 +0200" }, "message": "fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57\n\nThis patch applies CVE-2022-23960 workarounds for Cortex-A75,\nCortex-A73, Cortex-A72 \u0026 Cortex-A57. This patch also implements\nthe new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery\nhooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to\nenable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3\nis implemented for A57/A72 because some revisions are affected by both\nCVE-2022-23960 and CVE-2017-5715 and this allows callers to replace\nSMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details\nof SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification.\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c\n" }, { "commit": "be9121fd311ff48c94f3d90fe7efcf84586119e4", "tree": "e03acb68fbfdd7a0608856fc5448c0856c363486", "parents": [ "fdb9166b9494402eb2da7e0b004c121b322725e0" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Feb 15 23:24:51 2022 -0600" }, "committer": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Wed Mar 16 16:35:07 2022 -0500" }, "message": "fix(security): workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72\n\nImplements mitigation for Cortex-A72 CPU versions that support\nthe CSV2 feature(from r1p0). It also applies the mitigation for\nCortex-A57 CPU.\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I7cfcf06537710f144f6e849992612033ddd79d33\n" }, { "commit": "fdb9166b9494402eb2da7e0b004c121b322725e0", "tree": "7dcdd4eb478f1a90db3694585e93101eb481e93e", "parents": [ "fdbbd59e978489d3b502bdae63981a5cef8fa405" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 16 14:20:48 2022 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 16 14:20:48 2022 -0500" }, "message": "fix(fvp): disable reclaiming init code by default\n\nIn anticipation of Spectre BHB workaround mitigation patches, we\ndisable the RECLAIM_INIT_CODE for FVP platform. Since the spectre\nBHB mitigation workarounds inevitably increase the size of the various\nsegments due to additional instructions and/or macros, these segments\ncannot be fit in the existing memory layout designated for BL31 image.\nThe issue is specifically seen in complex build configs for FVP\nplatform. One such config has TBB with Dual CoT and test secure\npayload dispatcher(TSPD) enabled. Even a small increase in individual\nsegment size in order of few bytes might lead to build fails due to\nalignment requirements(PAGE_ALIGN to 4KB).\n\nThis is needed to workaround the following build failures observed\nacross multiple build configs:\n\naarch64-none-elf-ld.bfd: BL31 init has exceeded progbits limit.\n\naarch64-none-elf-ld.bfd: /work/workspace/workspace/tf-worker_ws_2/trusted_firmware/build/fvp/debug/bl31/bl31.elf section coherent_ram will not fit in region RAM\naarch64-none-elf-ld.bfd: BL31 image has exceeded its limit.\naarch64-none-elf-ld.bfd: region RAM overflowed by 4096 bytes\n\nChange-Id: Idfab539e9a40f4346ee11eea1e618c97e93e19a1\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "38dd6b61ae2ae6ba49f425771c0b529f7dbc9b4a", "tree": "f486be53f8642487ac6f69aa205d76954ff99926", "parents": [ "e58eb9d103f040a9a4c052b0b377c17d48b44c9e", "bb1768c67ea06ac466e2cdc7e5338c3d23dac79d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 16 15:41:31 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 16 15:41:31 2022 +0100" }, "message": "Merge \"fix(xilinx): fix coding style violations\" into integration" }, { "commit": "e58eb9d103f040a9a4c052b0b377c17d48b44c9e", "tree": "717ad66cf086327144c98a3ecf35f75dd2c1cc89", "parents": [ "02c6f36695e5c3bda35c8fa911480f5c79b73e5f", "e46e9df0d0e05f2aaee613fc4f697fcc8d79c0b3" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Mar 16 12:55:03 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 16 12:55:03 2022 +0100" }, "message": "Merge \"feat(mt8186): add DFD control in SiP service\" into integration" }, { "commit": "02c6f36695e5c3bda35c8fa911480f5c79b73e5f", "tree": "595b534450ffc2a87c377c365ab23ba297f8e8fb", "parents": [ "a5d15b4c2d98286f1030890e2d001b67b0030e9d", "30cdbe7043832f7bd96b40294ac062a8fc9c540f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Mar 16 12:37:17 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 16 12:37:17 2022 +0100" }, "message": "Merge \"fix(a3k): change fatal error to warning when CM3 reset is not implemented\" into integration" }, { "commit": "30cdbe7043832f7bd96b40294ac062a8fc9c540f", "tree": "e8303182bf88341b239c15b90de4c9f31a4ac52b", "parents": [ "29ba22e8eda2fee41e0b983233496eaf11f669b0" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Sat Mar 12 12:45:56 2022 +0100" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Wed Mar 16 11:42:47 2022 +0100" }, "message": "fix(a3k): change fatal error to warning when CM3 reset is not implemented\n\nThis allows TF-A\u0027s a3700_system_reset() function to try Warm reset\nmethod when CM3 reset method is not implemented by WTMI firmware.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I7303197373e1a8ca5a44ba0b1e90b48855d6c0c3\n" }, { "commit": "a5d15b4c2d98286f1030890e2d001b67b0030e9d", "tree": "8fc506ac1acda7b89b6cd8f255049b241076a1de", "parents": [ "fdbbd59e978489d3b502bdae63981a5cef8fa405", "a10a5cb609045de216c01111ec3fcf09a092da0b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 15 18:29:55 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 15 18:29:55 2022 +0100" }, "message": "Merge changes from topic \"spectre_bhb\" into integration\n\n* changes:\n fix(security): loop workaround for CVE-2022-23960 for Cortex-A76\n refactor(el3-runtime): change Cortex-A76 implementation of CVE-2018-3639\n" }, { "commit": "fdbbd59e978489d3b502bdae63981a5cef8fa405", "tree": "aacc7b00cfc34248f20e3f0cc4092af11a43140d", "parents": [ "29ba22e8eda2fee41e0b983233496eaf11f669b0", "64e04687d3b04e98c1f988d7fe77025c6dad2dfe" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 15 14:39:49 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 15 14:39:49 2022 +0100" }, "message": "Merge changes from topic \"revert-14286-uart_segregation-VURJFOWMTM\" into integration\n\n* changes:\n Revert \"feat(sgi): deviate from arm css common uart related defi...\"\n Revert \"feat(sgi): route TF-A logs via secure uart\"\n Revert \"feat(sgi): add page table translation entry for secure uart\"\n" }, { "commit": "29ba22e8eda2fee41e0b983233496eaf11f669b0", "tree": "7cbe49e951d208765e5100fe10d34ebec09039fd", "parents": [ "c5f9d99a7e43b11c87ea9b2a96ec5e628fbcd149", "1fe4a9d181ead0dcb2bc494e90552d3e7f0aaf4c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sat Mar 12 01:39:37 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Mar 12 01:39:37 2022 +0100" }, "message": "Merge \"fix(security): workaround for CVE-2022-23960\" into integration" }, { "commit": "64e04687d3b04e98c1f988d7fe77025c6dad2dfe", "tree": "7cdcd4e0e8b3ded4073fda4322bfdf9375aca56f", "parents": [ "162f7923f1a57646c86d4ba6ec41dab4837bc5eb" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 20:49:20 2022 +0100" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 21:49:20 2022 +0200" }, "message": "Revert \"feat(sgi): deviate from arm css common uart related defi...\"\n\nRevert submission 14286-uart_segregation\n\nReason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.\n\nReverted Changes:\nI8574b31d5:feat(sgi): add page table translation entry for se...\nI8896ae05e:feat(sgi): route TF-A logs via secure uart\nI39170848e:feat(sgi): deviate from arm css common uart relate...\n\nChange-Id: I28a370dd8b3a37087da621460eccc1acd7a30287\n" }, { "commit": "162f7923f1a57646c86d4ba6ec41dab4837bc5eb", "tree": "74237e61553f904dc87f573c4ce8fd2a761d095a", "parents": [ "6127767ae5416a453bf4e501e4737baca9c0d30c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 20:49:20 2022 +0100" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 21:49:20 2022 +0200" }, "message": "Revert \"feat(sgi): route TF-A logs via secure uart\"\n\nRevert submission 14286-uart_segregation\n\nReason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.\n\nReverted Changes:\nI8574b31d5:feat(sgi): add page table translation entry for se...\nI8896ae05e:feat(sgi): route TF-A logs via secure uart\nI39170848e:feat(sgi): deviate from arm css common uart relate...\n\nChange-Id: I7c488aed9fcb70c55686d705431b3fe017b8927d\n" }, { "commit": "6127767ae5416a453bf4e501e4737baca9c0d30c", "tree": "06991e03cfb60f7e4cac88688d67ff4cf29c0544", "parents": [ "33d10ac8bf134519f303fd7ce5fb5d583be2f515" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 20:49:20 2022 +0100" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 20:49:20 2022 +0100" }, "message": "Revert \"feat(sgi): add page table translation entry for secure uart\"\n\nRevert submission 14286-uart_segregation\n\nReason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.\n\nReverted Changes:\nI8574b31d5:feat(sgi): add page table translation entry for se...\nI8896ae05e:feat(sgi): route TF-A logs via secure uart\nI39170848e:feat(sgi): deviate from arm css common uart relate...\n\nChange-Id: I9bec02496f826e184c6efa643f869b2eb3b52539\n" }, { "commit": "c5f9d99a7e43b11c87ea9b2a96ec5e628fbcd149", "tree": "344cb34945671ef6b0d428cf203f5e42f1a096cf", "parents": [ "7d00e72a39552416ba24824a1745ffe345df8e52", "9492b391a35c66e1e7630e95347259191b28314d" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Mar 11 18:00:38 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 11 18:00:38 2022 +0100" }, "message": "Merge \"fix(st): don\u0027t try to read boot partition on SD cards\" into integration" }, { "commit": "e46e9df0d0e05f2aaee613fc4f697fcc8d79c0b3", "tree": "775b0e34f5e5c1f86df3942e1c9edb138f2db94b", "parents": [ "7d00e72a39552416ba24824a1745ffe345df8e52" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Thu Dec 02 14:03:44 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.com", "time": "Fri Mar 11 17:47:05 2022 +0800" }, "message": "feat(mt8186): add DFD control in SiP service\n\nDFD (Design for Debug) is a debugging tool, which scans flip-flops and\ndumps to internal RAM on the WDT reset. After system reboots, those\nvalues could be showed for debugging.\n\nBUG\u003db:222217317\nTEST\u003dbuild pass\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I659ea1e0789cf135a71a13b752edaa35123e0941\n" }, { "commit": "9492b391a35c66e1e7630e95347259191b28314d", "tree": "cc505e4270abb0ebce6e63aa71e87c1023ec0c6c", "parents": [ "7c6d460efffa3bfce1ad2a16cd1b5d6fc8801f4c" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Thu Mar 10 22:21:55 2022 +0100" }, "committer": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Fri Mar 11 10:39:57 2022 +0100" }, "message": "fix(st): don\u0027t try to read boot partition on SD cards\n\nWhen trying to boot from an SD card with STM32MP_EMMC_BOOT enabled,\nbooting fails with:\n\n\tERROR: Got unexpected value for active boot partition, 0\n\tASSERT: plat/st/common/bl2_stm32_io_storage.c:285\n\nbecause SD cards don\u0027t provide a boot partition. So only try reading\nfrom such a partition when booting from eMMC.\n\nFixes: 214c8a8d08b2 (\"feat(plat/st): add STM32MP_EMMC_BOOT option\")\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nChange-Id: I354b737a3ae3ea577e83dfeb7096df22275d852d\n" }, { "commit": "7d00e72a39552416ba24824a1745ffe345df8e52", "tree": "8ad71c6a2478fdc845b2d415a46edb816a969972", "parents": [ "7c6d460efffa3bfce1ad2a16cd1b5d6fc8801f4c", "903d5742953d9d4b224e71d8b1e62635e83f44a9" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Fri Mar 11 10:31:16 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 11 10:31:16 2022 +0100" }, "message": "Merge \"fix(brcm): allow build to specify mbedTLS absolute path\" into integration" }, { "commit": "a10a5cb609045de216c01111ec3fcf09a092da0b", "tree": "e9770d4fe327189f3039e38374f3c0a917df7110", "parents": [ "921081049ec37c285c7cac8b845c8a5e829b68c4" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Feb 08 19:32:38 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Mar 11 00:48:03 2022 -0600" }, "message": "fix(security): loop workaround for CVE-2022-23960 for Cortex-A76\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I8d433b39a5c0f9e1cef978df8a2986d7a35d3745\n" }, { "commit": "921081049ec37c285c7cac8b845c8a5e829b68c4", "tree": "64c40df4dfa8a4fef8f5040c3ddc69c24a4a1a19", "parents": [ "1fe4a9d181ead0dcb2bc494e90552d3e7f0aaf4c" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Feb 02 23:03:28 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Mar 11 00:03:03 2022 -0600" }, "message": "refactor(el3-runtime): change Cortex-A76 implementation of CVE-2018-3639\n\nRe-factored the prior implementation of workaround for CVE-2018-3639\nusing branch and link instruction to save vector space to include the\nworkaround for CVE-2022-23960.\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: Ib3fe949583160429b5de8f0a4a8e623eb91d87d4\n" }, { "commit": "1fe4a9d181ead0dcb2bc494e90552d3e7f0aaf4c", "tree": "a07f088625a7eea44aa57604ed6202e9f814b3b0", "parents": [ "fee7b2d3b4dc4fcf225c5191a7aad8427489ef64" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Jan 18 01:59:06 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Thu Mar 10 23:57:14 2022 -0600" }, "message": "fix(security): workaround for CVE-2022-23960\n\nImplements the loop workaround for Cortex-A77, Cortex-A78,\nCortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1\nCPUs.\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I11d342df7a2068a15e18f4974c645af3b341235b\n" }, { "commit": "7c6d460efffa3bfce1ad2a16cd1b5d6fc8801f4c", "tree": "0bc8001674049fcb917d122596e6aca5416395d8", "parents": [ "61fa552362234debb4a09a23ff8003c3a661be9f", "69cde5cd9563f0c665862f1e405ae8e8d2818c6e" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Mar 10 18:47:09 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 10 18:47:09 2022 +0100" }, "message": "Merge \"fix(fvp): op-tee sp manifest doesn\u0027t map gicd\" into integration" }, { "commit": "61fa552362234debb4a09a23ff8003c3a661be9f", "tree": "110a39bffab7c0955b458150de4613194847321d", "parents": [ "955be19907fa8d4d949cc2021df9583050d06a84", "0c55c10305df6217fd978d58ce203dbad3edd4d5" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Mar 10 18:24:14 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 10 18:24:14 2022 +0100" }, "message": "Merge \"fix(fvp): FCONF Trace Not Shown\" into integration" }, { "commit": "955be19907fa8d4d949cc2021df9583050d06a84", "tree": "929d94ca9331caaeadaa2b1c761152db4f1bb232", "parents": [ "1842d1f48d18a6b9ca8a7a85533deefcbc01ecb9", "33d10ac8bf134519f303fd7ce5fb5d583be2f515" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Mar 10 16:36:29 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 10 16:36:29 2022 +0100" }, "message": "Merge changes from topic \"uart_segregation\" into integration\n\n* changes:\n feat(sgi): add page table translation entry for secure uart\n feat(sgi): route TF-A logs via secure uart\n feat(sgi): deviate from arm css common uart related definitions\n" }, { "commit": "903d5742953d9d4b224e71d8b1e62635e83f44a9", "tree": "64aae75b86977394b7663d614aa021bd3f2bb2ef", "parents": [ "1842d1f48d18a6b9ca8a7a85533deefcbc01ecb9" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Mar 09 21:49:59 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Mar 10 15:24:52 2022 +0000" }, "message": "fix(brcm): allow build to specify mbedTLS absolute path\n\nUpdated makefile so that build can accept absolute mbedTLS path.\n\nChange-Id: Ife73266a01d7ed938aafc5e370240023237ebf61\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "0c55c10305df6217fd978d58ce203dbad3edd4d5", "tree": "7747b6b89e0c7f3afc25da16116d5a29b6b74fc3", "parents": [ "1842d1f48d18a6b9ca8a7a85533deefcbc01ecb9" ], "author": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Tue Feb 01 15:19:58 2022 -0500" }, "committer": { "name": "Juan Pablo Conde", "email": "juanpablo.conde@arm.com", "time": "Thu Mar 10 16:03:41 2022 +0100" }, "message": "fix(fvp): FCONF Trace Not Shown\n\nUpdating call order for arm_console_boot_init() and arm_bl31_early_platform_setup().\n\nSigned-off-by:  Juan Pablo Conde \u003cjuanpablo.conde@arm.com\u003e\nChange-Id: If932fff2ee4282a0aacf8751fa81e7665b886467\n" }, { "commit": "1842d1f48d18a6b9ca8a7a85533deefcbc01ecb9", "tree": "35631417778cab913417495e0bd1b88516974bd6", "parents": [ "9c33b087d29d41ffd1ba7fa6dad1a596427a5644", "95b5c0126b802b894ea0177d973978e06b6a254d" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Thu Mar 10 10:14:49 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 10 10:14:49 2022 +0100" }, "message": "Merge \"fix(brcm): fix the build failure with mbedTLS config\" into integration" }, { "commit": "9c33b087d29d41ffd1ba7fa6dad1a596427a5644", "tree": "fe1306fccfa2bb830e49e875ac8c5f9a5a6d987e", "parents": [ "5e29432ebed72aa5852879e6556e6c70108f660d", "6a00e9b0c8c37fc446f83ef63e95a75353e31e8b" ], "author": { "name": "Soby Mathew", "email": "soby.mathew@arm.com", "time": "Wed Mar 09 20:47:08 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 09 20:47:08 2022 +0100" }, "message": "Merge \"fix(gpt_rme): rework delegating/undelegating sequence\" into integration" }, { "commit": "95b5c0126b802b894ea0177d973978e06b6a254d", "tree": "bbaf2f6a9bb0fc5309022bae3dd65b462d51946d", "parents": [ "fee7b2d3b4dc4fcf225c5191a7aad8427489ef64" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Mar 09 14:12:34 2022 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Wed Mar 09 18:03:11 2022 +0000" }, "message": "fix(brcm): fix the build failure with mbedTLS config\n\nPatch [1] introduces a mechanism to provide the platform\nspecified mbedTLS config file, but that result in build failure\nfor Broadcom platform.\nThis build failure is due to the absence of the mbedTLS configuration\nfile i.e. brcm_mbedtls_config.h in the TF-A source code repository.\n\"fatal error: brcm_mbedtls_config.h: No such file or directory\"\n\nThis problem was resolved by removing the \u0027brcm_mbedtls_config.h\u0027 entry\nfrom the broadcom platform makefile, allowing this platform to use\nthe default mbedtls_config.h file.\n\n[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13726\n\nSigned-off-by: Manish V Badarkhe \u003cmanish.badarkhe@arm.com\u003e\nChange-Id: I7cc2efc049aefd3ebce1ae513df9b265fe31ded6\n" }, { "commit": "33d10ac8bf134519f303fd7ce5fb5d583be2f515", "tree": "44defedf70ed0d25f6e77d19e77dd0c0dde5b228", "parents": [ "987e2b7c20eb4ab4215ff5289b715300f5cec054" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Mon Dec 13 15:33:04 2021 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Wed Mar 09 15:32:55 2022 +0000" }, "message": "feat(sgi): add page table translation entry for secure uart\n\nAdd page table translation entry for secure uart so that logs from\nsecure partition can be routed via the same.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I8574b31d5d138d9f94972deb903124f8c5b70ce4\n" }, { "commit": "987e2b7c20eb4ab4215ff5289b715300f5cec054", "tree": "06991e03cfb60f7e4cac88688d67ff4cf29c0544", "parents": [ "f2ccccaa81ec14a80fedb48c37226e5d852ada7a" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Mon Dec 13 15:40:25 2021 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Wed Mar 09 15:32:55 2022 +0000" }, "message": "feat(sgi): route TF-A logs via secure uart\n\nRoute the boot, runtime and crash stage logs via secure UART port\ninstead of the existing use of non-secure UART. This aligns with the\nsecurity state the PE is in when logs are put out. In addition to this,\nthis allows consolidation of the UART related macros across all the\nvariants of the Neoverse reference design platforms.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I8896ae05eaedf06dead520659375af0329f31015\n" }, { "commit": "f2ccccaa81ec14a80fedb48c37226e5d852ada7a", "tree": "74237e61553f904dc87f573c4ce8fd2a761d095a", "parents": [ "5e29432ebed72aa5852879e6556e6c70108f660d" ], "author": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Mon Dec 13 13:50:15 2021 +0000" }, "committer": { "name": "Rohit Mathew", "email": "rohit.mathew@arm.com", "time": "Wed Mar 09 15:32:55 2022 +0000" }, "message": "feat(sgi): deviate from arm css common uart related definitions\n\nThe Neoverse reference design platforms will migrate to use different\nset of secure and non-secure UART ports. This implies that the board\nspecific macros defined in the common Arm platform code will no longer\nbe usable for Neoverse reference design platforms.\n\nIn preparation for migrating to a different set of UART ports, add a\nNeoverse reference design platform specific copy of the board\ndefinitions. The value of these definitions will be changed in\nsubsequent patches.\n\nSigned-off-by: Rohit Mathew \u003crohit.mathew@arm.com\u003e\nChange-Id: I39170848ecd81a7c1bbd3689bd905e45f9435f5c\n" }, { "commit": "6a00e9b0c8c37fc446f83ef63e95a75353e31e8b", "tree": "fe1306fccfa2bb830e49e875ac8c5f9a5a6d987e", "parents": [ "5e29432ebed72aa5852879e6556e6c70108f660d" ], "author": { "name": "Robert Wakim", "email": "robert.wakim@arm.com", "time": "Thu Oct 21 15:39:56 2021 +0100" }, "committer": { "name": "Robert WAKIM", "email": "RobertWak@review.trustedfirmware.org", "time": "Wed Mar 09 16:08:42 2022 +0100" }, "message": "fix(gpt_rme): rework delegating/undelegating sequence\n\nThe previous delegating/undelegating sequence was incorrect as per the\nspecification DDI0615, \"Architecture Reference Manual Supplement, The\nRealm Management Extension (RME), for Armv9-A\" Sections A1.1.1 and\nA1.1.2\n\nOff topic:\n - cleaning the gpt_is_gpi_valid and gpt_check_pass_overlap\n\nChange-Id: Idb64d0a2e6204f1708951137062847938ab5e0ac\nSigned-off-by: Robert Wakim \u003crobert.wakim@arm.com\u003e\n" }, { "commit": "5e29432ebed72aa5852879e6556e6c70108f660d", "tree": "7cdcd4e0e8b3ded4073fda4322bfdf9375aca56f", "parents": [ "fee7b2d3b4dc4fcf225c5191a7aad8427489ef64", "39f262cfb44343d80c7a529bb33b0920a4caf4c1" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 09 15:17:24 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 09 15:17:24 2022 +0100" }, "message": "Merge changes I713f6e93,Iac4fbf4d,I43d02c77,Iadecd544,Ib31f9c4a, ... into integration\n\n* changes:\n build(intel): enable access to on-chip ram in BL31 for N5X\n fix(intel): make FPGA memory configurations platform specific\n fix(intel): fix ECC Double Bit Error handling\n build(intel): define a macro for SIMICS build\n build(intel): add N5X as a new Intel platform\n build(intel): initial commit for crypto driver\n" }, { "commit": "69cde5cd9563f0c665862f1e405ae8e8d2818c6e", "tree": "d85ca224a37584d089d93c75c72ae1f73fac0929", "parents": [ "fee7b2d3b4dc4fcf225c5191a7aad8427489ef64" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Tue May 25 11:56:01 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Mar 09 10:40:32 2022 +0100" }, "message": "fix(fvp): op-tee sp manifest doesn\u0027t map gicd\n\nFollowing I2d274fa897171807e39b0ce9c8a28824ff424534:\nRemove GICD registers S2 mapping from OP-TEE partition when it runs in a\nsecure partition on top of Hafnium.\nThe partition is not meant to access the GIC directly but use the\nHafnium provided interfaces.\n\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\nChange-Id: I1a38101f6ae9911662828734a3c9572642123f32\n" }, { "commit": "bb1768c67ea06ac466e2cdc7e5338c3d23dac79d", "tree": "1da6e56fda02f1a56a8670c5f3e6b5ab6a7927a8", "parents": [ "fee7b2d3b4dc4fcf225c5191a7aad8427489ef64" ], "author": { "name": "Michal Simek", "email": "michal.simek@xilinx.com", "time": "Wed Mar 09 08:53:20 2022 +0100" }, "committer": { "name": "Michal Simek", "email": "michal.simek@xilinx.com", "time": "Wed Mar 09 09:14:33 2022 +0100" }, "message": "fix(xilinx): fix coding style violations\n\nFix coding style violations and alignments:\n- Remove additional newlines in headers\n- Remove additional newlines in code\n- Add newline to separate variable from the code\n- Use the same indentation in platform.mk\n- Align function parameters\n- Use tabs for indentation in kernel-doc format\n\nSigned-off-by: Michal Simek \u003cmichal.simek@xilinx.com\u003e\nChange-Id: I0b12804ff63bc19778e8f21041f9accba5b488b9\n" }, { "commit": "39f262cfb44343d80c7a529bb33b0920a4caf4c1", "tree": "391b4e928ca908e954ba262e87b0c9ab36525578", "parents": [ "f571183b066b1a91b7fb178c3aad9d6360d1918c" ], "author": { "name": "Boon Khai Ng", "email": "boon.khai.ng@intel.com", "time": "Fri May 21 22:56:37 2021 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 09 09:14:26 2022 +0800" }, "message": "build(intel): enable access to on-chip ram in BL31 for N5X\n\nThis adds the ncore ccu access and enable access to the\non-chip ram for N5X device in BL31.\n\nSigned-off-by: Boon Khai Ng \u003cboon.khai.ng@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: I713f6e93d33b6e91705547477ca32cfba5c8c13d\n" }, { "commit": "f571183b066b1a91b7fb178c3aad9d6360d1918c", "tree": "c20cdecc4c74c9de486175d9c65ae60a6ab02a66", "parents": [ "c703d752cce4fd101599378e72db66ccf53644fa" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Mon Feb 28 15:24:59 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 09 09:14:21 2022 +0800" }, "message": "fix(intel): make FPGA memory configurations platform specific\n\nDefine FPGA_CONFIG_SIZE and FPGA_CONFIG_ADDR in\nplatform-specific header. This is due to different\nallocated sizes between platforms.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Iac4fbf4d4940cdf31834a9d4332f9292870dee76\n" }, { "commit": "c703d752cce4fd101599378e72db66ccf53644fa", "tree": "c0cf27322c497f7771c4b1d7adc6bde17f5f64d7", "parents": [ "1f1c0206d8513e07a64b84b374b461c3db61b49c" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Mon Mar 07 12:13:04 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 09 09:14:16 2022 +0800" }, "message": "fix(intel): fix ECC Double Bit Error handling\n\nSError and Abort are handled in Linux (EL1) instead of\nEL3. This patch adds some functionality that complements the\nuse cases by Linux as follows:\n\n- Provide SMC for ECC DBE notification to EL3\n- Determine type of reset needed and service the request in\n place of Linux\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: I43d02c77f28004a31770be53599a5a42de412211\n" }, { "commit": "1f1c0206d8513e07a64b84b374b461c3db61b49c", "tree": "cc4114eb0bc12de8b4e8681ca0bcd3fc7f00f2db", "parents": [ "325eb35d24e89b2092bbf9a098a44a321de5fdd9" ], "author": { "name": "Abdul Halim, Muhammad Hadi Asyrafi", "email": "muhammad.hadi.asyrafi.abdul.halim@intel.com", "time": "Mon Jun 29 12:15:27 2020 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 09 09:14:06 2022 +0800" }, "message": "build(intel): define a macro for SIMICS build\n\nSIMICS builds have different UART configurations compared\nto hardware build. Hence, this patch defines a macro to\ndifferentiate between both.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Iadecd5445e06611486ac3c6a214a6d0dc8ccd27b\n" }, { "commit": "325eb35d24e89b2092bbf9a098a44a321de5fdd9", "tree": "2b6721cd8e25717dbaf7b92d6a96ff4869a5900b", "parents": [ "286b96f4bbf0cfe2fe91262015ad63a497be25f9" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Mon Mar 07 12:04:59 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 09 09:14:03 2022 +0800" }, "message": "build(intel): add N5X as a new Intel platform\n\nThis commit adds a new Intel platform called N5X.\nThis preliminary patch only have Bl31 support.\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: Ib31f9c4a5a0dabdce81c1d5b0d4776188add7195\n" }, { "commit": "286b96f4bbf0cfe2fe91262015ad63a497be25f9", "tree": "91f63922d85573f157da2bff268df85a8a7d5606", "parents": [ "a7ef8b31cec8d8e37fabb5358c4303d7ba0f18e5" ], "author": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 02 11:04:09 2022 +0800" }, "committer": { "name": "Sieu Mun Tang", "email": "sieu.mun.tang@intel.com", "time": "Wed Mar 09 09:13:20 2022 +0800" }, "message": "build(intel): initial commit for crypto driver\n\nThis patch adds driver for Intel FPGA\u0027s Crypto Services.\nThese services are provided by Intel platform\nSecure Device Manager(SDM) and are made accessible by\nprocessor components (ie ATF).\nBelow is the list of enabled features:\n- Send SDM certificates\n- Efuse provision data dump\n- Encryption/decryption service\n- Hardware IP random number generator\n\nSigned-off-by: Abdul Halim, Muhammad Hadi Asyrafi \u003cmuhammad.hadi.asyrafi.abdul.halim@intel.com\u003e\nSigned-off-by: Sieu Mun Tang \u003csieu.mun.tang@intel.com\u003e\nChange-Id: If7604cd1cacf27a38a9a29ec6b85b07385e1ea26\n" }, { "commit": "fee7b2d3b4dc4fcf225c5191a7aad8427489ef64", "tree": "7ef5e68936c9f061dd0d9910d824c7434eec78c4", "parents": [ "a82f5bbf9ed980d08325ef7296408a48dadfe299", "ef934cd17c30dcc39cd9022a1c4e9523ec8ba617" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Wed Mar 09 00:05:22 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 09 00:05:22 2022 +0100" }, "message": "Merge \"fix(errata): workaround for Cortex-A710 2282622\" into integration" }, { "commit": "ef934cd17c30dcc39cd9022a1c4e9523ec8ba617", "tree": "7ef5e68936c9f061dd0d9910d824c7434eec78c4", "parents": [ "a82f5bbf9ed980d08325ef7296408a48dadfe299" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Mon Feb 28 18:34:04 2022 -0600" }, "committer": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Mar 09 00:04:02 2022 +0100" }, "message": "fix(errata): workaround for Cortex-A710 2282622\n\nCortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions\nr0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set\nCPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like\nPLD/PRFM LD and not cause invalidations to other PE caches.\n\nSDEN can be found here:\nhttps://developer.arm.com/documentation/SDEN1775101\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: Ic48409822536e9eacc003300036a1f0489593020\n" }, { "commit": "a82f5bbf9ed980d08325ef7296408a48dadfe299", "tree": "0169f6bc23c909448f35cdb48376d96fe6cea023", "parents": [ "4cb2ec2ad250e3b57d391df663278f7ec0916ac5", "2d972cc9c10f4364eb90f129b9633140a01d8963" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 08 21:58:48 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 08 21:58:48 2022 +0100" }, "message": "Merge \"docs(security): security advisory for CVE-2022-23960\" into integration" }, { "commit": "2d972cc9c10f4364eb90f129b9633140a01d8963", "tree": "1ccf0db46c3b6217b14da0fdb5cafa4ecdd8cf23", "parents": [ "e0a6a512b51558b64eb500e6b731e4c743050af2" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Fri Feb 25 19:12:10 2022 -0600" }, "committer": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Mar 08 13:33:53 2022 -0600" }, "message": "docs(security): security advisory for CVE-2022-23960\n\nSigned-off-by: Bipin Ravi \u003cbipin.ravi@arm.com\u003e\nChange-Id: I17b0847ff71e4a291bf7ba41fd71fe08c400b5e8\n" }, { "commit": "4cb2ec2ad250e3b57d391df663278f7ec0916ac5", "tree": "c96ce241b212d9387ad96dbbfe318f3690cb5340", "parents": [ "95cfac5a9ad1fbef8335d79f59a72feccfe495e6", "b35b556718b60b78cb5d96b0c137e2fe82eb0086" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 08 16:29:49 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 08 16:29:49 2022 +0100" }, "message": "Merge changes I18d47384,Icc3c7424,I73f20d82,I07325644,Iff10ad26, ... into integration\n\n* changes:\n fix(zynqmp): query node status to power up APU\n feat(zynqmp): pm_api_clock_get_num_clocks cleanup\n feat(zynqmp): add feature check support\n fix(zynqmp): use common interface for eemi apis\n feat(zynqmp): add support to get info of xilfpga\n feat(zynqmp): pass ioctl calls to firmware\n" }, { "commit": "95cfac5a9ad1fbef8335d79f59a72feccfe495e6", "tree": "e7f8ac1f216b366065a1b574357b591807b1ea11", "parents": [ "af68314ddcec11d71153ad52f3532cb4ac8520cd", "57e6018305a97f4e3627d16d8b1886419f274b4a" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Mar 08 16:03:01 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Mar 08 16:03:01 2022 +0100" }, "message": "Merge \"fix(st-pmic): add static const to pmic_ops\" into integration" }, { "commit": "57e6018305a97f4e3627d16d8b1886419f274b4a", "tree": "e7f8ac1f216b366065a1b574357b591807b1ea11", "parents": [ "af68314ddcec11d71153ad52f3532cb4ac8520cd" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Feb 09 17:35:45 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Tue Mar 08 13:18:09 2022 +0100" }, "message": "fix(st-pmic): add static const to pmic_ops\n\nThe static was found by sparse tool:\ndrivers/st/pmic/stm32mp_pmic.c:456:18: warning: symbol \u0027pmic_ops\u0027\n was not declared. Should it be static?\nThe const was also missing.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: Ibb5cfaf67ac980bf0af27712a95dbef05b617c25\n" }, { "commit": "af68314ddcec11d71153ad52f3532cb4ac8520cd", "tree": "42f8bcfc593c78b1791879a18bedf3cbe5255f89", "parents": [ "1cfe48963f73b90fb4a4718505d3943abacba7d2", "033f61370af38c6397963075ac2477f3192714b9" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Mon Mar 07 21:40:26 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 07 21:40:26 2022 +0100" }, "message": "Merge \"refactor(mbedtls): allow platform to specify their config file\" into integration" }, { "commit": "1cfe48963f73b90fb4a4718505d3943abacba7d2", "tree": "9af7b2264234f6e9262ac399536efd88401abf35", "parents": [ "f083fe4abb1d7228be8b85d5d3528f41bc122b12", "44cf2b1abb9e6b2a8a5df71d35f95d0e845e8a95" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Mar 07 18:46:39 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 07 18:46:39 2022 +0100" }, "message": "Merge \"docs(maintainers): add maintained files for MediaTek SoCs\" into integration" }, { "commit": "f083fe4abb1d7228be8b85d5d3528f41bc122b12", "tree": "b21f34259806573b26baf7574c52678e3fd45453", "parents": [ "c507b060077d1a125ac469d5516168ef964da1b2", "ea04b3fe183b6661f656b4cc38cb93a73d9bc202" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Mar 07 16:05:21 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Mar 07 16:05:21 2022 +0100" }, "message": "Merge \"fix(versal): fix the incorrect log message\" into integration" }, { "commit": "ea04b3fe183b6661f656b4cc38cb93a73d9bc202", "tree": "55ddaf3ae3b848aa3d0bb468732118dcc6f2f551", "parents": [ "cf86fa1bfaf16a6783e462c2e1318f15869a36f5" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Thu Mar 03 01:58:36 2022 -0700" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Sun Mar 06 21:09:23 2022 -0700" }, "message": "fix(versal): fix the incorrect log message\n\nWhen the atf-handoff-params are updated we are returning\nFSBL_HANDOFF_SUCCESS, but the return condition is wrongly\nupdated and added a error log which is incorrect.\nFixing the incorrect log message.\n\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: I44ebbb861831b86afcb87f09ddb2e23614393c28\n" }, { "commit": "c507b060077d1a125ac469d5516168ef964da1b2", "tree": "1a83f6d2b1ba546a084bf690cf6d3fd58c6b3d5b", "parents": [ "8dec6481c38fa2f77b46ca02f4b478f07b7f8b03", "175758b2777eb6df3c4aefd79448e97e76a15272" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sun Mar 06 01:24:17 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Mar 06 01:24:17 2022 +0100" }, "message": "Merge \"fix(st-clock): initialize pllcfg table\" into integration" }, { "commit": "8dec6481c38fa2f77b46ca02f4b478f07b7f8b03", "tree": "517160179f47c0ac3f05fd37a8a2b103a0785e51", "parents": [ "b298d4df5efc5d7a350dc10ca10b85a91d4d46e0", "99887cb90474a4e9cfc5c7b622f223f88bda95eb" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Sun Mar 06 01:23:23 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sun Mar 06 01:23:23 2022 +0100" }, "message": "Merge changes from topic \"st-uart-baudrate\" into integration\n\n* changes:\n refactor(st): configure UART baudrate\n docs(stm32mp1): document some compilation flags\n feat(st-uart): manage oversampling by 8\n fix(st-uart): correctly fill BRR register\n" }, { "commit": "99887cb90474a4e9cfc5c7b622f223f88bda95eb", "tree": "517160179f47c0ac3f05fd37a8a2b103a0785e51", "parents": [ "975cf6ff5105530f3b05cbf2529c703cb5d16549" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Mar 02 14:31:55 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 04 14:55:18 2022 +0100" }, "message": "refactor(st): configure UART baudrate\n\nAdd the possibility to configure console UART baudrate, it can be passed\nas a command line parameter with STM32MP_UART_BAUDRATE. The default value\nremains 115200.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I000df70c10b2b4dac1449556596f9820c36cf243\n" }, { "commit": "975cf6ff5105530f3b05cbf2529c703cb5d16549", "tree": "0414625383cf4fd47c3d29f52b40d7bc3b394ddf", "parents": [ "1f60d1bd33d434b0c82a74e276699ee5a2f63833" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Mar 03 18:22:46 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 04 14:55:18 2022 +0100" }, "message": "docs(stm32mp1): document some compilation flags\n\nAdd missing serial boot devices flags.\nAdd optional compilation flags, and their defauld values.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I507f7110bcd7b9af136a6fc6b8af342b084c8dbc\n" }, { "commit": "1f60d1bd33d434b0c82a74e276699ee5a2f63833", "tree": "395da3ad693428bc87ccdac60070f6aae8f311d6", "parents": [ "af7775ab535138ff49643f749110dca143d4122c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Feb 28 18:28:06 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 04 14:55:18 2022 +0100" }, "message": "feat(st-uart): manage oversampling by 8\n\nUART oversampling by 8 allows higher baud rates for UART. This is\nrequired when (UART freq / baudrate) \u003c\u003d 16. In this case the OVER8 bit\nneeds to be enabled in CR1 register. And the BRR register management is\ndifferent:\nUSARTDIV \u003d (2 * UART freq / baudrate) (with div round nearest)\nBRR[15:4] \u003d USARTDIV[15:4]\nBRR[3] \u003d 0\nBRR[2:0] \u003d USARTDIV[3:0] \u003e\u003e 1\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Ia3fbeeb73a36a4dc485c7ba428c531e65b6f6c09\n" }, { "commit": "af7775ab535138ff49643f749110dca143d4122c", "tree": "8d7a7728bcd85849660b221156fa620aa1a98436", "parents": [ "b298d4df5efc5d7a350dc10ca10b85a91d4d46e0" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon Feb 28 17:29:49 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 04 14:55:18 2022 +0100" }, "message": "fix(st-uart): correctly fill BRR register\n\nTo get the nearest divisor for BRR register, we use:\nDivisor \u003d (Uart clock + (baudrate / 2)) / baudrate\nBut lsl was wrongly used instead of lsr to have the division by 2.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Iedcc3ccdb4cf8268012e82a66df2a9ec48fc1d79\n" }, { "commit": "175758b2777eb6df3c4aefd79448e97e76a15272", "tree": "2f3c4a4e472e83f2c8865174661e06ff982c64eb", "parents": [ "b298d4df5efc5d7a350dc10ca10b85a91d4d46e0" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 04 11:08:47 2022 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Fri Mar 04 13:48:53 2022 +0100" }, "message": "fix(st-clock): initialize pllcfg table\n\nThe issue was found by Coverity:\nCID 376582: (UNINIT)\n Using uninitialized value \"*pllcfg[_PLL4]\" when calling\n \"stm32mp1_check_pll_conf\".\nCID 376582: (UNINIT)\n Using uninitialized value \"*pllcfg[_PLL3]\" when calling\n \"stm32mp1_check_pll_conf\".\n\nCheck PLL configs are valid before using pllcfg.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@st.com\u003e\nChange-Id: I49de849eaf451d0c165a8eb8555112a0a4140bbc\n" }, { "commit": "b298d4df5efc5d7a350dc10ca10b85a91d4d46e0", "tree": "98d656d63b8d955e2eb0a43e8331d6f1629820dd", "parents": [ "a7ef8b31cec8d8e37fabb5358c4303d7ba0f18e5", "9944f55761c4d5cc1feefaf5e33bf7fb83d8f5f3" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Mar 04 13:22:45 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Mar 04 13:22:45 2022 +0100" }, "message": "Merge \"feat(ff-a): forward FFA_VERSION from SPMD to SPMC\" into integration" }, { "commit": "44cf2b1abb9e6b2a8a5df71d35f95d0e845e8a95", "tree": "277d6837739fb2f586fb5c13ea0a108a20b1222b", "parents": [ "9457cec8c02f78ba56fd9298dd795766c89281a2" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.com", "time": "Fri Mar 04 11:50:43 2022 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.com", "time": "Fri Mar 04 14:42:02 2022 +0800" }, "message": "docs(maintainers): add maintained files for MediaTek SoCs\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: I2d71b2fef2f2aee507a6e7c4b9b9d8175446a0ca\n" }, { "commit": "a7ef8b31cec8d8e37fabb5358c4303d7ba0f18e5", "tree": "504b0b43df3a5b3290215b59aa6068af309bc967", "parents": [ "cf86fa1bfaf16a6783e462c2e1318f15869a36f5", "9457cec8c02f78ba56fd9298dd795766c89281a2" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Mar 03 13:57:27 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Mar 03 13:57:27 2022 +0100" }, "message": "Merge \"feat(mt8186): disable 26MHz clock while suspending\" into integration" }, { "commit": "b35b556718b60b78cb5d96b0c137e2fe82eb0086", "tree": "cfdf63549fdd67b10aeadfff3ade819a3d1ee869", "parents": [ "e682d38b56854e1586b25d929dbc83543b4c66e4" ], "author": { "name": "Ravi Patel", "email": "ravi.patel@xilinx.com", "time": "Thu Apr 15 05:55:19 2021 -0700" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Mar 02 22:10:57 2022 -0800" }, "message": "fix(zynqmp): query node status to power up APU\n\nIf APU is in suspending state and if wakeup request comes then\nPMUFW returns error which is not handled at ATF side.\n\nTo fix this, get the APU node status before calling wakeup and\nreturn error if found in suspending state.\n\nHere, we can not handle the error code of pm_req_wakeup() from PMUFW\nbecause ATF is already calling pm_client_wakeup() before calling\npm_req_wakeup().\n\nSigned-off-by: Ravi Patel \u003cravi.patel@xilinx.com\u003e\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: I18d47384e46e22ae49e804093ad0641b7a6349e2\n" }, { "commit": "e682d38b56854e1586b25d929dbc83543b4c66e4", "tree": "4acc09baf94123bf21a6294d6aa9e753b227aae2", "parents": [ "223a6284b8a0a3ead884a7f0cf333a464d32e319" ], "author": { "name": "Michal Simek", "email": "michal.simek@xilinx.com", "time": "Wed Feb 02 09:15:31 2022 +0100" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Mar 02 22:10:49 2022 -0800" }, "message": "feat(zynqmp): pm_api_clock_get_num_clocks cleanup\n\nThere is no reason to have even one additional useless line that\u0027s why\nremove it.\n\nSigned-off-by: Michal Simek \u003cmichal.simek@xilinx.com\u003e\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: Icc3c74249dfe64173aa5c88fb0f9ffe7576fc2aa\n" }, { "commit": "223a6284b8a0a3ead884a7f0cf333a464d32e319", "tree": "2e360de038a164a0180849268320b987bb72aeab", "parents": [ "a469c1e1f4c1cd69f98ce45d6e0709de091b8cb3" ], "author": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Tue Dec 21 01:39:59 2021 -0800" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Mar 02 22:10:26 2022 -0800" }, "message": "feat(zynqmp): add feature check support\n\nThis API returns version of supported APIs.\n\nHere, there are three cases to check API version by using feature\ncheck implementation.\n\n1. Completely implemented in TF-A: I mean the EEMI APIs which are\ncompletely implemented in the TF-A only. So check those IDs and\nreturn appropriate version for the same. Right now, it is base\nversion.\n\n2. Completely implemented in firmware: I mean the EEMI APIs which are\ncompletely implemented in the firmware only. Here, TF-A only passes\nLinux request to the firmware to get the version of supported API. So\ncheck those IDs and send request to firmware to get the version and\nreturn to Linux if the version is supported or return the error code\nif the feature is not supported.\n\n3. Partially implemented (Implemented in TF-A and firmware both):\nFirst check dependent EEMI API version with the expected version in\nthe TF-A. If the dependent EEMI API is supported in firmware then\nreturn its version and check with the expected version in the TF-A.\nIf the version matches then check for the actual requested EEMI API\nversion. If the version is supported then return version of API\nimplemented in TF-A.\n\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: I73f20d8222c518df1cda7879548b408b130b5b2e\n" }, { "commit": "a469c1e1f4c1cd69f98ce45d6e0709de091b8cb3", "tree": "d077104ac2b6129ecff60735442a697ee868c2f0", "parents": [ "cc077c22273075db328bd30fa12c28abf9eef052" ], "author": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Thu Jan 20 23:11:18 2022 -0800" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Mar 02 22:10:11 2022 -0800" }, "message": "fix(zynqmp): use common interface for eemi apis\n\nCurrently all EEMI API has its own implementation in TF-A which is\nredundant. Most EEMI API implementation in TF-A does same work. It\nprepares payload received from kernel, sends payload to firmware,\nreceives response from firmware and send response back to kernel.\n\nSo use common interface for EEMI APIs which has similar functionality.\nThis will optimize TF-A code.\n\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: I07325644a1fae80211f2588d5807c21973f6d48f\n" }, { "commit": "cc077c22273075db328bd30fa12c28abf9eef052", "tree": "cc6929015bdf9c93afd3d25179ec3d78440e60c5", "parents": [ "76ff8c459e9e6d105e614d68648bd6680806f93e" ], "author": { "name": "Nava kishore Manne", "email": "nava.manne@xilinx.com", "time": "Thu Jan 13 13:29:36 2022 +0530" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Mar 02 22:10:04 2022 -0800" }, "message": "feat(zynqmp): add support to get info of xilfpga\n\nAdds support to get the xilfpga library version and feature list info.\n\nSigned-off-by: Nava kishore Manne \u003cnava.manne@xilinx.com\u003e\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: Iff10ad2628a6a90230c18dc3aebf9dde89f53ecd\n" }, { "commit": "76ff8c459e9e6d105e614d68648bd6680806f93e", "tree": "a08689f665ead8ffb6e6554f75c1a0a34ce7e16e", "parents": [ "cf86fa1bfaf16a6783e462c2e1318f15869a36f5" ], "author": { "name": "Rajan Vaja", "email": "rajan.vaja@xilinx.com", "time": "Tue Oct 12 03:30:09 2021 -0700" }, "committer": { "name": "Ronak Jain", "email": "ronak.jain@xilinx.com", "time": "Wed Mar 02 22:09:33 2022 -0800" }, "message": "feat(zynqmp): pass ioctl calls to firmware\n\nFirmware supports new IOCTL for different purposes. To avoid\nmaintaining new IOCTL IDs in ATF, pass IOCTL call to firmware\nfor IOCTL IDs implemented in firmware.\n\nSigned-off-by: Rajan Vaja \u003crajan.vaja@xilinx.com\u003e\nSigned-off-by: Ronak Jain \u003cronak.jain@xilinx.com\u003e\nChange-Id: Ie14697c8da9581b0f695f4d33f05161ece558385\n" }, { "commit": "cf86fa1bfaf16a6783e462c2e1318f15869a36f5", "tree": "dd18265961ba4ad4673426f00aef5b1958488aee", "parents": [ "f87fb0aca3d7692777b6a3e6252148066b4c382a", "4c4b9615b1d9512a4a89aa08e722547cc491a07b" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 02 19:28:13 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 02 19:28:13 2022 +0100" }, "message": "Merge \"feat(zynqmp): increase the max xlat tables when debug build is enabled\" into integration" }, { "commit": "f87fb0aca3d7692777b6a3e6252148066b4c382a", "tree": "e5d5397d4444bf511f7ac6c0ae9d047532cdbf83", "parents": [ "3f7c88617a061200137bd0f326d7b772f571257d", "18e2a79f8a5eaa72a2a7e641c2481beb9f827dce" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 02 18:30:48 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 02 18:30:48 2022 +0100" }, "message": "Merge \"feat(versal): remove the time stamp configuration\" into integration" }, { "commit": "3f7c88617a061200137bd0f326d7b772f571257d", "tree": "78156a6b4e9a8811c3e40d124a356e74545fa768", "parents": [ "df4520c6f017561d433cdaaa4aff195c86d73dbe", "1dd4bafb82f8bf3b5f9e571c90a0b6ee1411df57" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Mar 02 16:53:53 2022 +0100" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Mar 02 16:53:53 2022 +0100" }, "message": "Merge \"docs(rme): minor update to 4 world execution instructions\" into integration" } ], "next": "1dd4bafb82f8bf3b5f9e571c90a0b6ee1411df57" }