)]}' { "log": [ { "commit": "f3d2750aa2293c0279bc447a85771827ca8b74c1", "tree": "0b210256184d29346f776566b3840e263aa27488", "parents": [ "5014b52dec0c2527ca85c0fbe9c9281a24cc7b10" ], "author": { "name": "Vyacheslav Yurkov", "email": "uvv.mail@gmail.com", "time": "Fri Jun 04 10:08:39 2021 +0200" }, "committer": { "name": "Vyacheslav Yurkov", "email": "uvv.mail@gmail.com", "time": "Fri Jun 04 10:08:39 2021 +0200" }, "message": "feat(drivers/st): manage boot part in io_mmc\n\nUse dedicated read function for boot partition\n\nSigned-off-by: Vyacheslav Yurkov \u003cuvv.mail@gmail.com\u003e\nChange-Id: If75df7691fce0797205365736fc6e4e3429efdca\n" }, { "commit": "5014b52dec0c2527ca85c0fbe9c9281a24cc7b10", "tree": "fbaf832a7c55a84da35204a1d857534509c00eb7", "parents": [ "0ef419b1451ec68395f748c59b623bf62c54913c" ], "author": { "name": "Vyacheslav Yurkov", "email": "uvv.mail@gmail.com", "time": "Tue Mar 30 08:16:20 2021 +0200" }, "committer": { "name": "Vyacheslav Yurkov", "email": "uvv.mail@gmail.com", "time": "Fri Jun 04 09:52:37 2021 +0200" }, "message": "feat(drivers/mmc): boot partition read support\n\nAdded a public function to read blocks from a current boot partition.\nswitch between partitions has to respect eMMC partition switch timing.\n\nSigned-off-by: Vyacheslav Yurkov \u003cuvv.mail@gmail.com\u003e\nChange-Id: I55b0c910314253e5647486609583fd290dadd30a\n" }, { "commit": "0ef419b1451ec68395f748c59b623bf62c54913c", "tree": "6a6ec87642460cfa8eb6ef7aaa1a6d5948168019", "parents": [ "a49babce63cc99efe9ccb740295ee868c03cce3b", "4143268a5ca8f91f1014e0d83edf766946ffff76" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 03 16:52:26 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 03 16:52:26 2021 +0200" }, "message": "Merge \"feat(plat/zynqmp): add SDEI support\" into integration" }, { "commit": "4143268a5ca8f91f1014e0d83edf766946ffff76", "tree": "45e6524beed9159ac655c0d2fe01347413b204ba", "parents": [ "2512d0480f5d88c0e81ba2b3712613d1be203cbc" ], "author": { "name": "Jan Kiszka", "email": "jan.kiszka@siemens.com", "time": "Tue Jul 14 22:36:59 2020 +0200" }, "committer": { "name": "Jan Kiszka", "email": "jan.kiszka@siemens.com", "time": "Thu Jun 03 16:34:12 2021 +0200" }, "message": "feat(plat/zynqmp): add SDEI support\n\nAdd basic SDEI support, implementing the software event 0 only for now.\nThis already allows hypervisors like Jailhouse to use SDEI for internal\nsignaling while passing the GICC through to the guest (see also IMX8).\n\nWith SDEI on, we overrun the SRAM and need to stay in DRAM. So keep SDEI\noff by default.\n\nCo-developed-by: Angelo Ruocco \u003cangeloruocco90@gmail.com\u003e\nSigned-off-by: Angelo Ruocco \u003cangeloruocco90@gmail.com\u003e\nSigned-off-by: Jan Kiszka \u003cjan.kiszka@siemens.com\u003e\nChange-Id: Ic0d71b4ef0978c0a34393f4e3530ed1e24a39ca2\n" }, { "commit": "a49babce63cc99efe9ccb740295ee868c03cce3b", "tree": "8528a9c08f80311fe2e7a3785412e4f217d0087f", "parents": [ "cbcdf688a10c8032a938986c25257adbf9b6f903", "3f916a412afcf340781ed0dec31d3b67d94fdca4" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Jun 03 16:08:35 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 03 16:08:35 2021 +0200" }, "message": "Merge changes from topic \"stm32_bl2_io\" into integration\n\n* changes:\n refactor(plat/st): remove io_dummy code for OP-TEE\n refactor(plat/st): remove BL2 image loading\n refactor(plat/st): rename OP-TEE pager to core\n" }, { "commit": "3f916a412afcf340781ed0dec31d3b67d94fdca4", "tree": "8528a9c08f80311fe2e7a3785412e4f217d0087f", "parents": [ "e1db570a30661755c29ef03213c96f66a449c511" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Thu Jun 03 10:48:57 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Thu Jun 03 10:48:57 2021 +0200" }, "message": "refactor(plat/st): remove io_dummy code for OP-TEE\n\nThe io_dummy code and function calls are only used in case BL32 is TF-A\nSP_min, and not OP-TEE. This code in bl2_io_storage can then be put under\n#ifndef AARCH32_SP_OPTEE.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I52787a775160b335f97547203f653419621f5147\n" }, { "commit": "e1db570a30661755c29ef03213c96f66a449c511", "tree": "aeaf9b0e1b2ddf7c2a1aafddea7443a98bde273c", "parents": [ "06c3b100ea29336e34a3abde3f87e62c56d03b4c" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Tue May 11 13:39:55 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Thu Jun 03 10:45:17 2021 +0200" }, "message": "refactor(plat/st): remove BL2 image loading\n\nSTM32MP1 does not use BL1, the loading of BL2 is done by ROM code. It is\nthen useless to have an entry BL2_IMAGE_ID in the policies.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I464cedf588114d60522433123f8dbef32ae36818\n" }, { "commit": "06c3b100ea29336e34a3abde3f87e62c56d03b4c", "tree": "c2bb9751b2689423f72e241907758f019a95f4aa", "parents": [ "cbcdf688a10c8032a938986c25257adbf9b6f903" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed May 19 16:10:25 2021 +0200" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Thu Jun 03 10:43:42 2021 +0200" }, "message": "refactor(plat/st): rename OP-TEE pager to core\n\nOPTEE_PAGER defines are renamed OPTEE_CORE.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I4c28d3b0a6ed843088a3ef06e3e348ce689fabde\n" }, { "commit": "cbcdf688a10c8032a938986c25257adbf9b6f903", "tree": "d5491007b4b05a0dc4243ec296dd47ac0dba8f39", "parents": [ "2512d0480f5d88c0e81ba2b3712613d1be203cbc", "748bdd19aa27c15438d829bdba42fe4062a265a1" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jun 03 08:41:33 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jun 03 08:41:33 2021 +0200" }, "message": "Merge \"fix(plat/arm): correct UUID strings in FVP DT\" into integration" }, { "commit": "748bdd19aa27c15438d829bdba42fe4062a265a1", "tree": "d5491007b4b05a0dc4243ec296dd47ac0dba8f39", "parents": [ "2512d0480f5d88c0e81ba2b3712613d1be203cbc" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Mon May 03 11:52:50 2021 +0200" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jun 02 17:21:06 2021 +0200" }, "message": "fix(plat/arm): correct UUID strings in FVP DT\n\nThe UUID strings used in FW_CONFIG DT are not aligned with UUIDs defined\nin include/tools_share/firmware_image_package.h for BL32_EXTRA1 and\nTRUSTED_KEY_CERT.\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: I517f8f9311585931f2cb931e0588414da449b694\n" }, { "commit": "2512d0480f5d88c0e81ba2b3712613d1be203cbc", "tree": "58a37a65f5b81ee069de1e4c4153968833b2cb11", "parents": [ "203d48adcad8d90eb8fb5eb4bb2de4c65c9837af", "9ce232fe985a0bb308af459ede8a22629255d4e7" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jun 02 15:45:29 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jun 02 15:45:29 2021 +0200" }, "message": "Merge \"feat(plat/imx8m): add SiP call for secondary boot\" into integration" }, { "commit": "203d48adcad8d90eb8fb5eb4bb2de4c65c9837af", "tree": "daba4a83da18cac0ef2deefaf59276b750d315e5", "parents": [ "94869f0fd1d714f4591b1259683e3321bc8f2bb9", "3133625859b74df42deddd80b705578af6fc2fea" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 20:24:05 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 20:24:05 2021 +0200" }, "message": "Merge \"refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros\" into integration" }, { "commit": "94869f0fd1d714f4591b1259683e3321bc8f2bb9", "tree": "20ea37766ce5c94470c09811879cb73b33b2c8a2", "parents": [ "73a3db718c6d0ca5066da2e8c9dd235a68eadf4a", "6b557f48c37f5c91253d0c4876adc22121954e9c" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 18:58:39 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 18:58:39 2021 +0200" }, "message": "Merge \"refactor(plat/marvell/uart): remove unused macros\" into integration" }, { "commit": "73a3db718c6d0ca5066da2e8c9dd235a68eadf4a", "tree": "f9996d2d80e6db166b797948ccd8d129ac4c011e", "parents": [ "906116f82974885494a9a151427c307dfd0e5bbd", "7f2d23d9d790df90021de6c5165ef10fe5cc5590" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 17:07:45 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 17:07:45 2021 +0200" }, "message": "Merge \"fix(morello): initialise CNTFRQ in Non Secure CNTBaseN\" into integration" }, { "commit": "906116f82974885494a9a151427c307dfd0e5bbd", "tree": "8615e63504002bb6e035947528fa38aa7701c6ea", "parents": [ "4fe55a2fd8b7dbd00886ff4cc57429e16b99850e", "b9185c75f7ec2b600ebe0d49281e216a2456b764" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 16:45:49 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 16:45:49 2021 +0200" }, "message": "Merge \"fix(plat/marvell/a3720/uart): fix configuring UART clock\" into integration" }, { "commit": "3133625859b74df42deddd80b705578af6fc2fea", "tree": "8117a3b09bb4e4d0431a1a71b8103847b6fb0018", "parents": [ "6b557f48c37f5c91253d0c4876adc22121954e9c" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Fri May 14 13:21:56 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Jun 01 16:34:52 2021 +0200" }, "message": "refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macros\n\nMacros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined\nto same values. De-duplicate them into PLAT_MARVELL_UART* macros.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f\n" }, { "commit": "6b557f48c37f5c91253d0c4876adc22121954e9c", "tree": "eb276898c0eeaedb8d34f2056f3b8e6552a2820a", "parents": [ "b9185c75f7ec2b600ebe0d49281e216a2456b764" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Fri May 14 13:13:43 2021 +0200" }, "committer": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Tue Jun 01 16:34:08 2021 +0200" }, "message": "refactor(plat/marvell/uart): remove unused macros\n\nMacros PLAT_MARVELL_BL31_RUN_UART* are not used since commit\nd7c4420cb8a7 (\"plat/marvell: Migrate to multi-console API\").\n\nRemove them.\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I5ec959ef4de87dcfb332c017ad2599bf8af6ffc3\n" }, { "commit": "b9185c75f7ec2b600ebe0d49281e216a2456b764", "tree": "7c310c3dd2e99f75488a9ad5bf93fde4752a13dc", "parents": [ "66a7752834382595d26214783ae4698fd1f00bd6" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Thu May 13 15:11:06 2021 +0200" }, "committer": { "name": "pali", "email": "pali@kernel.org", "time": "Tue Jun 01 16:32:10 2021 +0200" }, "message": "fix(plat/marvell/a3720/uart): fix configuring UART clock\n\nWhen configuring the UART_BAUD_REG register, the function\nconsole_a3700_core_init() currently only changes the baud divisor field,\nleaving other fields to their previous value.\n\nThis is incorrect, because the baud divisor is computed with the\nassumption that the parent clock rate is 25 MHz, and since the other\nfields in this register configure the parent clock, which could have\nbeen changed by U-Boot or Linux.\n\nFix this function to also configure the other fields so that the UART\nparent clock is selected to be the xtal clock.\n\nFor example without this change TF-A prints only\n\n ERROR: a3700_system_off needs to be implemented\n\nfollowed by garbage after plat_crash_console_init() is called.\n\nAfter applying this change instead of garbage it also print crash info:\n\n PANIC at PC : 0x0000000004023800\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81\n" }, { "commit": "4fe55a2fd8b7dbd00886ff4cc57429e16b99850e", "tree": "c9e7be403227783cd6694e5f913b5cfd70b7f14a", "parents": [ "fb88c71d2ad9189359cd92253e14d64639318e99", "66a7752834382595d26214783ae4698fd1f00bd6" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 16:13:11 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 16:13:11 2021 +0200" }, "message": "Merge \"fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation\" into integration" }, { "commit": "fb88c71d2ad9189359cd92253e14d64639318e99", "tree": "f797e688d7429bf9b86a151b9980b66294fe1ef2", "parents": [ "e4622d3cec77d0a05139d3a8524709f06f38d30e", "7eb42237575eb3f241c9b22efc5fe91368470aa6" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 15:36:16 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 15:36:16 2021 +0200" }, "message": "Merge \"feat(plat/mdeiatek/mt8195): add display port control in SiP service\" into integration" }, { "commit": "e4622d3cec77d0a05139d3a8524709f06f38d30e", "tree": "1a78ea0f084819266dc56e176f9881c8511ffd5f", "parents": [ "b35f8f2d1e8f49073a8d9516741da3313e123f61", "7a30e08b70e7fbb745554d500182bb6e258c5ab8" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue Jun 01 15:35:45 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jun 01 15:35:45 2021 +0200" }, "message": "Merge \"feat(plat/zynqmp): add support for XCK26 silicon\" into integration" }, { "commit": "7f2d23d9d790df90021de6c5165ef10fe5cc5590", "tree": "e0ca6d4be72bfc13ef33fc77e3493a7b80798c21", "parents": [ "b35f8f2d1e8f49073a8d9516741da3313e123f61" ], "author": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Thu May 20 16:23:22 2021 +0100" }, "committer": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Tue Jun 01 13:11:50 2021 +0100" }, "message": "fix(morello): initialise CNTFRQ in Non Secure CNTBaseN\n\nMorello exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ\ncan be written but does not reflect the value of the CNTFRQ register\nin CNTCTLBase frame. This doesn\u0027t follow ARM ARM in that the value\nupdated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ.\n\nHence enable the workaround (applied to Juno) for Morello that updates\nthe CNTFRQ register in the Non Secure CNTBaseN frame.\n\nChange-Id: Iabe53bf3c25152052107e08321323e4bde5fbef4\nSigned-off-by: Manoj Kumar \u003cmanoj.kumar3@arm.com\u003e\n" }, { "commit": "b35f8f2d1e8f49073a8d9516741da3313e123f61", "tree": "f5e62a567d72abd73e4652214a861bdeceead950", "parents": [ "2ea8d41979fe1ccf936b079b2271d588511b1c4a", "ca9324819ee308f9b3a4bb004f02a512c8f301f6" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Mon May 31 08:44:33 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 31 08:44:33 2021 +0200" }, "message": "Merge \"feat(tc0): add support for trusted services\" into integration" }, { "commit": "7a30e08b70e7fbb745554d500182bb6e258c5ab8", "tree": "757f7309cfd011f76629b8987620b284423f30d1", "parents": [ "e55d12b7eb771c2822872bc5f7bf00c0f128b83e" ], "author": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Wed Apr 21 21:54:48 2021 -0600" }, "committer": { "name": "Venkatesh Yadav Abbarapu", "email": "venkatesh.abbarapu@xilinx.com", "time": "Sun May 30 21:37:20 2021 -0600" }, "message": "feat(plat/zynqmp): add support for XCK26 silicon\n\nAdd support for XCK26 silicon which is available on SOM board.\n\nSigned-off-by: Michal Simek \u003cmichal.simek@xilinx.com\u003e\nSigned-off-by: Venkatesh Yadav Abbarapu \u003cvenkatesh.abbarapu@xilinx.com\u003e\nChange-Id: Ic98213328702903af8a79f487a2868f3e6d60338\n" }, { "commit": "2ea8d41979fe1ccf936b079b2271d588511b1c4a", "tree": "91b8dc62e2c55cf3bf345ffa2104a70d7389bba5", "parents": [ "0f7d2e89111a5bd06735bc4a41893aed3129ace7", "c6ac4df622befb5bb42ac136745094e1498c91d8" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri May 28 22:08:24 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 28 22:08:24 2021 +0200" }, "message": "Merge \"fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs\" into integration" }, { "commit": "c6ac4df622befb5bb42ac136745094e1498c91d8", "tree": "1ecee7e379dae91a461a4b36f90af001bd723caf", "parents": [ "0fd12b9e11e564a03ab3ab91d0b0a4aa62c279ec" ], "author": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Tue May 18 15:23:31 2021 -0500" }, "committer": { "name": "johpow01", "email": "john.powell@arm.com", "time": "Fri May 28 13:53:23 2021 -0500" }, "message": "fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs\n\nThis patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to\nCortex A710, Cortex X2, and Cortex A510 respectively.\n\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nChange-Id: I056d3114210db71c2840a24562b51caf2546e195\n" }, { "commit": "66a7752834382595d26214783ae4698fd1f00bd6", "tree": "8ff36976b83ddea3962dfbcf3f0e4af08ee83e98", "parents": [ "c158878249f1bd930906ebd744b90d3f2a8265f1" ], "author": { "name": "Pali Rohár", "email": "pali@kernel.org", "time": "Thu May 13 14:53:44 2021 +0200" }, "committer": { "name": "Marek Behun", "email": "marek.behun@nic.cz", "time": "Fri May 28 10:13:06 2021 +0100" }, "message": "fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation\n\nUART parent clock is by default the platform\u0027s xtal clock, which is\n25 MHz.\n\nThe value defined in the driver, though, is 25.8048 MHz. This is a hack\nfor the suboptimal divisor calculation\n Divisor \u003d UART clock / (16 * baudrate)\nwhich does not use rounding division, resulting in a suboptimal value\nfor divisor if the correct parent clock rate was used.\n\nChange the code for divisor calculation to\n Divisor \u003d Round(UART clock / (16 * baudrate))\nand change the parent clock rate value to 25 MHz.\n\nThe final UART divisor for default baudrate 115200 is not affected by\nthis change.\n\n(Note that the parent clock rate should not be defined via a macro,\nsince the xtal clock can also be 40 MHz. This is outside of the scope of\nthis fix, though.)\n\nSigned-off-by: Pali Rohár \u003cpali@kernel.org\u003e\nChange-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6\n" }, { "commit": "0f7d2e89111a5bd06735bc4a41893aed3129ace7", "tree": "75ddcce7abb7b60229e14f1dfe4a7ac997d530ce", "parents": [ "1f8dceeac1dfa9093eeef340987019664b887083", "9ed4e6fb669b8fcafc4e8acfa6a36db305d27ac8" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 27 16:56:28 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 27 16:56:28 2021 +0200" }, "message": "Merge \"fix(plat/mediatek/pmic_wrap): update idle flow\" into integration" }, { "commit": "1f8dceeac1dfa9093eeef340987019664b887083", "tree": "ac28719b9c444a1a1e9519a44fac16d9747eba9e", "parents": [ "e55d12b7eb771c2822872bc5f7bf00c0f128b83e", "7bd64c70e91f73a236b84fb51d5045e308479b5a" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 27 15:50:00 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 27 15:50:00 2021 +0200" }, "message": "Merge \"feat(plat/sgi): enable use of PSCI extended state ID format\" into integration" }, { "commit": "e55d12b7eb771c2822872bc5f7bf00c0f128b83e", "tree": "b485cd3f51e751e1e97e528d3609ced9d09ddd45", "parents": [ "b941145973e2c8fb2c0c968eae16ba108a4fcf21", "2d31cb079b28bb2bc52572c328c840129670b8b5" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu May 27 09:49:10 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 27 09:49:10 2021 +0200" }, "message": "Merge changes from topic \"Arm_PCI_Config_Space_Interface\" into integration\n\n* changes:\n TF-A: Document SMC_PCI_SUPPORT option\n SMCCC/PCI: Handle std svc boilerplate\n SMCCC/PCI: Add initial PCI conduit definitions\n SMCCC: Hoist SMC_32 sanitization\n" }, { "commit": "7bd64c70e91f73a236b84fb51d5045e308479b5a", "tree": "c4d4f1b65779f980719d2bf98e7d91388370e63f", "parents": [ "b941145973e2c8fb2c0c968eae16ba108a4fcf21" ], "author": { "name": "Pranav Madhu", "email": "pranav.madhu@arm.com", "time": "Tue Apr 20 12:01:46 2021 +0530" }, "committer": { "name": "Pranav Madhu", "email": "pranav.madhu@arm.com", "time": "Thu May 27 10:29:17 2021 +0530" }, "message": "feat(plat/sgi): enable use of PSCI extended state ID format\n\nThe SGI/RD platforms have been using PSCI state ID format as defined in\nPSCI version prior to 1.0. This is being changed and the PSCI extended\nstate ID format as defined in PSCI version 1.1 is being adapted. In\naddition to this, the use of Arm recommended PSCI state ID encoding is\nenabled as well.\n\nChange-Id: I2be8a9820987a96b23f4281563b6fa22db48fa5f\nSigned-off-by: Pranav Madhu \u003cpranav.madhu@arm.com\u003e\n" }, { "commit": "9ed4e6fb669b8fcafc4e8acfa6a36db305d27ac8", "tree": "488317de68306b47a3fa7f7c9294023601662294", "parents": [ "c51afaff0d7eb5c5cb38efaefa2481148edf1115" ], "author": { "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com", "time": "Wed May 05 15:15:51 2021 +0800" }, "committer": { "name": "hsin-hsiung.wang", "email": "hsin-hsiung.wang@mediatek.com", "time": "Thu May 27 02:13:37 2021 +0100" }, "message": "fix(plat/mediatek/pmic_wrap): update idle flow\n\nUpdate idle flow in case of last read command timeout.\n\nSigned-off-by: Hsin-Hsiung Wang \u003chsin-hsiung.wang@mediatek.com\u003e\nChange-Id: Idb0552d70d59b23822c38269d0fa9fe9ac0d6975\n" }, { "commit": "b941145973e2c8fb2c0c968eae16ba108a4fcf21", "tree": "e151b1247cb16d313946f674de0608f4da703b04", "parents": [ "fa4718031ae25bd17ea3a7b2d388e38ba5c4555a", "67fad514ee974dcf0252fa0e9219eb3c580eb714" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 27 00:45:41 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 27 00:45:41 2021 +0200" }, "message": "Merge \"fix(services): drop warning on unimplemented calls\" into integration" }, { "commit": "fa4718031ae25bd17ea3a7b2d388e38ba5c4555a", "tree": "61477604f265d405a942a73df40539f3cc6b8527", "parents": [ "8d4aa7d95b53f707ce5094493f94e184094a886c", "481c7b6b9107a3f71ee750f89cacdd8f9c729838" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed May 26 20:02:36 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 26 20:02:36 2021 +0200" }, "message": "Merge \"fix(docs): fix typos in v2.5 release documentation\" into integration" }, { "commit": "8d4aa7d95b53f707ce5094493f94e184094a886c", "tree": "e24aba572bce55a19682e9a69ef0e67cad3d8dd9", "parents": [ "3bb3157ab3dd8e35b2f851eddcbba32705dfbac4", "f46e1f18539d6d992c82ae605c2cd2a1d0757fa4" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed May 26 16:36:21 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 26 16:36:21 2021 +0200" }, "message": "Merge changes from topic \"mt8192-apu\" into integration\n\n* changes:\n feat(plat/mediatek/apu): add mt8192 APU device apc driver\n feat(plat/mediatek/apu): add mt8192 APU SiP call support\n feat(plat/mediatek/apu): add mt8192 APU iommap regions\n feat(plat/mediatek/apu): setup mt8192 APU_S_S_4 and APU_S_S_5 permission\n" }, { "commit": "3bb3157ab3dd8e35b2f851eddcbba32705dfbac4", "tree": "f811f3f7b5af2bc98472ad9057d8c68f628bf963", "parents": [ "99b5dd65bb75a10f596933f6ecbe17bf86da3736", "e8b119e03ad9de5fc440e5929287c94c22fc3946" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed May 26 15:54:28 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 26 15:54:28 2021 +0200" }, "message": "Merge \"feat(plat/sgi): enable AMU for RD-V1-MC\" into integration" }, { "commit": "99b5dd65bb75a10f596933f6ecbe17bf86da3736", "tree": "3537188d09e22045a6cb35408fac455c3698617a", "parents": [ "09e153a9a84bc05b41bc40116372b10ef21308c0", "e1e5b1339b9f73f7f1893d8a6d4dfe4b19ba0ad1" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed May 26 15:26:58 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 26 15:26:58 2021 +0200" }, "message": "Merge \"fix(plat/xilinx/versal/include): correct IPI buffer offset\" into integration" }, { "commit": "f46e1f18539d6d992c82ae605c2cd2a1d0757fa4", "tree": "d0200330deb2581efd61f9463bc36e3551a19580", "parents": [ "ca4c0c2e78eb19d442de4608d9096a755b540a37" ], "author": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Tue Apr 20 18:08:35 2021 +0800" }, "committer": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Wed May 26 12:40:02 2021 +0800" }, "message": "feat(plat/mediatek/apu): add mt8192 APU device apc driver\n\nAdd APU device apc driver and setup permission.\n\nSigned-off-by: Flora Fu \u003cflora.fu@mediatek.com\u003e\nChange-Id: I2bbdb69d11267e4252b2138b5c5ac8faf752740f\n" }, { "commit": "ca4c0c2e78eb19d442de4608d9096a755b540a37", "tree": "617dd0ea291eed14cfda1df7467d313458a49a64", "parents": [ "2671f3187249d641c55929c812d6691aeeff502a" ], "author": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Tue Apr 20 12:53:15 2021 +0800" }, "committer": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Wed May 26 12:29:32 2021 +0800" }, "message": "feat(plat/mediatek/apu): add mt8192 APU SiP call support\n\nAdd APU SiP call support for start/stop mcu.\n\nSigned-off-by: Flora Fu \u003cflora.fu@mediatek.com\u003e\nChange-Id: Ibf93d8ccf22c414de3093cee9e13f7668588f69e\nSigned-off-by: Pi-Cheng Chen \u003cpi-cheng.chen@mediatek.com\u003e\n" }, { "commit": "7eb42237575eb3f241c9b22efc5fe91368470aa6", "tree": "9a38204dabdb7ea2b04f4b7756adecceb621637b", "parents": [ "0fd12b9e11e564a03ab3ab91d0b0a4aa62c279ec" ], "author": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.corp-partner.google.com", "time": "Mon Apr 12 11:10:31 2021 +0800" }, "committer": { "name": "Rex-BC Chen", "email": "rex-bc.chen@mediatek.com", "time": "Wed May 26 02:13:56 2021 +0100" }, "message": "feat(plat/mdeiatek/mt8195): add display port control in SiP service\n\nMTK display port mute/unmute control registers need to be\nset in secure world.\n\nSigned-off-by: Rex-BC Chen \u003crex-bc.chen@mediatek.com\u003e\nChange-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3\n" }, { "commit": "481c7b6b9107a3f71ee750f89cacdd8f9c729838", "tree": "d721a254d4a329bfe02355008e7ccb32b106f8c8", "parents": [ "09e153a9a84bc05b41bc40116372b10ef21308c0" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue May 25 15:15:10 2021 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Tue May 25 17:18:11 2021 -0500" }, "message": "fix(docs): fix typos in v2.5 release documentation\n\nTwo issues in documentation were identified after the release.\nThis patch fixes these typos.\n\n1. Matternhorn ELP CPU was made available through v2.5 release, not\n Matternhorn CPU\n2. We had upgraded TF-A to use GCC 10.2 toolchain family and used this\n toolchain for release testing\n\nChange-Id: I33e59bb5a6d13f4d40dbb3352004d5b133431d65\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "e1e5b1339b9f73f7f1893d8a6d4dfe4b19ba0ad1", "tree": "3537188d09e22045a6cb35408fac455c3698617a", "parents": [ "09e153a9a84bc05b41bc40116372b10ef21308c0" ], "author": { "name": "Rajan Vaja", "email": "rajan.vaja@xilinx.com", "time": "Tue Apr 20 02:53:01 2021 -0700" }, "committer": { "name": "Abhyuday Godhasara", "email": "abhyuday.godhasara@xilinx.com", "time": "Tue May 25 07:02:49 2021 -0700" }, "message": "fix(plat/xilinx/versal/include): correct IPI buffer offset\n\nUse proper offset for IPI data based on offset for IPI0\nchannel.\n\nSigned-off-by: Rajan Vaja \u003crajan.vaja@xilinx.com\u003e\nSigned-off-by: Abhyuday Godhasara \u003cabhyuday.godhasara@xilinx.com\u003e\nChange-Id: I3070517944dd353c3733aa595df0da030127751a\n" }, { "commit": "2d31cb079b28bb2bc52572c328c840129670b8b5", "tree": "71bb966df4970b42c9e602aaffbd41dbee33b98d", "parents": [ "1cdf1eb875ec8622e94493c0a99d21f2e0adeac8" ], "author": { "name": "Jeremy Linton", "email": "jeremy.linton@arm.com", "time": "Tue Jan 26 22:42:03 2021 -0600" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue May 25 14:49:15 2021 +0200" }, "message": "TF-A: Document SMC_PCI_SUPPORT option\n\nAdd some basic documentation and pointers for the SMCCC PCI\nbuild options.\n\nSigned-off-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\nChange-Id: Ia35f31d15066ea74135367cde2dce2f26e6ab31e\n" }, { "commit": "1cdf1eb875ec8622e94493c0a99d21f2e0adeac8", "tree": "482f30bd651959de020d9a98c9f7bc2657886b7e", "parents": [ "c7a28aa7988be1664a7c06726bd3ff9acfa19e29" ], "author": { "name": "Jeremy Linton", "email": "jeremy.linton@arm.com", "time": "Wed Nov 18 10:17:57 2020 -0600" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue May 25 14:49:08 2021 +0200" }, "message": "SMCCC/PCI: Handle std svc boilerplate\n\nAdd SMC wrappers for handshaking the existence\nand basic parameter validation for the SMCCC/PCI\nAPI. The actual read/write/segment validation is\nimplemented by a given platform which will enable\nthe API by defining SMC_PCI_SUPPORT.\n\nSigned-off-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\nChange-Id: I4485ad0fe6003cec6f5eedef688914d100513c21\n" }, { "commit": "c7a28aa7988be1664a7c06726bd3ff9acfa19e29", "tree": "da9c41da73192b6902dc91761007cc7cf709421e", "parents": [ "475333c8a9bf027dfb64dff7fe61fd0729548d2a" ], "author": { "name": "Jeremy Linton", "email": "jeremy.linton@arm.com", "time": "Wed Nov 18 10:12:41 2020 -0600" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue May 25 14:49:01 2021 +0200" }, "message": "SMCCC/PCI: Add initial PCI conduit definitions\n\nAdd constants, structures and build definition for the\nnew standard SMCCC PCI conduit. These are documented\nin DEN0115A.\n\nhttps://developer.arm.com/documentation/den0115/latest\n\nSigned-off-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\nChange-Id: If667800a26b9ae88626e8d895674c9c2e8c09658\n" }, { "commit": "475333c8a9bf027dfb64dff7fe61fd0729548d2a", "tree": "823caea181a38bf3f1399d2ac69ca57a3cac8310", "parents": [ "09e153a9a84bc05b41bc40116372b10ef21308c0" ], "author": { "name": "Jeremy Linton", "email": "jeremy.linton@arm.com", "time": "Thu Apr 01 13:10:24 2021 -0500" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Tue May 25 14:48:56 2021 +0200" }, "message": "SMCCC: Hoist SMC_32 sanitization\n\nThe SMCCC, part 3 indicates that only the bottom\n32-bits of a 32-bit SMC call are valid. The upper\nbits must be zero. Lets enforce that so standard\nservice code can assume its been called that way.\n\nSigned-off-by: Jeremy Linton \u003cjeremy.linton@arm.com\u003e\nChange-Id: I1bac50fbdc3b6ddca5fe2d1d1f96166a65ac4eb4\n" }, { "commit": "2671f3187249d641c55929c812d6691aeeff502a", "tree": "54c821bae28dd0c7e90995ead36024dcb0eac02c", "parents": [ "77b6801966d203e09ca118fad42543e934d73e6f" ], "author": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Tue Apr 20 11:23:21 2021 +0800" }, "committer": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Tue May 25 14:49:30 2021 +0800" }, "message": "feat(plat/mediatek/apu): add mt8192 APU iommap regions\n\nAdd APU iommap settings for reviser, apu_ao and\ndevapc control wrapper.\n\nSigned-off-by: Flora Fu \u003cflora.fu@mediatek.com\u003e\nChange-Id: Ie8e6a197c0f440f9e4ee8101202283a2dbf501a6\n" }, { "commit": "77b6801966d203e09ca118fad42543e934d73e6f", "tree": "135bbb785a9c2677895cdfed5ab25000a5660548", "parents": [ "c3ce73be0bfe31fa28805fe92b3e727232ffd37a" ], "author": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Tue Apr 20 11:45:56 2021 +0800" }, "committer": { "name": "Flora Fu", "email": "flora.fu@mediatek.com", "time": "Tue May 25 14:48:58 2021 +0800" }, "message": "feat(plat/mediatek/apu): setup mt8192 APU_S_S_4 and APU_S_S_5 permission\n\nSetup APU_S_S_4/APU_S_S_5 permission as SEC_RW_ONLY.\n\nSigned-off-by: Flora Fu \u003cflora.fu@mediatek.com\u003e\nChange-Id: I6c50b2913bf34270a1b0ffaf0e0c435fee192a4c\n" }, { "commit": "09e153a9a84bc05b41bc40116372b10ef21308c0", "tree": "f4119363801637684fc29df7349ba454aa329b89", "parents": [ "0fd12b9e11e564a03ab3ab91d0b0a4aa62c279ec", "a1cedadf73863ff103fecd64fa188334e1541337" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Mon May 24 17:47:18 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 24 17:47:18 2021 +0200" }, "message": "Merge \"feat(hw_crc): add support for HW computed CRC\" into integration" }, { "commit": "9ce232fe985a0bb308af459ede8a22629255d4e7", "tree": "b54706923eade670bdbb35b1347a17443f5034f6", "parents": [ "7bcb8ad260b1e6c45113c575e3be9ecd19c2a4e1" ], "author": { "name": "Igor Opaniuk", "email": "igor.opaniuk@foundries.io", "time": "Wed Mar 10 13:42:55 2021 +0200" }, "committer": { "name": "Igor Opaniuk", "email": "igor.opaniuk@foundries.io", "time": "Fri May 21 15:01:38 2021 +0300" }, "message": "feat(plat/imx8m): add SiP call for secondary boot\n\nIn iMX8MM it is possible to have two copies of bootloader in\nSD/eMMC and switch between them. The switch is triggered either\nby the BootROM in case the bootloader image is faulty OR can be\nenforced by the user. To trigger that switch the\nPERSIST_SECONDARY_BOOT bit should be set in GPR10 SRC register.\nAs the bit is retained after WARM reset, that permits to control\nBootROM behavior regarding what boot image it will boot after\nreset: primary or secondary.\n\nThis is useful for reliable bootloader A/B updates, as it permits\nswitching between two copies of bootloader at different offsets of\nthe same storage.\n\nIf the PERSIST_SECONDARY_BOOT is 0, the boot ROM uses address\n0x8400 for the primary image. If the PERSIST_SECONDARY_BOOT is 1,\nthe boot ROM reads that secondary image table from address 0x8200\non the boot media and uses the address specified in the table for\nthe secondary image.\n\nSecondary Image Table contains the sector of secondary bootloader\nimage, exluding the offset to that image (explained below in the\nnote). To generate the Secondary Image Table, use e.g.:\n$ printf \u0027\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x0\\x33\\x22\\x11\u0027\n \u0027\\x00\\x00\\x10\\x0\\x0\\x00\\x0\\x0\\x0\u0027\n \u003e /tmp/sit.bin\n$ hexdump -vC /tmp/sit.bin\n 00000000 00 00 00 00\n 00000004 00 00 00 00\n 00000008 33 22 11 00 \u003c--- This is the \"tag\"\n 0000000c 00 10 00 00 \u003c--- This is the \"firstSectorNumber\"\n 00000010 00 00 00 00\n\nYou can also use NXP script from [1][2] imx-mkimage tool for\nSIT generation. Note that the firstSectorNumber is NOT the offset\nof the IVT, but an offset of the IVT decremented by Image Vector\nTable offset (Table 6-25. Image Vector Table Offset and Initial\nLoad Region Size for iMX8MM/MQ), so for secondary SPL copy at\noffset 0x1042 sectors, firstSectorNumber must be 0x1000\n(0x42 sectors * 512 \u003d 0x8400 bytes offset).\n\nIn order to test redundant boot board should be closed and\nSD/MMC manufacture mode disabled, as secondary boot is not\nsupported in the SD/MMC manufacture mode, which can be disabled\nby blowing DISABLE_SDMMC_MFG (example for iMX8MM):\n\u003e fuse prog -y 2 1 0x00800000\n\nFor additional details check i.MX 8M Mini Apllication Processor\nReference Manual, 6.1.5.4.5 Redundant boot support for\nexpansion device chapter.\n\n[1] https://source.codeaurora.org/external/imx/imx-mkimage/\n[2] scripts/gen_sit.sh\nChange-Id: I0a5cea7295a4197f6c89183d74b4011cada52d4c\nSigned-off-by: Igor Opaniuk \u003cigor.opaniuk@foundries.io\u003e\n" }, { "commit": "0fd12b9e11e564a03ab3ab91d0b0a4aa62c279ec", "tree": "2650fd6437a990b9a58ad04f5d1a112b787ab347", "parents": [ "c158878249f1bd930906ebd744b90d3f2a8265f1", "63ca6bbad8d68ab93ee382e2012b396174d21fd6" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Thu May 20 17:06:23 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 20 17:06:23 2021 +0200" }, "message": "Merge \"refactor(juno): disable non-invasive debug of secure state\" into integration" }, { "commit": "a1cedadf73863ff103fecd64fa188334e1541337", "tree": "4e8b51fdf8bab46f4f4d8d488cbfef1e45d330ff", "parents": [ "1e13c500a0351ac4b55d09a63f7008e2438550f8" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Apr 22 14:41:27 2021 +0100" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed May 19 19:34:34 2021 +0100" }, "message": "feat(hw_crc): add support for HW computed CRC\n\nAdded support for HW computed CRC using Arm ACLE intrinsics.\nThese are built-in intrinsics available for ARMv8.1-A, and\nonwards.\nThese intrinsics are enabled via \u0027-march\u003darmv8-a+crc\u0027 compile\nswitch for ARMv8-A (supports CRC instructions optionally).\n\nHW CRC support is enabled unconditionally in BL2 for all Arm\nplatforms.\n\nHW CRC calculation is verified offline to ensure a similar\nresult as its respective ZLib utility function.\n\nHW CRC calculation support will be used in the upcoming\nfirmware update patches.\n\nChange-Id: Ia2ae801f62d2003e89a9c3e6d77469b5312614b3\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "63ca6bbad8d68ab93ee382e2012b396174d21fd6", "tree": "cb1059b98eafa33dead7d1cb014e93804bbf4a35", "parents": [ "57dde21207c7fecbb78c2019a71ffb65ca740dc3" ], "author": { "name": "Zelalem", "email": "zelalem.aweke@arm.com", "time": "Thu May 13 15:10:03 2021 -0500" }, "committer": { "name": "Zelalem", "email": "zelalem.aweke@arm.com", "time": "Mon May 17 10:19:26 2021 -0500" }, "message": "refactor(juno): disable non-invasive debug of secure state\n\nDisable non-invasive debug of secure state for Juno\nin release builds. This makes sure that PMU counts\nonly Non-secure events.\n\nSigned-off-by: Zelalem Aweke \u003czelalem.aweke@arm.com\u003e\nChange-Id: I0d1c3f96f3b4e48360a7211ae55851d65d291025\n" }, { "commit": "c158878249f1bd930906ebd744b90d3f2a8265f1", "tree": "c357c9718914791517d8700cf08b15e1bcf076da", "parents": [ "1e13c500a0351ac4b55d09a63f7008e2438550f8", "a4371d1c4b35f8c9fe63365f4282883420842dda" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon May 17 16:41:24 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon May 17 16:41:24 2021 +0200" }, "message": "Merge changes I10b5cc17,I382d599f into integration\n\n* changes:\n docs(prerequisites): add `--no-save` to `npm install`\n fix(hooks): downgrade `package-lock.json` version\n" }, { "commit": "a4371d1c4b35f8c9fe63365f4282883420842dda", "tree": "f1ded9a594d87e4b3c39455df50d586f75216e80", "parents": [ "7434b65208175bdf3f44e0e62aaaeabc9c494ee3" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon May 17 11:18:56 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon May 17 11:21:42 2021 +0100" }, "message": "docs(prerequisites): add `--no-save` to `npm install`\n\nTo avoid the mistake fixed by the previous commit, ensure users install\nthe Node.js dependencies without polluting the lock file by passing\n`--no-save` to the `npm install` line.\n\nChange-Id: I10b5cc17b9001fc2e26deee02bf99ce033a949c1\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "7434b65208175bdf3f44e0e62aaaeabc9c494ee3", "tree": "8d4fae5d597ab7c6a89b4f29b5bd0299aa43e371", "parents": [ "7fff6c70ed9de55ace9cccc1d9b65375bcdc33e3" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon May 17 11:13:42 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Mon May 17 11:17:06 2021 +0100" }, "message": "fix(hooks): downgrade `package-lock.json` version\n\nThe NPM lock file was accidentally updated using a later version of\nNode.js than required by the prerequisites. This upgraded the lock file\nto the v2 format, which causes a warning on Node.js 14 (the\nprerequisites version). This moves the lock file back to v1 by\ninstalling the dependencies with Node.js 14.\n\nChange-Id: I382d599fd2b67b07eb9234d14e7b631db6b11453\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "1e13c500a0351ac4b55d09a63f7008e2438550f8", "tree": "8556dd56364038109e9f13ea5fba171169a83db1", "parents": [ "c72b2c7a1125e6efb8ab338f7870850ff5a50e0f", "ff2da9e331c7bbc91aed5582d61fe47f94c94179" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri May 14 17:56:37 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 14 17:56:37 2021 +0200" }, "message": "Merge \"feat(makefile): incrementing minor version to reflect v2.5 release\" into integration" }, { "commit": "c72b2c7a1125e6efb8ab338f7870850ff5a50e0f", "tree": "acfb5909d752148a513917e51a6ac33240d631b5", "parents": [ "304c96207462f74002f4160fc83cbb74f29bd422", "92473b3be04fc5409ae27e8160a870221ea79fd5" ], "author": { "name": "bipin.ravi", "email": "bipin.ravi@arm.com", "time": "Fri May 14 16:30:55 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 14 16:30:55 2021 +0200" }, "message": "Merge \"docs(juno): update TF-A build instructions\" into integration" }, { "commit": "304c96207462f74002f4160fc83cbb74f29bd422", "tree": "c537a118a86830aedf2e14a724b9a1b44b6069cc", "parents": [ "96404aa27efbf1c9051d515075a60c3cf4fa47be", "b5dd2422a043b2f6166e530574d9bde45ee84b98" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri May 14 15:49:25 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 14 15:49:25 2021 +0200" }, "message": "Merge \"docs: spm design document refresh\" into integration" }, { "commit": "96404aa27efbf1c9051d515075a60c3cf4fa47be", "tree": "994f14289b705cb693f5493bd0a36773f0c471bd", "parents": [ "d506b558c0f3f7d1e9c1fc1ccb5982405137cf0a", "7fff6c70ed9de55ace9cccc1d9b65375bcdc33e3" ], "author": { "name": "Joanna Farley", "email": "joanna.farley@arm.com", "time": "Thu May 13 18:27:27 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 13 18:27:27 2021 +0200" }, "message": "Merge \"build(hooks): update Commitizen to ^4.2.4\" into integration" }, { "commit": "d506b558c0f3f7d1e9c1fc1ccb5982405137cf0a", "tree": "f0b554e8ffa06f6fbe4b5fadd4fa983726840589", "parents": [ "57dde21207c7fecbb78c2019a71ffb65ca740dc3", "b9a5706c07bc8e170827ba0b89089b0449baf505" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu May 13 15:15:17 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu May 13 15:15:17 2021 +0200" }, "message": "Merge \"docs(release): add change log for v2.5 release\" into integration" }, { "commit": "92473b3be04fc5409ae27e8160a870221ea79fd5", "tree": "796bdea42c23cffa284480323a8a6ff3f9316a20", "parents": [ "57dde21207c7fecbb78c2019a71ffb65ca740dc3" ], "author": { "name": "Zelalem", "email": "zelalem.aweke@arm.com", "time": "Wed May 12 20:41:54 2021 -0500" }, "committer": { "name": "Zelalem", "email": "zelalem.aweke@arm.com", "time": "Wed May 12 20:53:30 2021 -0500" }, "message": "docs(juno): update TF-A build instructions\n\nClean up instructions for building/running TF-A on the\nJuno platform and add correct link to SCP binaries.\n\nSigned-off-by: Zelalem Aweke \u003czelalem.aweke@arm.com\u003e\nChange-Id: I536f98082e167edbf45f29ca23cc0db44687bb3b\n" }, { "commit": "ff2da9e331c7bbc91aed5582d61fe47f94c94179", "tree": "c370b3d6da017e54398e33fdc0a15928e0ef765e", "parents": [ "57dde21207c7fecbb78c2019a71ffb65ca740dc3" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed May 12 16:44:08 2021 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed May 12 16:52:33 2021 -0500" }, "message": "feat(makefile): incrementing minor version to reflect v2.5 release\n\nUpdated the minor version in the makefile\n\nChange-Id: Ie2b3ce5b36a105a0e2fff52c3740cc9702ca3108\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "7fff6c70ed9de55ace9cccc1d9b65375bcdc33e3", "tree": "d5fe5490f3fbbb4a2849670c38e8986e36e61aec", "parents": [ "57dde21207c7fecbb78c2019a71ffb65ca740dc3" ], "author": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Wed May 12 15:22:42 2021 +0100" }, "committer": { "name": "Chris Kay", "email": "chris.kay@arm.com", "time": "Wed May 12 15:43:56 2021 +0100" }, "message": "build(hooks): update Commitizen to ^4.2.4\n\nAn indirect dependency of Commitizen (`merge`) is currently failing the\nNPM.js auditor due to vulnerability CVE-2020-28499. This commit moves\nthe minimum version of Commitizen to 4.2.4, which has resolved this\nvulnerability.\n\nChange-Id: Ia9455bdbe02f7406c1a106f173c4095943a201ed\nSigned-off-by: Chris Kay \u003cchris.kay@arm.com\u003e\n" }, { "commit": "b5dd2422a043b2f6166e530574d9bde45ee84b98", "tree": "d0ef9cc5e3a72968731f5812cd33629f9117398d", "parents": [ "57dde21207c7fecbb78c2019a71ffb65ca740dc3" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 30 14:42:24 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed May 12 15:45:27 2021 +0200" }, "message": "docs: spm design document refresh\n\nGeneral refresh of the SPM document.\n\nChange-Id: I2f8e37c3f34bc8511b115f00b9a53b6a6ff41bea\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\n" }, { "commit": "ca9324819ee308f9b3a4bb004f02a512c8f301f6", "tree": "e549199d06a0b9e35ecec4e3023940cb23ef9bdd", "parents": [ "6794378d2e955d2bf378ff2aa726a29d5884dc1f" ], "author": { "name": "Davidson K", "email": "davidson.kumaresan@arm.com", "time": "Wed Mar 10 12:07:15 2021 +0530" }, "committer": { "name": "Davidson K", "email": "davidson.kumaresan@arm.com", "time": "Mon May 10 18:39:37 2021 +0530" }, "message": "feat(tc0): add support for trusted services\n\nThis patch adds support for the crypto and secure storage secure\npartitions for the Total Compute platform. These secure partitions\nhave to be managed by Hafnium executing at S-EL2\n\nChange-Id: I2df690e3a99bf6bf50e2710994a905914a07026e\nSigned-off-by: Davidson K \u003cdavidson.kumaresan@arm.com\u003e\n" }, { "commit": "b9a5706c07bc8e170827ba0b89089b0449baf505", "tree": "ff137a5d09f2a2fc52e9d22d05f3f7934eea413a", "parents": [ "08532d75c076a994dd63c4c341babbfb23393eed" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Thu Apr 29 18:01:41 2021 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri May 07 10:35:36 2021 -0500" }, "message": "docs(release): add change log for v2.5 release\n\nChange log for trusted-firmware-a v2.5 release\n\nChange-Id: I6ffc8a40d2cc3a18145b87f895acdc1400db485a\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" }, { "commit": "57dde21207c7fecbb78c2019a71ffb65ca740dc3", "tree": "6ad1d761b125b6f948af20e12eb5f0d4e44f3d0f", "parents": [ "c51afaff0d7eb5c5cb38efaefa2481148edf1115", "c3ce73be0bfe31fa28805fe92b3e727232ffd37a" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Fri May 07 17:03:01 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri May 07 17:03:01 2021 +0200" }, "message": "Merge \"fix(plat/arm_fpga): increase initrd size\" into integration" }, { "commit": "c51afaff0d7eb5c5cb38efaefa2481148edf1115", "tree": "b994e58855d49a1776c6aaabe57be484ee3462b0", "parents": [ "a45e0580b3664fd7b80aeffb4051583d3a9c8580", "e3bb8666a3b01e1e62527f316b3c28b651ec72d9" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed May 05 20:49:33 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed May 05 20:49:33 2021 +0200" }, "message": "Merge \"docs: removing \"upcoming\" change log\" into integration" }, { "commit": "e3bb8666a3b01e1e62527f316b3c28b651ec72d9", "tree": "2b0e474c6fcf69cc5b0a3d5f434a5593fb075a37", "parents": [ "08532d75c076a994dd63c4c341babbfb23393eed" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed May 05 12:07:19 2021 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Wed May 05 12:08:45 2021 -0500" }, "message": "docs: removing \"upcoming\" change log\n\nRemoving the \"Upcoming\" change log due to the change in change log\nprocessing.\n\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\nChange-Id: I6d2cc095dca3e654bd7e6fec2077c58bfbc48bb5\n" }, { "commit": "c3ce73be0bfe31fa28805fe92b3e727232ffd37a", "tree": "cd1eb2041b2e20a6cde27480a08aa704d92599cd", "parents": [ "08532d75c076a994dd63c4c341babbfb23393eed" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 05 13:00:23 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed May 05 13:23:01 2021 +0100" }, "message": "fix(plat/arm_fpga): increase initrd size\n\nIn the comment in the ARM FPGA DT we promise a generous 100 MB initrd,\nbut actually describe only a size of 20 MB.\n\nAs initrds are the most common and easy userland option for the boards,\nlet\u0027s increase the maximum size to the advertised 100 MB, to avoid\nunpacking errors when an initrd exceeds the current limit of 20 MB.\n\nChange-Id: If08ba3fabdad27b2c2aff93b18c3f664728b4348\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "a45e0580b3664fd7b80aeffb4051583d3a9c8580", "tree": "61ac137a7bb12bd0853c24ffb51a2e7ae67d282f", "parents": [ "08532d75c076a994dd63c4c341babbfb23393eed", "9cfb878f952874ddfa2c188d574c3389ec488cf1" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Tue May 04 20:54:59 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue May 04 20:54:59 2021 +0200" }, "message": "Merge \"docs: revert FVP versions for select models\" into integration" }, { "commit": "9cfb878f952874ddfa2c188d574c3389ec488cf1", "tree": "61ac137a7bb12bd0853c24ffb51a2e7ae67d282f", "parents": [ "08532d75c076a994dd63c4c341babbfb23393eed" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue May 04 10:23:14 2021 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue May 04 10:24:44 2021 -0500" }, "message": "docs: revert FVP versions for select models\n\nReverting FVP versions to previous version 11.12.38 for Cortex-A32x4\nand Neoverse-N2x4.\n\nChange-Id: I81e8ad24794dd425a9e9a66dc8bb02b42191abf1\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\n" }, { "commit": "67fad514ee974dcf0252fa0e9219eb3c580eb714", "tree": "018f9f34aab140c2e833ba06cc468b45d636efbf", "parents": [ "08e7cc533e5a019b53e466a3e03eb646980710fa" ], "author": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Wed Apr 28 15:59:21 2021 +0100" }, "committer": { "name": "Andre Przywara", "email": "andre.przywara@arm.com", "time": "Tue May 04 10:30:15 2021 +0100" }, "message": "fix(services): drop warning on unimplemented calls\n\nStandard Secure Services, complying to the SMCCC specification, are\ndiscoverable: Any user can do the SMC call, and derive from the return\nvalue (-1) if the service is implemented. Consequently we should not\n*warn* if BL31 does not implement a service, as some services (TRNG, for\ninstance) might never be implemented for devices, as they are lacking\nhardware.\n\nShort of dropping the existing warning message altogether, change the\nlevel to VERBOSE, which should prevent it actually being printed in\nnormal situations.\n\nThis removes the pointless TF-A messages on the console when booting\nLinux, as modern kernels now call the SOCID and the TRNG service\nunconditionally.\n\nChange-Id: I08b0b02e0f46322ebe0b40b3991c3c9b5bed4f97\nSigned-off-by: Andre Przywara \u003candre.przywara@arm.com\u003e\n" }, { "commit": "e8b119e03ad9de5fc440e5929287c94c22fc3946", "tree": "085cb554b83be3cd5329d926e5d7437aea397ff1", "parents": [ "6794378d2e955d2bf378ff2aa726a29d5884dc1f" ], "author": { "name": "Pranav Madhu", "email": "pranav.madhu@arm.com", "time": "Tue Mar 23 11:04:08 2021 +0530" }, "committer": { "name": "Pranav Madhu", "email": "pranav.madhu@arm.com", "time": "Mon May 03 23:01:03 2021 +0530" }, "message": "feat(plat/sgi): enable AMU for RD-V1-MC\n\nAMU counters are used for monitoring the CPU performance. RD-V1-MC\nplatform has architected AMU available for each core. Enable the use of\nAMU by non-secure OS for supporting the use of counters for processor\nperformance control (ACPI CPPC).\n\nChange-Id: I33be594cee669e7f4031e5e5a371eec7c7451030\nSigned-off-by: Pranav Madhu \u003cpranav.madhu@arm.com\u003e\n" }, { "commit": "08532d75c076a994dd63c4c341babbfb23393eed", "tree": "094ab8236681cd477e4ef6b9086b7e28d91afb05", "parents": [ "9738cf96883db549139bff1eac828e9a4ca0f711", "6f09bcced3c4b7b2a3e6d54a8d509b70d7eaa5d0" ], "author": { "name": "Lauren Wehrmeister", "email": "lauren.wehrmeister@arm.com", "time": "Fri Apr 30 21:00:28 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 21:00:28 2021 +0200" }, "message": "Merge \"docs: update list of supported FVP platforms\" into integration" }, { "commit": "9738cf96883db549139bff1eac828e9a4ca0f711", "tree": "31b31649bbe7426c116ddc76bb46bd9890d89c43", "parents": [ "44de593d196dc5a81adfd44c9983c00da08520a9", "7006f208b65676d08c70ecb0608895e544b593a1" ], "author": { "name": "bipin.ravi", "email": "bipin.ravi@arm.com", "time": "Fri Apr 30 19:00:19 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 19:00:19 2021 +0200" }, "message": "Merge \"docs(threat model): add TF-A threat model\" into integration" }, { "commit": "7006f208b65676d08c70ecb0608895e544b593a1", "tree": "31b31649bbe7426c116ddc76bb46bd9890d89c43", "parents": [ "44de593d196dc5a81adfd44c9983c00da08520a9" ], "author": { "name": "Zelalem", "email": "zelalem.aweke@arm.com", "time": "Wed Feb 24 19:20:09 2021 -0600" }, "committer": { "name": "Zelalem Aweke", "email": "zelalem.aweke@arm.com", "time": "Fri Apr 30 17:59:22 2021 +0200" }, "message": "docs(threat model): add TF-A threat model\n\nThis is the first release of the public Trusted\nFirmware A class threat model. This release\nprovides the baseline for future updates to be\napplied as required by developments to the\nTF-A code base.\n\nSigned-off-by: Zelalem Aweke \u003czelalem.aweke@arm.com\u003e\nChange-Id: I3c9aadc46196837679f0b1377bec9ed4fc42ff11\n" }, { "commit": "6f09bcced3c4b7b2a3e6d54a8d509b70d7eaa5d0", "tree": "7e29865c787b98f0eb0465730f6c3f39ac6b3bb7", "parents": [ "08e7cc533e5a019b53e466a3e03eb646980710fa" ], "author": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Tue Apr 27 13:58:06 2021 -0500" }, "committer": { "name": "laurenw-arm", "email": "lauren.wehrmeister@arm.com", "time": "Fri Apr 30 10:33:41 2021 -0500" }, "message": "docs: update list of supported FVP platforms\n\nUpdated the list of supported FVP platforms as per the latest FVP\nrelease.\n\nChange-Id: I1abd0a7885b1133715062ee1b176733556a4820e\nSigned-off-by: Lauren Wehrmeister \u003clauren.wehrmeister@arm.com\u003e\n" }, { "commit": "44de593d196dc5a81adfd44c9983c00da08520a9", "tree": "1eb0085268e005ab8a475dbcbf988e95774d572c", "parents": [ "711505f045cb02092ffb756000871a185e9b7b0b", "f714ca80b8e3dc4e953b8728fc7b9457094b2a12" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Apr 30 13:04:23 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 13:04:23 2021 +0200" }, "message": "Merge \"plat/st: do not rely on tainted value for dt property length\" into integration" }, { "commit": "711505f045cb02092ffb756000871a185e9b7b0b", "tree": "c896d728e149e8e12902dbc6cc11d96a77f4642e", "parents": [ "dd6efc9ea52e9dbfaeacbb439abbc0f8ecddd89c", "7f9390d3a3ffc76ea23853920ae31ecdcd68d1d4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Apr 30 13:01:48 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 13:01:48 2021 +0200" }, "message": "Merge changes from topic \"imx8mp_fix\" into integration\n\n* changes:\n plat: imx8mp: change the bl31 physical load address\n plat: imx8m: Fix the macro define error\n" }, { "commit": "7f9390d3a3ffc76ea23853920ae31ecdcd68d1d4", "tree": "c896d728e149e8e12902dbc6cc11d96a77f4642e", "parents": [ "8c72a7ab20355b48070caa834211ef3474f899a2" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Thu Oct 22 16:18:51 2020 +0800" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Apr 30 12:28:41 2021 +0200" }, "message": "plat: imx8mp: change the bl31 physical load address\n\non i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K,\ncurrently, OCRAM @0x960000-0x980000 is reserved for BL31, it will\nleave the last 64KB in non-continuous space. To provide a continuous\n384KB + 64KB space for generic use, so move the BL31 space to\n0x970000-0x990000 range.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I96d572fc0f87f05a60f55e0552a68b6e70f8e7f4\n" }, { "commit": "8c72a7ab20355b48070caa834211ef3474f899a2", "tree": "6ed6bb5a128f4518c738c518e9e1af8d86ec67b9", "parents": [ "dd6efc9ea52e9dbfaeacbb439abbc0f8ecddd89c" ], "author": { "name": "Jacky Bai", "email": "ping.bai@nxp.com", "time": "Tue Aug 11 15:56:29 2020 +0800" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Apr 30 12:28:37 2021 +0200" }, "message": "plat: imx8m: Fix the macro define error\n\nthe \u0027always_on\u0027 member should be initialized from \u0027on\u0027.\n\nSigned-off-by: Jacky Bai \u003cping.bai@nxp.com\u003e\nChange-Id: I5746ff40075b4fcda2ac7d04a8d7f1269af17e91\n" }, { "commit": "dd6efc9ea52e9dbfaeacbb439abbc0f8ecddd89c", "tree": "56eaafebb56112c237f6e44ea48bacab15f14b9e", "parents": [ "674803667e9c4774af2f5c85a1d4cc96ef3cc005", "3dd87efb2e63249c7896dcae5324e1303bfc7b40" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Apr 30 12:23:04 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 12:23:04 2021 +0200" }, "message": "Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration\n\n* changes:\n plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0\n plat: ti: k3: board: Lets cast our macros\n plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing\n plat: ti: k3: platform_def.h: Define the correct number of max table entries\n plat: ti: k3: board: lite: Increase SRAM size to account for additional table\n" }, { "commit": "674803667e9c4774af2f5c85a1d4cc96ef3cc005", "tree": "ec10ebc433c1f9c54fff55817a1792b63b2e2bc9", "parents": [ "5c3bcfcdf42505c36a9b0f12028aa62c36ba0ca2", "a2f6294c98935895d4592ef7e30058ca6e995f4b" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 30 11:12:54 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 11:12:54 2021 +0200" }, "message": "Merge \"feat(tc0): update Matterhorn ELP DVFS clock index\" into integration" }, { "commit": "a2f6294c98935895d4592ef7e30058ca6e995f4b", "tree": "ec10ebc433c1f9c54fff55817a1792b63b2e2bc9", "parents": [ "5c3bcfcdf42505c36a9b0f12028aa62c36ba0ca2" ], "author": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Wed Apr 07 11:48:22 2021 +0100" }, "committer": { "name": "Usama Arif", "email": "usama.arif@arm.com", "time": "Fri Apr 30 10:39:08 2021 +0200" }, "message": "feat(tc0): update Matterhorn ELP DVFS clock index\n\nThis allows the the Matterhorn ELP Arm core to operate at its\ndesignated OPP.\n\nSigned-off-by: Usama Arif \u003cusama.arif@arm.com\u003e\nChange-Id: I7ccef0cfd079d630c3cfe7874590bf42789a1dca\n" }, { "commit": "5c3bcfcdf42505c36a9b0f12028aa62c36ba0ca2", "tree": "41abd9c8f63ab23762221e28e42adb12a109fcd2", "parents": [ "8ff71de7cd1bc3d204d815150692cee4eb3a1bd7", "1b17f4f1f8af0ce7f1bbcef94a9ef546330c0b34" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 30 09:56:45 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 09:56:45 2021 +0200" }, "message": "Merge \"docs: remove PSA wording for SPM chapters\" into integration" }, { "commit": "8ff71de7cd1bc3d204d815150692cee4eb3a1bd7", "tree": "700ee8529028bc79601df96c4caa91d3405e65ab", "parents": [ "6794378d2e955d2bf378ff2aa726a29d5884dc1f", "8a73b563e5cde94010271faa308a103446b56798" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 30 09:32:12 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Apr 30 09:32:12 2021 +0200" }, "message": "Merge \"revert(commitlint): disable `signed-off-by` rule\" into integration" }, { "commit": "1b17f4f1f8af0ce7f1bbcef94a9ef546330c0b34", "tree": "4e8efaacccaeb47d800b1fb53af80eb3f82fe640", "parents": [ "08e7cc533e5a019b53e466a3e03eb646980710fa" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Wed Apr 21 11:22:23 2021 +0200" }, "committer": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Fri Apr 30 08:44:26 2021 +0200" }, "message": "docs: remove PSA wording for SPM chapters\n\nPSA wording is not longer associated with FF-A.\n\nChange-Id: Id7c53b9c6c8f383543f6a32a15eb15b7749d8658\nSigned-off-by: Olivier Deprez \u003colivier.deprez@arm.com\u003e\n" }, { "commit": "f714ca80b8e3dc4e953b8728fc7b9457094b2a12", "tree": "2606da2d96777854931f3390e6d66961483eceb2", "parents": [ "6794378d2e955d2bf378ff2aa726a29d5884dc1f" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Wed Mar 10 14:07:34 2021 +0100" }, "committer": { "name": "Yann Gautier", "email": "yann.gautier@foss.st.com", "time": "Thu Apr 29 17:57:47 2021 +0200" }, "message": "plat/st: do not rely on tainted value for dt property length\n\nTo compare the \"okay\" string of a property, strncmp is used but with the\nlength given by fdt_getprop. This len value is reported as tainted by\nCoverity [1]. We just can use strlen(\"okay\") which is a known value\nto compare the 2 strings.\n\n [1] https://scan4.coverity.com/reports.htm#v51972/p11439/fileInstanceId\u003d96515154\u0026defectInstanceId\u003d14219121\u0026mergedDefectId\u003d342997\n\nSigned-off-by: Yann Gautier \u003cyann.gautier@foss.st.com\u003e\nChange-Id: Ic8fb6ccf3126a37df615e433eb028861812015da\n" }, { "commit": "6794378d2e955d2bf378ff2aa726a29d5884dc1f", "tree": "85903d5b87e990f5e03e96a3373f77f811895569", "parents": [ "08e7cc533e5a019b53e466a3e03eb646980710fa", "e3be1086c471bbfc65f4e696ea918009f9de3b47" ], "author": { "name": "Olivier Deprez", "email": "olivier.deprez@arm.com", "time": "Thu Apr 29 14:49:10 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 29 14:49:10 2021 +0200" }, "message": "Merge changes from topic \"fw-update\" into integration\n\n* changes:\n docs: add build options for GPT support enablement\n feat(plat/arm): add GPT parser support\n" }, { "commit": "08e7cc533e5a019b53e466a3e03eb646980710fa", "tree": "c492c08b08291e0701c92e9b1aef3119e8003490", "parents": [ "800b8849c0e2ca0ac2eaa652d7bd0ed44d36c669", "62fbb31516807207d58cdba705d2adf54fec3a5d" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Apr 29 13:57:31 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Apr 29 13:57:31 2021 +0200" }, "message": "Merge changes I15e7cc43,Id7411bd5,I92bafe70,I8f1c0658 into integration\n\n* changes:\n stm32mp1: enable PIE for BL32\n stm32mp1: set BL sizes regardless of flags\n Add PIE support for AARCH32\n Avoid the use of linker *_SIZE__ macros\n" }, { "commit": "e3be1086c471bbfc65f4e696ea918009f9de3b47", "tree": "304dbd0939c8fb096984cd781be02d99566ba1b2", "parents": [ "ef1daa420f7b2920b2ee35379de2aefed6ab2605" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Wed Mar 10 18:33:36 2021 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Apr 29 11:13:08 2021 +0200" }, "message": "docs: add build options for GPT support enablement\n\nDocumented the build options used in Arm GPT parser enablement.\n\nChange-Id: I9d7ef2f44b8f9d2731dd17c2639e5ed0eb6d0b3a\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "ef1daa420f7b2920b2ee35379de2aefed6ab2605", "tree": "113ac6e07443d62a77178c3d89e0d9632f0e0752", "parents": [ "49e9ac281156e5f222c024b29690ca9e6f11f5ba" ], "author": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Mon Feb 22 17:30:17 2021 +0000" }, "committer": { "name": "Manish V Badarkhe", "email": "Manish.Badarkhe@arm.com", "time": "Thu Apr 29 10:11:06 2021 +0100" }, "message": "feat(plat/arm): add GPT parser support\n\nAdded GPT parser support in BL2 for Arm platforms to get the entry\naddress and length of the FIP in the GPT image.\n\nAlso, increased BL2 maximum size for FVP platform to successfully\ncompile ROM-enabled build with this change.\n\nVerified this change using a patch:\nhttps://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654\n\nChange-Id: Ie8026db054966653b739a82d9ba106d283f534d0\nSigned-off-by: Manish V Badarkhe \u003cManish.Badarkhe@arm.com\u003e\n" }, { "commit": "800b8849c0e2ca0ac2eaa652d7bd0ed44d36c669", "tree": "db15cdcb7b041af9deeb8cef2a6196d81ff68b48", "parents": [ "081c5e5afde04bfc952fa2a68eb624d40619334d", "49e9ac281156e5f222c024b29690ca9e6f11f5ba" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Apr 28 21:16:20 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 28 21:16:20 2021 +0200" }, "message": "Merge \"refactor(plat/arm): replace FIP base and size macro with a generic name\" into integration" }, { "commit": "081c5e5afde04bfc952fa2a68eb624d40619334d", "tree": "26746c30e1d6e8b7caea691ddbddf6e9ef62a253", "parents": [ "b29dec5c21367e2bf574a68382172fbfd4981a12", "7d111d99c63f318bec742663884dbe6c46789dca" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Apr 28 21:08:35 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 28 21:08:35 2021 +0200" }, "message": "Merge \"refactor(plat/arm): store UUID as a string, rather than ints\" into integration" }, { "commit": "b29dec5c21367e2bf574a68382172fbfd4981a12", "tree": "f06f0ec8b42547a9080890fb8ded347534c2adb2", "parents": [ "2ba56793d1982cda3d4a5a762a51a6589977088e", "d13dbb6f1d5e28737a3319af035a6cb991bc6f8f" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Apr 28 21:07:28 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 28 21:07:28 2021 +0200" }, "message": "Merge \"feat(fdt): introduce wrapper function to read DT UUIDs\" into integration" }, { "commit": "2ba56793d1982cda3d4a5a762a51a6589977088e", "tree": "a109eba59d9133bbd41d3e2f10bff27b27f5b8c3", "parents": [ "50b11c3c2be0dbc647d0471c7b98da6969108309", "a2a5a9456969266dc68d5845f31e05be0c3ff2e3" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Wed Apr 28 21:02:12 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 28 21:02:12 2021 +0200" }, "message": "Merge \"fix(driver/auth): avoid NV counter upgrade without certificate validation\" into integration" }, { "commit": "50b11c3c2be0dbc647d0471c7b98da6969108309", "tree": "1f699367aa1532c5ce8c70d27ad30a235f72de37", "parents": [ "967f0621b903e9d6dabb048dad4c2e755683e28f", "1328076cdd5db36d5a20b152cab61cc9afeb6607" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Apr 28 17:31:23 2021 +0200" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Apr 28 17:31:23 2021 +0200" }, "message": "Merge changes from topic \"mp/update_release_timelines\" into integration\n\n* changes:\n docs: update release information for v2.6\n docs: update code freeze \u0026 target date for v2.5\n" }, { "commit": "1328076cdd5db36d5a20b152cab61cc9afeb6607", "tree": "1f699367aa1532c5ce8c70d27ad30a235f72de37", "parents": [ "a6edefe0086d3631ed75a31e1f1eea4b35954d19" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Mon Apr 26 19:01:18 2021 -0500" }, "committer": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Apr 28 08:03:31 2021 -0500" }, "message": "docs: update release information for v2.6\n\nUpdated tentative code freeze and release target date for v2.6\nrelease.\n\nChange-Id: I3dd6cfef1a07f3e0159ec7996d18f6cbcb975da7\nSigned-off-by: Madhukar Pappireddy \u003cmadhukar.pappireddy@arm.com\u003e\n" } ], "next": "a6edefe0086d3631ed75a31e1f1eea4b35954d19" }