Trusted Firmware for M profile Arm CPUs

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  1. 5c29c5f RSE: Fremont: Load LCP 1-N ramfw images by Joel Goddard · 4 months ago main
  2. e8e7cfe RSE: Fremont: Load LCP 0 ramfw image by Joel Goddard · 4 months ago
  3. d72781e Mailbox: Tweak behaviour of clear_queue_slot_all_replied() by Chris Brand · 3 weeks ago
  4. 11b9009 RSE: Fremont: Configure System Control NI-Tower under SYSTOP by Arnold Gabriel Benedict · 5 weeks ago
  5. 06ceef8 RSE: Fremont: Add lcp_axis APU config by Arnold Gabriel Benedict · 7 weeks ago
  6. 5059e16 RSE: Fremont: Add lcp_axim APU config by Arnold Gabriel Benedict · 7 weeks ago
  7. 298956c RSE: Fremont: Add app_axim APU config by Arnold Gabriel Benedict · 7 weeks ago
  8. dddcc88 RSE: Fremont: Add app_axis APU config by Arnold Gabriel Benedict · 7 weeks ago
  9. cf83ee1 RSE: Fremont: Add lcp_axis PSAM config by Arnold Gabriel Benedict · 6 weeks ago
  10. 79357d4 RSE: Fremont: Add app_axis PSAM config by Arnold Gabriel Benedict · 7 weeks ago
  11. 9126154 Platform: Add option to get UART init state by Raef Coles · 3 weeks ago
  12. fac1e8c RSE: Make integrity checker accesses privileged by Raef Coles · 3 weeks ago
  13. 623e18c RSE: Log provisioning progress by Raef Coles · 3 weeks ago
  14. 83c4393 RSE: Change bringup helpers order by Raef Coles · 4 weeks ago
  15. ade5657 RSE: Update DMA ICS to use 8-byte ICS words by Raef Coles · 4 weeks ago
  16. 209d61f RSE: Align manufacturing data to 8 byte boundary by Raef Coles · 4 weeks ago
  17. 8c592fb RSE: Sanity check that LCM zero counts fit by Raef Coles · 4 weeks ago
  18. 34a445f RSE: Align integrity checked items to 8 bytes by Raef Coles · 13 days ago
  19. dacc371 RSE: Remove SAM config from OTP and provisioning by Raef Coles · 13 days ago
  20. c12f788 RSE: Fremont: Allow SCP to control SCP ATU by Joel Goddard · 7 weeks ago