Reapply "fix: increase TSRAM of 'fvp-tbb-mbedtls-bl2-el3'"
This reverts commit 22155ff5be724e3c642690bdfc68d42d82d22a98.
Change-Id: Ie2aa6cf12755327d44c890f3e3de7809d2a90d7a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index 87ed27c..15b866d 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -52,7 +52,7 @@
# Try all possible SPDs.
clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
- TSP_NS_INTR_ASYNC_PREEMPT=1
+ TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 SPD_PNCD_S_IRQ=15