ci: merge all the code coverage into a single group
Currently we have two code coverage group, one running daily and other
running weekly. There is not much value in running code coverage daily
so keep it just weekly run. But because we have a single coverage group
remove extensive from the weekly one.
Change-Id: I33da31d4fecbc3acd4f4c39f7b560e7e56c278f6
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug b/group/tf-l3-code-coverage/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-memory-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-memory-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-memory-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
index 8c2d647..b452bbf 100644
--- a/group/tf-l3-code-coverage/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/group/tf-l3-code-coverage/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug b/group/tf-l3-code-coverage/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
index aab4796..b452bbf 100644
--- a/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -1,6 +1,5 @@
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-
diff --git a/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug b/group/tf-l3-code-coverage/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug b/group/tf-l3-code-coverage/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
index aab4796..5515958 100644
--- a/group/tf-l3-code-coverage/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/group/tf-l3-code-coverage/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
index aab4796..5515958 100644
--- a/group/tf-l3-code-coverage/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug b/group/tf-l3-code-coverage/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug b/group/tf-l3-code-coverage/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
index 5515958..b452bbf 100644
--- a/group/tf-l3-code-coverage/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
@@ -3,4 +3,3 @@
#
# SPDX-License-Identifier: BSD-3-Clause
#
-
diff --git a/group/tf-l3-code-coverage/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug b/group/tf-l3-code-coverage/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
index aab4796..5515958 100644
--- a/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug b/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
index aab4796..5515958 100644
--- a/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
+++ b/group/tf-l3-code-coverage/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/group/tf-l3-code-coverage/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug b/group/tf-l3-code-coverage/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#