Initial commit for TF-A CI scripts
Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
diff --git a/model/base-aemv8a-common.sh b/model/base-aemv8a-common.sh
new file mode 100644
index 0000000..8b5a59e
--- /dev/null
+++ b/model/base-aemv8a-common.sh
@@ -0,0 +1,113 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+reset_var cluster_0_has_el2
+reset_var cluster_1_has_el2
+
+reset_var cluster_0_reg_reset
+reset_var cluster_1_reg_reset
+
+reset_var cluster_0_num_cores
+reset_var cluster_1_num_cores
+
+reset_var aarch64_only
+reset_var aarch32
+
+reset_var gicv3_gicv2_only
+
+reset_var sve_plugin
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${cluster_0_reg_reset+-C cluster0.register_reset_data=$cluster_0_reg_reset}
+${cluster_1_reg_reset+-C cluster1.register_reset_data=$cluster_1_reg_reset}
+
+${cluster_0_has_el2+-C cluster0.has_el2=$cluster_0_has_el2}
+${cluster_1_has_el2+-C cluster1.has_el2=$cluster_1_has_el2}
+
+${reset_to_bl31+-C cluster0.cpu0.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu1.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu2.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu3.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu1.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu2.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu3.RVBAR=${bl31_addr:?}}
+
+${reset_to_spmin+-C cluster0.cpu0.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster1.cpu0.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster1.cpu1.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster1.cpu2.RVBAR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster1.cpu3.RVBAR=${bl32_addr:?}}
+
+${cluster_0_num_cores+-C cluster0.NUM_CORES=$cluster_0_num_cores}
+${cluster_1_num_cores+-C cluster1.NUM_CORES=$cluster_1_num_cores}
+
+${el3_payload_bin+--data cluster0.cpu0=$el3_payload_bin@${el3_payload_addr:?}}
+
+${aarch64_only+-C cluster0.max_32bit_el=-1}
+${aarch64_only+-C cluster1.max_32bit_el=-1}
+
+${aarch32+-C cluster0.cpu0.CONFIG64=0}
+${aarch32+-C cluster0.cpu1.CONFIG64=0}
+${aarch32+-C cluster0.cpu2.CONFIG64=0}
+${aarch32+-C cluster0.cpu3.CONFIG64=0}
+${aarch32+-C cluster1.cpu0.CONFIG64=0}
+${aarch32+-C cluster1.cpu1.CONFIG64=0}
+${aarch32+-C cluster1.cpu2.CONFIG64=0}
+${aarch32+-C cluster1.cpu3.CONFIG64=0}
+
+${gicv3_gicv2_only+-C gicv3.gicv2-only=$gicv3_gicv2_only}
+
+${sve_plugin+--plugin=$sve_plugin_path}
+${sve_plugin+-C SVE.ScalableVectorExtension.enable_at_reset=0}
+${sve_plugin+-C SVE.ScalableVectorExtension.veclen=$((128 / 8))}
+
+${bl2_at_el3+-C cluster0.cpu0.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster0.cpu1.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster0.cpu2.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster0.cpu3.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster1.cpu0.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster1.cpu1.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster1.cpu2.RVBAR=${bl2_addr:?}}
+${bl2_at_el3+-C cluster1.cpu3.RVBAR=${bl2_addr:?}}
+EOF
+
+# Parameters to select architecture version
+if [ "$arch_version" = "8.3" ]; then
+ cat <<EOF >>"$model_param_file"
+-C cluster0.has_arm_v8-3=1
+-C cluster1.has_arm_v8-3=1
+EOF
+fi
+
+if [ "$arch_version" = "8.4" ]; then
+ cat <<EOF >>"$model_param_file"
+-C cluster0.has_arm_v8-4=1
+-C cluster1.has_arm_v8-4=1
+EOF
+fi
+
+# Parameters for fault injection
+if [ "$fault_inject" = "1" ]; then
+ cat <<EOF >>"$model_param_file"
+-C cluster0.number_of_error_records=2
+-C cluster1.number_of_error_records=2
+-C cluster0.has_ras=2
+-C cluster1.has_ras=2
+
+-C cluster0.error_record_feature_register='{"INJ":0x1,"ED":0x1,"UI":0x0,"FI":0x0,"UE":0x1,"CFI":0x0,"CEC":0x0,"RP":0x0,"DUI":0x0,"CEO":0x0}'
+-C cluster1.error_record_feature_register='{"INJ":0x1,"ED":0x1,"UI":0x0,"FI":0x0,"UE":0x1,"CFI":0x0,"CEC":0x0,"RP":0x0,"DUI":0x0,"CEO":0x0}'
+-C cluster0.pseudo_fault_generation_feature_register='{"UC":true,"UEU":true,"UER":false,"UEO":false,"DE":false,"CE":false,"R":false}'
+-C cluster1.pseudo_fault_generation_feature_register='{"UC":true,"UEU":true,"UER":false,"UEO":false,"DE":false,"CE":false,"R":false}'
+EOF
+fi
diff --git a/model/base-aemv8a-latest-revb.sh b/model/base-aemv8a-latest-revb.sh
new file mode 100644
index 0000000..df5bd93
--- /dev/null
+++ b/model/base-aemv8a-latest-revb.sh
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/0.8/9810/models/Linux64_GCC-4.9/FVP_Base_AEMv8A-AEMv8A"
+
+default_var sve_plugin_path "$warehouse/SysGen/ShojiPlugin/0.8/9905/hpc-00rel3/Linux64_GCC-4.9/ScalableVectorExtension.so"
+
+source "$ci_root/model/base-aemv8a-common.sh"
diff --git a/model/base-aemv8a-revb.sh b/model/base-aemv8a-revb.sh
new file mode 100644
index 0000000..01bf771
--- /dev/null
+++ b/model/base-aemv8a-revb.sh
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Use revb model
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_AEMv8A-AEMv8A"
+
+default_var sve_plugin_path "$warehouse/SysGen/ShojiPlugin/$model_version/$model_build/hpc-00rel4_1/Linux64_GCC-4.9/ScalableVectorExtension.so"
+
+source "$ci_root/model/base-aemv8a-common.sh"
diff --git a/model/base-aemv8a.sh b/model/base-aemv8a.sh
new file mode 100644
index 0000000..bf4d7d1
--- /dev/null
+++ b/model/base-aemv8a.sh
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Use revc model
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_RevC-2xAEMv8A"
+
+default_var sve_plugin_path "$warehouse/SysGen/ShojiPlugin/$model_version/$model_build/hpc-00rel5/Linux64_GCC-4.9/ScalableVectorExtension.so"
+
+source "$ci_root/model/base-aemv8a-common.sh"
diff --git a/model/cortex-a32x4.sh b/model/cortex-a32x4.sh
new file mode 100644
index 0000000..d7d49e8
--- /dev/null
+++ b/model/cortex-a32x4.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A32x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBARADDR=${bl32_addr:?}}
+
+EOF
diff --git a/model/cortex-a35x4.sh b/model/cortex-a35x4.sh
new file mode 100644
index 0000000..ac4d93b
--- /dev/null
+++ b/model/cortex-a35x4.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A35x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBARADDR=${bl32_addr:?}}
+
+EOF
diff --git a/model/cortex-a53x4.sh b/model/cortex-a53x4.sh
new file mode 100644
index 0000000..844ed02
--- /dev/null
+++ b/model/cortex-a53x4.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A53x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBARADDR=${bl32_addr:?}}
+
+EOF
diff --git a/model/cortex-a55x4-a75x4.sh b/model/cortex-a55x4-a75x4.sh
new file mode 100644
index 0000000..ba751d4
--- /dev/null
+++ b/model/cortex-a55x4-a75x4.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A55x4+Cortex-A75x4"
+
+source "$ci_root/model/fvp_common.sh"
diff --git a/model/cortex-a55x4.sh b/model/cortex-a55x4.sh
new file mode 100644
index 0000000..90979a9
--- /dev/null
+++ b/model/cortex-a55x4.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A55x4"
+
+source "$ci_root/model/fvp_common.sh"
diff --git a/model/cortex-a57x1-a53x1.sh b/model/cortex-a57x1-a53x1.sh
new file mode 100644
index 0000000..e698245
--- /dev/null
+++ b/model/cortex-a57x1-a53x1.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A57x1-A53x1"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_bl31+-C cluster0.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBARADDR=${bl31_addr:?}}
+
+EOF
diff --git a/model/cortex-a57x2-a53x4.sh b/model/cortex-a57x2-a53x4.sh
new file mode 100644
index 0000000..b814ed3
--- /dev/null
+++ b/model/cortex-a57x2-a53x4.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A57x2-A53x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_bl31+-C cluster0.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu3.RVBARADDR=${bl31_addr:?}}
+
+EOF
diff --git a/model/cortex-a57x4-a53x4.sh b/model/cortex-a57x4-a53x4.sh
new file mode 100644
index 0000000..b641285
--- /dev/null
+++ b/model/cortex-a57x4-a53x4.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A57x4-A53x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_bl31+-C cluster0.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu3.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu3.RVBARADDR=${bl31_addr:?}}
+
+EOF
diff --git a/model/cortex-a57x4.sh b/model/cortex-a57x4.sh
new file mode 100644
index 0000000..16ad9aa
--- /dev/null
+++ b/model/cortex-a57x4.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A57x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBARADDR=${bl32_addr:?}}
+
+EOF
diff --git a/model/cortex-a72x4-a53x4.sh b/model/cortex-a72x4-a53x4.sh
new file mode 100644
index 0000000..c7524bc
--- /dev/null
+++ b/model/cortex-a72x4-a53x4.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A72x4-A53x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_bl31+-C cluster0.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu3.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu3.RVBARADDR=${bl31_addr:?}}
+
+EOF
diff --git a/model/cortex-a72x4.sh b/model/cortex-a72x4.sh
new file mode 100644
index 0000000..0c69ad2
--- /dev/null
+++ b/model/cortex-a72x4.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A72x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBARADDR=${bl32_addr:?}}
+
+EOF
diff --git a/model/cortex-a73x4-a53x4.sh b/model/cortex-a73x4-a53x4.sh
new file mode 100644
index 0000000..c4490fa
--- /dev/null
+++ b/model/cortex-a73x4-a53x4.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A73x4-A53x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_bl31+-C cluster0.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu3.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu1.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu2.RVBARADDR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu3.RVBARADDR=${bl31_addr:?}}
+
+EOF
diff --git a/model/cortex-a73x4.sh b/model/cortex-a73x4.sh
new file mode 100644
index 0000000..2cbb7af
--- /dev/null
+++ b/model/cortex-a73x4.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A73x4"
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
+${reset_to_spmin+-C cluster0.cpu3.RVBARADDR=${bl32_addr:?}}
+
+EOF
diff --git a/model/cortex-a75x4.sh b/model/cortex-a75x4.sh
new file mode 100644
index 0000000..b4629fb
--- /dev/null
+++ b/model/cortex-a75x4.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A75x4"
+
+source "$ci_root/model/fvp_common.sh"
diff --git a/model/cortex-a76x4.sh b/model/cortex-a76x4.sh
new file mode 100644
index 0000000..2d9dc40
--- /dev/null
+++ b/model/cortex-a76x4.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Cortex-A76x4"
+
+source "$ci_root/model/fvp_common.sh"
diff --git a/model/css-rde1edge.sh b/model/css-rde1edge.sh
new file mode 100644
index 0000000..e397b75
--- /dev/null
+++ b/model/css-rde1edge.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "/arm/projectscratch/ssg/trusted-fw/models/0.0_5137/FVP_RD_E1_edge"
+
+cat <<EOF >"$model_param_file"
+-C board.flashloader0.fname=$fip_bin
+-C board.virtioblockdevice.image_path=$busybox_bin
+-C css.cmn600.force_on_from_start=1
+-C css.cmn600.mesh_config_file=RD_N1_E1_cmn600.yml
+-C css.mcp.ROMloader.fname=$mcp_rom_bin
+-C css.pl011_uart_ap.unbuffered_output=1
+-C css.scp.ROMloader.fname=$scp_rom_bin
+-C css.trustedBootROMloader.fname=$bl1_bin
+-C soc.pl011_uart0.unbuffered_output=1
+-C soc.pl011_uart1.unbuffered_output=1
+--data css.scp.armcortexm7ct=$scp_ram_bin@$scp_ram_addr
+EOF
diff --git a/model/css-rdn1edge.sh b/model/css-rdn1edge.sh
new file mode 100644
index 0000000..9221ddd
--- /dev/null
+++ b/model/css-rdn1edge.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/SubSystemModels/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_RD_N1_edge"
+
+cat <<EOF >"$model_param_file"
+-C board.flashloader0.fname=$fip_bin
+-C board.virtioblockdevice.image_path=$busybox_bin
+-C css.cmn600.force_on_from_start=1
+-C css.cmn600.mesh_config_file=RD_N1_E1_cmn600.yml
+-C css.mcp.ROMloader.fname=$mcp_rom_bin
+-C css.pl011_uart_ap.unbuffered_output=1
+-C css.scp.ROMloader.fname=$scp_rom_bin
+-C css.trustedBootROMloader.fname=$bl1_bin
+-C soc.pl011_uart0.unbuffered_output=1
+-C soc.pl011_uart1.unbuffered_output=1
+--data css.scp.armcortexm7ct=$scp_ram_bin@$scp_ram_addr
+EOF
diff --git a/model/css-sgi575-ports.awk b/model/css-sgi575-ports.awk
new file mode 100644
index 0000000..f34bff1
--- /dev/null
+++ b/model/css-sgi575-ports.awk
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+/terminal_s0/ { ports[0] = $NF }
+/terminal_s1/ { ports[1] = $NF }
+/terminal_uart_aon/ { ports[2] = $NF }
+END {
+ for (i = 0; i < num_uarts; i++) {
+ if (ports[i] != "")
+ print "ports[" i "]=" ports[i]
+ }
+}
diff --git a/model/css-sgi575.sh b/model/css-sgi575.sh
new file mode 100644
index 0000000..23566ba
--- /dev/null
+++ b/model/css-sgi575.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "${pinned_css:?}/FVP_CSS_SGI-575"
+
+cat <<EOF >"$model_param_file"
+-C board.flashloader0.fname=$fip_bin
+-C board.virtioblockdevice.image_path=$busybox_bin
+-C css.cmn600.force_on_from_start=1
+-C css.cmn600.mesh_config_file=SGI-575_cmn600.yml
+-C css.mcp.ROMloader.fname=$mcp_rom_bin
+-C css.pl011_uart_ap.unbuffered_output=1
+-C css.scp.ROMloader.fname=$scp_rom_bin
+-C css.trustedBootROMloader.fname=$bl1_bin
+-C soc.pl011_uart0.unbuffered_output=1
+-C soc.pl011_uart1.unbuffered_output=1
+--data css.scp.armcortexm7ct=$scp_ram_bin@$scp_ram_addr
+EOF
diff --git a/model/css-sgm775.sh b/model/css-sgm775.sh
new file mode 100644
index 0000000..ba5bcc2
--- /dev/null
+++ b/model/css-sgm775.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "${pinned_css:?}/FVP_CSS_SGM-775"
+
+cat <<EOF >"$model_param_file"
+${bl1_bin+-C css.trustedBootROMloader.fname=$bl1_bin}
+${scp_rom_bin+-C css.scp.ROMloader.fname=$scp_rom_bin}
+${fip_bin+-C board.flashloader0.fname=$fip_bin}
+${initrd_bin+--data css.cluster0.cpu0=$initrd_bin@${initrd_addr:?}}
+${kernel_bin+--data css.cluster0.cpu0=$kernel_bin@${kernel_addr:?}}
+${dtb_bin+--data css.cluster0.cpu0=$dtb_bin@0x83000000}
+${uart0_out+-C soc.pl011_uart0.out_file=$uart0_out}
+${uart0_out+-C soc.pl011_uart0.unbuffered_output=1}
+${uart1_out+-C soc.pl011_uart1.out_file=$uart1_out}
+${uart1_out+-C soc.pl011_uart1.unbuffered_output=1}
+-C config_id=0
+-C displayController=2
+EOF
diff --git a/model/foundationv8.sh b/model/foundationv8.sh
new file mode 100644
index 0000000..d4b8def
--- /dev/null
+++ b/model/foundationv8.sh
@@ -0,0 +1,27 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/Foundation_Platform"
+
+default_var ncores 4
+default_var quantum 1000
+
+cat <<EOF >"$model_param_file"
+
+--no-visualization
+--data=$bl1_bin@$bl1_addr
+${fip_bin+--data=$fip_bin@$fip_addr}
+${dtb_bin+--data=$dtb_bin@$dtb_addr}
+${kernel_bin+--data=$kernel_bin@$kernel_addr}
+${initrd_bin+--data=$initrd_bin@$initrd_addr}
+${rootfs_bin+--block-device=$rootfs_bin}
+--cores=$ncores
+--secure-memory
+--gicv3
+--quantum=$quantum
+${arch_version+--arm-v$arch_version}
+EOF
diff --git a/model/fvp_common.sh b/model/fvp_common.sh
new file mode 100644
index 0000000..f2b4982
--- /dev/null
+++ b/model/fvp_common.sh
@@ -0,0 +1,71 @@
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# This file contains common model controls and parameters across *ALL* FVP
+# models.
+
+default_var pctl_startup 0.0.0.0
+default_var quantum 1000
+
+reset_var cache_state_modelled
+reset_var has_bl1
+reset_var has_fip
+reset_var preload_bl33
+reset_var reset_to_bl31
+reset_var reset_to_spmin
+reset_var secure_memory
+reset_var secure_ram_fill
+
+
+if [ "$bl2_at_el3" ]; then
+ has_fip=1
+elif [ -z "$reset_to_spmin" -a -z "$reset_to_bl31" ]; then
+ has_bl1=1
+ has_fip=1
+fi
+
+cat <<EOF >"$model_param_file"
+
+-C bp.ve_sysregs.exit_on_shutdown=1
+-C pctl.startup=$pctl_startup
+
+${secure_memory+-C bp.secure_memory=$secure_memory}
+${cache_state_modelled+-C cache_state_modelled=$cache_state_modelled}
+
+${secure_ram_fill+-C bp.secureSRAM.fill1=0x00000000}
+${secure_ram_fill+-C bp.secureSRAM.fill2=0x00000000}
+
+${bl2_at_el3+--data cluster0.cpu0=$bl2_bin@${bl2_addr:?}}
+
+${reset_to_bl31+--data cluster0.cpu0=$bl31_bin@${bl31_addr:?}}
+${preload_bl33+--data cluster0.cpu0=$preload_bl33_bin@${bl33_addr:?}}
+
+${reset_to_spmin+--data cluster0.cpu0=$bl32_bin@${bl32_addr:?}}
+${reset_to_spmin+--data cluster0.cpu0=$uboot_bin@${bl33_addr:?}}
+
+${memprotect+--data cluster0.cpu0=$memprotect@${memprotect_addr:?}}
+${romlib_bin+--data cluster0.cpu0=$romlib_bin@${romlib_addr:?}}
+
+${has_bl1+-C bp.secureflashloader.fname=$bl1_bin}
+${has_fip+-C bp.flashloader0.fname=$fip_bin}
+
+${dtb_bin+--data cluster0.cpu0=$dtb_bin@${dtb_addr:?}}
+${kernel_bin+--data cluster0.cpu0=$kernel_bin@${kernel_addr:?}}
+${initrd_bin+--data cluster0.cpu0=$initrd_bin@${initrd_addr:?}}
+
+${ns_bl1u_bin+--data cluster0.cpu0=$ns_bl1u_bin@$ns_bl1u_addr}
+${fwu_fip_bin+--data cluster0.cpu0=$fwu_fip_bin@$fwu_fip_addr}
+${backup_fip_bin+--data cluster0.cpu0=$backup_fip_bin@$backup_fip_addr}
+
+${flashloader1_bin+-C bp.flashloader1.fname=$flashloader1_bin}
+${rootfs_bin+-C bp.virtioblockdevice.image_path=$rootfs_bin}
+
+${uart0_out+-C bp.pl011_uart0.out_file=$uart0_out}
+${uart0_out+-C bp.pl011_uart0.unbuffered_output=1}
+
+${no_quantum--Q ${quantum}}
+
+EOF
diff --git a/model/neoverse_n1.sh b/model/neoverse_n1.sh
new file mode 100644
index 0000000..8f77e74
--- /dev/null
+++ b/model/neoverse_n1.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/Linux64_GCC-4.9/FVP_Base_Neoverse-N1x4"
+
+source "$ci_root/model/fvp_common.sh"