Enable cache modelling for fvp-aemv8a.quad model
Linux kernel boot failed with cache modelling enabled in
fvp-aemv8a.quad model hence we disabled the cache modelling
on this FVP model as workaround.
After investigation, we found that U-boot supports only cache
coherent interconnects CCN-400 and CCN-504, but not CCN-502,
and hence U-boot fails to boot the Linux kernel as it can not
perform CCN-502 L3 cache operations.
Hence passed extra parameter to this FVP model i.e.
"ccn502.cache_size_in_kbytes=0" to disable only L3 cache.
and enable back the cache state modelling. (to enable other cache
support in the model)
Also, this patch adds a config to test this FVP model with TFTF.
Change-Id: Icc6061341788f64e8abad6aa306611b3a3983c56
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
diff --git a/model/base-aemv8a-quad.sh b/model/base-aemv8a-quad.sh
index 6ba94f2..972aa05 100644
--- a/model/base-aemv8a-quad.sh
+++ b/model/base-aemv8a-quad.sh
@@ -14,6 +14,8 @@
reset_var gicv3_gicv2_only
+reset_var ccn502_cache_size_in_kbytes
+
reset_var aarch64_only
source "$ci_root/model/fvp_common.sh"
@@ -49,4 +51,6 @@
${gicv3_gicv2_only+-C gicv3.gicv2-only=$gicv3_gicv2_only}
+${ccn502_cache_size_in_kbytes+-C ccn502.cache_size_in_kbytes=$ccn502_cache_size_in_kbytes}
+
EOF