commit c722e72dc12d1bf4d61ddb7e0a152b0cd9f68771
author Sona Mathew <SonaRebecca.Mathew@arm.com> Thu Aug 10 16:31:45 2023 -0500
committer Lauren Wehrmeister <lauren.wehrmeister@arm.com> Fri Sep 29 18:57:48 2023 +0200
tree 896edd8513457b621e9b96ec933fcbf30ee609f3
parent 48c50de3fa29f65988027a6424abca9122c09103

fix: increase TSRAM of 'fvp-tbb-mbedtls-bl2-el3'

This build job is currently failing the errata framework
based cpu conversion patches due to lack of available
SRAM.

Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: Ied03ad8dc5ecdf1f84f91ae737122176042800f0
(cherry picked from commit 40e5be98b3e227d74d0a26b2827f96c0b97de8c0)

script/tf-coverity/tf-cov-make

diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index 26f92c6..3d51ad6 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -52,7 +52,7 @@
 # Try all possible SPDs.
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
-    TSP_NS_INTR_ASYNC_PREEMPT=1
+    TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 SPD_PNCD_S_IRQ=15