| commit | 041e48a9200e1578ecb3d47da642120455296036 | [log] [tgz] |
|---|---|---|
| author | Akshay Belsare <akshay.belsare@amd.com> | Fri Jul 14 14:20:31 2023 +0530 |
| committer | Manish V Badarkhe <manish.badarkhe@arm.com> | Thu Jul 20 10:13:41 2023 +0200 |
| tree | 714ec777c3f629b081c09175a6c188c6e3d2764c | |
| parent | 6dafb5f6006eaf2a41fc4e2be80144d29f037226 [diff] |
build(versal): update config for ddr A build time parameter XILINX_OF_BOARD_DTB_ADDR is introduced for Versal platform which provides the DTB address. When the TF_A is placed and executed from DDR and DTB load address is provided in above param, TF-A will update the DTB, at runtime, adding a reserved memory node for its address range in ddr. Signed-off-by: Akshay Belsare <akshay.belsare@amd.com> Change-Id: I7d79cd37efeb4a3382cafd302461b876f1732277