rdn1edgex2: add patch to improve the reliability of cross chip events
RD-N1-Edge-Dual FVP has known reliability issue with stlr instruction
while sending events across the chip through the CCIX link. This can be
fixed by explicitly sending event using sev instruction after strl. Add
this patch as part of the pre tf build step.
Change-Id: Id9e53b0e66c298c27d2101c41453401e07039e07
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
diff --git a/patch/css_rd_multichip_fvp/spinlock-send-explicit-event-after-store-release.patch b/patch/css_rd_multichip_fvp/spinlock-send-explicit-event-after-store-release.patch
new file mode 100644
index 0000000..b579a3d
--- /dev/null
+++ b/patch/css_rd_multichip_fvp/spinlock-send-explicit-event-after-store-release.patch
@@ -0,0 +1,33 @@
+From f1cd888433a0f04806f0074ea3572eb79f781274 Mon Sep 17 00:00:00 2001
+From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
+Date: Wed, 23 Oct 2019 11:48:02 +0530
+Subject: [PATCH] [HACK]: spinlock: send explicit event after store release
+ instruction
+
+stlr instruction in the spin_unlock function is expected to send an
+implicit event to all CPU cores. In a cross chip scenario, FVP has
+stability issues while sending this implicit event across chips.
+To avoid the stability issues, add sev instruction which sends explicit
+events to all cores. Explicit events are propagated across chips without
+any stability issues.
+
+Change-Id: I94db4f940e98f9b60f4120d0bde4930f9d31440c
+Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
+---
+ lib/locks/exclusive/aarch64/spinlock.S | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/lib/locks/exclusive/aarch64/spinlock.S b/lib/locks/exclusive/aarch64/spinlock.S
+index e941b8a34..2c01a3bee 100644
+--- a/lib/locks/exclusive/aarch64/spinlock.S
++++ b/lib/locks/exclusive/aarch64/spinlock.S
+@@ -71,5 +71,6 @@ endfunc spin_lock
+ */
+ func spin_unlock
+ stlr wzr, [x0]
++ sev
+ ret
+ endfunc spin_unlock
+--
+2.17.1
+
diff --git a/run_config/fvp-rdn1edgex2 b/run_config/fvp-rdn1edgex2
index b57a32f..c23a518 100644
--- a/run_config/fvp-rdn1edgex2
+++ b/run_config/fvp-rdn1edgex2
@@ -27,6 +27,16 @@
uart="3" file="hold_uart.exp" track_expect
}
+pre_tf_build() {
+ #
+ # Dual-Chip RD-N1-Edge FVP has reliability issues with stlr instruction
+ # while sending events across the chip through CCIX link. Apply 'send
+ # explicit event after store release instruction' patch to improve the
+ # reliability of cross chip events.
+ #
+ apply_tf_patch "css_rd_multichip_fvp/spinlock-send-explicit-event-after-store-release.patch"
+}
+
post_fetch_tf_resource() {
model="css-rdn1edgex2" gen_model_params
set_run_env "ports_script" "$ci_root/model/css-rdinfra-ports.awk"