commit eb9c1bb75dabe3fdbc7ed7deeaaaf7ce3da5eedd
author Zelalem <zelalem.aweke@arm.com> Tue Aug 04 12:40:46 2020 -0500
committer Sandrine Bailleux <sandrine.bailleux@arm.com> Wed Aug 05 09:35:56 2020 +0000
tree 3b0c019b020e9fd634252630cca2012868f65cfd
parent c9531f85b100a6a20f95ef8c5d19adea24858a45

Sync model scripts with internal CI

Sync model scripts with open-ci patch:
539c151d0cd99a5e6ca6c0e6966f6d8579fe864e

Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: I0d28301c86b8efd633a5ff31e548e2bfb81507a7

model/base-aemv8a-quad.sh

diff --git a/model/base-aemv8a-quad.sh b/model/base-aemv8a-quad.sh
new file mode 100644
index 0000000..9dfeb4b
--- /dev/null
+++ b/model/base-aemv8a-quad.sh
@@ -0,0 +1,52 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+set_model_path "$warehouse/SysGen/Models/$model_version/$model_build/models/$model_flavour/FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502"
+
+default_var cluster_0_num_cores 4
+default_var cluster_1_num_cores 4
+default_var cluster_2_num_cores 4
+default_var cluster_3_num_cores 4
+
+reset_var gicv3_gicv2_only
+
+reset_var aarch64_only
+
+source "$ci_root/model/fvp_common.sh"
+
+cat <<EOF >>"$model_param_file"
+
+${cluster_0_num_cores+-C cluster0.NUM_CORES=$cluster_0_num_cores}
+${cluster_1_num_cores+-C cluster1.NUM_CORES=$cluster_1_num_cores}
+${cluster_2_num_cores+-C cluster2.NUM_CORES=$cluster_2_num_cores}
+${cluster_3_num_cores+-C cluster3.NUM_CORES=$cluster_3_num_cores}
+
+${reset_to_bl31+-C cluster0.cpu0.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu1.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu2.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster0.cpu3.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu0.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu1.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu2.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster1.cpu3.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster2.cpu0.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster2.cpu1.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster2.cpu2.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster2.cpu3.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster3.cpu0.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster3.cpu1.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster3.cpu2.RVBAR=${bl31_addr:?}}
+${reset_to_bl31+-C cluster3.cpu3.RVBAR=${bl31_addr:?}}
+
+${el3_payload_bin+--data cluster0.cpu0=$el3_payload_bin@${el3_payload_addr:?}}
+
+${aarch64_only+-C cluster2.max_32bit_el=-1}
+${aarch64_only+-C cluster3.max_32bit_el=-1}
+
+${gicv3_gicv2_only+-C gicv3.gicv2-only=$gicv3_gicv2_only}
+
+EOF