diff --git a/group/spm-l2-boot-tests/fvp-default,fvp-spm,fvp-48bit-pa:fvp-spm.48bit_pa b/group/spm-l2-boot-tests/fvp-default,fvp-spm,fvp-48bit-pa:fvp-spm.48bit_pa
new file mode 100644
index 0000000..b8939c8
--- /dev/null
+++ b/group/spm-l2-boot-tests/fvp-default,fvp-spm,fvp-48bit-pa:fvp-spm.48bit_pa
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index de4df6a..f6dabe2 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -19,6 +19,8 @@
 
 reset_var plat_variant
 
+reset_var pa_size
+
 #------------ GIC configuration --------------
 
 # GICv2 compatibility is not supported and GICD_CTLR.ARE_* is always one
@@ -141,6 +143,8 @@
 #------------ Cluster0 configuration --------------
 
 cat <<EOF >>"$model_param_file"
+${pa_size+-C cluster0.PA_SIZE=$pa_size}
+
 ${cluster_0_reg_reset+-C cluster0.register_reset_data=$cluster_0_reg_reset}
 
 ${cluster_0_has_el2+-C cluster0.has_el2=$cluster_0_has_el2}
@@ -239,9 +243,20 @@
 	else
 		cat <<EOF >>"$model_param_file"
 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
+EOF
+
+                # Align pci.pci_smmuv3.mmu.SMMU_IDR5 to define 48 bit physical
+                # address size as for the PE.
+                if [ "$pa_size" = "48" ]; then
+                    cat <<EOF >>"$model_param_file"
+-C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475
+EOF
+                else
+                    cat <<EOF >>"$model_param_file"
 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472
 EOF
-	fi
+	        fi
+        fi
 fi
 
 # Parameters to select architecture version
@@ -317,6 +332,8 @@
 #------------ Cluster1 configuration (if exists) --------------
 if [ "$is_dual_cluster" = "1" ]; then
 	cat <<EOF >>"$model_param_file"
+${pa_size+-C cluster1.PA_SIZE=$pa_size}
+
 ${cluster_1_reg_reset+-C cluster1.register_reset_data=$cluster_1_reg_reset}
 
 ${cluster_1_has_el2+-C cluster1.has_el2=$cluster_1_has_el2}
@@ -444,3 +461,13 @@
 EOF
 fi
 fi
+
+# 48bit PA size: in order to access memory in high address ranges the
+# model must declare and the interconnect has to be configured to
+# support such address width.
+if [ "$pa_size" = "48" ]; then
+cat <<EOF >>"$model_param_file"
+-C bp.dram_size=4000000
+-C cci550.addr_width=48
+EOF
+fi
diff --git a/run_config/fvp-spm.48bit_pa b/run_config/fvp-spm.48bit_pa
new file mode 100644
index 0000000..cacbaa3
--- /dev/null
+++ b/run_config/fvp-spm.48bit_pa
@@ -0,0 +1,37 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+	build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+fetch_tf_resource() {
+	# Expect scripts
+	uart="0" file="tftf.exp" track_expect
+	uart="2" file="spm-uart2.exp" track_expect
+
+	payload_type="tftf" gen_fvp_yaml_template
+}
+
+post_fetch_tf_resource() {
+        local model="base-aemv8a"
+
+	# SPM(reference implementation of S-EL2 firmware) has SMMUv3 driver
+	# enabled to help with stage-2 translation and virtualization of
+	# upstream peripheral devices. Hence, enable the SMMUv3 IP in FVP
+	# by configuring the appropriate parameters of the SMMUv3 AEM.
+
+	model="$model" \
+	arch_version="8.5" \
+	has_smmuv3_params="1" \
+	has_branch_target_exception="1" \
+	memory_tagging_support_level="2" \
+	pa_size="48" \
+		gen_model_params
+
+	model="$model" gen_fvp_yaml
+}
diff --git a/tftf_config/fvp-48bit-pa b/tftf_config/fvp-48bit-pa
new file mode 100644
index 0000000..2a04d05
--- /dev/null
+++ b/tftf_config/fvp-48bit-pa
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+PA_SIZE=48
+TESTS=spm