Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 1 | diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S |
Jayanth Dodderi Chidanand | 496a405 | 2024-09-10 14:30:14 +0100 | [diff] [blame] | 2 | index 742380568..5ff6d3dd8 100644 |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 3 | --- a/bl31/aarch64/runtime_exceptions.S |
| 4 | +++ b/bl31/aarch64/runtime_exceptions.S |
| 5 | @@ -228,6 +228,9 @@ vector_entry sync_exception_aarch64 |
| 6 | */ |
| 7 | save_x30 |
| 8 | apply_at_speculative_wa |
| 9 | + mrs x30, scr_el3 |
| 10 | + orr x30, x30, SCR_EA_BIT |
| 11 | + msr scr_el3, x30 |
| 12 | sync_and_handle_pending_serror |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 13 | handle_sync_exception |
Jayanth Dodderi Chidanand | 496a405 | 2024-09-10 14:30:14 +0100 | [diff] [blame] | 14 | end_vector_entry sync_exception_aarch64 |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 15 | diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c |
Boyan Karatotev | 1f4be38 | 2025-01-10 10:39:41 +0000 | [diff] [blame] | 16 | index 6acd1b60f..76a5b6ded 100644 |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 17 | --- a/services/arm_arch_svc/arm_arch_svc_setup.c |
| 18 | +++ b/services/arm_arch_svc/arm_arch_svc_setup.c |
Boyan Karatotev | 1f4be38 | 2025-01-10 10:39:41 +0000 | [diff] [blame] | 19 | @@ -16,10 +16,37 @@ |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 20 | #include <plat/common/platform.h> |
Boyan Karatotev | 1f4be38 | 2025-01-10 10:39:41 +0000 | [diff] [blame] | 21 | #include <arch_features.h> |
| 22 | #include <arch_helpers.h> |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 23 | +#include <context.h> |
Boyan Karatotev | 1f4be38 | 2025-01-10 10:39:41 +0000 | [diff] [blame] | 24 | #include <lib/el3_runtime/context_mgmt.h> |
| 25 | |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 26 | +static void target_ea_to_lower_el(void) |
| 27 | +{ |
| 28 | + u_register_t scr_el3; |
| 29 | + cpu_context_t *ctx = cm_get_context(NON_SECURE); |
| 30 | + el3_state_t *el3_ctx = get_el3state_ctx(ctx); |
| 31 | + scr_el3 = read_ctx_reg(el3_ctx, CTX_SCR_EL3); |
| 32 | + scr_el3 &= ~SCR_EA_BIT; |
| 33 | + write_ctx_reg(el3_ctx, CTX_SCR_EL3, scr_el3); |
| 34 | +} |
Boyan Karatotev | 1f4be38 | 2025-01-10 10:39:41 +0000 | [diff] [blame] | 35 | + |
Manish Pandey | fb4b2ff | 2023-06-16 16:56:46 +0100 | [diff] [blame] | 36 | static int32_t smccc_version(void) |
| 37 | { |
| 38 | + /* |
| 39 | + * This patch is used in RAS FFH case. |
| 40 | + * In RAS FFH case lower EL EAs are routed to EL3 but to do reflection |
| 41 | + * of SError tests we need SError to be pended in tftf when SMC call is |
| 42 | + * made. Taking an SError depends on PSTATE.A bit of EL but if SCR_EL3.EA |
| 43 | + * is set, the SError is immediately taken. So to allow SError to be |
| 44 | + * pended in tftf we need to clear SCR_EL3.EA along with PSTATE.A masked |
| 45 | + * (which is done in tftf as part of test). |
| 46 | + * Since tftf cannot modify SCR_EL3 register, this hack is used in |
| 47 | + * SMCCC_VERSION path which tftf calls before running actual test. |
| 48 | + * |
| 49 | + * We can't directly modify SCR_EL3 and preserve it in context switch that |
| 50 | + * is why the context value is modified. The value of SCR_EL3 is modified |
| 51 | + * again while exiting EL3 in reflection path. |
| 52 | + */ |
| 53 | + target_ea_to_lower_el(); |
| 54 | return MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION); |
| 55 | } |
| 56 | |