RSE: Enable BL1_1 tests
Also, add generic support for runnning the BL1_1 and BL1_2 testsuites in
CI.
Change-Id: I85f0cf0018e0f025cf16d8484c944167191efc4f
Signed-off-by: Raef Coles <raef.coles@arm.com>
diff --git a/build_helper/build_helper_config_maps.py b/build_helper/build_helper_config_maps.py
index bb68300..9086f7f 100644
--- a/build_helper/build_helper_config_maps.py
+++ b/build_helper/build_helper_config_maps.py
@@ -47,6 +47,8 @@
"RegBL2" : "-DTEST_BL2=ON ",
"RegS" : "-DTEST_S=ON ",
"RegNS" : "-DTEST_NS=ON -DTEST_NS_FLIH_IRQ=OFF ",
+ "RegBL1_1" : "-DTEST_BL1_1=ON ",
+ "RegBL1_2" : "-DTEST_BL1_2=ON ",
}
# Map PSA Arch Tests to short format
diff --git a/build_helper/build_helper_configs.py b/build_helper/build_helper_configs.py
index 390531e..0f30bff 100755
--- a/build_helper/build_helper_configs.py
+++ b/build_helper/build_helper_configs.py
@@ -115,10 +115,18 @@
"-o %(ci_build_root_dir)s/"
"spe/bin/tfm.hex -Intel; "
"fi;"),
- "arm/rse/tc/tc2": ("srec_cat "
+ "arm/rse/tc/tc2": ("if [ -f \"%(ci_build_root_dir)s/spe/bin/rse_bl1_tests.bin\" ]; then "
+ "srec_cat "
+ "%(ci_build_root_dir)s/spe/bin/bl1_1.bin -Binary -offset 0x0 "
+ "%(ci_build_root_dir)s/spe/bin/rse_bl1_tests.bin -Binary -offset 0x10000 "
+ "%(ci_build_root_dir)s/spe/bin/rom_dma_ics.bin -Binary -offset 0x1F000 "
+ "-o %(ci_build_root_dir)s/spe/bin/rom.bin -Binary;"
+ "else "
+ "srec_cat "
"%(ci_build_root_dir)s/spe/bin/bl1_1.bin -Binary -offset 0x0 "
"%(ci_build_root_dir)s/spe/bin/rom_dma_ics.bin -Binary -offset 0x1F000 "
"-o %(ci_build_root_dir)s/spe/bin/rom.bin -Binary;"
+ "fi;"
"curl --fail --no-progress-meter --connect-timeout 10 --retry 6 -LS -o fiptool https://downloads.trustedfirmware.org/tf-m/rse/tc/fiptool;"
"chmod 755 fiptool;"
"curl --fail --no-progress-meter --connect-timeout 10 --retry 6 -LS -o fip.bin https://downloads.trustedfirmware.org/tf-m/rse/tc/fip.bin;"
@@ -355,6 +363,9 @@
# RSE_TC2_GCC_2_RegS_RegNS_Debug_BL2
("arm/rse/tc/tc2", "GCC_10_3", "2",
"RegS, RegNS", "OFF", "Debug", True, "", ""),
+ # RSE_TC_GCC_2_RegBL1_1_RegBL1_2_Debug_BL2
+ ("arm/rse/tc/tc2", "GCC_10_3", "2",
+ "RegBL1_1", "OFF", "Debug", True, "", ""),
# RSE_RDFremont_GCC_2_Release_BL2_NSOFF_CFG0
("arm/rse/rdfremont", "GCC_10_3", "2",
"OFF", "OFF", "Release", True, "", "NSOFF, CFG0"),
diff --git a/lava_helper/lava_helper_configs.py b/lava_helper/lava_helper_configs.py
index 31311a4..1e5d809 100644
--- a/lava_helper/lava_helper_configs.py
+++ b/lava_helper/lava_helper_configs.py
@@ -65,6 +65,22 @@
'fixup': {"pass": "PASSED", "fail": "FAILED", "skip": "SKIPPED"},
}
+bl1_1_reg_tests_monitors_cfg = {
+ 'name': 'BL1_1_regression_suite',
+ 'start': 'Execute test suites for the BL1_1 area',
+ 'end': 'End of BL1_1 test suites',
+ 'pattern': r"TEST: (?P<test_case_id>.+?) - (?P<result>(PASSED|FAILED|SKIPPED))",
+ 'fixup': {"pass": "PASSED", "fail": "FAILED", "skip": "SKIPPED"},
+}
+
+bl1_2_reg_tests_monitors_cfg = {
+ 'name': 'BL1_2_regression_suite',
+ 'start': 'Execute test suites for the BL1_2 area',
+ 'end': 'End of BL1_2 test suites',
+ 'pattern': r"TEST: (?P<test_case_id>.+?) - (?P<result>(PASSED|FAILED|SKIPPED))",
+ 'fixup': {"pass": "PASSED", "fail": "FAILED", "skip": "SKIPPED"},
+}
+
arch_tests_monitors_cfg = {
'name': 'psa_api_suite',
'start': 'Running..',
@@ -81,7 +97,9 @@
reg_tests_monitors = [] + \
([mcuboot_tests_monitor_cfg] if "RegBL2" in os.getenv("TEST_REGRESSION") and os.getenv("BL2") == "True" else []) + \
([s_reg_tests_monitors_cfg] if "RegS" in os.getenv("TEST_REGRESSION") else []) + \
- ([ns_reg_tests_monitors_cfg] if "RegNS" in os.getenv("TEST_REGRESSION") else [])
+ ([ns_reg_tests_monitors_cfg] if "RegNS" in os.getenv("TEST_REGRESSION") else []) + \
+ ([bl1_1_reg_tests_monitors_cfg] if "RegBL1_1" in os.getenv("TEST_REGRESSION") else []) + \
+ ([bl1_2_reg_tests_monitors_cfg] if "RegBL1_2" in os.getenv("TEST_REGRESSION") else [])
arch_tests_monitors = [arch_tests_monitors_cfg]