feat(rd): secure hafnium build for rdfremontcfg1
Add hafnium build support for RD-Fremont-Cfg1 platform. FVP version of
RD-Fremont-Cfg1 support 8 CPUs with 8 GICR frames.
Change-Id: Ie113a60bf9ec443bbfae10552dce3181465d46e4
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
diff --git a/BUILD.gn b/BUILD.gn
index 4340c5d..301eb46 100644
--- a/BUILD.gn
+++ b/BUILD.gn
@@ -35,6 +35,10 @@
deps = [ "//src:hafnium(:secure_rd_fremont_clang)" ]
}
+group("secure_rd_fremont_cfg1") {
+ deps = [ "//src:hafnium(:secure_rd_fremont_cfg1_clang)" ]
+}
+
group("root") {
deps = [
":aem_v8a_fvp_vhe",
@@ -43,6 +47,7 @@
":secure_aem_v8a_fvp_vhe",
":secure_qemu_aarch64",
":secure_rd_fremont",
+ ":secure_rd_fremont_cfg1",
":secure_tc",
"//src/arch/aarch64/qemuloader:bl(:qemu_aarch64_vhe_clang)",
]
@@ -108,6 +113,31 @@
}
}
+aarch64_toolchains("secure_rd_fremont_cfg1") {
+ cpu = "cortex-a57"
+ origin_address = "0xF9000000"
+ boot_flow = "//src/boot_flow:spmc"
+ console = "//src/arch/aarch64/pl011"
+ iommu = "//src/iommu:absent"
+ gic_version = 4
+ gicd_base_address = "0x30000000"
+ gicr_base_address = "0x30100000"
+ gicr_frames = 8
+ heap_pages = 180
+ max_cpus = 8
+ max_vms = 8
+ toolchain_args = {
+ plat_ffa = "//src/arch/aarch64/plat/ffa:spmc"
+ plat_psci = "//src/arch/aarch64/plat/psci:spmc"
+ plat_interrupts = "//src/arch/aarch64/plat/interrupts:gicv3"
+ secure_world = "1"
+ pl011_base_address = "0x2A410000"
+ enable_mte = "1"
+ plat_log_level = "LOG_LEVEL_INFO"
+ plat_num_virtual_interrupts_ids = 1024
+ }
+}
+
aarch64_toolchains("secure_aem_v8a_fvp_vhe") {
cpu = "cortex-a57"
origin_address = "0x06000000"
diff --git a/secure_rd_fremont_cfg1/BUILD.gn b/secure_rd_fremont_cfg1/BUILD.gn
new file mode 100644
index 0000000..38afb8a
--- /dev/null
+++ b/secure_rd_fremont_cfg1/BUILD.gn
@@ -0,0 +1,8 @@
+# Copyright 2023 The Hafnium Authors.
+#
+# Use of this source code is governed by a BSD-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/BSD-3-Clause.
+
+source_set("secure_rd_fremont_cfg1") {
+}