diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index be05beb..4bb957e 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -2190,6 +2190,8 @@
         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC5"/>         
         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC6"/>             
         <file category="linkerScript" name="Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct"       version="1.0.0" attr="config" condition="ARMCC6"/>         
+        <file category="sourceC"      name="Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="other"        name="Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld"        version="1.0.0" attr="config" condition="GCC"/>
         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/system_ARMCA5.c"      version="1.0.0" attr="config"/>
         <file category="sourceC"      name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c"         version="1.0.0" attr="config"/>
         <file category="header"       name="Device/ARM/ARMCA5/Include/system_ARMCA5.h"     version="1.0.0" attr="config"/>
@@ -2209,6 +2211,8 @@
         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC5"/> 
         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC6"/>             
         <file category="linkerScript" name="Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct"       version="1.0.0" attr="config" condition="ARMCC6"/> 
+        <file category="sourceC"      name="Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c" version="1.0.0" attr="config" condition="GCC"/>
+        <file category="other"        name="Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld"        version="1.0.0" attr="config" condition="GCC"/>
         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/system_ARMCA7.c"      version="1.0.0" attr="config"/>
         <file category="sourceC"      name="Device/ARM/ARMCA7/Source/mmu_ARMCA7.c"         version="1.0.0" attr="config"/>
         <file category="header"       name="Device/ARM/ARMCA7/Include/system_ARMCA7.h"     version="1.0.0" attr="config"/>
diff --git a/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
index d10e50f..0bffdc8 100644
--- a/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
+++ b/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c
@@ -1,6 +1,6 @@
 /******************************************************************************
  * @file     startup_ARMCA5.c
- * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
  * @version  V1.00
  * @date     22 Feb 2017
  *
diff --git a/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld b/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld
new file mode 100644
index 0000000..ff1f39e
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld
@@ -0,0 +1,181 @@
+#include "mem_ARMCA5.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}
diff --git a/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct b/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct
new file mode 100644
index 0000000..41e562c
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct
@@ -0,0 +1,77 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE       ; load region size_region
+{
+  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+  {
+      * (RESET, +FIRST)         ; Vector table and other startup code
+      * (InRoot$$Sections)      ; All (library) code that must be in a root region
+      * (+RO-CODE)              ; Application RO code (.text)
+      * (+RO-DATA)              ; Application RO data (.constdata)
+  }
+  
+  RW_DATA __RAM_BASE __RW_DATA_SIZE
+  { * (+RW) }                   ; Application RW data (.data)
+  
+  ZI_DATA (__RAM_BASE+
+           __RW_DATA_SIZE) __ZI_DATA_SIZE
+  { * (+ZI) }                   ; Application ZI data (.bss)
+  
+  ARM_LIB_HEAP  (__RAM_BASE
+                +__RW_DATA_SIZE
+                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up
+  { }
+    
+  ARM_LIB_STACK (__RAM_BASE
+                +__RAM_SIZE       
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE
+                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }              
+                
+  UND_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE
+                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack
+  { }
+  
+  ABT_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE
+                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack
+  { }
+  
+  SVC_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE
+                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack
+  { }  
+  
+  IRQ_STACK     (__RAM_BASE
+                +__RAM_SIZE
+                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack
+  { }  
+  
+  FIQ_STACK     (__RAM_BASE
+                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack
+  { }
+  
+  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU
+  { }                                        
+}
diff --git a/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c
new file mode 100644
index 0000000..7c8c7d4
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCA5.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     _start                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}
diff --git a/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld b/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld
new file mode 100644
index 0000000..62c4ba1
--- /dev/null
+++ b/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld
@@ -0,0 +1,181 @@
+#include "mem_ARMCA7.h" 
+
+MEMORY
+{
+  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE 
+  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        KEEP(*(.isr_vector))
+        Image$$VECTORS$$Limit = .;
+
+        *(SVC_TABLE)
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        Image$$RO_DATA$$Base = .;
+        *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
+
+        KEEP(*(.eh_frame*))
+    } > ROM
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > ROM
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > ROM
+    __exidx_end = .;
+
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        __copy_table_end__ = .;
+    } > ROM
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > ROM
+
+    __etext = .;
+        
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += __TTB_SIZE;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
+    .data : AT (__etext)
+    {
+        Image$$RW_DATA$$Base = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+        Image$$RW_DATA$$Limit = .;
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    
+    .bss ALIGN(0x400):
+    {
+        Image$$ZI_DATA$$Base = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+        Image$$ZI_DATA$$Limit = .;
+        __end__ = .;
+        end = __end__;
+    } > RAM
+
+#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        Image$$HEAP$$ZI$$Base = .;
+        . += __HEAP_SIZE;
+        Image$$HEAP$$ZI$$Limit = .;
+        __HeapLimit = .;
+    } > RAM  
+#endif
+
+    .stack (NOLOAD):
+    {
+        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;
+        . = ALIGN(8);
+        
+        __StackTop = .;
+        Image$$SYS_STACK$$ZI$$Base = .;
+        . += __STACK_SIZE;
+        Image$$SYS_STACK$$ZI$$Limit = .;
+        __stack = .;
+
+        Image$$FIQ_STACK$$ZI$$Base = .;
+        . += __FIQ_STACK_SIZE;
+        Image$$FIQ_STACK$$ZI$$Limit = .;
+
+        Image$$IRQ_STACK$$ZI$$Base = .;
+        . += __IRQ_STACK_SIZE;
+        Image$$IRQ_STACK$$ZI$$Limit = .;
+
+        Image$$SVC_STACK$$ZI$$Base = .;
+        . += __SVC_STACK_SIZE;
+        Image$$SVC_STACK$$ZI$$Limit = .;
+
+        Image$$ABT_STACK$$ZI$$Base = .;
+        . += __ABT_STACK_SIZE;
+        Image$$ABT_STACK$$ZI$$Limit = .;
+
+        Image$$UND_STACK$$ZI$$Base = .;
+        . += __UND_STACK_SIZE;
+        Image$$UND_STACK$$ZI$$Limit = .;
+        
+    } > RAM
+}
diff --git a/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
new file mode 100644
index 0000000..dcce016
--- /dev/null
+++ b/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c
@@ -0,0 +1,138 @@
+/******************************************************************************
+ * @file     startup_ARMCA7.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     22 Feb 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+  __ASM volatile(
+  "LDR    PC, =Reset_Handler                        \n"
+  "LDR    PC, =Undef_Handler                        \n"
+  "LDR    PC, =SVC_Handler                          \n"
+  "LDR    PC, =PAbt_Handler                         \n"
+  "LDR    PC, =DAbt_Handler                         \n"
+  "NOP                                              \n"
+  "LDR    PC, =IRQ_Handler                          \n"
+  "LDR    PC, =FIQ_Handler                          \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+  __ASM volatile(
+
+  // Mask interrupts
+  "CPSID   if                                      \n"
+
+  // Put any cores other than 0 to sleep
+  "MRC     p15, 0, R0, c0, c0, 5                   \n"  // Read MPIDR
+  "ANDS    R0, R0, #3                              \n"
+  "goToSleep:                                      \n"
+  "WFINE                                           \n"
+  "BNE     goToSleep                               \n"
+
+  // Reset SCTLR Settings
+  "MRC     p15, 0, R0, c1, c0, 0                   \n"  // Read CP15 System Control register
+  "BIC     R0, R0, #(0x1 << 12)                    \n"  // Clear I bit 12 to disable I Cache
+  "BIC     R0, R0, #(0x1 <<  2)                    \n"  // Clear C bit  2 to disable D Cache
+  "BIC     R0, R0, #0x1                            \n"  // Clear M bit  0 to disable MMU
+  "BIC     R0, R0, #(0x1 << 11)                    \n"  // Clear Z bit 11 to disable branch prediction
+  "BIC     R0, R0, #(0x1 << 13)                    \n"  // Clear V bit 13 to disable hivecs
+  "MCR     p15, 0, R0, c1, c0, 0                   \n"  // Write value back to CP15 System Control register
+  "ISB                                             \n"
+
+  // Configure ACTLR
+  "MRC     p15, 0, r0, c1, c0, 1                   \n"  // Read CP15 Auxiliary Control Register
+  "ORR     r0, r0, #(1 <<  1)                      \n"  // Enable L2 prefetch hint (UNK/WI since r4p1)
+  "MCR     p15, 0, r0, c1, c0, 1                   \n"  // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  "LDR    R0, =Vectors                             \n"
+  "MCR    p15, 0, R0, c12, c0, 0                   \n"
+
+  // Setup Stack for each exceptional mode
+  "CPS    #0x11                                    \n"
+  "LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x12                                    \n"
+  "LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \n"
+  "CPS    #0x13                                    \n"
+  "LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \n"
+  "CPS    #0x17                                    \n"
+  "LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1B                                    \n"
+  "LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \n"
+  "CPS    #0x1F                                    \n"
+  "LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \n"
+
+  // Call SystemInit
+  "BL     SystemInit                               \n"
+
+  // Unmask interrupts
+  "CPSIE  if                                       \n"
+
+  // Call __main
+  "BL     _start                                   \n"
+  );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+  while(1);
+}