added FPU usage option to partition template. update default memory
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index c349d20..bf35e29 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -351,8 +351,10 @@
 Cortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.
       </description>
       <debug svd="Device/ARM/SVD/ARMCM23.svd"/>
-      <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
+      <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
+      <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
+      <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 
       <device Dname="ARMCM23">
@@ -374,9 +376,11 @@
 class processor based on the ARMv8-M mainline architecture with ARM TrustZone security.
       </description>
       <debug svd="Device/ARM/SVD/ARMCM33.svd"/>
-      <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
+      <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
+      <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
-      <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
+      <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
+      <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"          default="1"/-->
 
       <device Dname="ARMCM33">
         <processor Dcore="Cortex-M33" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dtz="NO_TZ" Dendian="Configurable" Dclock="10000000"/>
@@ -446,8 +450,10 @@
 ARMv8-M Baseline based device with TrustZone
       </description>
       <debug svd="Device/ARM/SVD/ARMv8MBL.svd"/>
-      <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
+      <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
+      <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
+      <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 
       <device Dname="ARMv8MBL">
@@ -463,8 +469,10 @@
 ARMv8-M Mainline based device with TrustZone
       </description>
       <debug svd="Device/ARM/SVD/ARMv8MML.svd"/>
-      <memory id="IROM1"                                start="0x00000000" size="0x00040000" startup="1" default="1"/>
+      <memory id="IROM1"                                start="0x00000000" size="0x00200000" startup="1" default="1"/>
+      <memory id="IROM2"                                start="0x00200000" size="0x00200000" startup="0" default="0"/>
       <memory id="IRAM1"                                start="0x20000000" size="0x00020000" init   ="0" default="1"/>
+      <memory id="IRAM2"                                start="0x20200000" size="0x00020000" init   ="0" default="0"/>
       <!--algorithm name="Device/ARM/Flash/NEW_DEVICE.FLM" start="0x00000000" size="0x00040000"             default="1"/-->
 
       <device Dname="ARMv8MML">
diff --git a/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h b/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
index 7df13dc..e82e5d4 100644
--- a/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
+++ b/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h
@@ -2,7 +2,7 @@
  * @file     partition_ARMCM33.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33
  * @version  V5.00
- * @date     28. October 2016
+ * @date     04. November 2016
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -315,6 +315,10 @@
 // </e>
 */
 
+/*
+// <o>Floating Point Unit usage <0=> Secure state only <1=> Secure and Non-Secure state 
+*/
+#define TZ_FPU_NS_USAGE 1 
 
 /*
 // <h>Setup Interrupt Target
@@ -1137,6 +1141,10 @@
                    ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
   #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
 
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+    SCB->NSACR |= (0x3U << 10U);  // enable non-secure access to CP10 and CP11
+  #endif
+
   #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
     NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
   #endif
diff --git a/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h b/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
index 774c8cf..6457171 100644
--- a/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
+++ b/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h
@@ -2,7 +2,7 @@
  * @file     partition_ARMv8MML.h
  * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8M
  * @version  V5.00
- * @date     27. October 2016
+ * @date     04. November 2016
  ******************************************************************************/
 /*
  * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
@@ -315,6 +315,10 @@
 // </e>
 */
 
+/*
+// <o>Floating Point Unit usage <0=> Secure state only <1=> Secure and Non-Secure state 
+*/
+#define TZ_FPU_NS_USAGE 1 
 
 /*
 // <h>Setup Interrupt Target
@@ -1137,6 +1141,10 @@
                    ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);
   #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
 
+  #if defined (__FPU_USED) && (__FPU_USED == 1U) && defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
+    SCB->NSACR |= (0x3U << 10U);  // enable non-secure access to CP10 and CP11
+  #endif
+
   #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
     NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
   #endif