Updated Core_A devices
Added Cortex-A5 support
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 2395a88..abc7e81 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -16,7 +16,7 @@
- Generic Timer functions
- L1 and L2 Cache functions
- MMU functions
- - Added ARMCA7 and ARMCA9 devices
+ - Added ARMCA5, ARMCA7 and ARMCA9 devices
- Added Startup, System and MMU configuration files
</release>
<release version="5.0.2-dev0">
@@ -492,6 +492,21 @@
</device>
</family>
+ <!-- ****************************** Cortex-A5 ****************************** -->
+ <family Dfamily="ARM Cortex A5" Dvendor="ARM:82">
+ <book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/index.html" title="Cortex-A5 Technical Reference Manual"/>
+ <description>
+The ARM Cortex-A5 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full
+virtual memory capabilities. The Cortex-A5 processor implements the ARMv7-A architecture profile and can execute 32-bit
+ARM instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.
+ </description>
+
+ <device Dname="ARMCA5">
+ <processor Dcore="Cortex-A5" DcoreVersion="r0p1" Dfpu="DP_FPU" Dmpu="MPU" Dendian="Configurable"/>
+ <compile header="Device/ARM/ARMCA5/Include/ARMCA5.h" define="ARMCA5"/>
+ </device>
+ </family>
+
<!-- ****************************** Cortex-A7 ****************************** -->
<family Dfamily="ARM Cortex A7" Dvendor="ARM:82">
<book name="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html" title="Cortex-A7 MPCore Technical Reference Manual"/>
@@ -509,7 +524,7 @@
<!-- ****************************** Cortex-A9 ****************************** -->
<family Dfamily="ARM Cortex A9" Dvendor="ARM:82">
- <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex‑A9 Technical Reference Manual"/>
+ <book name="http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/index.html" title="Cortex-A9 Technical Reference Manual"/>
<description>
The Cortex-A9 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities.
The Cortex-A9 processor implements the ARMv7-A architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions,
@@ -694,6 +709,7 @@
</condition>
<condition id="ARMv7-A Device">
<description>ARMv7-A architecture based device</description>
+ <accept Dcore="Cortex-A5"/>
<accept Dcore="Cortex-A7"/>
<accept Dcore="Cortex-A9"/>
</condition>
@@ -1709,6 +1725,12 @@
<require condition="GCC"/>
</condition>
+ <condition id="ARMCA5 CMSIS">
+ <description>Generic ARM Cortex-A5 device startup and depends on CMSIS Core</description>
+ <require Dvendor="ARM:82" Dname="ARMCA5"/>
+ <require Cclass="CMSIS" Cgroup="CORE"/>
+ </condition>
+
<condition id="ARMCA7 CMSIS">
<description>Generic ARM Cortex-A7 device startup and depends on CMSIS Core</description>
<require Dvendor="ARM:82" Dname="ARMCA7"/>
@@ -1779,6 +1801,7 @@
<description>CMSIS-CORE for Cortex-A</description>
<files>
<!-- CPU independent -->
+ <file category="doc" name="CMSIS/Documentation/Core_A/html/index.html"/>
<file category="include" name="CMSIS/Core_A/Include/"/>
</files>
</component>
@@ -2072,7 +2095,7 @@
<description>System and Startup for Generic ARM ARMv8MML device</description>
<files>
<!-- include folder / device header file -->
- <file category="include" name="Device/ARM/ARMv8MML/Include/"/>
+ <file category="include" name="Device/ARM/ARMv8MML/Include/"/>
<!-- startup / system file -->
<file category="sourceC" name="Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.c" version="1.0.0" attr="config" condition="GCC"/>
<file category="linkerScript" name="Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld" version="1.0.0" attr="config" condition="GCC"/>
@@ -2082,12 +2105,28 @@
</files>
</component>
+ <!-- Cortex-A5 -->
+ <component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="ARMCA5 CMSIS">
+ <description>System and Startup for Generic ARM Cortex-A5 device</description>
+ <files>
+ <!-- include folder / device header file -->
+ <file category="include" name="Device/ARM/ARMCA5/Include/"/>
+ <!-- startup / system / mmu files -->
+ <file category="sourceC" name="Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c" version="1.0.0" attr="config" condition="ARMCC"/>
+ <file category="sourceC" name="Device/ARM/ARMCA5/Source/system_ARMCA5.c" version="1.0.0" attr="config"/>
+ <file category="sourceC" name="Device/ARM/ARMCA5/Source/mmu_ARMCA5.c" version="1.0.0" attr="config"/>
+ <file category="header" name="Device/ARM/ARMCA5/Include/system_ARMCA5.h" version="1.0.0" attr="config"/>
+ <file category="header" name="Device/ARM/ARMCA5/Include/mem_ARMCA5.h" version="1.0.0" attr="config"/>
+ <file category="linkerScript" name="Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct" version="1.0.0" attr="config"/>
+ </files>
+ </component>
+
<!-- Cortex-A7 -->
<component Cclass="Device" Cgroup="Startup" Cversion="1.0.0" condition="ARMCA7 CMSIS">
<description>System and Startup for Generic ARM Cortex-A7 device</description>
<files>
<!-- include folder / device header file -->
- <file category="include" name="Device/ARM/ARMCA7/Include/"/>
+ <file category="include" name="Device/ARM/ARMCA7/Include/"/>
<!-- startup / system / mmu files -->
<file category="sourceC" name="Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c" version="1.0.0" attr="config" condition="ARMCC"/>
<file category="sourceC" name="Device/ARM/ARMCA7/Source/system_ARMCA7.c" version="1.0.0" attr="config"/>
diff --git a/CMSIS/Core_A/Include/cmsis_armcc.h b/CMSIS/Core_A/Include/cmsis_armcc.h
index b712ce4..a6c0d16 100644
--- a/CMSIS/Core_A/Include/cmsis_armcc.h
+++ b/CMSIS/Core_A/Include/cmsis_armcc.h
@@ -218,6 +218,16 @@
return(__regCPSR);
}
+
+/** \brief Set CPSR Register
+ \param [in] cpsr CPSR value to set
+ */
+__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
+{
+ register uint32_t __regCPSR __ASM("cpsr");
+ __regCPSR = cpsr;
+}
+
/** \brief Get Mode
\return Processor Mode
*/
diff --git a/CMSIS/Core_A/Include/core_ca.h b/CMSIS/Core_A/Include/core_ca.h
index a014584..0e2ce14 100644
--- a/CMSIS/Core_A/Include/core_ca.h
+++ b/CMSIS/Core_A/Include/core_ca.h
@@ -138,6 +138,21 @@
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
+
+ #ifndef __GIC_PRESENT
+ #define __GIC_PRESENT 1U
+ #warning "__GIC_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __TIM_PRESENT
+ #define __TIM_PRESENT 1U
+ #warning "__TIM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __L2C_PRESENT
+ #define __L2C_PRESENT 0U
+ #warning "__L2C_PRESENT not defined in device header file; using default!"
+ #endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
@@ -513,6 +528,7 @@
#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< L2C_310 Declaration */
#endif
+#if (__GIC_PRESENT == 1U)
/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
*/
typedef struct
@@ -554,10 +570,12 @@
} GICInterface_Type;
#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
+#endif
+#if (__TIM_PRESENT == 1U)
+#if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
/** \brief Structure type to access the Private Timer
*/
-#if (__CORTEX_A == 9U)
typedef struct
{
__IO uint32_t LOAD; // +0x000 - RW - Private Timer Load Register
@@ -574,6 +592,7 @@
} Timer_Type;
#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< Timer configuration struct */
#endif
+#endif
/*******************************************************************************
* Hardware Abstraction Layer
@@ -805,7 +824,8 @@
#endif
/* ########################## GIC functions ###################################### */
-
+#if (__GIC_PRESENT == 1U)
+
__STATIC_INLINE void GIC_EnableDistributor(void)
{
GICDistributor->ICDDCR |= 1; //enable distributor
@@ -1026,9 +1046,11 @@
GIC_DistInit();
GIC_CPUInterfaceInit(); //per CPU
}
+#endif
/* ########################## Generic Timer functions ############################ */
-
+#if (__TIM_PRESENT == 1U)
+
/* PL1 Physical Timer */
#if (__CORTEX_A == 7U)
__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
@@ -1046,7 +1068,7 @@
}
/* Private Timer */
-#elif (__CORTEX_A == 9U)
+#elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U))
__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
PTIM->LOAD = value;
}
@@ -1071,6 +1093,7 @@
PTIM->ISR = 1;
}
#endif
+#endif
/* ########################## MMU functions ###################################### */
diff --git a/Device/ARM/ARMCA5/Include/ARMCA5.h b/Device/ARM/ARMCA5/Include/ARMCA5.h
new file mode 100644
index 0000000..02d80d2
--- /dev/null
+++ b/Device/ARM/ARMCA5/Include/ARMCA5.h
@@ -0,0 +1,135 @@
+/******************************************************************************
+ * @file ARMCA5.h
+ * @brief CMSIS Cortex-A5 Core Peripheral Access Layer Header File
+ * @version V1.00
+ * @data 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARMCA5_H__
+#define __ARMCA5_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/****** SGI Interrupts Numbers ****************************************/
+ SGI0_IRQn = 0,
+ SGI1_IRQn = 1,
+ SGI2_IRQn = 2,
+ SGI3_IRQn = 3,
+ SGI4_IRQn = 4,
+ SGI5_IRQn = 5,
+ SGI6_IRQn = 6,
+ SGI7_IRQn = 7,
+ SGI8_IRQn = 8,
+ SGI9_IRQn = 9,
+ SGI10_IRQn = 10,
+ SGI11_IRQn = 11,
+ SGI12_IRQn = 12,
+ SGI13_IRQn = 13,
+ SGI14_IRQn = 14,
+ SGI15_IRQn = 15,
+
+/****** Cortex-A5 Processor Exceptions Numbers ****************************************/
+ GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */
+ PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */
+ PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */
+
+/****** Platform Exceptions Numbers ***************************************************/
+ Watchdog_IRQn = 32, /*!< SP805 Interrupt */
+ Timer0_IRQn = 34, /*!< SP804 Interrupt */
+ Timer1_IRQn = 35, /*!< SP804 Interrupt */
+ RTClock_IRQn = 36, /*!< PL031 Interrupt */
+ UART0_IRQn = 37, /*!< PL011 Interrupt */
+ UART1_IRQn = 38, /*!< PL011 Interrupt */
+ UART2_IRQn = 39, /*!< PL011 Interrupt */
+ UART3_IRQn = 40, /*!< PL011 Interrupt */
+ MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */
+ MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */
+ AACI_IRQn = 43, /*!< PL041 Interrupt */
+ Keyboard_IRQn = 44, /*!< PL050 Interrupt */
+ Mouse_IRQn = 45, /*!< PL050 Interrupt */
+ CLCD_IRQn = 46, /*!< PL111 Interrupt */
+ Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */
+ VFS2_IRQn = 73, /*!< VFS2 Interrupt */
+} IRQn_Type;
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+/* Peripheral and RAM base address */
+#define VE_A5_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
+#define VE_A5_MP_FLASH_BASE1 (0x08000000UL) /*!< (FLASH1 ) Base Address */
+#define VE_A5_MP_PERIPH_BASE (0x18000000UL) /*!< (Peripheral) Base Address */
+#define VE_A5_MP_SRAM_BASE (0x2E000000UL) /*!< (SRAM ) Base Address */
+#define VE_A5_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */
+#define VE_A5_MP_VRAM_BASE (0x18000000UL) /*!< (VRAM ) Base Address */
+#define VE_A5_MP_ETHERNET_BASE (0x02000000UL + VE_A5_MP_PERIPH_BASE) /*!< (ETHERNET ) Base Address */
+#define VE_A5_MP_USB_BASE (0x03000000UL + VE_A5_MP_PERIPH_BASE) /*!< (USB ) Base Address */
+#define VE_A5_MP_DAP_BASE (0x1C000000UL) /*!< (DAP ) Base Address */
+#define VE_A5_MP_SYSTEM_REG_BASE (0x00010000UL + 0x1C000000UL) /*!< (SYSTEM REG) Base Address */
+#define VE_A5_MP_SERIAL_BASE (0x00030000UL + 0x1C000000UL) /*!< (SERIAL ) Base Address */
+#define VE_A5_MP_AACI_BASE (0x00040000UL + 0x1C000000UL) /*!< (AACI ) Base Address */
+#define VE_A5_MP_MMCI_BASE (0x00050000UL + 0x1C000000UL) /*!< (MMCI ) Base Address */
+#define VE_A5_MP_KMI0_BASE (0x00060000UL + 0x1C000000UL) /*!< (KMI0 ) Base Address */
+#define VE_A5_MP_UART_BASE (0x00090000UL + 0x1C000000UL) /*!< (UART ) Base Address */
+#define VE_A5_MP_WDT_BASE (0x000F0000UL + 0x1C000000UL) /*!< (WDT ) Base Address */
+#define VE_A5_MP_TIMER_BASE (0x00110000UL + 0x1C000000UL) /*!< (TIMER ) Base Address */
+#define VE_A5_MP_DVI_BASE (0x00160000UL + 0x1C000000UL) /*!< (DVI ) Base Address */
+#define VE_A5_MP_RTC_BASE (0x00170000UL + 0x1C000000UL) /*!< (RTC ) Base Address */
+#define VE_A5_MP_UART4_BASE (0x001B0000UL + 0x1C000000UL) /*!< (UART4 ) Base Address */
+#define VE_A5_MP_CLCD_BASE (0x001F0000UL + 0x1C000000UL) /*!< (CLCD ) Base Address */
+#define VE_A5_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + 0x2C000000UL) /*!< (GIC DIST ) Base Address */
+#define VE_A5_MP_GIC_INTERFACE_BASE (0x00000100UL + 0x2C000000UL) /*!< (GIC CPU IF) Base Address */
+#define VE_A5_MP_PRIVATE_TIMER (0x00000600UL + 0x2C000000UL) /*!< (PTIM ) Base Address */
+#define GIC_DISTRIBUTOR_BASE VE_A5_MP_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE VE_A5_MP_GIC_INTERFACE_BASE
+#define TIMER_BASE VE_A5_MP_PRIVATE_TIMER
+
+//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.
+//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.
+#define VE_A5_MP_PL310_BASE (0x2C0F0000UL) /*!< (L2C-310 ) Base Address */
+#define L2C_310_BASE VE_A5_MP_PL310_BASE
+
+/* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */
+#define __CA_REV 0x0000U /* Core revision r0p0 */
+#define __CORTEX_A 5U /* Cortex-A5 Core */
+#define __FPU_PRESENT 1U /* FPU present */
+#define __GIC_PRESENT 1U /* GIC present */
+#define __TIM_PRESENT 1U /* TIM present */
+#define __L2C_PRESENT 0U /* L2C present */
+
+#include "core_ca.h"
+#include <system_ARMCA5.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ARMCA5_H__
diff --git a/Device/ARM/ARMCA5/Include/mem_ARMCA5.h b/Device/ARM/ARMCA5/Include/mem_ARMCA5.h
new file mode 100644
index 0000000..10efc94
--- /dev/null
+++ b/Device/ARM/ARMCA5/Include/mem_ARMCA5.h
@@ -0,0 +1,94 @@
+/**************************************************************************//**
+ * @file mem_ARMCA5.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/Device/ARM/ARMCA5/Include/system_ARMCA5.h b/Device/ARM/ARMCA5/Include/system_ARMCA5.h
new file mode 100644
index 0000000..691e6be
--- /dev/null
+++ b/Device/ARM/ARMCA5/Include/system_ARMCA5.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+ * @file system_ARMCA5.h
+ * @brief CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void(*IRQHandler)();
+uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+uint32_t InterruptHandlerUnregister(IRQn_Type);
+void SystemCoreClockUpdate (void);
+extern uint32_t SystemCoreClock;
+void SystemInit (void);
+void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct b/Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct
new file mode 100644
index 0000000..a807d93
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/ARM/ARMCA5.sct
@@ -0,0 +1,77 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd. All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express
+
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x80000000.
+
+#include "mem_ARMCA5.h"
+
+SDRAM __ROM_BASE __ROM_SIZE ; load region size_region
+{
+ VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address
+ {
+ * (RESET, +FIRST) ; Vector table and other startup code
+ * (InRoot$$Sections) ; All (library) code that must be in a root region
+ * (+RO-CODE) ; Application RO code (.text)
+ * (+RO-DATA) ; Application RO data (.constdata)
+ }
+
+ RW_DATA __RAM_BASE __RW_DATA_SIZE
+ { * (+RW) } ; Application RW data (.data)
+
+ ZI_DATA (__RAM_BASE+
+ __RW_DATA_SIZE) __ZI_DATA_SIZE
+ { * (+ZI) } ; Application ZI data (.bss)
+
+ ARM_LIB_HEAP (__RAM_BASE
+ +__RW_DATA_SIZE
+ +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up
+ { }
+
+ UND_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__STACK_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE
+ -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack
+ { }
+
+ ABT_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__STACK_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE
+ -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack
+ { }
+
+ SVC_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__STACK_SIZE
+ -__FIQ_STACK_SIZE
+ -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack
+ { }
+
+ IRQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__STACK_SIZE
+ -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack
+ { }
+
+ FIQ_STACK (__RAM_BASE
+ +__RAM_SIZE
+ -__STACK_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack
+ { }
+
+ ARM_LIB_STACK (__RAM_BASE
+ +__RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
+ { }
+
+ TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU
+ { }
+}
diff --git a/Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c b/Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c
new file mode 100644
index 0000000..3e3175c
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/ARM/startup_ARMCA5.c
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t Image$$FIQ_STACK$$ZI$$Limit;
+extern uint32_t Image$$IRQ_STACK$$ZI$$Limit;
+extern uint32_t Image$$SVC_STACK$$ZI$$Limit;
+extern uint32_t Image$$ABT_STACK$$ZI$$Limit;
+extern uint32_t Image$$UND_STACK$$ZI$$Limit;
+extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) __attribute__ ((section("RESET")));
+__ASM void Vectors(void) {
+ IMPORT Reset_Handler
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+uint32_t reg;
+
+ // Put any cores other than 0 to sleep
+ if ((__get_MPIDR()&3U)!=0) __WFI();
+
+ reg = __get_SCTLR(); // Read CP15 System Control register
+ reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
+ reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
+ reg &= ~(0x1 << 0); // Clear M bit 0 to disable MMU
+ reg &= ~(0x1 << 11); // Clear Z bit 11 to disable branch prediction
+ reg &= ~(0x1 << 13); // Clear V bit 13 to disable hivecs
+ __set_SCTLR(reg); // Write value back to CP15 System Control register
+ __ISB();
+
+ reg = __get_ACTRL(); // Read CP15 Auxiliary Control Register
+ reg |= (0x1 << 1); // Enable L2 prefetch hint (UNK/WI since r4p1)
+ __set_ACTRL(reg); // Write CP15 Auxiliary Control Register
+
+ __set_VBAR((uint32_t)((uint32_t*)&Vectors));
+
+ // Setup Stack for each exceptional mode
+ __set_mode(FIQ_MODE);
+ __set_SP((uint32_t)&Image$$FIQ_STACK$$ZI$$Limit);
+ __set_mode(IRQ_MODE);
+ __set_SP((uint32_t)&Image$$IRQ_STACK$$ZI$$Limit);
+ __set_mode(SVC_MODE);
+ __set_SP((uint32_t)&Image$$SVC_STACK$$ZI$$Limit);
+ __set_mode(ABT_MODE);
+ __set_SP((uint32_t)&Image$$ABT_STACK$$ZI$$Limit);
+ __set_mode(UND_MODE);
+ __set_SP((uint32_t)&Image$$UND_STACK$$ZI$$Limit);
+ __set_mode(SYS_MODE);
+ __set_SP((uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit);
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ __L1C_CleanInvalidateCache(0);
+
+ // Enable MMU, but leave caches disabled (they will be enabled later)
+ reg = __get_SCTLR(); // Read CP15 System Control register
+ reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
+ reg &= ~(0x1 << 28); // Clear TRE bit 28 to disable TEX remap
+ reg &= ~(0x1 << 12); // Clear I bit 12 to disable I Cache
+ reg &= ~(0x1 << 2); // Clear C bit 2 to disable D Cache
+ reg &= ~(0x1 << 1); // Clear A bit 1 to disable strict alignment fault checking
+ reg |= (0x1 << 0); // Set M bit 0 to enable MMU
+ __set_SCTLR(reg); // Write CP15 System Control register
+
+ SystemInit();
+
+ extern void __main(void);
+ __main();
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c b/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c
new file mode 100644
index 0000000..1633bd7
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c
@@ -0,0 +1,235 @@
+/**************************************************************************//**
+ * @file mmu_ARMCA5.c
+ * @brief MMU Configuration for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x0 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x1 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x1 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/Device/ARM/ARMCA5/Source/system_ARMCA5.c b/Device/ARM/ARMCA5/Source/system_ARMCA5.c
new file mode 100644
index 0000000..cab0a98
--- /dev/null
+++ b/Device/ARM/ARMCA5/Source/system_ARMCA5.c
@@ -0,0 +1,85 @@
+/******************************************************************************
+ * @file system_ARMCA5.c
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 16 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ IRQ Handler Register/Unregister
+ *----------------------------------------------------------------------------*/
+IRQHandler IRQTable[40U] = { 0U };
+
+uint32_t IRQCount = sizeof IRQTable / 4U;
+
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+ if (irq < IRQCount) {
+ IRQTable[irq] = handler;
+ return 0U;
+ }
+ else {
+ return 1U;
+ }
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+ if (irq < IRQCount) {
+ IRQTable[irq] = 0U;
+ return 0U;
+ }
+ else {
+ return 1U;
+ }
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+ GIC_Enable();
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+ __FPU_Enable();
+}
diff --git a/Device/ARM/ARMCA7/Include/ARMCA7.h b/Device/ARM/ARMCA7/Include/ARMCA7.h
index abfd243..cb232a4 100644
--- a/Device/ARM/ARMCA7/Include/ARMCA7.h
+++ b/Device/ARM/ARMCA7/Include/ARMCA7.h
@@ -119,6 +119,9 @@
#define __CA_REV 0x0000U /* Core revision r0p0 */
#define __CORTEX_A 7U /* Cortex-A7 Core */
#define __FPU_PRESENT 1U /* FPU present */
+#define __GIC_PRESENT 1U /* GIC present */
+#define __TIM_PRESENT 1U /* TIM present */
+#define __L2C_PRESENT 0U /* L2C present */
#include "core_ca.h"
#include <system_ARMCA7.h>
diff --git a/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c b/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c
index 18fc611..112632d 100644
--- a/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c
+++ b/Device/ARM/ARMCA7/Source/ARM/startup_ARMCA7.c
@@ -1,5 +1,5 @@
/******************************************************************************
- * @file system_ARMCA7.c
+ * @file startup_ARMCA7.c
* @brief CMSIS Device System Source File for ARM Cortex-A7 Device Series
* @version V1.00
* @date 22 Feb 2017
@@ -140,17 +140,6 @@
// Invalidate data cache
__L1C_CleanInvalidateCache(0);
- // Invalidate entire Unified TLB
- __set_TLBIALL(0);
- // Invalidate entire branch predictor array
- __set_BPIALL(0);
- __DSB();
- __ISB();
- // Invalidate instruction cache and flush branch target cache
- __set_ICIALLU(0);
- __DSB();
- __ISB();
-
// Enable MMU, but leave caches disabled (they will be enabled later)
reg = __get_SCTLR(); // Read CP15 System Control register
reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
diff --git a/Device/ARM/ARMCA9/Include/ARMCA9.h b/Device/ARM/ARMCA9/Include/ARMCA9.h
index 567831e..cd5aa3b 100644
--- a/Device/ARM/ARMCA9/Include/ARMCA9.h
+++ b/Device/ARM/ARMCA9/Include/ARMCA9.h
@@ -121,6 +121,9 @@
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
#define __CORTEX_A 9U /*!< Cortex-A9 Core */
#define __FPU_PRESENT 1U /* FPU present */
+#define __GIC_PRESENT 1U /* GIC present */
+#define __TIM_PRESENT 1U /* TIM present */
+#define __L2C_PRESENT 0U /* L2C present */
#include "core_ca.h"
#include <system_ARMCA9.h>
diff --git a/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c b/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c
index efa4b51..a8af5c0 100644
--- a/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/ARM/startup_ARMCA9.c
@@ -1,5 +1,5 @@
/******************************************************************************
- * @file system_ARMCA9.c
+ * @file startup_ARMCA9.c
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 22 Feb 2017
@@ -140,17 +140,6 @@
// Invalidate data cache
__L1C_CleanInvalidateCache(0);
- // Invalidate entire Unified TLB
- __set_TLBIALL(0);
- // Invalidate entire branch predictor array
- __set_BPIALL(0);
- __DSB();
- __ISB();
- // Invalidate instruction cache and flush branch target cache
- __set_ICIALLU(0);
- __DSB();
- __ISB();
-
// Enable MMU, but leave caches disabled (they will be enabled later)
reg = __get_SCTLR(); // Read CP15 System Control register
reg |= (0x1 << 29); // Set AFE bit 29 to enable simplified access permissions model
diff --git a/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c b/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c
index bfb3282..960808e 100644
--- a/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c
+++ b/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c
@@ -1,6 +1,6 @@
/**************************************************************************//**
- * @file mmu_ARMCA7.c
- * @brief MMU Configuration for ARM Cortex-A7 Device Series
+ * @file mmu_ARMCA9.c
+ * @brief MMU Configuration for ARM Cortex-A9 Device Series
* @version V1.00
* @date 22 Feb 2017
*
@@ -208,7 +208,7 @@
// Define private address space entry.
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Define L2CC entry. Uncomment if PL310 is present
- // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A7_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A9_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);