Core(M): Update CoreValidation
Fix scatter files after adding __NO_INIT
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf
new file mode 100644
index 0000000..ce564bb
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf
@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+define symbol __ICFEDIT_size_ttb__ = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
+
+define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
+
+do not initialize { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region { readonly };
+place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region { block TTB };
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0
new file mode 100644
index 0000000..ce564bb
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0
@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+define symbol __ICFEDIT_size_ttb__ = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
+
+define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
+
+do not initialize { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region { readonly };
+place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region { block TTB };
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1 b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1
new file mode 100644
index 0000000..1bdd541
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1
@@ -0,0 +1,136 @@
+/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version V1.0.1
+ * @date 10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =SVC_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s
new file mode 100644
index 0000000..85babb9
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s
@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file startup_ARMCA9.s
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ MODULE ?startup_ARMCA5
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+ PUBLIC Reset_Handler
+ PUBWEAK Undef_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PAbt_Handler
+ PUBWEAK DAbt_Handler
+ PUBWEAK IRQ_Handler
+ PUBWEAK FIQ_Handler
+
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+ section RESET:CODE:NOROOT(2)
+ PUBLIC Vectors
+
+Vectors:
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+
+ section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+
+Reset_Handler:
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5
+ ANDS R0, R0, #3
+goToSleep:
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exception mode
+ CPS #0x11
+ LDR SP, =SFE(FIQ_STACK)
+ CPS #0x12
+ LDR SP, =SFE(IRQ_STACK)
+ CPS #0x13
+ LDR SP, =SFE(SVC_STACK)
+ CPS #0x17
+ LDR SP, =SFE(ABT_STACK)
+ CPS #0x1B
+ LDR SP, =SFE(UND_STACK)
+ CPS #0x1F
+ LDR SP, =SFE(USR_STACK)
+
+ // Call SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __iar_program_start
+ BL __iar_program_start
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+ B .
+
+ END
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0
new file mode 100644
index 0000000..85babb9
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0
@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file startup_ARMCA9.s
+ * @brief CMSIS Device System Source File for ARM Cortex-A5 Device Series
+ * @version V1.00
+ * @date 01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ MODULE ?startup_ARMCA5
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+ PUBLIC Reset_Handler
+ PUBWEAK Undef_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PAbt_Handler
+ PUBWEAK DAbt_Handler
+ PUBWEAK IRQ_Handler
+ PUBWEAK FIQ_Handler
+
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+ section RESET:CODE:NOROOT(2)
+ PUBLIC Vectors
+
+Vectors:
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+
+ section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+
+Reset_Handler:
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5
+ ANDS R0, R0, #3
+goToSleep:
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exception mode
+ CPS #0x11
+ LDR SP, =SFE(FIQ_STACK)
+ CPS #0x12
+ LDR SP, =SFE(IRQ_STACK)
+ CPS #0x13
+ LDR SP, =SFE(SVC_STACK)
+ CPS #0x17
+ LDR SP, =SFE(ABT_STACK)
+ CPS #0x1B
+ LDR SP, =SFE(UND_STACK)
+ CPS #0x1F
+ LDR SP, =SFE(USR_STACK)
+
+ // Call SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __iar_program_start
+ BL __iar_program_start
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+ B .
+
+ END
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1 b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1
new file mode 100644
index 0000000..5f599f6
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA5.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version V1.0.1
+ * @date 13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h
new file mode 100644
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA5.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0
new file mode 100644
index 0000000..6a2a6da
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA5.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf
new file mode 100644
index 0000000..ce564bb
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf
@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+define symbol __ICFEDIT_size_ttb__ = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
+
+define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
+
+do not initialize { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region { readonly };
+place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region { block TTB };
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0
new file mode 100644
index 0000000..ce564bb
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0
@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+define symbol __ICFEDIT_size_ttb__ = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
+
+define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
+
+do not initialize { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region { readonly };
+place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region { block TTB };
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1 b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1
new file mode 100644
index 0000000..da8ae87
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1
@@ -0,0 +1,136 @@
+/******************************************************************************
+ * @file startup_ARMCA7.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
+ * @version V1.0.1
+ * @date 10. January 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA7.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+void Default_Handler(void) __attribute__ ((noreturn));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =SVC_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s
new file mode 100644
index 0000000..6872e9e
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s
@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file startup_ARMCA7.s
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ MODULE ?startup_ARMCA7
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+ PUBLIC Reset_Handler
+ PUBWEAK Undef_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PAbt_Handler
+ PUBWEAK DAbt_Handler
+ PUBWEAK IRQ_Handler
+ PUBWEAK FIQ_Handler
+
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+ section RESET:CODE:NOROOT(2)
+ PUBLIC Vectors
+
+Vectors:
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+
+ section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+
+Reset_Handler:
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5
+ ANDS R0, R0, #3
+goToSleep:
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exception mode
+ CPS #0x11
+ LDR SP, =SFE(FIQ_STACK)
+ CPS #0x12
+ LDR SP, =SFE(IRQ_STACK)
+ CPS #0x13
+ LDR SP, =SFE(SVC_STACK)
+ CPS #0x17
+ LDR SP, =SFE(ABT_STACK)
+ CPS #0x1B
+ LDR SP, =SFE(UND_STACK)
+ CPS #0x1F
+ LDR SP, =SFE(USR_STACK)
+
+ // Call SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __iar_program_start
+ BL __iar_program_start
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+ B .
+
+ END
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0
new file mode 100644
index 0000000..6872e9e
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0
@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file startup_ARMCA7.s
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ MODULE ?startup_ARMCA7
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+ PUBLIC Reset_Handler
+ PUBWEAK Undef_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PAbt_Handler
+ PUBWEAK DAbt_Handler
+ PUBWEAK IRQ_Handler
+ PUBWEAK FIQ_Handler
+
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+ section RESET:CODE:NOROOT(2)
+ PUBLIC Vectors
+
+Vectors:
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+
+ section .text:CODE:NOROOT(4)
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+
+Reset_Handler:
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5
+ ANDS R0, R0, #3
+goToSleep:
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exception mode
+ CPS #0x11
+ LDR SP, =SFE(FIQ_STACK)
+ CPS #0x12
+ LDR SP, =SFE(IRQ_STACK)
+ CPS #0x13
+ LDR SP, =SFE(SVC_STACK)
+ CPS #0x17
+ LDR SP, =SFE(ABT_STACK)
+ CPS #0x1B
+ LDR SP, =SFE(UND_STACK)
+ CPS #0x1F
+ LDR SP, =SFE(USR_STACK)
+
+ // Call SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __iar_program_start
+ BL __iar_program_start
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+ B .
+
+ END
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1 b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1
new file mode 100644
index 0000000..803ec49
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1
@@ -0,0 +1,93 @@
+/******************************************************************************
+ * @file system_ARMCA7.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series
+ * @version V1.0.1
+ * @date 13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h
new file mode 100644
index 0000000..0405aa3
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA7.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0
new file mode 100644
index 0000000..0405aa3
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA7.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA7_H
+#define __SYSTEM_ARMCA7_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA7_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf
new file mode 100644
index 0000000..ce564bb
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf
@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+define symbol __ICFEDIT_size_ttb__ = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
+
+define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
+
+do not initialize { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region { readonly };
+place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region { block TTB };
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0
new file mode 100644
index 0000000..ce564bb
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0
@@ -0,0 +1,67 @@
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;
+define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF;
+define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;
+define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
+define symbol __ICFEDIT_region_TTB_start__ = 0x80500000;
+define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+define symbol __ICFEDIT_size_ttb__ = 0x4000;
+
+define memory mem with size = 4G;
+define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
+ | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
+ | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
+ | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
+ | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
+define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ];
+
+define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB };
+
+do not initialize { section .noinit };
+
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ // Required in a multi-threaded application
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };
+place in IROM_region { readonly };
+place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };
+place in TTB_region { block TTB };
\ No newline at end of file
diff --git a/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s
new file mode 100644
index 0000000..5db9773
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s
@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file startup_ARMCA9.s
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ MODULE ?startup_ARMCA9
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+ PUBLIC Reset_Handler
+ PUBWEAK Undef_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PAbt_Handler
+ PUBWEAK DAbt_Handler
+ PUBWEAK IRQ_Handler
+ PUBWEAK FIQ_Handler
+
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+ section RESET:CODE:NOROOT(2)
+ PUBLIC Vectors
+
+Vectors:
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+
+ section .text:CODE:NOROOT(2)
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+
+Reset_Handler:
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5
+ ANDS R0, R0, #3
+goToSleep:
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exception mode
+ CPS #0x11
+ LDR SP, =SFE(FIQ_STACK)
+ CPS #0x12
+ LDR SP, =SFE(IRQ_STACK)
+ CPS #0x13
+ LDR SP, =SFE(SVC_STACK)
+ CPS #0x17
+ LDR SP, =SFE(ABT_STACK)
+ CPS #0x1B
+ LDR SP, =SFE(UND_STACK)
+ CPS #0x1F
+ LDR SP, =SFE(USR_STACK)
+
+ // Call SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __iar_program_start
+ BL __iar_program_start
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+ B .
+
+ END
diff --git a/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0
new file mode 100644
index 0000000..5db9773
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0
@@ -0,0 +1,140 @@
+/******************************************************************************
+ * @file startup_ARMCA9.s
+ * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version V1.00
+ * @date 01 Nov 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ MODULE ?startup_ARMCA9
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+ PUBLIC Reset_Handler
+ PUBWEAK Undef_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PAbt_Handler
+ PUBWEAK DAbt_Handler
+ PUBWEAK IRQ_Handler
+ PUBWEAK FIQ_Handler
+
+ SECTION SVC_STACK:DATA:NOROOT(3)
+ SECTION IRQ_STACK:DATA:NOROOT(3)
+ SECTION FIQ_STACK:DATA:NOROOT(3)
+ SECTION ABT_STACK:DATA:NOROOT(3)
+ SECTION UND_STACK:DATA:NOROOT(3)
+ SECTION USR_STACK:DATA:NOROOT(3)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+
+ section RESET:CODE:NOROOT(2)
+ PUBLIC Vectors
+
+Vectors:
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+
+ section .text:CODE:NOROOT(2)
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+ EXTERN SystemInit
+ EXTERN __iar_program_start
+
+Reset_Handler:
+
+ // Mask interrupts
+ CPSID if
+
+ // Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5
+ ANDS R0, R0, #3
+goToSleep:
+ WFINE
+ BNE goToSleep
+
+ // Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
+ ISB
+
+ // Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ // Setup Stack for each exception mode
+ CPS #0x11
+ LDR SP, =SFE(FIQ_STACK)
+ CPS #0x12
+ LDR SP, =SFE(IRQ_STACK)
+ CPS #0x13
+ LDR SP, =SFE(SVC_STACK)
+ CPS #0x17
+ LDR SP, =SFE(ABT_STACK)
+ CPS #0x1B
+ LDR SP, =SFE(UND_STACK)
+ CPS #0x1F
+ LDR SP, =SFE(USR_STACK)
+
+ // Call SystemInit
+ BL SystemInit
+
+ // Unmask interrupts
+ CPSIE if
+
+ // Call __iar_program_start
+ BL __iar_program_start
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+Undef_Handler:
+SVC_Handler:
+PAbt_Handler:
+DAbt_Handler:
+IRQ_Handler:
+FIQ_Handler:
+Default_Handler:
+ B .
+
+ END
diff --git a/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h
new file mode 100644
index 0000000..b60ce5a
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA9.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA9_H
+#define __SYSTEM_ARMCA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0
new file mode 100644
index 0000000..b60ce5a
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0
@@ -0,0 +1,65 @@
+/******************************************************************************
+ * @file system_ARMCA9.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA9_H
+#define __SYSTEM_ARMCA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA9_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct
index 63630f1..5300b01 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3
new file mode 100644
index 0000000..fb32110
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3
@@ -0,0 +1,146 @@
+/******************************************************************************
+ * @file startup_ARMCM0.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM0)
+ #include "ARMCM0.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10..31 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct
index 447f912..0f499b2 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3
new file mode 100644
index 0000000..76d1fa8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3
@@ -0,0 +1,148 @@
+/******************************************************************************
+ * @file startup_ARMCM0plus.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM0P)
+ #include "ARMCM0plus.h"
+#elif defined (ARMCM0P_MPU)
+ #include "ARMCM0plus_MPU.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10..31 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct
index 8dc2303..840ba3b 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct
@@ -94,8 +94,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __RAM_NOINIT_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0
new file mode 100644
index 0000000..080c7a8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0
@@ -0,0 +1,161 @@
+/******************************************************************************
+ * @file startup_ARMCM23.c
+ * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct
index 150e459..93ab22b 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct
@@ -92,8 +92,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0
new file mode 100644
index 0000000..080c7a8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0
@@ -0,0 +1,161 @@
+/******************************************************************************
+ * @file startup_ARMCM23.c
+ * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0
new file mode 100644
index 0000000..080c7a8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0
@@ -0,0 +1,161 @@
+/******************************************************************************
+ * @file startup_ARMCM23.c
+ * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0
new file mode 100644
index 0000000..080c7a8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0
@@ -0,0 +1,161 @@
+/******************************************************************************
+ * @file startup_ARMCM23.c
+ * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM23)
+ #include "ARMCM23.h"
+#elif defined (ARMCM23_TZ)
+ #include "ARMCM23_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct
index dda75e3..4309a0b 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0
new file mode 100644
index 0000000..dda75e3
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0
@@ -0,0 +1,76 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc
+; command above MUST be in first line (no comment above!)
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+
+/*----------------------------------------------------------------------------
+ Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+#define __RO_BASE __ROM_BASE
+#define __RO_SIZE __ROM_SIZE
+
+#define __RW_BASE __RAM_BASE
+#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)
+
+
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3
new file mode 100644
index 0000000..b541573
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3
@@ -0,0 +1,150 @@
+/******************************************************************************
+ * @file startup_ARMCM3.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM3)
+ #include "ARMCM3.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1 b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1
new file mode 100644
index 0000000..3c5eda7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1
@@ -0,0 +1,65 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device
+ * @version V1.0.1
+ * @date 15. November 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct
index 1e58a0d..2eeea2e 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct
@@ -92,8 +92,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0
new file mode 100644
index 0000000..044feb7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM33.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M33 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct
index 41ffab1..f000106 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct
@@ -92,8 +92,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0
new file mode 100644
index 0000000..044feb7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM33.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M33 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0
new file mode 100644
index 0000000..044feb7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM33.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M33 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0
new file mode 100644
index 0000000..044feb7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM33.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M33 Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM33)
+ #include "ARMCM33.h"
+#elif defined (ARMCM33_TZ)
+ #include "ARMCM33_TZ.h"
+#elif defined (ARMCM33_DSP_FP)
+ #include "ARMCM33_DSP_FP.h"
+#elif defined (ARMCM33_DSP_FP_TZ)
+ #include "ARMCM33_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVCall Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct
index 9771f25..cefaac3 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct
@@ -92,8 +92,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0
new file mode 100644
index 0000000..d2d21d8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM35P.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M35P Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM35P)
+ #include "ARMCM35P.h"
+#elif defined (ARMCM35P_TZ)
+ #include "ARMCM35P_TZ.h"
+#elif defined (ARMCM35P_DSP_FP)
+ #include "ARMCM35P_DSP_FP.h"
+#elif defined (ARMCM35P_DSP_FP_TZ)
+ #include "ARMCM35P_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct
index b5c400d..05da593 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct
@@ -92,8 +92,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0
new file mode 100644
index 0000000..d2d21d8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM35P.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M35P Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM35P)
+ #include "ARMCM35P.h"
+#elif defined (ARMCM35P_TZ)
+ #include "ARMCM35P_TZ.h"
+#elif defined (ARMCM35P_DSP_FP)
+ #include "ARMCM35P_DSP_FP.h"
+#elif defined (ARMCM35P_DSP_FP_TZ)
+ #include "ARMCM35P_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0
new file mode 100644
index 0000000..d2d21d8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM35P.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M35P Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM35P)
+ #include "ARMCM35P.h"
+#elif defined (ARMCM35P_TZ)
+ #include "ARMCM35P_TZ.h"
+#elif defined (ARMCM35P_DSP_FP)
+ #include "ARMCM35P_DSP_FP.h"
+#elif defined (ARMCM35P_DSP_FP_TZ)
+ #include "ARMCM35P_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0 b/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0
new file mode 100644
index 0000000..d2d21d8
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0
@@ -0,0 +1,170 @@
+/******************************************************************************
+ * @file startup_ARMCM35P.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M35P Device
+ * @version V2.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM35P)
+ #include "ARMCM35P.h"
+#elif defined (ARMCM35P_TZ)
+ #include "ARMCM35P_TZ.h"
+#elif defined (ARMCM35P_DSP_FP)
+ #include "ARMCM35P_DSP_FP.h"
+#elif defined (ARMCM35P_DSP_FP_TZ)
+ #include "ARMCM35P_DSP_FP_TZ.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct
index 991e4e3..eb67b5f 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3
new file mode 100644
index 0000000..2d7ca21
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3
@@ -0,0 +1,152 @@
+/******************************************************************************
+ * @file startup_ARMCM4.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+ #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+ #include "ARMCM4_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct
index 991e4e3..eb67b5f 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3
new file mode 100644
index 0000000..2d7ca21
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3
@@ -0,0 +1,152 @@
+/******************************************************************************
+ * @file startup_ARMCM4.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+ #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+ #include "ARMCM4_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct
index 1b4de8c..632d7ae 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct
@@ -92,8 +92,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0
new file mode 100644
index 0000000..970df5c
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0
@@ -0,0 +1,119 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+; <o0> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_SIZE 0x200
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#define __CV_SIZE ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE ( 0 )
+#endif
+
+#define __RO_BASE ( __ROM_BASE )
+#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE ( __RAM_BASE )
+#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
+
+
+/*----------------------------------------------------------------------------
+ Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
+ ER_CMSE_VENEER __CV_BASE __CV_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
+#endif
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0
new file mode 100644
index 0000000..0557c5f
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCM55.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M55 Device
+ * @version V1.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM55)
+ #include "ARMCM55.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0
new file mode 100644
index 0000000..d66624d
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0
@@ -0,0 +1,107 @@
+/**************************************************************************//**
+ * @file system_ARMCM55.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM55 Device
+ * @version V1.1.0
+ * @date 28. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM55)
+ #include "ARMCM55.h"
+#else
+ #error device not specified!
+#endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM55.h"
+ #endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
+#endif
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+
+ /* Set low-power state for PDEPU */
+ /* 0b00 | ON, PDEPU is not in low-power state */
+ /* 0b01 | ON, but the clock is off */
+ /* 0b10 | RET(ention) */
+ /* 0b11 | OFF */
+
+ /* Clear ELPSTATE, value is 0b11 on Cold reset */
+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
+
+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
+ /* PDEPU ON, Clock OFF */
+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+ __DSB();
+ __ISB();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0
new file mode 100644
index 0000000..a369523
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0
@@ -0,0 +1,119 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+; <o0> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_SIZE 0x200
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#define __CV_SIZE ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE ( 0 )
+#endif
+
+#define __RO_BASE ( __ROM_BASE )
+#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE ( __RAM_BASE )
+#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
+
+
+/*----------------------------------------------------------------------------
+ Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
+ ER_CMSE_VENEER __CV_BASE __CV_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
+#endif
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0
new file mode 100644
index 0000000..0557c5f
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCM55.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M55 Device
+ * @version V1.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM55)
+ #include "ARMCM55.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0
new file mode 100644
index 0000000..d66624d
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0
@@ -0,0 +1,107 @@
+/**************************************************************************//**
+ * @file system_ARMCM55.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM55 Device
+ * @version V1.1.0
+ * @date 28. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM55)
+ #include "ARMCM55.h"
+#else
+ #error device not specified!
+#endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM55.h"
+ #endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
+#endif
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+
+ /* Set low-power state for PDEPU */
+ /* 0b00 | ON, PDEPU is not in low-power state */
+ /* 0b01 | ON, but the clock is off */
+ /* 0b10 | RET(ention) */
+ /* 0b11 | OFF */
+
+ /* Clear ELPSTATE, value is 0b11 on Cold reset */
+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
+
+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
+ /* PDEPU ON, Clock OFF */
+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+ __DSB();
+ __ISB();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0
new file mode 100644
index 0000000..a369523
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0
@@ -0,0 +1,119 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+; <o0> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_SIZE 0x200
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#define __CV_SIZE ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE ( 0 )
+#endif
+
+#define __RO_BASE ( __ROM_BASE )
+#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE ( __RAM_BASE )
+#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
+
+
+/*----------------------------------------------------------------------------
+ Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
+ ER_CMSE_VENEER __CV_BASE __CV_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
+#endif
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0
new file mode 100644
index 0000000..0557c5f
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCM55.c
+ * @brief CMSIS-Core Device Startup File for Cortex-M55 Device
+ * @version V1.1.0
+ * @date 16. December 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM55)
+ #include "ARMCM55.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0
new file mode 100644
index 0000000..d66624d
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0
@@ -0,0 +1,107 @@
+/**************************************************************************//**
+ * @file system_ARMCM55.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM55 Device
+ * @version V1.1.0
+ * @date 28. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM55)
+ #include "ARMCM55.h"
+#else
+ #error device not specified!
+#endif
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM55.h"
+ #endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (5U * XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
+#endif
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+
+ /* Set low-power state for PDEPU */
+ /* 0b00 | ON, PDEPU is not in low-power state */
+ /* 0b01 | ON, but the clock is off */
+ /* 0b10 | RET(ention) */
+ /* 0b11 | OFF */
+
+ /* Clear ELPSTATE, value is 0b11 on Cold reset */
+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);
+
+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
+ /* PDEPU ON, Clock OFF */
+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+ __DSB();
+ __ISB();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct
index e1b77e5..3cba29e 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3
new file mode 100644
index 0000000..509cd33
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3
@@ -0,0 +1,154 @@
+/******************************************************************************
+ * @file startup_ARMCM7.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct
index e1b77e5..3cba29e 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3
new file mode 100644
index 0000000..509cd33
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3
@@ -0,0 +1,154 @@
+/******************************************************************************
+ * @file startup_ARMCM7.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct
index e1b77e5..3cba29e 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct
@@ -62,8 +62,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3 b/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3
new file mode 100644
index 0000000..509cd33
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3
@@ -0,0 +1,154 @@
+/******************************************************************************
+ * @file startup_ARMCM7.c
+ * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device
+ * @version V2.0.3
+ * @date 31. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[240];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 223 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct
index 11cba96..347fb70 100644
--- a/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct
+++ b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct
@@ -99,8 +99,12 @@
.ANY (+XO)
}
- RW_RAM __RW_BASE __RW_SIZE { ; RW data
- .ANY (+RW +ZI)
+ RW_NOINIT __RW_BASE UNINIT __RW_SIZE {
+ *(.bss.noinit)
+ }
+
+ RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+ *(+RW +ZI)
}
#if __HEAP_SIZE > 0
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0
new file mode 100644
index 0000000..cf72c41
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0
@@ -0,0 +1,126 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
+; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
+; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_BASE 0xFFFFFFFF
+#define __CMSEVENEER_SIZE 0x00000400
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
+#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#else
+#define __CV_BASE ( __CMSEVENEER_BASE )
+#endif
+#define __CV_SIZE ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE ( 0 )
+#endif
+
+#define __RO_BASE ( __ROM_BASE )
+#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE ( __RAM_BASE )
+#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
+
+
+/*----------------------------------------------------------------------------
+ Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
+ ER_CMSE_VENEER __CV_BASE __CV_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
+#endif
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0
new file mode 100644
index 0000000..028ca8e
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0
@@ -0,0 +1,314 @@
+/******************************************************************************
+ * @file gcc_arm.ld
+ * @brief GNU Linker Script for Cortex-M based device
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+ <h> Flash Configuration
+ <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ <h> RAM Configuration
+ <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+ <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ <h> Stack / Heap Configuration
+ <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+/* ARMv8-M stack sealing:
+ to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
+ */
+__STACKSEAL_SIZE = 0;
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __StackSeal (only if ARMv8-M stack sealing is used)
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option ‘--section-start’ or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+ __zero_table_end__ = .;
+ } > FLASH
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAM2
+*/
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM AT > RAM
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAM2 AT > RAM2
+*/
+
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAM
+
+ .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAM
+ PROVIDE(__stack = __StackTop);
+
+ /* ARMv8-M stack sealing:
+ to use ARMv8-M stack sealing uncomment '.stackseal' section
+ */
+/*
+ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackSeal = .;
+ . = . + 8;
+ . = ALIGN(8);
+ } > RAM
+*/
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0
new file mode 100644
index 0000000..067871d
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCM85.c
+ * @brief CMSIS Device Startup File for ARMCM85 Device
+ * @version V1.0.0
+ * @date 07. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM85)
+ #include "ARMCM85.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0
new file mode 100644
index 0000000..7a16501
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0
@@ -0,0 +1,106 @@
+/**************************************************************************//**
+ * @file system_ARMCM85.c
+ * @brief CMSIS Device System Source File for ARMCM85 Device
+ * @version V1.0.0
+ * @date 30. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM85)
+ #include "ARMCM85.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM85.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
+#endif
+
+ /* Set CPDLPSTATE.RLPSTATE to 0
+ Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.
+ Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */
+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |
+ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |
+ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk );
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+
+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
+ /* PDEPU ON, Clock OFF */
+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+
+ /* Enable Branch Prediction */
+ SCB->CCR |= SCB_CCR_BP_Msk;
+
+ __DSB();
+ __ISB();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0
new file mode 100644
index 0000000..3eddea7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0
@@ -0,0 +1,126 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
+; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
+; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_BASE 0xFFFFFFFF
+#define __CMSEVENEER_SIZE 0x00000400
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
+#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#else
+#define __CV_BASE ( __CMSEVENEER_BASE )
+#endif
+#define __CV_SIZE ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE ( 0 )
+#endif
+
+#define __RO_BASE ( __ROM_BASE )
+#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE ( __RAM_BASE )
+#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
+
+
+/*----------------------------------------------------------------------------
+ Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
+ ER_CMSE_VENEER __CV_BASE __CV_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
+#endif
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0
new file mode 100644
index 0000000..028ca8e
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0
@@ -0,0 +1,314 @@
+/******************************************************************************
+ * @file gcc_arm.ld
+ * @brief GNU Linker Script for Cortex-M based device
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+ <h> Flash Configuration
+ <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ <h> RAM Configuration
+ <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+ <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ <h> Stack / Heap Configuration
+ <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+/* ARMv8-M stack sealing:
+ to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
+ */
+__STACKSEAL_SIZE = 0;
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __StackSeal (only if ARMv8-M stack sealing is used)
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option ‘--section-start’ or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+ __zero_table_end__ = .;
+ } > FLASH
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAM2
+*/
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM AT > RAM
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAM2 AT > RAM2
+*/
+
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAM
+
+ .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAM
+ PROVIDE(__stack = __StackTop);
+
+ /* ARMv8-M stack sealing:
+ to use ARMv8-M stack sealing uncomment '.stackseal' section
+ */
+/*
+ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackSeal = .;
+ . = . + 8;
+ . = ALIGN(8);
+ } > RAM
+*/
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0
new file mode 100644
index 0000000..a3d881a
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0
@@ -0,0 +1,1301 @@
+/**************************************************************************//**
+ * @file partition_ARMCM85.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
+ * @version V1.0.0
+ * @date 07. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM85_H
+#define PARTITION_ARMCM85_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> Value for SAU->CTRL register bit ALLNS
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>Initialize SAU Region 0
+// <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 1
+// <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 2
+// <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 3
+// <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 4
+// <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 5
+// <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 6
+// <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 7
+// <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point and Vector Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// <o>Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+// <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 256..287
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 288..319
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 320..351
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 352..383
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 384..415
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 416..447
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 448..479
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 480..511
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
+ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM85_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0
new file mode 100644
index 0000000..067871d
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCM85.c
+ * @brief CMSIS Device Startup File for ARMCM85 Device
+ * @version V1.0.0
+ * @date 07. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM85)
+ #include "ARMCM85.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0
new file mode 100644
index 0000000..7a16501
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0
@@ -0,0 +1,106 @@
+/**************************************************************************//**
+ * @file system_ARMCM85.c
+ * @brief CMSIS Device System Source File for ARMCM85 Device
+ * @version V1.0.0
+ * @date 30. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM85)
+ #include "ARMCM85.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM85.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
+#endif
+
+ /* Set CPDLPSTATE.RLPSTATE to 0
+ Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.
+ Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */
+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |
+ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |
+ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk );
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+
+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
+ /* PDEPU ON, Clock OFF */
+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+
+ /* Enable Branch Prediction */
+ SCB->CCR |= SCB_CCR_BP_Msk;
+
+ __DSB();
+ __ISB();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0
new file mode 100644
index 0000000..3eddea7
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0
@@ -0,0 +1,126 @@
+#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
+; command above MUST be in first line (no comment above!)
+
+;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
+; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse
+
+
+/*
+;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+*/
+
+/*--------------------- Flash Configuration ----------------------------------
+; <h> Flash Configuration
+; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x00000000
+#define __ROM_SIZE 0x00080000
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+; <h> RAM Configuration
+; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x20000000
+#define __RAM_SIZE 0x00040000
+
+/*--------------------- Stack / Heap Configuration ---------------------------
+; <h> Stack / Heap Configuration
+; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __STACK_SIZE 0x00000400
+#define __HEAP_SIZE 0x00000C00
+
+/*--------------------- CMSE Veneer Configuration ---------------------------
+; <h> CMSE Veneer Configuration
+; <o0> CMSE VeneerBase Address <0x0-0xFFFFFFFF:8>
+; <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)
+; <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>
+; </h>
+ *----------------------------------------------------------------------------*/
+#define __CMSEVENEER_BASE 0xFFFFFFFF
+#define __CMSEVENEER_SIZE 0x00000400
+
+/*
+;------------- <<< end of configuration section >>> ---------------------------
+*/
+
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap boundary definition
+ *----------------------------------------------------------------------------*/
+#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */
+#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */
+
+/* ----------------------------------------------------------------------------
+ Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE ( 8 )
+#else
+#define __STACKSEAL_SIZE ( 0 )
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Region base & size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)
+#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )
+#else
+#define __CV_BASE ( __CMSEVENEER_BASE )
+#endif
+#define __CV_SIZE ( __CMSEVENEER_SIZE )
+#else
+#define __CV_SIZE ( 0 )
+#endif
+
+#define __RO_BASE ( __ROM_BASE )
+#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE )
+
+#define __RW_BASE ( __RAM_BASE )
+#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )
+
+
+/*----------------------------------------------------------------------------
+ Scatter Region definition
+ *----------------------------------------------------------------------------*/
+LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
+ ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ .ANY (+XO)
+ }
+
+ RW_RAM __RW_BASE __RW_SIZE { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+#if __HEAP_SIZE > 0
+ ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
+ }
+#endif
+
+ ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
+ }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
+ }
+#endif
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers
+ ER_CMSE_VENEER __CV_BASE __CV_SIZE {
+ *(Veneer$$CMSE)
+ }
+}
+#endif
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0
new file mode 100644
index 0000000..028ca8e
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0
@@ -0,0 +1,314 @@
+/******************************************************************************
+ * @file gcc_arm.ld
+ * @brief GNU Linker Script for Cortex-M based device
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
+ */
+
+/*---------------------- Flash Configuration ----------------------------------
+ <h> Flash Configuration
+ <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__ROM_BASE = 0x00000000;
+__ROM_SIZE = 0x00040000;
+
+/*--------------------- Embedded RAM Configuration ----------------------------
+ <h> RAM Configuration
+ <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+ <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00020000;
+
+/*--------------------- Stack / Heap Configuration ----------------------------
+ <h> Stack / Heap Configuration
+ <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ </h>
+ -----------------------------------------------------------------------------*/
+__STACK_SIZE = 0x00000400;
+__HEAP_SIZE = 0x00000C00;
+
+/*
+ *-------------------- <<< end of configuration section >>> -------------------
+ */
+
+/* ARMv8-M stack sealing:
+ to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
+ */
+__STACKSEAL_SIZE = 0;
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+ RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __StackSeal (only if ARMv8-M stack sealing is used)
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ /*
+ * SG veneers:
+ * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address
+ * must be set, either with the command line option ‘--section-start’ or in a linker script,
+ * to indicate where to place these veneers in memory.
+ */
+/*
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ } > FLASH
+*/
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG ((__data_end__ - __data_start__) / 4)
+
+ /* Add each additional data section here */
+/*
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG ((__data2_end__ - __data2_start__) / 4)
+*/
+ __copy_table_end__ = .;
+ } > FLASH
+
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ /* Add each additional bss section here */
+/*
+ LONG (__bss2_start__)
+ LONG ((__bss2_end__ - __bss2_start__) / 4)
+*/
+ __zero_table_end__ = .;
+ } > FLASH
+
+ /**
+ * Location counter can end up 2byte aligned with narrow Thumb code but
+ * __etext is assumed by startup code to be the LMA of a section in RAM
+ * which must be 4byte aligned
+ */
+ __etext = ALIGN (4);
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data)
+ *(.data.*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ /*
+ * Secondary data section, optional
+ *
+ * Remember to add each additional data section
+ * to the .copy.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ __etext2 = ALIGN (4);
+
+ .data2 : AT (__etext2)
+ {
+ . = ALIGN(4);
+ __data2_start__ = .;
+ *(.data2)
+ *(.data2.*)
+ . = ALIGN(4);
+ __data2_end__ = .;
+
+ } > RAM2
+*/
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM AT > RAM
+
+ /*
+ * Secondary bss section, optional
+ *
+ * Remember to add each additional bss section
+ * to the .zero.table above to asure proper
+ * initialization during startup.
+ */
+/*
+ .bss2 :
+ {
+ . = ALIGN(4);
+ __bss2_start__ = .;
+ *(.bss2)
+ *(.bss2.*)
+ . = ALIGN(4);
+ __bss2_end__ = .;
+ } > RAM2 AT > RAM2
+*/
+
+ .heap (COPY) :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ . = . + __HEAP_SIZE;
+ . = ALIGN(8);
+ __HeapLimit = .;
+ } > RAM
+
+ .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ . = . + __STACK_SIZE;
+ . = ALIGN(8);
+ __StackTop = .;
+ } > RAM
+ PROVIDE(__stack = __StackTop);
+
+ /* ARMv8-M stack sealing:
+ to use ARMv8-M stack sealing uncomment '.stackseal' section
+ */
+/*
+ .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :
+ {
+ . = ALIGN(8);
+ __StackSeal = .;
+ . = . + 8;
+ . = ALIGN(8);
+ } > RAM
+*/
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0
new file mode 100644
index 0000000..a3d881a
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0
@@ -0,0 +1,1301 @@
+/**************************************************************************//**
+ * @file partition_ARMCM85.h
+ * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline
+ * @version V1.0.0
+ * @date 07. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PARTITION_ARMCM85_H
+#define PARTITION_ARMCM85_H
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+/*
+// <e>Initialize Security Attribution Unit (SAU) CTRL register
+*/
+#define SAU_INIT_CTRL 1
+
+/*
+// <q> Enable SAU
+// <i> Value for SAU->CTRL register bit ENABLE
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+// <o> When SAU is disabled
+// <0=> All Memory is Secure
+// <1=> All Memory is Non-Secure
+// <i> Value for SAU->CTRL register bit ALLNS
+// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS 0
+
+/*
+// </e>
+*/
+
+/*
+// <h>Initialize Security Attribution Unit (SAU) Address Regions
+// <i>SAU configuration specifies regions to be one of:
+// <i> - Secure and Non-Secure Callable
+// <i> - Non-Secure
+// <i>Note: All memory regions not configured by SAU are Secure
+*/
+#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
+
+/*
+// <e>Initialize SAU Region 0
+// <i> Setup SAU Region 0 memory attributes
+*/
+#define SAU_INIT_REGION0 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR0 "NSC code" /* description SAU region 0 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0 1
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 1
+// <i> Setup SAU Region 1 memory attributes
+*/
+#define SAU_INIT_REGION1 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR1 "NS code" /* description SAU region 1 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1 0x00200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1 0x003FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 2
+// <i> Setup SAU Region 2 memory attributes
+*/
+#define SAU_INIT_REGION2 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR2 "NS data" /* description SAU region 2 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2 0x20200000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2 0x203FFFFF
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 3
+// <i> Setup SAU Region 3 memory attributes
+*/
+#define SAU_INIT_REGION3 1
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR3 "NS peripherals" /* description SAU region 3 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3 0x40000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3 0x40040000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 4
+// <i> Setup SAU Region 4 memory attributes
+*/
+#define SAU_INIT_REGION4 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR4 "SAU region 4" /* description SAU region 4 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 5
+// <i> Setup SAU Region 5 memory attributes
+*/
+#define SAU_INIT_REGION5 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR5 "SAU region 5" /* description SAU region 5 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 6
+// <i> Setup SAU Region 6 memory attributes
+*/
+#define SAU_INIT_REGION6 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR6 "SAU region 6" /* description SAU region 6 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6 0
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize SAU Region 7
+// <i> Setup SAU Region 7 memory attributes
+*/
+#define SAU_INIT_REGION7 0
+
+/*
+// <s>Description
+*/
+#define SAU_INIT_DSCR7 "SAU region 7" /* description SAU region 7 */
+
+/*
+// <o>Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7 0x00000000
+
+/*
+// <o>End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7 0x00000000
+
+/*
+// <o>Region is
+// <0=>Non-Secure
+// <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7 0
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+/*
+// <e>Setup behaviour of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT 1
+
+/*
+// <o> Deep Sleep can be enabled by
+// <0=>Secure and Non-Secure state
+// <1=>Secure state only
+// <i> Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL 1
+
+/*
+// <o>System reset request accessible from
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL 1
+
+/*
+// <o>Priority of Non-Secure exceptions is
+// <0=> Not altered
+// <1=> Lowered to 0x80-0xFF
+// <i> Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL 1
+
+/*
+// <o>BusFault, HardFault, and NMI target
+// <0=> Secure state
+// <1=> Non-Secure state
+// <i> Value for SCB->AIRCR register bit BFHFNMINS
+*/
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// </e>
+*/
+
+/*
+// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)
+*/
+#define TZ_FPU_NS_USAGE 1
+
+/*
+// <o>Floating Point and Vector Unit usage
+// <0=> Secure state only
+// <3=> Secure and Non-Secure state
+// <i> Value for SCB->NSACR register bits CP10, CP11
+*/
+#define SCB_NSACR_CP10_11_VAL 3
+
+/*
+// <o>Treat floating-point registers as Secure
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit TS
+*/
+#define FPU_FPCCR_TS_VAL 0
+
+/*
+// <o>Clear on return (CLRONRET) accessibility
+// <0=> Secure and Non-Secure state
+// <1=> Secure state only
+// <i> Value for FPU->FPCCR register bit CLRONRETS
+*/
+#define FPU_FPCCR_CLRONRETS_VAL 0
+
+/*
+// <o>Clear floating-point caller saved registers on exception return
+// <0=> Disabled
+// <1=> Enabled
+// <i> Value for FPU->FPCCR register bit CLRONRET
+*/
+#define FPU_FPCCR_CLRONRET_VAL 1
+
+/*
+// </e>
+*/
+
+/*
+// <h>Setup Interrupt Target
+*/
+
+/*
+// <e>Initialize ITNS 0 (Interrupts 0..31)
+*/
+#define NVIC_INIT_ITNS0 1
+
+/*
+// Interrupts 0..31
+// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS0_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 1 (Interrupts 32..63)
+*/
+#define NVIC_INIT_ITNS1 1
+
+/*
+// Interrupts 32..63
+// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS1_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 2 (Interrupts 64..95)
+*/
+#define NVIC_INIT_ITNS2 0
+
+/*
+// Interrupts 64..95
+// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS2_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 3 (Interrupts 96..127)
+*/
+#define NVIC_INIT_ITNS3 0
+
+/*
+// Interrupts 96..127
+// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS3_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 4 (Interrupts 128..159)
+*/
+#define NVIC_INIT_ITNS4 0
+
+/*
+// Interrupts 128..159
+// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS4_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 5 (Interrupts 160..191)
+*/
+#define NVIC_INIT_ITNS5 0
+
+/*
+// Interrupts 160..191
+// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS5_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 6 (Interrupts 192..223)
+*/
+#define NVIC_INIT_ITNS6 0
+
+/*
+// Interrupts 192..223
+// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS6_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 7 (Interrupts 224..255)
+*/
+#define NVIC_INIT_ITNS7 0
+
+/*
+// Interrupts 224..255
+// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS7_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 8 (Interrupts 256..287)
+*/
+#define NVIC_INIT_ITNS8 0
+
+/*
+// Interrupts 256..287
+// <o.0> Interrupt 256 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 257 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 258 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 259 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 260 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 261 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 262 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 263 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 264 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 265 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS8_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 9 (Interrupts 288..319)
+*/
+#define NVIC_INIT_ITNS9 0
+
+/*
+// Interrupts 288..319
+// <o.0> Interrupt 288 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 289 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 290 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 291 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 292 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 293 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 294 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 295 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 296 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 297 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS9_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 10 (Interrupts 320..351)
+*/
+#define NVIC_INIT_ITNS10 0
+
+/*
+// Interrupts 320..351
+// <o.0> Interrupt 320 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 321 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 322 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 323 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 324 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 325 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 326 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 327 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 328 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 329 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS10_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 11 (Interrupts 352..383)
+*/
+#define NVIC_INIT_ITNS11 0
+
+/*
+// Interrupts 352..383
+// <o.0> Interrupt 352 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 353 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 354 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 355 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 356 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 357 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 358 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 359 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 360 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 361 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS11_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 12 (Interrupts 384..415)
+*/
+#define NVIC_INIT_ITNS12 0
+
+/*
+// Interrupts 384..415
+// <o.0> Interrupt 384 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 385 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 386 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 387 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 388 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 389 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 390 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 391 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 392 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 393 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS12_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 13 (Interrupts 416..447)
+*/
+#define NVIC_INIT_ITNS13 0
+
+/*
+// Interrupts 416..447
+// <o.0> Interrupt 416 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 417 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 418 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 419 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 420 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 421 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 422 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 423 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 424 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 425 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS13_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 14 (Interrupts 448..479)
+*/
+#define NVIC_INIT_ITNS14 0
+
+/*
+// Interrupts 448..479
+// <o.0> Interrupt 448 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 449 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 450 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 451 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 452 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 453 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 454 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 455 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 456 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 457 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS14_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// <e>Initialize ITNS 15 (Interrupts 480..511)
+*/
+#define NVIC_INIT_ITNS15 0
+
+/*
+// Interrupts 480..511
+// <o.0> Interrupt 480 <0=> Secure state <1=> Non-Secure state
+// <o.1> Interrupt 481 <0=> Secure state <1=> Non-Secure state
+// <o.2> Interrupt 482 <0=> Secure state <1=> Non-Secure state
+// <o.3> Interrupt 483 <0=> Secure state <1=> Non-Secure state
+// <o.4> Interrupt 484 <0=> Secure state <1=> Non-Secure state
+// <o.5> Interrupt 485 <0=> Secure state <1=> Non-Secure state
+// <o.6> Interrupt 486 <0=> Secure state <1=> Non-Secure state
+// <o.7> Interrupt 487 <0=> Secure state <1=> Non-Secure state
+// <o.8> Interrupt 488 <0=> Secure state <1=> Non-Secure state
+// <o.9> Interrupt 489 <0=> Secure state <1=> Non-Secure state
+// <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state
+// <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state
+// <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state
+// <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state
+// <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state
+// <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state
+// <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state
+// <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state
+// <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state
+// <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state
+// <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state
+// <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state
+// <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state
+// <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state
+// <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state
+// <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state
+// <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state
+// <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state
+// <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state
+// <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state
+// <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state
+// <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state
+*/
+#define NVIC_INIT_ITNS15_VAL 0x00000000
+
+/*
+// </e>
+*/
+
+/*
+// </h>
+*/
+
+
+
+/*
+ max 128 SAU regions.
+ SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+ SAU->RNR = (n & SAU_RNR_REGION_Msk); \
+ SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
+ SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
+ ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
+
+/**
+ \brief Setup a SAU Region
+ \details Writes the region information contained in SAU_Region to the
+ registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+__STATIC_INLINE void TZ_SAU_Setup (void)
+{
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+
+ #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+ SAU_INIT_REGION(0);
+ #endif
+
+ #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+ SAU_INIT_REGION(1);
+ #endif
+
+ #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+ SAU_INIT_REGION(2);
+ #endif
+
+ #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+ SAU_INIT_REGION(3);
+ #endif
+
+ #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+ SAU_INIT_REGION(4);
+ #endif
+
+ #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+ SAU_INIT_REGION(5);
+ #endif
+
+ #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+ SAU_INIT_REGION(6);
+ #endif
+
+ #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+ SAU_INIT_REGION(7);
+ #endif
+
+ /* repeat this for all possible SAU regions */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+
+ #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+ SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+ ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
+ #endif
+
+ #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+ SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
+ ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
+
+ SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
+ SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) |
+ ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
+ ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+ ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
+ ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
+ #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+ #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \
+ (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))
+
+ SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
+ ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
+
+ FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
+ ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
+ ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
+ ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
+ #endif
+
+ #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
+ NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
+ NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
+ NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
+ NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
+ NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
+ NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
+ NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
+ NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)
+ NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)
+ NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)
+ NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)
+ NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)
+ NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)
+ NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)
+ NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;
+ #endif
+
+ #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)
+ NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;
+ #endif
+
+ /* repeat this for all possible ITNS elements */
+
+}
+
+#endif /* PARTITION_ARMCM85_H */
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0
new file mode 100644
index 0000000..067871d
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0
@@ -0,0 +1,164 @@
+/******************************************************************************
+ * @file startup_ARMCM85.c
+ * @brief CMSIS Device Startup File for ARMCM85 Device
+ * @version V1.0.0
+ * @date 07. February 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM85)
+ #include "ARMCM85.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
+#endif
+
+extern __NO_RETURN void __PROGRAM_START(void);
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+ void Default_Handler(void);
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+/* Exceptions */
+void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler (void) __attribute__ ((weak));
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+ const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14 NMI Handler */
+ HardFault_Handler, /* -13 Hard Fault Handler */
+ MemManage_Handler, /* -12 MPU Fault Handler */
+ BusFault_Handler, /* -11 Bus Fault Handler */
+ UsageFault_Handler, /* -10 Usage Fault Handler */
+ SecureFault_Handler, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5 SVC Handler */
+ DebugMon_Handler, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2 PendSV Handler */
+ SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ Interrupt0_Handler, /* 0 Interrupt 0 */
+ Interrupt1_Handler, /* 1 Interrupt 1 */
+ Interrupt2_Handler, /* 2 Interrupt 2 */
+ Interrupt3_Handler, /* 3 Interrupt 3 */
+ Interrupt4_Handler, /* 4 Interrupt 4 */
+ Interrupt5_Handler, /* 5 Interrupt 5 */
+ Interrupt6_Handler, /* 6 Interrupt 6 */
+ Interrupt7_Handler, /* 7 Interrupt 7 */
+ Interrupt8_Handler, /* 8 Interrupt 8 */
+ Interrupt9_Handler /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
+{
+ __set_PSP((uint32_t)(&__INITIAL_SP));
+
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+ __set_PSPLIM((uint32_t)(&__STACK_LIMIT));
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));
+#endif
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+/*----------------------------------------------------------------------------
+ Hard Fault Handler
+ *----------------------------------------------------------------------------*/
+void HardFault_Handler(void)
+{
+ while(1);
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
diff --git a/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0 b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0
new file mode 100644
index 0000000..7a16501
--- /dev/null
+++ b/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0
@@ -0,0 +1,106 @@
+/**************************************************************************//**
+ * @file system_ARMCM85.c
+ * @brief CMSIS Device System Source File for ARMCM85 Device
+ * @version V1.0.0
+ * @date 30. March 2022
+ ******************************************************************************/
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM85)
+ #include "ARMCM85.h"
+
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ #include "partition_ARMCM85.h"
+ #endif
+#else
+ #error device not specified!
+#endif
+
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);
+#endif
+
+ /* Set CPDLPSTATE.RLPSTATE to 0
+ Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.
+ Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */
+ PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |
+ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |
+ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk );
+
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+
+ /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */
+ /* PDEPU ON, Clock OFF */
+ PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ /* Enable Loop and branch info cache */
+ SCB->CCR |= SCB_CCR_LOB_Msk;
+
+ /* Enable Branch Prediction */
+ SCB->CCR |= SCB_CCR_BP_Msk;
+
+ __DSB();
+ __ISB();
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+ TZ_SAU_Setup();
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/CoreValidation/Project/Validation.csolution.yml b/CMSIS/CoreValidation/Project/Validation.csolution.yml
index 0449ac0..633387b 100644
--- a/CMSIS/CoreValidation/Project/Validation.csolution.yml
+++ b/CMSIS/CoreValidation/Project/Validation.csolution.yml
@@ -231,5 +231,5 @@
output-dirs:
cprjdir: ./$Project$.$BuildType$+$TargetType$
- intdir: ./$Project$.$BuildType$+$TargetType$/$Project$.$BuildType$+$TargetType$_intdir
- outdir: ./$Project$.$BuildType$+$TargetType$/$Project$.$BuildType$+$TargetType$_outdir
+ intdir: ./$Project$.$BuildType$+$TargetType$/intdir
+ outdir: ./$Project$.$BuildType$+$TargetType$/outdir
diff --git a/CMSIS/CoreValidation/Project/build.py b/CMSIS/CoreValidation/Project/build.py
index d680ae1..f07b887 100644
--- a/CMSIS/CoreValidation/Project/build.py
+++ b/CMSIS/CoreValidation/Project/build.py
@@ -139,11 +139,11 @@
def output_dir(config):
- return f"{project_name(config)}_outdir"
+ return "outdir"
def bl_output_dir(config):
- return f"{bl_project_name(config)}_outdir"
+ return "outdir"
def model_config(config):