CMSIS Driver: Updated NAND API V2.3.0 (extended ARM_NAND_ECC_INFO structure)
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 9599863..9f8a840 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -19,6 +19,7 @@
CMSIS-DSP: 1.5.2 (see revision history for details)
CMSIS-Driver:
- CAN Driver API V1.2.0
+ - NAND Driver API V2.3.0
CMSIS-RTOS:
- RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.
CMSIS-RTOS2:
@@ -694,7 +695,7 @@
<file category="header" name="CMSIS/Driver/Include/Driver_MCI.h" />
</files>
</api>
- <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.2.0" exclusive="0">
+ <api Cclass="CMSIS Driver" Cgroup="NAND" Capiversion="2.3.0" exclusive="0">
<description>NAND Flash Driver API for Cortex-M</description>
<files>
<file category="doc" name="CMSIS/Documentation/Driver/html/group__nand__interface__gr.html" />
diff --git a/CMSIS/DoxyGen/Driver/src/Driver_NAND.c b/CMSIS/DoxyGen/Driver/src/Driver_NAND.c
index efd24ea..c276aa3 100644
--- a/CMSIS/DoxyGen/Driver/src/Driver_NAND.c
+++ b/CMSIS/DoxyGen/Driver/src/Driver_NAND.c
@@ -269,8 +269,67 @@
/**
\struct ARM_NAND_ECC_INFO
+
\details
-Structure with information about the Error Correction Code for a NAND.
+Stores the characteristics of a ECC (Error Correction Code) algorithm and provides the information about necessary
+application data handling in order to protect stored data from NAND bit errors.
+
+ECC algorithms applied on NAND memory typically operate on NAND device page level which is virtually divided to multiple
+main and spare areas. Data from main and spare area is taken into account when generating ECC data which is also stored
+into spare area. ECC codeword defines how much data will be protected and how much ECC data will be generated.
+
+To describe how application data must be organized, ECC information structure specifies protection \em type which
+defines the protected part of data. As main and spare are of different size, two different algorithms could be
+provided, we can describe them as ECC0 and ECC1. Type can then have the following values:
+
+Type| Description
+:---|:-----------
+ 0 | ECC algorithm not used
+ 1 | ECC0 algorithm protects main data
+ 2 | ECC0 algorithm protects main and spare data
+ 3 | ECC0 algorithm protects main and ECC1 algorithm protects spare data
+
+Virtual page division is described with page layout (\em page_layout), number of pages (\em page_count) and
+virtual page size (\em page_size or \em virtual_page_size). Virtual page size used by ECC algorithm can be defined
+by either \em page_size or \em virtual_page_size, depending on the \em page_size values:
+
+Value| Main + Spare size
+:----|:-----------
+ 0 | 512 + 16
+ 1 | 1024 + 32
+ 2 | 2048 + 64
+ 3 | 4096 + 128
+ 4 | 8192 + 256
+ 8 | 512 + 28
+ 9 | 1024 + 56
+ 10 | 2048 + 112
+ 11 | 4096 + 224
+ 12 | 8192 + 448
+ 15 | Not used, use virtual_page_size
+
+Structure member \em virtual_page_size is an array of two 16-bit values. First field of array (i.e. \em virtual_page_size[0])
+contains main area size while second (i.e. \em virtual_page_size[1]) contains spare area size. Number of virtual pages N
+is defined with \em page_count and must be calculated as N = 2 ^ page_count.
+
+Page layout defines main and spare ordering and two different page layouts are possible. First ordering assumes that
+spare area follows after every main area, while in second case all main areas build one contiguous region followed by
+contiguous region of spare areas. This is defined by member \em page_layout:
+
+Layout| Description
+:-----|:-----------
+ 0 | Single spare follows after single main: Main0,Spare0 ... MainN-1,SpareN-1
+ 1 | Contiguous spare follows after contiguous main: Main0 ... MainN-1,Spare0 ... SpareN-1
+
+ECC codeword size defines the size of data that is protected by ECC algorithm and is different for main and spare
+area. All structure members that define the codeword are therefore arrays of two 16-bit values. Codeword offset defines
+where ECC protected data starts in main (\em codeword_offset[0]) or spare (\em codeword_offset[1]) area, codeword
+size (\em codeword_size) defines the number of data that is protected i.e. data over which ECC is calculated and
+codeword gap (\em codeword_gap) defines the space between two consecutive codeword regions.
+
+Generated ECC data is stored into spare area and is described similar as codeword, with offset from start of spare area
+(\em ecc_offset), size of generated data (\em ecc_size) and gap (\em ecc_gap) between two consecutive ECC data regions.
+
+Number of bits that ECC algorithm can correct per codeword is defined with \em correctable_bits.
<b>Parameter for:</b>
- \ref ARM_NAND_InquireECC
diff --git a/CMSIS/Driver/Include/Driver_NAND.h b/CMSIS/Driver/Include/Driver_NAND.h
index d2296ea..827fd4b 100644
--- a/CMSIS/Driver/Include/Driver_NAND.h
+++ b/CMSIS/Driver/Include/Driver_NAND.h
@@ -15,13 +15,15 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*
- * $Date: 2. Feb 2017
- * $Revision: V2.2
+ * $Date: 14. Nov 2017
+ * $Revision: V2.3
*
* Project: NAND Flash Driver definitions
*/
/* History:
+ * Version 2.3
+ * Extended ARM_NAND_ECC_INFO structure
* Version 2.2
* ARM_NAND_STATUS made volatile
* Version 2.1
@@ -51,7 +53,7 @@
#include "Driver_Common.h"
-#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
+#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
/****** NAND Device Power *****/
@@ -175,15 +177,20 @@
\brief NAND ECC (Error Correction Code) Information
*/
typedef struct _ARM_NAND_ECC_INFO {
- uint32_t type : 2; ///< Type: 1=ECC0 over Data, 2=ECC0 over Data+Spare, 3=ECC0 over Data and ECC1 over Spare
- uint32_t page_layout : 1; ///< Page layout: 0=|Data0|Spare0|...|DataN-1|SpareN-1|, 1=|Data0|...|DataN-1|Spare0|...|SpareN-1|
+ uint32_t type : 2; ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare
+ uint32_t page_layout : 1; ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|
uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count
- uint32_t page_size : 4; ///< Virtual Page size (Data+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448
+ uint32_t page_size : 4; ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)
uint32_t reserved : 14; ///< Reserved (must be zero)
uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size)
- uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated
- uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up)
- uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare area)
+ uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated
+ uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up)
+ uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare)
+ /* Extended description */
+ uint16_t virtual_page_size [2]; ///< Virtual Page size in bytes (Main/Spare)
+ uint16_t codeword_offset [2]; ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)
+ uint16_t codeword_gap [2]; ///< Codeword gap in bytes till next protected data
+ uint16_t ecc_gap [2]; ///< ECC gap in bytes till next generated ECC
} ARM_NAND_ECC_INFO;
@@ -334,7 +341,7 @@
/**
\fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
\brief Inquire about available ECC.
- \param[in] index Device number
+ \param[in] index Inquire ECC index
\param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
\return \ref execution_status
*/