tree 602760916d00b7346a2e447cc931727f2ebf172f
parent 13e9162a883635abc67a8f7af62dfa0d4df5fc7e
author Jonatan Antoni <jonatan.antoni@arm.com> 1525778050 +0200
committer Jonatan Antoni <jonatan.antoni@arm.com> 1525778050 +0200

CoreValidation: Fixed/enhanced test cases.
- TC_CoreFunc_IRQVect needs to place ram vector table 512-byte aligned due to a limitation on Cortex-M23 FVP.
- TC_CoreFunc_FPUType preprocessor switch __FPU_PRESENT was not evaluated properly.
- TC_CoreFunc_FPSCR now ensures RAZ/WI behaviour if FPU not used/available.

Change-Id: Ic37c84c3c09c37742af8042b9b2383aacda86636