diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/Abstract.txt b/CMSIS/RTOS2/RTX/Examples/Migration/Abstract.txt
new file mode 100644
index 0000000..5a44255
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/Abstract.txt
@@ -0,0 +1,26 @@
+The RTX_Blinky project is a simple RTX Kernel based example
+for a simulated Cortex-M3 device
+
+Example functionality:
+ - Clock Settings:
+   - XTAL    =  12 MHz
+   - Core    =  12 MHz
+
+The simple RTX Kernel based example simulates the step-motor 
+driver. Four LEDs are blinking simulating the activation of 
+the four output driver stages
+The simulation does not provide LEDs, so the state changes
+are output on the Debug printf window:
+
+- phase A
+- phase B
+- phase C
+- phase D
+
+This example simulates Half step driver mode and
+CW rotation direction.
+
+
+The BLINKY example program is available for one target:
+
+  Simulation:          configured for a simulated on-chip Flash
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c
new file mode 100644
index 0000000..1c8d507
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c
@@ -0,0 +1,162 @@
+/* -------------------------------------------------------------------------- 
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *      Name:    BLinky.c
+ *      Purpose: RTX example program
+ *
+ *---------------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "ARMCM3.h"                     // Device header
+#include "cmsis_os.h"                   // ARM::CMSIS:RTOS:Keil RTX5
+#include "cmsis_os2.h"                  // ARM::CMSIS:RTOS2:Keil RTX5
+
+
+osThreadId_t tid_phaseA;                /* Thread id of thread: phase_a      */
+osThreadId_t tid_phaseB;                /* Thread id of thread: phase_b      */
+osThreadId_t tid_phaseC;                /* Thread id of thread: phase_c      */
+osThreadId_t tid_phaseD;                /* Thread id of thread: phase_d      */
+osThreadId_t tid_clock;                 /* Thread id of thread: clock        */
+
+struct phases_t {
+	int_fast8_t phaseA;
+	int_fast8_t phaseB;
+	int_fast8_t phaseC;
+	int_fast8_t phaseD;
+} g_phases;
+
+/*----------------------------------------------------------------------------
+ *      Switch LED on
+ *---------------------------------------------------------------------------*/
+void Switch_On (unsigned char led) {
+  printf("LED On: #%d\n\r", led);
+}
+
+/*----------------------------------------------------------------------------
+ *      Switch LED off
+ *---------------------------------------------------------------------------*/
+void Switch_Off (unsigned char led) {
+  printf("LED Off: #%d\n\r", led);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      Function 'signal_func' called from multiple threads
+ *---------------------------------------------------------------------------*/
+void signal_func (osThreadId_t tid)  {
+  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */
+  osDelay(500);                             /* delay 500ms                   */
+  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */
+  osDelay(500);                             /* delay 500ms                   */
+  osThreadFlagsSet(tid, 0x0001);            /* set signal to thread 'thread' */
+  osDelay(500);                             /* delay 500ms                   */
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 1 'phaseA': Phase A output
+ *---------------------------------------------------------------------------*/
+void phaseA (void *argument) {
+  for (;;) {
+    osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever);    /* wait for an event flag 0x0001 */
+    g_phases.phaseA = 1;
+    signal_func(tid_phaseB);                                     /* call common signal function   */
+    g_phases.phaseA = 0;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 2 'phaseB': Phase B output
+ *---------------------------------------------------------------------------*/
+void phaseB (void *argument) {
+  for (;;) {
+    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */
+    g_phases.phaseB = 1;
+    signal_func(tid_phaseC);                /* call common signal function   */
+    g_phases.phaseB = 0;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 3 'phaseC': Phase C output
+ *---------------------------------------------------------------------------*/
+void phaseC (void *argument) {
+  for (;;) {
+    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */
+    g_phases.phaseC = 1;
+    signal_func(tid_phaseD);                /* call common signal function   */
+    g_phases.phaseC = 0;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 4 'phaseD': Phase D output
+ *---------------------------------------------------------------------------*/
+void phaseD (void *argument) {
+  for (;;) {
+    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */
+    g_phases.phaseD = 1;
+    signal_func(tid_phaseA);                /* call common signal function   */
+    g_phases.phaseD = 0;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ *      Thread 5 'clock': Signal Clock
+ *---------------------------------------------------------------------------*/
+void clock (void const *argument) {
+  for (;;) {
+    osSignalWait(0x0100, osWaitForever);    /* wait for an event flag 0x0100 */
+    osDelay(80);                            /* delay  80ms                   */
+  }
+}
+
+/* Define the API v1 thread */
+osThreadDef(clock,  osPriorityNormal, 1, 0);
+
+/*----------------------------------------------------------------------------
+ *      Main: Initialize and start RTX Kernel
+ *---------------------------------------------------------------------------*/
+void app_main (void *argument) {
+
+  tid_phaseA = osThreadNew(phaseA, NULL, NULL);
+  tid_phaseB = osThreadNew(phaseB, NULL, NULL);
+  tid_phaseC = osThreadNew(phaseC, NULL, NULL);
+  tid_phaseD = osThreadNew(phaseD, NULL, NULL);
+  tid_clock  = osThreadCreate(osThread(clock),  NULL);
+
+  osThreadFlagsSet(tid_phaseA, 0x0001);          /* set signal to phaseA thread   */
+
+  osDelay(osWaitForever);
+  while(1);
+}
+
+int main (void) {
+
+  // System Initialization
+  SystemCoreClockUpdate();
+  // ...
+  osKernelInitialize();                 // Initialize CMSIS-RTOS
+  osThreadNew(app_main, NULL, NULL);    // Create application main thread
+  if (osKernelGetState() == osKernelReady) {
+    osKernelStart();                    // Start thread execution
+  }
+
+  while(1);
+}
+
+
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvguix b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvguix
new file mode 100644
index 0000000..85bb7a4
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvguix
@@ -0,0 +1,1358 @@
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diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvoptx b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvoptx
new file mode 100644
index 0000000..91014b6
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvoptx
@@ -0,0 +1,310 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
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+    <dwHighDateTime>0</dwHighDateTime>
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+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
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diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvprojx b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvprojx
new file mode 100644
index 0000000..f2b2fb4
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvprojx
@@ -0,0 +1,511 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
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+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
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+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>  -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4097</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x1A000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Files</GroupName>
+          <Files>
+            <File>
+              <FileName>Blinky.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>.\Blinky.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Documentation</GroupName>
+          <Files>
+            <File>
+              <FileName>Abstract.txt</FileName>
+              <FileType>5</FileType>
+              <FilePath>.\Abstract.txt</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>::CMSIS</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Compiler</GroupName>
+        </Group>
+        <Group>
+          <GroupName>::Device</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis>
+      <api Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" exclusive="1">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </api>
+      <api Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta11"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </api>
+    </apis>
+    <components>
+      <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.0.0" condition="ARMv6_7_8-M Device">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </component>
+      <component Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX5" Cvendor="ARM" Cversion="5.0.0" condition="RTOS RTX5">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </component>
+      <component Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.0.0" condition="RTOS2 RTX5">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </component>
+      <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS">
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta11"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </component>
+      <component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="I/O" Csub="STDOUT" Cvariant="ITM" Cvendor="Keil" Cversion="1.1.0" condition="ARMCC Cortex-M with ITM">
+        <package name="ARM_Compiler" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="1.2.0-Dev9"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </component>
+    </components>
+    <files>
+      <file attr="config" category="source" name="CMSIS\RTOS\RTX\Templates\RTX_Conf_CM.c" version="4.70.1">
+        <instance index="0" removed="1">RTE\CMSIS\RTX_Conf_CM.c</instance>
+        <component Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.81.0" condition="RTOS RTX Dependency"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta11"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.0.0">
+        <instance index="0">RTE\CMSIS\RTX_Config.c</instance>
+        <component Capiversion="2.0" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.0.0" condition="RTOS2 RTX5"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM3\Source\ARM\startup_ARMCM3.s" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM3\startup_ARMCM3.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="sourceC" name="Device\ARM\ARMCM3\Source\system_ARMCM3.c" version="1.0.0">
+        <instance index="0">RTE\Device\ARMCM3\system_ARMCM3.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM3 CMSIS"/>
+        <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.0.0-Beta15"/>
+        <targetInfos>
+          <targetInfo name="Simulation"/>
+        </targetInfos>
+      </file>
+      <file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="2.00">
+        <instance index="0" removed="1">RTE\Device\LPC1857\RTE_Device.h</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" condition="ARM Compiler" name="Device\Source\ARM\startup_LPC18xx.s" version="1.0.0">
+        <instance index="0" removed="1">RTE\Device\LPC1857\startup_LPC18xx.s</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0"/>
+        <targetInfos/>
+      </file>
+      <file attr="config" category="source" name="Device\Source\system_LPC18xx.c" version="1.0.1">
+        <instance index="0" removed="1">RTE\Device\LPC1857\system_LPC18xx.c</instance>
+        <component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC1800 CMSIS"/>
+        <package name="LPC1800_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.6.0"/>
+        <targetInfos/>
+      </file>
+    </files>
+  </RTE>
+
+</Project>
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/EventRecorderStub.scvd b/CMSIS/RTOS2/RTX/Examples/Migration/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+
+<component name="EventRecorderStub" version="1.0.0"/>       <!--name and version of the component-->
+  <events>
+  </events>
+
+</component_viewer>
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.c b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.c
new file mode 100644
index 0000000..c1950a0
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision:   V5.0.0
+ *
+ * Project:     CMSIS-RTOS RTX
+ * Title:       RTX Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+ 
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+ 
+// <h>System Configuration
+// =======================
+ 
+//     <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
+//     <i> Defines the combined global dynamic memory size.
+//     <i> Default: 4096
+#define OS_DYNAMIC_MEM_SIZE         4096
+ 
+//   <o>Kernel Tick Frequency [Hz] <1-1000000>
+//   <i> Defines base time unit for delays and timeouts.
+//   <i> Default: 1000 (1ms tick)
+#define OS_TICK_FREQ                1000
+ 
+//   <e>Round-Robin Thread switching
+//   <i> Enables Round-Robin Thread switching.
+#define OS_ROBIN_ENABLE             1
+ 
+//     <o>Round-Robin Timeout <1-1000>
+//     <i> Defines how many ticks a thread will execute before a thread switch.
+//     <i> Default: 5
+#define OS_ROBIN_TIMEOUT            5
+ 
+//   </e>
+ 
+//   <o>ISR FIFO Queue 
+//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries
+//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries
+//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries
+//   <i> RTOS Functions called from ISR store requests to this buffer.
+//   <i> Default: 16 entries
+#define OS_ISR_FIFO_QUEUE           16
+ 
+// </h>
+ 
+// <h>Thread Configuration
+// =======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_THREAD_OBJ_MEM           1
+ 
+//     <o>Number of user Threads (total) <1-1000>
+//     <i> Defines maximum number of user threads that can be active at the same time.
+//     <i> Applies to user threads with system provided memory for control blocks.
+#define OS_THREAD_NUM               6
+ 
+//     <o>Number of user Threads with user-provided Stack size <0-1000>
+//     <i> Defines maximum number of user threads with user-provided stack size.
+//     <i> Default: 0
+#define OS_THREAD_USER_STACK_NUM    0
+ 
+//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
+//     <i> Defines the combined stack size for user threads with user-provided stack size.
+//     <i> Default: 0
+#define OS_THREAD_USER_STACK_SIZE   0
+ 
+//   </e>
+ 
+//   <o>Default Thread Stack size [bytes] <96-1073741824:8>
+//   <i> Defines stack size for threads with zero stack size specified.
+//   <i> Default: 200
+#define OS_STACK_SIZE               400
+ 
+//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>
+//   <i> Defines stack size for Idle thread.
+//   <i> Default: 200
+#define OS_IDLE_THREAD_STACK_SIZE   200
+ 
+//   <q>Stack overrun checking
+//   <i> Enable stack overrun checks at thread switch.
+//   <i> Enabling this option increases slightly the execution time of a thread switch.
+#define OS_STACK_CHECK              1
+ 
+//   <q>Stack usage watermark
+//   <i> Initialize thread stack with watermark pattern for analyzing stack usage.
+//   <i> Enabling this option increases significantly the execution time of thread creation.
+#define OS_STACK_WATERMARK          1
+ 
+//   <o>Processor mode for Thread execution 
+//     <0=> Unprivileged mode 
+//     <1=> Privileged mode
+//   <i> Default: Privileged mode
+#define OS_PRIVILEGE_MODE           1
+ 
+// </h>
+ 
+// <h>Timer Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_TIMER_OBJ_MEM            0
+ 
+//     <o>Number of Timer objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#define OS_TIMER_NUM                1
+ 
+//   </e>
+ 
+//   <o>Timer Thread Priority
+//      <8=> Low
+//     <16=> Below Normal  <24=> Normal  <32=> Above Normal
+//     <40=> High
+//     <48=> Realtime
+//   <i> Defines priority for timer thread
+//   <i> Default: High
+#define OS_TIMER_THREAD_PRIO        40
+ 
+//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>
+//   <i> Defines stack size for Timer thread.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 200
+#define OS_TIMER_THREAD_STACK_SIZE  200
+ 
+//   <o>Timer Callback Queue entries <0-256>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> May be set to 0 when timers are not used.
+//   <i> Default: 4
+#define OS_TIMER_CB_QUEUE           4
+ 
+// </h>
+ 
+// <h>Event Flags Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_EVFLAGS_OBJ_MEM          0
+ 
+//     <o>Number of Event Flags objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#define OS_EVFLAGS_NUM              1
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Mutex Configuration
+// ======================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_MUTEX_OBJ_MEM            0
+ 
+//     <o>Number of Mutex objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#define OS_MUTEX_NUM                1
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Semaphore Configuration
+// ==========================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_SEMAPHORE_OBJ_MEM        0
+ 
+//     <o>Number of Semaphore objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#define OS_SEMAPHORE_NUM            1
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Memory Pool Configuration
+// ============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_MEMPOOL_OBJ_MEM          0
+ 
+//     <o>Number of Memory Pool objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#define OS_MEMPOOL_NUM              1
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:4>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#define OS_MEMPOOL_DATA_SIZE        0
+ 
+//   </e>
+ 
+// </h>
+ 
+// <h>Message Queue Configuration
+// ==============================
+ 
+//   <e>Object specific Memory allocation
+//   <i> Enables object specific memory allocation.
+#define OS_MSGQUEUE_OBJ_MEM         0
+ 
+//     <o>Number of Message Queue objects <1-1000>
+//     <i> Defines maximum number of objects that can be active at the same time.
+//     <i> Applies to objects with system provided memory for control blocks.
+#define OS_MSGQUEUE_NUM             1
+ 
+//     <o>Data Storage Memory size [bytes] <0-1073741824:4>
+//     <i> Defines the combined data storage memory size.
+//     <i> Applies to objects with system provided memory for data storage.
+//     <i> Default: 0
+#define OS_MSGQUEUE_DATA_SIZE       0
+ 
+//   </e>
+ 
+// </h>
+ 
+// Number of Threads which use standard C/C++ library libspace
+// (when thread specific memory allocation is not used).
+#if (OS_THREAD_OBJ_MEM == 0)
+#define OS_THREAD_LIBSPACE_NUM      4
+#else
+#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM
+#endif
+ 
+//------------- <<< end of configuration section >>> ---------------------------
+ 
+#include "rtx_os.h"
+ 
+// OS Idle Thread
+__NO_RETURN void os_IdleThread (void *argument) {
+  (void)argument;
+
+  for (;;) {}
+}
+ 
+// OS Error Callback function
+uint32_t os_Error (uint32_t code, void *object_id) {
+  (void)object_id;
+
+  switch (code) {
+    case os_ErrorStackUnderflow:
+      // Stack underflow detected for thread (thread_id=object_id)
+      break;
+    case os_ErrorISRQueueOverflow:
+      // ISR Queue overflow detected when inserting object (object_id)
+      break;
+    case os_ErrorTimerQueueOverflow:
+      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+      break;
+    case os_ErrorClibSpace:
+      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+      break;
+    case os_ErrorClibMutex:
+      // Standard C/C++ library mutex initialization failed
+      break;
+    default:
+      break;
+  }
+  for (;;) {}
+//return 0U;
+}
+ 
+#include "rtx_config.h"
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/startup_ARMCM3.s b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/startup_ARMCM3.s
new file mode 100644
index 0000000..b625dfa
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/startup_ARMCM3.s
@@ -0,0 +1,262 @@
+;/**************************************************************************//**
+; * @file     startup_ARMCM3.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM3 Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000C00
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler            ;  0:  Watchdog Timer
+                DCD     RTC_IRQHandler            ;  1:  Real Time Clock
+                DCD     TIM0_IRQHandler           ;  2:  Timer0 / Timer1
+                DCD     TIM2_IRQHandler           ;  3:  Timer2 / Timer3
+                DCD     MCIA_IRQHandler           ;  4:  MCIa
+                DCD     MCIB_IRQHandler           ;  5:  MCIb
+                DCD     UART0_IRQHandler          ;  6:  UART0 - DUT FPGA
+                DCD     UART1_IRQHandler          ;  7:  UART1 - DUT FPGA
+                DCD     UART2_IRQHandler          ;  8:  UART2 - DUT FPGA
+                DCD     UART4_IRQHandler          ;  9:  UART4 - not connected
+                DCD     AACI_IRQHandler           ; 10: AACI / AC97
+                DCD     CLCD_IRQHandler           ; 11: CLCD Combined Interrupt
+                DCD     ENET_IRQHandler           ; 12: Ethernet
+                DCD     USBDC_IRQHandler          ; 13: USB Device
+                DCD     USBHC_IRQHandler          ; 14: USB Host Controller
+                DCD     CHLCD_IRQHandler          ; 15: Character LCD
+                DCD     FLEXRAY_IRQHandler        ; 16: Flexray
+                DCD     CAN_IRQHandler            ; 17: CAN
+                DCD     LIN_IRQHandler            ; 18: LIN
+                DCD     I2C_IRQHandler            ; 19: I2C ADC/DAC
+                DCD     0                         ; 20: Reserved
+                DCD     0                         ; 21: Reserved
+                DCD     0                         ; 22: Reserved
+                DCD     0                         ; 23: Reserved
+                DCD     0                         ; 24: Reserved
+                DCD     0                         ; 25: Reserved
+                DCD     0                         ; 26: Reserved
+                DCD     0                         ; 27: Reserved
+                DCD     CPU_CLCD_IRQHandler       ; 28: Reserved - CPU FPGA CLCD
+                DCD     0                         ; 29: Reserved - CPU FPGA
+                DCD     UART3_IRQHandler          ; 30: UART3    - CPU FPGA
+                DCD     SPI_IRQHandler            ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WDT_IRQHandler            [WEAK]
+                EXPORT  RTC_IRQHandler            [WEAK]
+                EXPORT  TIM0_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler           [WEAK]
+                EXPORT  MCIA_IRQHandler           [WEAK]
+                EXPORT  MCIB_IRQHandler           [WEAK]
+                EXPORT  UART0_IRQHandler          [WEAK]
+                EXPORT  UART1_IRQHandler          [WEAK]
+                EXPORT  UART2_IRQHandler          [WEAK]
+                EXPORT  UART3_IRQHandler          [WEAK]
+                EXPORT  UART4_IRQHandler          [WEAK]
+                EXPORT  AACI_IRQHandler           [WEAK]
+                EXPORT  CLCD_IRQHandler           [WEAK]
+                EXPORT  ENET_IRQHandler           [WEAK]
+                EXPORT  USBDC_IRQHandler          [WEAK]
+                EXPORT  USBHC_IRQHandler          [WEAK]
+                EXPORT  CHLCD_IRQHandler          [WEAK]
+                EXPORT  FLEXRAY_IRQHandler        [WEAK]
+                EXPORT  CAN_IRQHandler            [WEAK]
+                EXPORT  LIN_IRQHandler            [WEAK]
+                EXPORT  I2C_IRQHandler            [WEAK]
+                EXPORT  CPU_CLCD_IRQHandler       [WEAK]
+                EXPORT  SPI_IRQHandler            [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+                ENDP
+
+                ALIGN
+
+                ENDIF
+
+
+                END
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/system_ARMCM3.c b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/system_ARMCM3.c
new file mode 100644
index 0000000..3c9aa3a
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/system_ARMCM3.c
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM3 Device Series
+ * @version  V5.00
+ * @date     08. April 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define  XTAL            ( 5000000U)      /* Oscillator frequency */
+
+#define  SYSTEM_CLOCK    (5 * XTAL)
+
+
+/*----------------------------------------------------------------------------
+  Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+  extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+  SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+  System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1)
+  SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+  SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/CMSIS/RTOS2/RTX/Examples/Migration/RTE/_Simulation/RTE_Components.h b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/_Simulation/RTE_Components.h
new file mode 100644
index 0000000..efb5e9e
--- /dev/null
+++ b/CMSIS/RTOS2/RTX/Examples/Migration/RTE/_Simulation/RTE_Components.h
@@ -0,0 +1,26 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'Blinky' 
+ * Target:  'Simulation' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "ARMCM3.h"
+
+#define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */
+        #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */
+#define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */
+        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */
+#define RTE_Compiler_IO_STDOUT          /* Compiler I/O: STDOUT */
+          #define RTE_Compiler_IO_STDOUT_ITM      /* Compiler I/O: STDOUT ITM */
+
+#endif /* RTE_COMPONENTS_H */