CMSIS-Core(M): Initial contribution for generic MPU functions.
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index bb4ed93..bfe1752 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -8,6 +8,10 @@
<url>http://www.keil.com/pack/</url>
<releases>
+ <release version="5.0.2-dev5">
+ CMSIS-Core(M):
+ - Added MPU Management Functions for CM0+/3/4/7
+ </release>
<release version="5.0.2-dev4">
CMSIS Device:
- Added OS Tick API
diff --git a/CMSIS/Core/Include/core_cm0plus.h b/CMSIS/Core/Include/core_cm0plus.h
index dd699b6..5c61358 100644
--- a/CMSIS/Core/Include/core_cm0plus.h
+++ b/CMSIS/Core/Include/core_cm0plus.h
@@ -934,6 +934,13 @@
/*@} end of CMSIS_Core_NVICFunctions */
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
/* ########################## FPU functions #################################### */
/**
diff --git a/CMSIS/Core/Include/core_cm3.h b/CMSIS/Core/Include/core_cm3.h
index 62976df..3c1f01f 100644
--- a/CMSIS/Core/Include/core_cm3.h
+++ b/CMSIS/Core/Include/core_cm3.h
@@ -1763,6 +1763,13 @@
/*@} end of CMSIS_Core_NVICFunctions */
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
/* ########################## FPU functions #################################### */
/**
diff --git a/CMSIS/Core/Include/core_cm4.h b/CMSIS/Core/Include/core_cm4.h
index b47cbaa..ad3bc27 100644
--- a/CMSIS/Core/Include/core_cm4.h
+++ b/CMSIS/Core/Include/core_cm4.h
@@ -1937,6 +1937,14 @@
/*@} end of CMSIS_Core_NVICFunctions */
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
/* ########################## FPU functions #################################### */
/**
diff --git a/CMSIS/Core/Include/core_cm7.h b/CMSIS/Core/Include/core_cm7.h
index 2051a3f..bf701fe 100644
--- a/CMSIS/Core/Include/core_cm7.h
+++ b/CMSIS/Core/Include/core_cm7.h
@@ -2145,6 +2145,13 @@
/*@} end of CMSIS_Core_NVICFunctions */
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
/* ########################## FPU functions #################################### */
/**
diff --git a/CMSIS/Core/Include/mpu_armv7.h b/CMSIS/Core/Include/mpu_armv7.h
new file mode 100644
index 0000000..2f1ee3b
--- /dev/null
+++ b/CMSIS/Core/Include/mpu_armv7.h
@@ -0,0 +1,177 @@
+/**************************************************************************//**
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for ARMv7 MPU
+ * @version V5.0.2
+ * @date 09. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MPU_ARMV7_H
+#define MPU_ARMV7_H
+
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
+
+#define MPU_AP_NONE 0u
+#define MPU_AP_PRIV 1u
+#define MPU_AP_URO 2u
+#define MPU_AP_FULL 3u
+#define MPU_AP_PRO 5u
+#define MPU_AP_RO 6u
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
+
+/**
+* MPU Region Attribut and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cachable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region be configured, for example 4K, 8K.
+*/
+#define MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ ((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ ((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ ((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ ((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ ((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
+ ((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ ((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ ((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _MPU_Region_t {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void MPU_Enable(uint32_t MPU_Control)
+{
+ __DSB();
+ __ISB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void MPU_Disable()
+{
+ __DSB();
+ __ISB();
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0u;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/
+__STATIC_INLINE void MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* restrict src, uint32_t len)
+{
+ for (uint32_t i = 0u; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void MPU_Load(MPU_Region_t const* table, uint32_t cnt)
+{
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(MPU_Region_t)/4u);
+}
+
+#endif
diff --git a/CMSIS/DoxyGen/Core/core.dxy b/CMSIS/DoxyGen/Core/core.dxy
index e8997cd..bcb537c 100644
--- a/CMSIS/DoxyGen/Core/core.dxy
+++ b/CMSIS/DoxyGen/Core/core.dxy
@@ -763,6 +763,7 @@
src/Ref_cmInstr.txt \
src/Ref_cm4_simd.txt \
src/Ref_FPU.txt \
+ src/Ref_MPU.txt \
src/Ref_Systick.txt \
src/Ref_Debug.txt \
src/Ref_Trustzone.txt \
diff --git a/CMSIS/DoxyGen/Core/src/Ref_MPU.txt b/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
new file mode 100644
index 0000000..fda2e10
--- /dev/null
+++ b/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
@@ -0,0 +1,432 @@
+/**
+\defgroup mpu_functions MPU Functions (ARMv7)
+\brief Functions that relate to the Memory Protection Unit.
+\details
+Devices based on Cortex-M processors M0+, M3, M4 and M7 optionally can contain a Memory Protection Unit.
+If available the MPU can be used to prevent errornous memory accesses.
+
+<b>Example:</b>
+\code
+void main()
+{
+ // Set Region 0
+ MPU_SetRegionEx(0UL, 0x08000000UL, MPU_RASR(0UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_1MB));
+
+ MPU_Enable(0);
+
+ // Do MPU protected stuff
+
+ MPU_Disable();
+}
+\endcode
+
+@{
+*/
+
+/**
+*/
+typedef struct {} MPU_Type;
+
+/** \def MPU_RBAR
+* \brief MPU Region Base Address Register Value
+*
+* This preprocessor function can be used to construct a valid \ref MPU_Type::RBAR "RBAR" value.
+* The VALID bit is implicitly set to 1.
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define MPU_RBAR(Region, BaseAddress)
+
+/**
+* \def MPU_RASR
+* \brief MPU Region Attribut and Size Register Value
+*
+* This preprocessor function can be used to construct a valid \ref MPU_Type::RASR "RASR" value.
+* The ENABLE bit is implicitly set to 1.
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. See \ref mpu_functions_access_permissions.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cachable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region be configured, for example 4K, 8K. See \ref mpu_functions_region_size.
+*/
+#define MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
+
+/**
+* \brief Struct for a single MPU Region
+* \details An array of MPU Regions can be used to set up an MPU Table.
+* Using a table of precompiled register values can be used at runtime to
+* efficently update a bunch of regions at once using \ref MPU_Load.
+*
+* <b>Example:</b>
+* \code
+* const MPU_Region_t mpuTable[3][4] = {
+* {
+* { .RBAR = MPU_RBAR(0UL, 0x08000000UL), .RASR = MPU_RASR(0UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_1MB) },
+* { .RBAR = MPU_RBAR(1UL, 0x20000000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_32KB) },
+* { .RBAR = MPU_RBAR(2UL, 0x40020000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, MPU_REGION_SIZE_8KB) },
+* { .RBAR = MPU_RBAR(3UL, 0x40022000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, MPU_REGION_SIZE_4KB) }
+* },
+* {
+* { .RBAR = MPU_RBAR(4UL, 0x08000000UL), .RASR = MPU_RASR(0UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_1MB) },
+* { .RBAR = MPU_RBAR(5UL, 0x20000000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_32KB) },
+* { .RBAR = MPU_RBAR(6UL, 0x40020000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, MPU_REGION_SIZE_8KB) },
+* { .RBAR = MPU_RBAR(7UL, 0x40022000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, MPU_REGION_SIZE_4KB) }
+* },
+* {
+* { .RBAR = MPU_RBAR(4UL, 0x18000000UL), .RASR = MPU_RASR(0UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_1MB) },
+* { .RBAR = MPU_RBAR(5UL, 0x30000000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, MPU_REGION_SIZE_32KB) },
+* { .RBAR = MPU_RBAR(6UL, 0x50020000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, MPU_REGION_SIZE_8KB) },
+* { .RBAR = MPU_RBAR(7UL, 0x50022000UL), .RASR = MPU_RASR(1UL, MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, MPU_REGION_SIZE_4KB) }
+* }
+* };
+*
+* void UpdateMpu(uint32_t idx)
+* {
+* Load_MPU(mpuTable[idx], 4u);
+* }
+* \endcode
+*
+* \note As stream loading the MPU makes use of the REGION field in \ref MPU_Type::RBAR only up to 16 regions can be handled this way.
+*/
+typedef struct _MPU_Region_t {
+ uint32_t RBAR; //!< The region base address register value (\ref MPU_Type::RBAR "RBAR")
+ uint32_t RASR; //!< The region attribute and size register value (\ref MPU_Type::RASR "RASR"), see \ref MPU_RASR.
+} MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void MPU_Enable(uint32_t MPU_Control);
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void MPU_Disable();
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void MPU_ClrRegion(uint32_t rnr);
+
+/** Configure an MPU region.
+*
+* The region number should be contained in the rbar value.
+*
+* \param rbar Value for \ref MPU_Type::RBAR "RBAR" register.
+* \param rasr Value for \ref MPU_Type::RASR "RASR" register.
+*/
+__STATIC_INLINE void MPU_SetRegion(uint32_t rbar, uint32_t rasr);
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for \ref MPU_Type::RBAR "RBAR" register.
+* \param rasr Value for \ref MPU_Type::RASR "RASR" register.
+*/
+__STATIC_INLINE void MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr);
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void MPU_Load(MPU_Region_t const* table, uint32_t cnt);
+
+
+/**
+ @}
+
+\defgroup mpu_functions_region_size Defines MPU_REGION_SIZE_
+\ingroup mpu_functions
+\brief Defines for valid MPU region sizes.
+@{
+*/
+
+/** \def MPU_REGION_SIZE_32B
+* \brief Region size 32 Bytes.
+*/
+#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
+
+/** \def MPU_REGION_SIZE_64B
+* \brief Region size 64 Bytes.
+*/
+#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
+
+/** \def MPU_REGION_SIZE_128B
+* \brief Region size 128 Bytes.
+*/
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
+
+/** \def MPU_REGION_SIZE_256B
+* \brief Region size 256 Bytes.
+*/
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
+
+/** \def MPU_REGION_SIZE_512B
+* \brief Region size 512 Bytes.
+*/
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
+
+/** \def MPU_REGION_SIZE_1KB
+* \brief Region size 1KB.
+*/
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
+
+/** \def MPU_REGION_SIZE_2KB
+* \brief Region size 2KB.
+*/
+#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
+
+/** \def MPU_REGION_SIZE_4KB
+* \brief Region size 4KB.
+*/
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
+
+/** \def MPU_REGION_SIZE_8KB
+* \brief Region size 8KB.
+*/
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
+
+/** \def MPU_REGION_SIZE_16KB
+* \brief Region size 16KB.
+*/
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
+
+/** \def MPU_REGION_SIZE_32KB
+* \brief Region size 32KB.
+*/
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
+
+/** \def MPU_REGION_SIZE_64KB
+* \brief Region size 64KB.
+*/
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
+
+/** \def MPU_REGION_SIZE_128KB
+* \brief Region size 128KB.
+*/
+#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
+
+/** \def MPU_REGION_SIZE_256KB
+* \brief Region size 256KB.
+*/
+#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
+
+/** \def MPU_REGION_SIZE_512KB
+* \brief Region size 512KB.
+*/
+#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
+
+/** \def MPU_REGION_SIZE_1MB
+* \brief Region size 1MB.
+*/
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
+
+/** \def MPU_REGION_SIZE_2MB
+* \brief Region size 2MB.
+*/
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
+
+/** \def MPU_REGION_SIZE_4MB
+* \brief Region size 4MB.
+*/
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
+
+/** \def MPU_REGION_SIZE_8MB
+* \brief Region size 8MB.
+*/
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
+
+/** \def MPU_REGION_SIZE_16MB
+* \brief Region size 16MB.
+*/
+#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
+
+/** \def MPU_REGION_SIZE_32MB
+* \brief Region size 32MB.
+*/
+#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
+
+/** \def MPU_REGION_SIZE_64MB
+* \brief Region size 64MB.
+*/
+#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
+
+/** \def MPU_REGION_SIZE_128MB
+* \brief Region size 128MB.
+*/
+#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
+
+/** \def MPU_REGION_SIZE_256MB
+* \brief Region size 256MB
+*/
+#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
+
+/** \def MPU_REGION_SIZE_512MB
+* \brief Region size 512MB.
+*/
+#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
+
+/** \def MPU_REGION_SIZE_1GB
+* \brief Region size 1GB.
+*/
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
+
+/** \def MPU_REGION_SIZE_2GB
+* \brief Region size 2GB.
+*/
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
+
+/** \def MPU_REGION_SIZE_4GB
+* \brief Region size 4GB.
+*/
+#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
+
+/**
+ @}
+
+\defgroup mpu_functions_access_permissions Defines MPU_AP_
+\ingroup mpu_functions
+\brief Defines for valid MPU region access permissions
+@{
+*/
+
+/** \def MPU_AP_NONE
+* Access permissions: None.
+* Any access generates a permission fault.
+*/
+#define MPU_AP_NONE 0u
+
+/** \def MPU_AP_PRIV
+* Access permissions: Privileged Read/Write.
+* Privileged access only. Any unprivileged access generates a permission fault.
+*/
+#define MPU_AP_PRIV 1u
+
+/** \def MPU_AP_URO
+* Access permissions: Privileged Read/Write. Unprivileged Read-only.
+* Any unprivileged write generates a permission fault.
+*/
+#define MPU_AP_URO 2u
+
+/** \def MPU_AP_FULL
+* Access permissions: Privileged Read/Write. Unprivileged Read/Write.
+* Full access, permission faults are never generated.
+*/
+#define MPU_AP_FULL 3u
+
+/** \def MPU_AP_PRO
+* Access permissions: Privileged Read-only.
+* Any unprivileged access or privileged write generates a permission fault.
+*/
+#define MPU_AP_PRO 5u
+
+/** \def MPU_AP_RO
+* Access permissions: Privileged and Unprivileged Read-only.
+* Any write generates a permission fault.
+*/
+#define MPU_AP_RO 6u
+
+/** @} */
+
+/**
+
+\var MPU_Region_t::RBAR
+This value specifies the start address of the MPU protected memory region.
+The address must be a multiple of the region size, i.e. size aligned.
+
+See \ref MPU_Type::RBAR for details about field bit format.
+
+\var MPU_Region_t::RASR
+This value specifies the size of the MPU protected memory region.
+
+Valid values are limited to sizes
+- of at least 32 bytes, and
+- with power of 2
+
+Use one of the \ref mpu_functions_region_size.
+
+\var MPU_Type::TYPE
+The MPU Type Register indicates how many regions the MPU support. Software can use it
+to determine if the processor implements an MPU.
+
+| Bits | Name | Function |
+| :------ | :------------ | :------------------------------------------------------------ |
+| [31:24] | - | Reserved. |
+| [23:16] | IREGION | Instruction region. RAZ. ARMv7-M only supports a unified MPU. |
+| [15:8] | DREGION | Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. |
+| [7:1] | - | Reserved. |
+| [0] | SEPARATE | Indicates support for separate instruction and data address maps. RAZ. ARMv7-M only supports a unified MPU. |
+
+\var MPU_Type::CTRL
+Enables the MPU, and when the MPU is enabled, controls whether the default memory map
+is enabled as a background region for privileged accesses, and whether the MPU is enabled
+for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.
+
+| Bits | Name | Function |
+| :------ | :------------ | :------------------------------------------------------------ |
+| [31:3] | - | Reserved. |
+| [2] | PRIVDEFENA | 0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access. |
+| [1] | HFNMIENA | 0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers. |
+| [0] | ENABLE | 0 - The MPU is disabled. 1 - The MPU is enabled. |
+
+\var MPU_Type::RNR
+Selects the region currently accessed by \ref MPU_Type::RBAR and \ref MPU_Type::RASR.
+
+| Bits | Name | Function |
+| :------ | :------------ | :------------------------------------------------------------ |
+| [31:8] | - | Reserved. |
+| [7:0] | REGION | Indicates the memory region accessed. |
+
+\var MPU_Type::RBAR
+Holds the base address of the region identified by MPU_RNR. On a write, can also be used
+to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR
+with the new region number.
+
+| Bits | Name | Function |
+| :------ | :------------ | :------------------------------------------------------------ |
+| [31:5] | ADDR | Base address of the region. |
+| [4] | VALID | 1 - Update \ref MPU_Type::RNR to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region. |
+| [3:0] | REGION | On writes, can specify the number of the region to update, see VALID field description. |
+
+\var MPU_Type::RASR
+Defines the size and access behavior of the region identified by MPU_RNR, and enables
+that region.
+
+| Bits | Name | Function |
+| :------ | :------------ | :------------------------------------------------------------ |
+| [31:29] | - | Reserved. |
+| [28] | XN | Execute Never. |
+| [27] | - | Reserved. |
+| [26:24] | AP | Access Permissions, see \ref mpu_functions_access_permissions. |
+| [23:22] | - | Reserved. |
+| [21:19] | TEX | Type Extension. |
+| [18] | S | Shareable. |
+| [17] | C | Cachable. |
+| [16] | B | Bufferable. |
+| [15:8] | SRD | Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether ne of the eight equal subregions is enabled (0) or disabled (1).
+| [7:6] | - | Reserved. |
+| [5:1] | SIZE | Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes. |
+| [0] | ENABLE | 0 - This region is disabled. 1 - This region is enabled. |
+
+\var MPU_Type::RBAR_A1
+Alias for \ref MPU_Type::RBAR.
+
+\var MPU_Type::RASR_A1
+Alias for \ref MPU_Type::RASR.
+
+\var MPU_Type::RBAR_A2
+Alias for \ref MPU_Type::RBAR.
+
+\var MPU_Type::RASR_A2
+Alias for \ref MPU_Type::RASR.
+
+\var MPU_Type::RBAR_A3
+Alias for \ref MPU_Type::RBAR.
+
+\var MPU_Type::RASR_A3
+Alias for \ref MPU_Type::RASR.
+
+*/