Core(M): Fixed device config checks for missing defines.
- Added __VTOR_PRESENT to all VTOR-capable cores, defaulting to 1.
- Added __FPU_DP, __DCACHE_PRESENT and __ICACHE_PRESENT to Armv8.1-M cores.
- Updated defines to affected device headers.
Change-Id: I3e0c6a35e4b526b46c583566e2adc69d89b7020a
diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc
index 650d23b..5a9b169 100644
--- a/ARM.CMSIS.pdsc
+++ b/ARM.CMSIS.pdsc
@@ -8,8 +8,12 @@
<url>http://www.keil.com/pack/</url>
<releases>
- <release version="5.7.0-dev6">
+ <release version="5.7.0-dev7">
Active development...
+ CMSIS-Core(M): 5.5.0
+ - Fixed device config define checks.
+ </release>
+ <release version="5.7.0-dev6">
CMSIS-DSP:
- reworked examples
</release>
@@ -26,7 +30,7 @@
- Added MVE support
</release>
<release version="5.7.0-dev3">
- CMSIS-Core(M):
+ CMSIS-Core(M): 5.5.0
- L1 Cache functions for Armv7-M and later
Devices:
- Include L1 Cache functions in ARMv8MML/ARMv81MML devices
diff --git a/CMSIS/Core/Include/core_armv81mml.h b/CMSIS/Core/Include/core_armv81mml.h
index e1e7752..1ad19e2 100644
--- a/CMSIS/Core/Include/core_armv81mml.h
+++ b/CMSIS/Core/Include/core_armv81mml.h
@@ -2,7 +2,7 @@
* @file core_armv81mml.h
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
* @version V1.3.1
- * @date 18. March 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
@@ -210,18 +210,35 @@
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
-
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
+
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
- #ifndef __PMU_PRESENT
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __PMU_PRESENT
#define __PMU_PRESENT 0U
#warning "__PMU_PRESENT not defined in device header file; using default!"
#endif
- #if __PMU_PRESENT != 0
+ #if __PMU_PRESENT != 0U
#ifndef __PMU_NUM_EVENTCNT
#define __PMU_NUM_EVENTCNT 2U
#warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
@@ -240,6 +257,11 @@
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_armv8mbl.h b/CMSIS/Core/Include/core_armv8mbl.h
index f57fd20..932d3d1 100644
--- a/CMSIS/Core/Include/core_armv8mbl.h
+++ b/CMSIS/Core/Include/core_armv8mbl.h
@@ -2,7 +2,7 @@
* @file core_armv8mbl.h
* @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
* @version V5.1.0
- * @date 11. February 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
@@ -70,7 +70,7 @@
#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
__ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
+#define __CORTEX_M (2U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
diff --git a/CMSIS/Core/Include/core_armv8mml.h b/CMSIS/Core/Include/core_armv8mml.h
index 63ce17a..71f000b 100644
--- a/CMSIS/Core/Include/core_armv8mml.h
+++ b/CMSIS/Core/Include/core_armv8mml.h
@@ -2,7 +2,7 @@
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
* @version V5.2.0
- * @date 03. March 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
@@ -70,7 +70,7 @@
#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
__ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-#define __CORTEX_M (81U) /*!< Cortex-M Core */
+#define __CORTEX_M (80U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
@@ -250,6 +250,11 @@
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_cm3.h b/CMSIS/Core/Include/core_cm3.h
index e568fa3..24453a8 100644
--- a/CMSIS/Core/Include/core_cm3.h
+++ b/CMSIS/Core/Include/core_cm3.h
@@ -2,10 +2,10 @@
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V5.1.1
- * @date 19. August 2019
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -142,6 +142,11 @@
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_cm33.h b/CMSIS/Core/Include/core_cm33.h
index c76b37c..13359be 100644
--- a/CMSIS/Core/Include/core_cm33.h
+++ b/CMSIS/Core/Include/core_cm33.h
@@ -2,7 +2,7 @@
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
* @version V5.2.0
- * @date 11. February 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
@@ -250,6 +250,11 @@
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_cm35p.h b/CMSIS/Core/Include/core_cm35p.h
index 58f4cf3..6a5f6ad 100644
--- a/CMSIS/Core/Include/core_cm35p.h
+++ b/CMSIS/Core/Include/core_cm35p.h
@@ -2,7 +2,7 @@
* @file core_cm35p.h
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
* @version V1.1.0
- * @date 11. February 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
@@ -249,7 +249,12 @@
#define __DSP_PRESENT 0U
#warning "__DSP_PRESENT not defined in device header file; using default!"
#endif
-
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_cm4.h b/CMSIS/Core/Include/core_cm4.h
index cfd5af2..4e0e886 100644
--- a/CMSIS/Core/Include/core_cm4.h
+++ b/CMSIS/Core/Include/core_cm4.h
@@ -2,10 +2,10 @@
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V5.1.1
- * @date 19. August 2019
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -194,6 +194,11 @@
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_cm55.h b/CMSIS/Core/Include/core_cm55.h
index 09ee602..6efaa3f 100644
--- a/CMSIS/Core/Include/core_cm55.h
+++ b/CMSIS/Core/Include/core_cm55.h
@@ -2,7 +2,7 @@
* @file core_cm55.h
* @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File
* @version V1.0.0
- * @date 18. March 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2018-2020 Arm Limited. All rights reserved.
@@ -210,18 +210,40 @@
#define __FPU_PRESENT 0U
#warning "__FPU_PRESENT not defined in device header file; using default!"
#endif
+
+ #if __FPU_PRESENT != 0U
+ #ifndef __FPU_DP
+ #define __FPU_DP 0U
+ #warning "__FPU_DP not defined in device header file; using default!"
+ #endif
+ #endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
#ifndef __PMU_PRESENT
#define __PMU_PRESENT 0U
#warning "__PMU_PRESENT not defined in device header file; using default!"
#endif
- #if __PMU_PRESENT != 0
+ #if __PMU_PRESENT != 0U
#ifndef __PMU_NUM_EVENTCNT
#define __PMU_NUM_EVENTCNT 8U
#warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_cm7.h b/CMSIS/Core/Include/core_cm7.h
index 7e126fa..e1c31c2 100644
--- a/CMSIS/Core/Include/core_cm7.h
+++ b/CMSIS/Core/Include/core_cm7.h
@@ -2,7 +2,7 @@
* @file core_cm7.h
* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
* @version V5.1.2
- * @date 03. March 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
@@ -209,6 +209,11 @@
#warning "__DTCM_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_sc000.h b/CMSIS/Core/Include/core_sc000.h
index a8a4061..dbc755f 100644
--- a/CMSIS/Core/Include/core_sc000.h
+++ b/CMSIS/Core/Include/core_sc000.h
@@ -2,10 +2,10 @@
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V5.0.7
- * @date 19. August 2019
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -142,6 +142,11 @@
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/CMSIS/Core/Include/core_sc300.h b/CMSIS/Core/Include/core_sc300.h
index f3f2024..e8914ba 100644
--- a/CMSIS/Core/Include/core_sc300.h
+++ b/CMSIS/Core/Include/core_sc300.h
@@ -2,10 +2,10 @@
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
* @version V5.0.9
- * @date 19. August 2019
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -142,6 +142,11 @@
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 3U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
diff --git a/Device/ARM/ARMCM55/Include/ARMCM55.h b/Device/ARM/ARMCM55/Include/ARMCM55.h
index 0e848d4..9e05668 100644
--- a/Device/ARM/ARMCM55/Include/ARMCM55.h
+++ b/Device/ARM/ARMCM55/Include/ARMCM55.h
@@ -4,7 +4,7 @@
* ARMCM55 Device Series (configured for ARMCM55 with double precision FPU,
* DSP extension, MVE, TrustZone)
* @version V1.0.0
- * @date 26. March 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
@@ -102,8 +102,8 @@
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __PMU_PRESENT 1U /* PMU present */
#define __PMU_NUM_EVENTCNT 8U /* PMU Event Counters */
-#define __ICACHE_PRESENT 1U
-#define __DCACHE_PRESENT 1U
+#define __ICACHE_PRESENT 1U /* Instruction Cache present */
+#define __DCACHE_PRESENT 1U /* Data Cache present */
#include "core_cm55.h" /* Processor and core peripherals */
#include "system_ARMCM55.h" /* System Header */
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7.h b/Device/ARM/ARMCM7/Include/ARMCM7.h
index 4db9527..5149599 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7.h
@@ -2,11 +2,11 @@
* @file ARMCM7.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM7 Device (configured for CM7 without FPU)
- * @version V5.3.1
- * @date 09. July 2018
+ * @version V5.3.2
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -96,9 +96,9 @@
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#define __FPU_DP 0U /* unused */
-#define __ICACHE_PRESENT 1U
-#define __DCACHE_PRESENT 1U
-#define __DTCM_PRESENT 1U
+#define __ICACHE_PRESENT 1U /* Instruction Cache present */
+#define __DCACHE_PRESENT 1U /* Data Cache present */
+#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
#include "core_cm7.h" /* Processor and core peripherals */
#include "system_ARMCM7.h" /* System Header */
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7_DP.h b/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
index d1626fa..f26f951 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7_DP.h
@@ -2,11 +2,11 @@
* @file ARMCM7_DP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM7 Device (configured for CM7 with double precision FPU)
- * @version V5.3.1
- * @date 09. July 2018
+ * @version V5.3.2
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -96,9 +96,9 @@
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /* FPU present */
#define __FPU_DP 1U /* double precision FPU */
-#define __ICACHE_PRESENT 1U
-#define __DCACHE_PRESENT 1U
-#define __DTCM_PRESENT 1U
+#define __ICACHE_PRESENT 1U /* Instruction Cache present */
+#define __DCACHE_PRESENT 1U /* Data Cache present */
+#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
#include "core_cm7.h" /* Processor and core peripherals */
#include "system_ARMCM7.h" /* System Header */
diff --git a/Device/ARM/ARMCM7/Include/ARMCM7_SP.h b/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
index c993210..52bfeb6 100644
--- a/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
+++ b/Device/ARM/ARMCM7/Include/ARMCM7_SP.h
@@ -2,11 +2,11 @@
* @file ARMCM7_SP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM7 Device (configured for CM7 with single precision FPU)
- * @version V5.3.1
- * @date 09. July 2018
+ * @version V5.3.2
+ * @date 27. March 2020
******************************************************************************/
/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -96,9 +96,9 @@
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /* FPU present */
#define __FPU_DP 0U /* single precision FPU */
-#define __ICACHE_PRESENT 1U
-#define __DCACHE_PRESENT 1U
-#define __DTCM_PRESENT 1U
+#define __ICACHE_PRESENT 1U /* Instruction Cache present */
+#define __DCACHE_PRESENT 1U /* Data Cache present */
+#define __DTCM_PRESENT 1U /* Data Tightly Coupled Memory present */
#include "core_cm7.h" /* Processor and core peripherals */
#include "system_ARMCM7.h" /* System Header */
diff --git a/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h b/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h
index a97d7db..b1f2817 100644
--- a/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h
+++ b/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h
@@ -3,7 +3,7 @@
* @brief CMSIS Core Peripheral Access Layer Header File for
* Armv8.1-M Mainline Device Series (configured for Armv8.1-M Mainline with double precision FPU, with DSP extension, with TrustZone)
* @version V1.1.0
- * @date 03. March 2020
+ * @date 27. March 2020
******************************************************************************/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
@@ -100,8 +100,8 @@
#define __FPU_PRESENT 1U /* FPU present */
#define __FPU_DP 1U /* double precision FPU */
#define __DSP_PRESENT 1U /* DSP extension present */
-#define __ICACHE_PRESENT 1U
-#define __DCACHE_PRESENT 1U
+#define __ICACHE_PRESENT 1U /* Instruction Cache present */
+#define __DCACHE_PRESENT 1U /* Data Cache present */
#include "core_armv81mml.h" /* Processor and core peripherals */
#include "system_ARMv81MML.h" /* System Header */