Martin Günther | 1e56003 | 2016-04-08 10:56:27 +0200 | [diff] [blame] | 1 | <?xml version="1.0" encoding="utf-8"?> |
| 2 | |
| 3 | <!-- File naming: <vendor>_<part/series name>.svd --> |
| 4 | |
| 5 | <!-- |
| 6 | Copyright (C) 2012 ARM Limited. All rights reserved. |
| 7 | |
| 8 | Purpose: System Viewer Description (SVD) Example (Schema Version 1.1) |
| 9 | This is a description of a none-existent and incomplete device |
| 10 | for demonstration purposes only. |
| 11 | |
| 12 | Redistribution and use in source and binary forms, with or without |
| 13 | modification, are permitted provided that the following conditions are met: |
| 14 | - Redistributions of source code must retain the above copyright |
| 15 | notice, this list of conditions and the following disclaimer. |
| 16 | - Redistributions in binary form must reproduce the above copyright |
| 17 | notice, this list of conditions and the following disclaimer in the |
| 18 | documentation and/or other materials provided with the distribution. |
| 19 | - Neither the name of ARM nor the names of its contributors may be used |
| 20 | to endorse or promote products derived from this software without |
| 21 | specific prior written permission. |
| 22 | |
| 23 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 24 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 25 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 26 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
| 27 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 28 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 29 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 30 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 31 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 32 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 33 | POSSIBILITY OF SUCH DAMAGE. |
| 34 | --> |
| 35 | |
| 36 | <device schemaVersion="1.2" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" > |
| 37 | <vendor>ARM Ltd.</vendor> <!-- device vendor name --> |
| 38 | <vendorID>ARM</vendorID> <!-- device vendor short name --> |
| 39 | <name>ARMCM0P</name> <!-- name of part--> |
| 40 | <series>ARMCM</series> <!-- device series the device belongs to --> |
| 41 | <version>1.2</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags --> |
| 42 | <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description> |
| 43 | <licenseText> <!-- this license text will appear in header file. \n force line breaks --> |
| 44 | ARM Limited (ARM) is supplying this software for use with Cortex-M\n |
| 45 | processor based microcontroller, but can be equally used for other\n |
| 46 | suitable processor architectures. This file can be freely distributed.\n |
| 47 | Modifications to this file shall be clearly marked.\n |
| 48 | \n |
| 49 | THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n |
| 50 | OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n |
| 51 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n |
| 52 | ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n |
| 53 | CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| 54 | </licenseText> |
| 55 | <cpu> <!-- details about the cpu embedded in the device --> |
| 56 | <name>CM0+</name> |
| 57 | <revision>r0p0</revision> |
| 58 | <endian>little</endian> |
| 59 | <mpuPresent>false</mpuPresent> |
| 60 | <fpuPresent>false</fpuPresent> |
| 61 | <nvicPrioBits>3</nvicPrioBits> |
| 62 | <vendorSystickConfig>false</vendorSystickConfig> |
| 63 | </cpu> |
| 64 | <addressUnitBits>8</addressUnitBits> <!-- byte addressable memory --> |
| 65 | <width>32</width> <!-- bus width is 32 bits --> |
| 66 | <!-- default settings implicitly inherited by subsequent sections --> |
| 67 | <size>32</size> <!-- this is the default size (number of bits) of all peripherals |
| 68 | and register that do not define "size" themselves --> |
| 69 | <access>read-write</access> <!-- default access permission for all subsequent registers --> |
| 70 | <resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset --> |
| 71 | <resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used --> |
| 72 | |
| 73 | <peripherals> |
| 74 | <peripheral> |
| 75 | <name>SysTick</name> |
| 76 | <description>24Bit System Tick Timer for use in RTOS</description> |
| 77 | <baseAddress>0xE000E010</baseAddress> |
| 78 | |
| 79 | <addressBlock> |
| 80 | <offset>0</offset> |
| 81 | <size>0x10</size> |
| 82 | <usage>registers</usage> |
| 83 | </addressBlock> |
| 84 | |
| 85 | <registers> |
| 86 | <register> |
| 87 | <name>CSR</name> |
| 88 | <description>SysTick Control and Status Register</description> |
| 89 | <addressOffset>0</addressOffset> |
| 90 | <size>32</size> |
| 91 | <resetValue>0x4</resetValue> |
| 92 | <resetMask>0xFFFFFFFF</resetMask> |
| 93 | <fields> |
| 94 | <field> |
| 95 | <name>ENABLE</name> |
| 96 | <description>Enable SysTick Timer</description> |
| 97 | <bitOffset>0</bitOffset> |
| 98 | <bitWidth>1</bitWidth> |
| 99 | <access>read-write</access> |
| 100 | <enumeratedValues> |
| 101 | <enumeratedValue> |
| 102 | <name>0</name> |
| 103 | <description>disabled</description> |
| 104 | <value>0</value> |
| 105 | </enumeratedValue> |
| 106 | <enumeratedValue> |
| 107 | <name>1</name> |
| 108 | <description>enabled</description> |
| 109 | <value>1</value> |
| 110 | </enumeratedValue> |
| 111 | </enumeratedValues> |
| 112 | </field> |
| 113 | <field> |
| 114 | <name>TICKINT</name> |
| 115 | <description>Generate Tick Interrupt</description> |
| 116 | <bitOffset>1</bitOffset> |
| 117 | <bitWidth>1</bitWidth> |
| 118 | <access>read-write</access> |
| 119 | <enumeratedValues> |
| 120 | <enumeratedValue> |
| 121 | <name>0</name> |
| 122 | <description>Enable SysTick Exception</description> |
| 123 | <value>0</value> |
| 124 | </enumeratedValue> |
| 125 | <enumeratedValue> |
| 126 | <name>1</name> |
| 127 | <description>Disable SysTick Exception</description> |
| 128 | <value>1</value> |
| 129 | </enumeratedValue> |
| 130 | </enumeratedValues> |
| 131 | </field> |
| 132 | <field> |
| 133 | <name>CLKSOURCE</name> |
| 134 | <description>Source to count from</description> |
| 135 | <bitOffset>2</bitOffset> |
| 136 | <bitWidth>1</bitWidth> |
| 137 | <access>read-write</access> |
| 138 | <enumeratedValues> |
| 139 | <enumeratedValue> |
| 140 | <name>0</name> |
| 141 | <description>External Clock</description> |
| 142 | <value>0</value> |
| 143 | </enumeratedValue> |
| 144 | <enumeratedValue> |
| 145 | <name>1</name> |
| 146 | <description>CPU Clock</description> |
| 147 | <value>1</value> |
| 148 | </enumeratedValue> |
| 149 | </enumeratedValues> |
| 150 | </field> |
| 151 | <field> |
| 152 | <name>COUNTFLAG</name> |
| 153 | <description>SysTick counted to zero</description> |
| 154 | <bitOffset>16</bitOffset> |
| 155 | <bitWidth>1</bitWidth> |
| 156 | <access>read-write</access> |
| 157 | </field> |
| 158 | </fields> |
| 159 | </register> |
| 160 | <register> |
| 161 | <name>RVR</name> |
| 162 | <description>SysTick Reload Value Register</description> |
| 163 | <addressOffset>0x4</addressOffset> |
| 164 | <size>32</size> |
| 165 | <resetValue>0</resetValue> |
| 166 | <resetMask>0xFFFFFFFF</resetMask> |
| 167 | <fields> |
| 168 | <field> |
| 169 | <name>RELOAD</name> |
| 170 | <description>Value to auto reload SysTick after reaching zero</description> |
| 171 | <bitOffset>0</bitOffset> |
| 172 | <bitWidth>24</bitWidth> |
| 173 | <access>read-write</access> |
| 174 | </field> |
| 175 | </fields> |
| 176 | </register> |
| 177 | <register> |
| 178 | <name>CVR</name> |
| 179 | <description>SysTick Current Value Register</description> |
| 180 | <addressOffset>0x8</addressOffset> |
| 181 | <size>32</size> |
| 182 | <resetValue>0</resetValue> |
| 183 | <resetMask>0xFFFFFFFF</resetMask> |
| 184 | <fields> |
| 185 | <field> |
| 186 | <name>CURRENT</name> |
| 187 | <description>Current value</description> |
| 188 | <bitOffset>0</bitOffset> |
| 189 | <bitWidth>24</bitWidth> |
| 190 | <access>read-write</access> |
| 191 | </field> |
| 192 | </fields> |
| 193 | </register> |
| 194 | <register> |
| 195 | <name>CALIB</name> |
| 196 | <description>SysTick Calibration Value Register</description> |
| 197 | <addressOffset>0xC</addressOffset> |
| 198 | <size>32</size> |
| 199 | <resetValue>0</resetValue> |
| 200 | <resetMask>0xFFFFFFFF</resetMask> |
| 201 | <fields> |
| 202 | <field> |
| 203 | <name>TENMS</name> |
| 204 | <description>Reload value to use for 10ms timing</description> |
| 205 | <bitOffset>0</bitOffset> |
| 206 | <bitWidth>24</bitWidth> |
| 207 | <access>read-only</access> |
| 208 | </field> |
| 209 | <field> |
| 210 | <name>SKEW</name> |
| 211 | <description>Clock Skew</description> |
| 212 | <bitOffset>30</bitOffset> |
| 213 | <bitWidth>1</bitWidth> |
| 214 | <access>read-only</access> |
| 215 | <enumeratedValues> |
| 216 | <enumeratedValue> |
| 217 | <name>0</name> |
| 218 | <description>10ms calibration value is exact</description> |
| 219 | <value>0</value> |
| 220 | </enumeratedValue> |
| 221 | <enumeratedValue> |
| 222 | <name>1</name> |
| 223 | <description>10ms calibration value is inexact, because of the clock frequency</description> |
| 224 | <value>1</value> |
| 225 | </enumeratedValue> |
| 226 | </enumeratedValues> |
| 227 | </field> |
| 228 | <field> |
| 229 | <name>NOREF</name> |
| 230 | <description>No Ref</description> |
| 231 | <bitOffset>31</bitOffset> |
| 232 | <bitWidth>1</bitWidth> |
| 233 | <access>read-only</access> |
| 234 | <enumeratedValues> |
| 235 | <enumeratedValue> |
| 236 | <name>0</name> |
| 237 | <description>Ref Clk available</description> |
| 238 | <value>0</value> |
| 239 | </enumeratedValue> |
| 240 | <enumeratedValue> |
| 241 | <name>1</name> |
| 242 | <description>Ref Clk not available</description> |
| 243 | <value>1</value> |
| 244 | </enumeratedValue> |
| 245 | </enumeratedValues> |
| 246 | </field> |
| 247 | </fields> |
| 248 | </register> |
| 249 | </registers> |
| 250 | </peripheral> |
| 251 | |
| 252 | <peripheral> |
| 253 | <name>WDT</name> |
| 254 | <description>Watchdog Timer</description> |
| 255 | <baseAddress>0x40001000</baseAddress> |
| 256 | |
| 257 | <addressBlock> |
| 258 | <offset>0</offset> |
| 259 | <size>0x10</size> |
| 260 | <usage>registers</usage> |
| 261 | </addressBlock> |
| 262 | |
| 263 | <interrupt> |
| 264 | <name>WDT</name> |
| 265 | <value>1</value> |
| 266 | </interrupt> |
| 267 | |
| 268 | <registers> |
| 269 | <register> |
| 270 | <name>CSR</name> |
| 271 | <description>Watchdog Control and Status Register</description> |
| 272 | <addressOffset>0</addressOffset> |
| 273 | <size>32</size> |
| 274 | <resetValue>0x4</resetValue> |
| 275 | <resetMask>0xFFFFFFFF</resetMask> |
| 276 | </register> |
| 277 | </registers> |
| 278 | </peripheral> |
| 279 | </peripherals> |
| 280 | </device> |