| Joachim Krech | c477341 | 2016-02-18 09:17:07 +0100 | [diff] [blame] | 1 |
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| 2 | /****************************************************************************************************//**
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| 3 | * @file ARM_Example.h
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| 4 | *
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| 5 | * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
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| 6 | * ARM_Example from ARM Ltd..
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| 7 | *
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| 8 | * @version V1.2
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| 9 | * @date 16. April 2014
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| 10 | *
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| 11 | * @note Generated with SVDConv V2.81e
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| 12 | * from CMSIS SVD File 'ARM_Example.svd' Version 1.2,
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| 13 | *
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| 14 | * @par ARM Limited (ARM) is supplying this software for use with Cortex-M
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| 15 | * processor based microcontroller, but can be equally used for other
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| 16 | * suitable processor architectures. This file can be freely distributed.
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| 17 | * Modifications to this file shall be clearly marked.
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| 18 | *
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| 19 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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| 20 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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| 21 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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| 22 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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| 23 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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| 24 | *
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| 25 | *******************************************************************************************************/
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| 26 |
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| 27 |
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| 28 |
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| 29 | /** @addtogroup ARM Ltd.
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| 30 | * @{
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| 31 | */
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| 32 |
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| 33 | /** @addtogroup ARM_Example
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| 34 | * @{
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| 35 | */
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| 36 |
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| 37 | #ifndef ARM_EXAMPLE_H
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| 38 | #define ARM_EXAMPLE_H
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| 39 |
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| 40 | #ifdef __cplusplus
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| 41 | extern "C" {
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| 42 | #endif
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| 43 |
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| 44 |
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| 45 | /* ------------------------- Interrupt Number Definition ------------------------ */
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| 46 |
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| 47 | typedef enum {
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| 48 | /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
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| 49 | Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
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| 50 | NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
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| 51 | HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
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| 52 | MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
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| 53 | and No Match */
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| 54 | BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
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| 55 | related Fault */
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| 56 | UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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| 57 | SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
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| 58 | DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
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| 59 | PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
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| 60 | SysTick_IRQn = -1, /*!< 15 System Tick Timer */
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| 61 | /* ------------------- ARM_Example Specific Interrupt Numbers ------------------- */
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| 62 | TIMER0_IRQn = 0, /*!< 0 TIMER0 */
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| 63 | TIMER1_IRQn = 4, /*!< 4 TIMER1 */
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| 64 | TIMER2_IRQn = 6 /*!< 6 TIMER2 */
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| 65 | } IRQn_Type;
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| 66 |
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| 67 |
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| 68 | /** @addtogroup Configuration_of_CMSIS
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| 69 | * @{
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| 70 | */
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| 71 |
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| 72 |
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| 73 | /* ================================================================================ */
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| 74 | /* ================ Processor and Core Peripheral Section ================ */
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| 75 | /* ================================================================================ */
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| 76 |
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| 77 | /* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
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| 78 | #define __CM3_REV 0x0100 /*!< Cortex-M3 Core Revision */
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| 79 | #define __MPU_PRESENT 1 /*!< MPU present or not */
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| 80 | #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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| 81 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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| 82 | /** @} */ /* End of group Configuration_of_CMSIS */
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| 83 |
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| 84 | #include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
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| 85 | #include "system_ARMCM3.h" /*!< ARM_Example System */
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| 86 |
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| 87 |
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| 88 | /* ================================================================================ */
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| 89 | /* ================ Device Specific Peripheral Section ================ */
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| 90 | /* ================================================================================ */
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| 91 |
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| 92 |
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| 93 | /** @addtogroup Device_Peripheral_Registers
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| 94 | * @{
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| 95 | */
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| 96 |
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| 97 |
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| 98 | /* ------------------- Start of section using anonymous unions ------------------ */
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| 99 | #if defined(__CC_ARM)
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| 100 | #pragma push
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| 101 | #pragma anon_unions
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| 102 | #elif defined(__ICCARM__)
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| 103 | #pragma language=extended
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| 104 | #elif defined(__GNUC__)
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| 105 | /* anonymous unions are enabled by default */
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| 106 | #elif defined(__TMS470__)
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| 107 | /* anonymous unions are enabled by default */
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| 108 | #elif defined(__TASKING__)
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| 109 | #pragma warning 586
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| 110 | #else
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| 111 | #warning Not supported compiler type
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| 112 | #endif
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| 113 |
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| 114 |
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| 115 |
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| 116 | /* ================================================================================ */
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| 117 | /* ================ TIMER0 ================ */
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| 118 | /* ================================================================================ */
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| 119 |
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| 120 |
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| 121 | /**
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| 122 | * @brief 32 Timer / Counter, counting up or down from different sources (TIMER0)
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| 123 | */
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| 124 |
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| 125 | typedef struct { /*!< TIMER0 Structure */
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| 126 | __IO uint32_t CR; /*!< Control Register */
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| 127 | __IO uint16_t SR; /*!< Status Register */
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| 128 | __I uint16_t RESERVED0[5];
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| 129 | __IO uint16_t INT; /*!< Interrupt Register */
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| 130 | __I uint16_t RESERVED1[7];
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| 131 | __IO uint32_t COUNT; /*!< The Counter Register reflects the actual Value of the Timer/Counter */
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| 132 | __IO uint32_t MATCH; /*!< The Match Register stores the compare Value for the MATCH condition */
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| 133 |
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| 134 | union {
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| 135 | __O uint32_t PRESCALE_WR; /*!< The Prescale Register stores the Value for the prescaler. The
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| 136 | cont event gets divided by this value */
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| 137 | __I uint32_t PRESCALE_RD; /*!< The Prescale Register stores the Value for the prescaler. The
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| 138 | cont event gets divided by this value */
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| 139 | };
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| 140 | __I uint32_t RESERVED2[9];
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| 141 | __IO uint32_t RELOAD[4]; /*!< The Reload Register stores the Value the COUNT Register gets
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| 142 | reloaded on a when a condition was met. */
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| 143 | } TIMER0_Type;
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| 144 |
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| 145 |
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| 146 | /* -------------------- End of section using anonymous unions ------------------- */
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| 147 | #if defined(__CC_ARM)
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| 148 | #pragma pop
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| 149 | #elif defined(__ICCARM__)
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| 150 | /* leave anonymous unions enabled */
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| 151 | #elif defined(__GNUC__)
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| 152 | /* anonymous unions are enabled by default */
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| 153 | #elif defined(__TMS470__)
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| 154 | /* anonymous unions are enabled by default */
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| 155 | #elif defined(__TASKING__)
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| 156 | #pragma warning restore
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| 157 | #else
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| 158 | #warning Not supported compiler type
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| 159 | #endif
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| 160 |
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| 161 |
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| 162 |
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| 163 |
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| 164 | /* ================================================================================ */
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| 165 | /* ================ Peripheral memory map ================ */
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| 166 | /* ================================================================================ */
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| 167 |
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| 168 | #define TIMER0_BASE 0x40010000UL
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| 169 | #define TIMER1_BASE 0x40010100UL
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| 170 | #define TIMER2_BASE 0x40010200UL
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| 171 |
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| 172 |
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| 173 | /* ================================================================================ */
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| 174 | /* ================ Peripheral declaration ================ */
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| 175 | /* ================================================================================ */
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| 176 |
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| 177 | #define TIMER0 ((TIMER0_Type *) TIMER0_BASE)
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| 178 | #define TIMER1 ((TIMER0_Type *) TIMER1_BASE)
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| 179 | #define TIMER2 ((TIMER0_Type *) TIMER2_BASE)
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| 180 |
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| 181 |
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| 182 | /** @} */ /* End of group Device_Peripheral_Registers */
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| 183 | /** @} */ /* End of group ARM_Example */
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| 184 | /** @} */ /* End of group ARM Ltd. */
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| 185 |
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| 186 | #ifdef __cplusplus
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| 187 | }
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| 188 | #endif
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| 189 |
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| 190 |
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| 191 | #endif /* ARM_Example_H */
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| 192 |
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